1 /*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009-12 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/gcd.h>
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/slab.h>
25 #include <sound/core.h>
26 #include <sound/jack.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
32 #include <trace/events/asoc.h>
33
34 #include <linux/mfd/wm8994/core.h>
35 #include <linux/mfd/wm8994/registers.h>
36 #include <linux/mfd/wm8994/pdata.h>
37 #include <linux/mfd/wm8994/gpio.h>
38
39 #include "wm8994.h"
40 #include "wm_hubs.h"
41
42 #define WM1811_JACKDET_MODE_NONE 0x0000
43 #define WM1811_JACKDET_MODE_JACK 0x0100
44 #define WM1811_JACKDET_MODE_MIC 0x0080
45 #define WM1811_JACKDET_MODE_AUDIO 0x0180
46
47 #define WM8994_NUM_DRC 3
48 #define WM8994_NUM_EQ 3
49
50 static struct {
51 unsigned int reg;
52 unsigned int mask;
53 } wm8994_vu_bits[] = {
54 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
55 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
56 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
57 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
58 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
59 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
60 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
61 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
62 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
63 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
64
65 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
66 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
67 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
68 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
69 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
70 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
71 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
72 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
73 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
74 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
75 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
76 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
77 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
78 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
79 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
80 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
81 };
82
83 static int wm8994_drc_base[] = {
84 WM8994_AIF1_DRC1_1,
85 WM8994_AIF1_DRC2_1,
86 WM8994_AIF2_DRC_1,
87 };
88
89 static int wm8994_retune_mobile_base[] = {
90 WM8994_AIF1_DAC1_EQ_GAINS_1,
91 WM8994_AIF1_DAC2_EQ_GAINS_1,
92 WM8994_AIF2_EQ_GAINS_1,
93 };
94
95 static const struct wm8958_micd_rate micdet_rates[] = {
96 { 32768, true, 1, 4 },
97 { 32768, false, 1, 1 },
98 { 44100 * 256, true, 7, 10 },
99 { 44100 * 256, false, 7, 10 },
100 };
101
102 static const struct wm8958_micd_rate jackdet_rates[] = {
103 { 32768, true, 0, 1 },
104 { 32768, false, 0, 1 },
105 { 44100 * 256, true, 10, 10 },
106 { 44100 * 256, false, 7, 8 },
107 };
108
wm8958_micd_set_rate(struct snd_soc_component * component)109 static void wm8958_micd_set_rate(struct snd_soc_component *component)
110 {
111 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
112 struct wm8994 *control = wm8994->wm8994;
113 int best, i, sysclk, val;
114 bool idle;
115 const struct wm8958_micd_rate *rates;
116 int num_rates;
117
118 idle = !wm8994->jack_mic;
119
120 sysclk = snd_soc_component_read32(component, WM8994_CLOCKING_1);
121 if (sysclk & WM8994_SYSCLK_SRC)
122 sysclk = wm8994->aifclk[1];
123 else
124 sysclk = wm8994->aifclk[0];
125
126 if (control->pdata.micd_rates) {
127 rates = control->pdata.micd_rates;
128 num_rates = control->pdata.num_micd_rates;
129 } else if (wm8994->jackdet) {
130 rates = jackdet_rates;
131 num_rates = ARRAY_SIZE(jackdet_rates);
132 } else {
133 rates = micdet_rates;
134 num_rates = ARRAY_SIZE(micdet_rates);
135 }
136
137 best = 0;
138 for (i = 0; i < num_rates; i++) {
139 if (rates[i].idle != idle)
140 continue;
141 if (abs(rates[i].sysclk - sysclk) <
142 abs(rates[best].sysclk - sysclk))
143 best = i;
144 else if (rates[best].idle != idle)
145 best = i;
146 }
147
148 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
149 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
150
151 dev_dbg(component->dev, "MICD rate %d,%d for %dHz %s\n",
152 rates[best].start, rates[best].rate, sysclk,
153 idle ? "idle" : "active");
154
155 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
156 WM8958_MICD_BIAS_STARTTIME_MASK |
157 WM8958_MICD_RATE_MASK, val);
158 }
159
configure_aif_clock(struct snd_soc_component * component,int aif)160 static int configure_aif_clock(struct snd_soc_component *component, int aif)
161 {
162 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
163 int rate;
164 int reg1 = 0;
165 int offset;
166
167 if (aif)
168 offset = 4;
169 else
170 offset = 0;
171
172 switch (wm8994->sysclk[aif]) {
173 case WM8994_SYSCLK_MCLK1:
174 rate = wm8994->mclk[0];
175 break;
176
177 case WM8994_SYSCLK_MCLK2:
178 reg1 |= 0x8;
179 rate = wm8994->mclk[1];
180 break;
181
182 case WM8994_SYSCLK_FLL1:
183 reg1 |= 0x10;
184 rate = wm8994->fll[0].out;
185 break;
186
187 case WM8994_SYSCLK_FLL2:
188 reg1 |= 0x18;
189 rate = wm8994->fll[1].out;
190 break;
191
192 default:
193 return -EINVAL;
194 }
195
196 if (rate >= 13500000) {
197 rate /= 2;
198 reg1 |= WM8994_AIF1CLK_DIV;
199
200 dev_dbg(component->dev, "Dividing AIF%d clock to %dHz\n",
201 aif + 1, rate);
202 }
203
204 wm8994->aifclk[aif] = rate;
205
206 snd_soc_component_update_bits(component, WM8994_AIF1_CLOCKING_1 + offset,
207 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
208 reg1);
209
210 return 0;
211 }
212
configure_clock(struct snd_soc_component * component)213 static int configure_clock(struct snd_soc_component *component)
214 {
215 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
216 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
217 int change, new;
218
219 /* Bring up the AIF clocks first */
220 configure_aif_clock(component, 0);
221 configure_aif_clock(component, 1);
222
223 /* Then switch CLK_SYS over to the higher of them; a change
224 * can only happen as a result of a clocking change which can
225 * only be made outside of DAPM so we can safely redo the
226 * clocking.
227 */
228
229 /* If they're equal it doesn't matter which is used */
230 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
231 wm8958_micd_set_rate(component);
232 return 0;
233 }
234
235 if (wm8994->aifclk[0] < wm8994->aifclk[1])
236 new = WM8994_SYSCLK_SRC;
237 else
238 new = 0;
239
240 change = snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
241 WM8994_SYSCLK_SRC, new);
242 if (change)
243 snd_soc_dapm_sync(dapm);
244
245 wm8958_micd_set_rate(component);
246
247 return 0;
248 }
249
check_clk_sys(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)250 static int check_clk_sys(struct snd_soc_dapm_widget *source,
251 struct snd_soc_dapm_widget *sink)
252 {
253 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
254 int reg = snd_soc_component_read32(component, WM8994_CLOCKING_1);
255 const char *clk;
256
257 /* Check what we're currently using for CLK_SYS */
258 if (reg & WM8994_SYSCLK_SRC)
259 clk = "AIF2CLK";
260 else
261 clk = "AIF1CLK";
262
263 return strcmp(source->name, clk) == 0;
264 }
265
266 static const char *sidetone_hpf_text[] = {
267 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
268 };
269
270 static SOC_ENUM_SINGLE_DECL(sidetone_hpf,
271 WM8994_SIDETONE, 7, sidetone_hpf_text);
272
273 static const char *adc_hpf_text[] = {
274 "HiFi", "Voice 1", "Voice 2", "Voice 3"
275 };
276
277 static SOC_ENUM_SINGLE_DECL(aif1adc1_hpf,
278 WM8994_AIF1_ADC1_FILTERS, 13, adc_hpf_text);
279
280 static SOC_ENUM_SINGLE_DECL(aif1adc2_hpf,
281 WM8994_AIF1_ADC2_FILTERS, 13, adc_hpf_text);
282
283 static SOC_ENUM_SINGLE_DECL(aif2adc_hpf,
284 WM8994_AIF2_ADC_FILTERS, 13, adc_hpf_text);
285
286 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
287 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
288 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
289 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
290 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
291 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
292 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
293
294 #define WM8994_DRC_SWITCH(xname, reg, shift) \
295 SOC_SINGLE_EXT(xname, reg, shift, 1, 0, \
296 snd_soc_get_volsw, wm8994_put_drc_sw)
297
wm8994_put_drc_sw(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)298 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
299 struct snd_ctl_elem_value *ucontrol)
300 {
301 struct soc_mixer_control *mc =
302 (struct soc_mixer_control *)kcontrol->private_value;
303 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
304 int mask, ret;
305
306 /* Can't enable both ADC and DAC paths simultaneously */
307 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
308 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
309 WM8994_AIF1ADC1R_DRC_ENA_MASK;
310 else
311 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
312
313 ret = snd_soc_component_read32(component, mc->reg);
314 if (ret < 0)
315 return ret;
316 if (ret & mask)
317 return -EINVAL;
318
319 return snd_soc_put_volsw(kcontrol, ucontrol);
320 }
321
wm8994_set_drc(struct snd_soc_component * component,int drc)322 static void wm8994_set_drc(struct snd_soc_component *component, int drc)
323 {
324 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
325 struct wm8994 *control = wm8994->wm8994;
326 struct wm8994_pdata *pdata = &control->pdata;
327 int base = wm8994_drc_base[drc];
328 int cfg = wm8994->drc_cfg[drc];
329 int save, i;
330
331 /* Save any enables; the configuration should clear them. */
332 save = snd_soc_component_read32(component, base);
333 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
334 WM8994_AIF1ADC1R_DRC_ENA;
335
336 for (i = 0; i < WM8994_DRC_REGS; i++)
337 snd_soc_component_update_bits(component, base + i, 0xffff,
338 pdata->drc_cfgs[cfg].regs[i]);
339
340 snd_soc_component_update_bits(component, base, WM8994_AIF1DAC1_DRC_ENA |
341 WM8994_AIF1ADC1L_DRC_ENA |
342 WM8994_AIF1ADC1R_DRC_ENA, save);
343 }
344
345 /* Icky as hell but saves code duplication */
wm8994_get_drc(const char * name)346 static int wm8994_get_drc(const char *name)
347 {
348 if (strcmp(name, "AIF1DRC1 Mode") == 0)
349 return 0;
350 if (strcmp(name, "AIF1DRC2 Mode") == 0)
351 return 1;
352 if (strcmp(name, "AIF2DRC Mode") == 0)
353 return 2;
354 return -EINVAL;
355 }
356
wm8994_put_drc_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)357 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
358 struct snd_ctl_elem_value *ucontrol)
359 {
360 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
361 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
362 struct wm8994 *control = wm8994->wm8994;
363 struct wm8994_pdata *pdata = &control->pdata;
364 int drc = wm8994_get_drc(kcontrol->id.name);
365 int value = ucontrol->value.enumerated.item[0];
366
367 if (drc < 0)
368 return drc;
369
370 if (value >= pdata->num_drc_cfgs)
371 return -EINVAL;
372
373 wm8994->drc_cfg[drc] = value;
374
375 wm8994_set_drc(component, drc);
376
377 return 0;
378 }
379
wm8994_get_drc_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)380 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
381 struct snd_ctl_elem_value *ucontrol)
382 {
383 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
384 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
385 int drc = wm8994_get_drc(kcontrol->id.name);
386
387 if (drc < 0)
388 return drc;
389 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
390
391 return 0;
392 }
393
wm8994_set_retune_mobile(struct snd_soc_component * component,int block)394 static void wm8994_set_retune_mobile(struct snd_soc_component *component, int block)
395 {
396 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
397 struct wm8994 *control = wm8994->wm8994;
398 struct wm8994_pdata *pdata = &control->pdata;
399 int base = wm8994_retune_mobile_base[block];
400 int iface, best, best_val, save, i, cfg;
401
402 if (!pdata || !wm8994->num_retune_mobile_texts)
403 return;
404
405 switch (block) {
406 case 0:
407 case 1:
408 iface = 0;
409 break;
410 case 2:
411 iface = 1;
412 break;
413 default:
414 return;
415 }
416
417 /* Find the version of the currently selected configuration
418 * with the nearest sample rate. */
419 cfg = wm8994->retune_mobile_cfg[block];
420 best = 0;
421 best_val = INT_MAX;
422 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
423 if (strcmp(pdata->retune_mobile_cfgs[i].name,
424 wm8994->retune_mobile_texts[cfg]) == 0 &&
425 abs(pdata->retune_mobile_cfgs[i].rate
426 - wm8994->dac_rates[iface]) < best_val) {
427 best = i;
428 best_val = abs(pdata->retune_mobile_cfgs[i].rate
429 - wm8994->dac_rates[iface]);
430 }
431 }
432
433 dev_dbg(component->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
434 block,
435 pdata->retune_mobile_cfgs[best].name,
436 pdata->retune_mobile_cfgs[best].rate,
437 wm8994->dac_rates[iface]);
438
439 /* The EQ will be disabled while reconfiguring it, remember the
440 * current configuration.
441 */
442 save = snd_soc_component_read32(component, base);
443 save &= WM8994_AIF1DAC1_EQ_ENA;
444
445 for (i = 0; i < WM8994_EQ_REGS; i++)
446 snd_soc_component_update_bits(component, base + i, 0xffff,
447 pdata->retune_mobile_cfgs[best].regs[i]);
448
449 snd_soc_component_update_bits(component, base, WM8994_AIF1DAC1_EQ_ENA, save);
450 }
451
452 /* Icky as hell but saves code duplication */
wm8994_get_retune_mobile_block(const char * name)453 static int wm8994_get_retune_mobile_block(const char *name)
454 {
455 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
456 return 0;
457 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
458 return 1;
459 if (strcmp(name, "AIF2 EQ Mode") == 0)
460 return 2;
461 return -EINVAL;
462 }
463
wm8994_put_retune_mobile_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)464 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
465 struct snd_ctl_elem_value *ucontrol)
466 {
467 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
468 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
469 struct wm8994 *control = wm8994->wm8994;
470 struct wm8994_pdata *pdata = &control->pdata;
471 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
472 int value = ucontrol->value.enumerated.item[0];
473
474 if (block < 0)
475 return block;
476
477 if (value >= pdata->num_retune_mobile_cfgs)
478 return -EINVAL;
479
480 wm8994->retune_mobile_cfg[block] = value;
481
482 wm8994_set_retune_mobile(component, block);
483
484 return 0;
485 }
486
wm8994_get_retune_mobile_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)487 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
488 struct snd_ctl_elem_value *ucontrol)
489 {
490 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
491 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
492 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
493
494 if (block < 0)
495 return block;
496
497 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
498
499 return 0;
500 }
501
502 static const char *aif_chan_src_text[] = {
503 "Left", "Right"
504 };
505
506 static SOC_ENUM_SINGLE_DECL(aif1adcl_src,
507 WM8994_AIF1_CONTROL_1, 15, aif_chan_src_text);
508
509 static SOC_ENUM_SINGLE_DECL(aif1adcr_src,
510 WM8994_AIF1_CONTROL_1, 14, aif_chan_src_text);
511
512 static SOC_ENUM_SINGLE_DECL(aif2adcl_src,
513 WM8994_AIF2_CONTROL_1, 15, aif_chan_src_text);
514
515 static SOC_ENUM_SINGLE_DECL(aif2adcr_src,
516 WM8994_AIF2_CONTROL_1, 14, aif_chan_src_text);
517
518 static SOC_ENUM_SINGLE_DECL(aif1dacl_src,
519 WM8994_AIF1_CONTROL_2, 15, aif_chan_src_text);
520
521 static SOC_ENUM_SINGLE_DECL(aif1dacr_src,
522 WM8994_AIF1_CONTROL_2, 14, aif_chan_src_text);
523
524 static SOC_ENUM_SINGLE_DECL(aif2dacl_src,
525 WM8994_AIF2_CONTROL_2, 15, aif_chan_src_text);
526
527 static SOC_ENUM_SINGLE_DECL(aif2dacr_src,
528 WM8994_AIF2_CONTROL_2, 14, aif_chan_src_text);
529
530 static const char *osr_text[] = {
531 "Low Power", "High Performance",
532 };
533
534 static SOC_ENUM_SINGLE_DECL(dac_osr,
535 WM8994_OVERSAMPLING, 0, osr_text);
536
537 static SOC_ENUM_SINGLE_DECL(adc_osr,
538 WM8994_OVERSAMPLING, 1, osr_text);
539
540 static const struct snd_kcontrol_new wm8994_common_snd_controls[] = {
541 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
542 WM8994_AIF1_ADC1_RIGHT_VOLUME,
543 1, 119, 0, digital_tlv),
544 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
545 WM8994_AIF2_ADC_RIGHT_VOLUME,
546 1, 119, 0, digital_tlv),
547
548 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
549 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
550 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
551 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
552
553 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
554 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
555 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
556 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
557
558 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
559 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
560 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
561 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
562
563 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
564 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
565
566 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
567 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
568
569 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
570 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
571 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
572
573 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
574 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
575 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
576
577 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
578 5, 12, 0, st_tlv),
579 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
580 0, 12, 0, st_tlv),
581 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
582 5, 12, 0, st_tlv),
583 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
584 0, 12, 0, st_tlv),
585 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
586 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
587
588 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
589 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
590
591 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
592 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
593
594 SOC_ENUM("ADC OSR", adc_osr),
595 SOC_ENUM("DAC OSR", dac_osr),
596
597 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
598 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
599 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
600 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
601
602 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
603 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
604 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
605 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
606
607 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
608 6, 1, 1, wm_hubs_spkmix_tlv),
609 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
610 2, 1, 1, wm_hubs_spkmix_tlv),
611
612 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
613 6, 1, 1, wm_hubs_spkmix_tlv),
614 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
615 2, 1, 1, wm_hubs_spkmix_tlv),
616
617 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
618 10, 15, 0, wm8994_3d_tlv),
619 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
620 8, 1, 0),
621 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
622 10, 15, 0, wm8994_3d_tlv),
623 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
624 8, 1, 0),
625 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
626 10, 15, 0, wm8994_3d_tlv),
627 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
628 8, 1, 0),
629 };
630
631 /* Controls not available on WM1811 */
632 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
633 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
634 WM8994_AIF1_ADC2_RIGHT_VOLUME,
635 1, 119, 0, digital_tlv),
636 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
637 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
638
639 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
640
641 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
642 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
643 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
644
645 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
646 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
647 };
648
649 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
650 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
651 eq_tlv),
652 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
653 eq_tlv),
654 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
655 eq_tlv),
656 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
657 eq_tlv),
658 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
659 eq_tlv),
660
661 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
662 eq_tlv),
663 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
664 eq_tlv),
665 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
666 eq_tlv),
667 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
668 eq_tlv),
669 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
670 eq_tlv),
671
672 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
673 eq_tlv),
674 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
675 eq_tlv),
676 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
677 eq_tlv),
678 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
679 eq_tlv),
680 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
681 eq_tlv),
682 };
683
684 static const struct snd_kcontrol_new wm8994_drc_controls[] = {
685 SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
686 WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
687 WM8994_AIF1ADC1R_DRC_ENA),
688 SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
689 WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
690 WM8994_AIF1ADC2R_DRC_ENA),
691 SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
692 WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
693 WM8994_AIF2ADCR_DRC_ENA),
694 };
695
696 static const char *wm8958_ng_text[] = {
697 "30ms", "125ms", "250ms", "500ms",
698 };
699
700 static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac1_ng_hold,
701 WM8958_AIF1_DAC1_NOISE_GATE,
702 WM8958_AIF1DAC1_NG_THR_SHIFT,
703 wm8958_ng_text);
704
705 static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac2_ng_hold,
706 WM8958_AIF1_DAC2_NOISE_GATE,
707 WM8958_AIF1DAC2_NG_THR_SHIFT,
708 wm8958_ng_text);
709
710 static SOC_ENUM_SINGLE_DECL(wm8958_aif2dac_ng_hold,
711 WM8958_AIF2_DAC_NOISE_GATE,
712 WM8958_AIF2DAC_NG_THR_SHIFT,
713 wm8958_ng_text);
714
715 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
716 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
717
718 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
719 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
720 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
721 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
722 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
723 7, 1, ng_tlv),
724
725 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
726 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
727 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
728 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
729 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
730 7, 1, ng_tlv),
731
732 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
733 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
734 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
735 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
736 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
737 7, 1, ng_tlv),
738 };
739
740 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
741 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
742 mixin_boost_tlv),
743 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
744 mixin_boost_tlv),
745 };
746
747 /* We run all mode setting through a function to enforce audio mode */
wm1811_jackdet_set_mode(struct snd_soc_component * component,u16 mode)748 static void wm1811_jackdet_set_mode(struct snd_soc_component *component, u16 mode)
749 {
750 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
751
752 if (!wm8994->jackdet || !wm8994->micdet[0].jack)
753 return;
754
755 if (wm8994->active_refcount)
756 mode = WM1811_JACKDET_MODE_AUDIO;
757
758 if (mode == wm8994->jackdet_mode)
759 return;
760
761 wm8994->jackdet_mode = mode;
762
763 /* Always use audio mode to detect while the system is active */
764 if (mode != WM1811_JACKDET_MODE_NONE)
765 mode = WM1811_JACKDET_MODE_AUDIO;
766
767 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
768 WM1811_JACKDET_MODE_MASK, mode);
769 }
770
active_reference(struct snd_soc_component * component)771 static void active_reference(struct snd_soc_component *component)
772 {
773 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
774
775 mutex_lock(&wm8994->accdet_lock);
776
777 wm8994->active_refcount++;
778
779 dev_dbg(component->dev, "Active refcount incremented, now %d\n",
780 wm8994->active_refcount);
781
782 /* If we're using jack detection go into audio mode */
783 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_AUDIO);
784
785 mutex_unlock(&wm8994->accdet_lock);
786 }
787
active_dereference(struct snd_soc_component * component)788 static void active_dereference(struct snd_soc_component *component)
789 {
790 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
791 u16 mode;
792
793 mutex_lock(&wm8994->accdet_lock);
794
795 wm8994->active_refcount--;
796
797 dev_dbg(component->dev, "Active refcount decremented, now %d\n",
798 wm8994->active_refcount);
799
800 if (wm8994->active_refcount == 0) {
801 /* Go into appropriate detection only mode */
802 if (wm8994->jack_mic || wm8994->mic_detecting)
803 mode = WM1811_JACKDET_MODE_MIC;
804 else
805 mode = WM1811_JACKDET_MODE_JACK;
806
807 wm1811_jackdet_set_mode(component, mode);
808 }
809
810 mutex_unlock(&wm8994->accdet_lock);
811 }
812
clk_sys_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)813 static int clk_sys_event(struct snd_soc_dapm_widget *w,
814 struct snd_kcontrol *kcontrol, int event)
815 {
816 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
817 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
818
819 switch (event) {
820 case SND_SOC_DAPM_PRE_PMU:
821 return configure_clock(component);
822
823 case SND_SOC_DAPM_POST_PMU:
824 /*
825 * JACKDET won't run until we start the clock and it
826 * only reports deltas, make sure we notify the state
827 * up the stack on startup. Use a *very* generous
828 * timeout for paranoia, there's no urgency and we
829 * don't want false reports.
830 */
831 if (wm8994->jackdet && !wm8994->clk_has_run) {
832 queue_delayed_work(system_power_efficient_wq,
833 &wm8994->jackdet_bootstrap,
834 msecs_to_jiffies(1000));
835 wm8994->clk_has_run = true;
836 }
837 break;
838
839 case SND_SOC_DAPM_POST_PMD:
840 configure_clock(component);
841 break;
842 }
843
844 return 0;
845 }
846
vmid_reference(struct snd_soc_component * component)847 static void vmid_reference(struct snd_soc_component *component)
848 {
849 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
850
851 pm_runtime_get_sync(component->dev);
852
853 wm8994->vmid_refcount++;
854
855 dev_dbg(component->dev, "Referencing VMID, refcount is now %d\n",
856 wm8994->vmid_refcount);
857
858 if (wm8994->vmid_refcount == 1) {
859 snd_soc_component_update_bits(component, WM8994_ANTIPOP_1,
860 WM8994_LINEOUT1_DISCH |
861 WM8994_LINEOUT2_DISCH, 0);
862
863 wm_hubs_vmid_ena(component);
864
865 switch (wm8994->vmid_mode) {
866 default:
867 WARN_ON(NULL == "Invalid VMID mode");
868 /* fall through */
869 case WM8994_VMID_NORMAL:
870 /* Startup bias, VMID ramp & buffer */
871 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
872 WM8994_BIAS_SRC |
873 WM8994_VMID_DISCH |
874 WM8994_STARTUP_BIAS_ENA |
875 WM8994_VMID_BUF_ENA |
876 WM8994_VMID_RAMP_MASK,
877 WM8994_BIAS_SRC |
878 WM8994_STARTUP_BIAS_ENA |
879 WM8994_VMID_BUF_ENA |
880 (0x2 << WM8994_VMID_RAMP_SHIFT));
881
882 /* Main bias enable, VMID=2x40k */
883 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1,
884 WM8994_BIAS_ENA |
885 WM8994_VMID_SEL_MASK,
886 WM8994_BIAS_ENA | 0x2);
887
888 msleep(300);
889
890 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
891 WM8994_VMID_RAMP_MASK |
892 WM8994_BIAS_SRC,
893 0);
894 break;
895
896 case WM8994_VMID_FORCE:
897 /* Startup bias, slow VMID ramp & buffer */
898 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
899 WM8994_BIAS_SRC |
900 WM8994_VMID_DISCH |
901 WM8994_STARTUP_BIAS_ENA |
902 WM8994_VMID_BUF_ENA |
903 WM8994_VMID_RAMP_MASK,
904 WM8994_BIAS_SRC |
905 WM8994_STARTUP_BIAS_ENA |
906 WM8994_VMID_BUF_ENA |
907 (0x2 << WM8994_VMID_RAMP_SHIFT));
908
909 /* Main bias enable, VMID=2x40k */
910 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1,
911 WM8994_BIAS_ENA |
912 WM8994_VMID_SEL_MASK,
913 WM8994_BIAS_ENA | 0x2);
914
915 msleep(400);
916
917 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
918 WM8994_VMID_RAMP_MASK |
919 WM8994_BIAS_SRC,
920 0);
921 break;
922 }
923 }
924 }
925
vmid_dereference(struct snd_soc_component * component)926 static void vmid_dereference(struct snd_soc_component *component)
927 {
928 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
929
930 wm8994->vmid_refcount--;
931
932 dev_dbg(component->dev, "Dereferencing VMID, refcount is now %d\n",
933 wm8994->vmid_refcount);
934
935 if (wm8994->vmid_refcount == 0) {
936 if (wm8994->hubs.lineout1_se)
937 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_3,
938 WM8994_LINEOUT1N_ENA |
939 WM8994_LINEOUT1P_ENA,
940 WM8994_LINEOUT1N_ENA |
941 WM8994_LINEOUT1P_ENA);
942
943 if (wm8994->hubs.lineout2_se)
944 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_3,
945 WM8994_LINEOUT2N_ENA |
946 WM8994_LINEOUT2P_ENA,
947 WM8994_LINEOUT2N_ENA |
948 WM8994_LINEOUT2P_ENA);
949
950 /* Start discharging VMID */
951 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
952 WM8994_BIAS_SRC |
953 WM8994_VMID_DISCH,
954 WM8994_BIAS_SRC |
955 WM8994_VMID_DISCH);
956
957 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1,
958 WM8994_VMID_SEL_MASK, 0);
959
960 msleep(400);
961
962 /* Active discharge */
963 snd_soc_component_update_bits(component, WM8994_ANTIPOP_1,
964 WM8994_LINEOUT1_DISCH |
965 WM8994_LINEOUT2_DISCH,
966 WM8994_LINEOUT1_DISCH |
967 WM8994_LINEOUT2_DISCH);
968
969 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_3,
970 WM8994_LINEOUT1N_ENA |
971 WM8994_LINEOUT1P_ENA |
972 WM8994_LINEOUT2N_ENA |
973 WM8994_LINEOUT2P_ENA, 0);
974
975 /* Switch off startup biases */
976 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
977 WM8994_BIAS_SRC |
978 WM8994_STARTUP_BIAS_ENA |
979 WM8994_VMID_BUF_ENA |
980 WM8994_VMID_RAMP_MASK, 0);
981
982 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1,
983 WM8994_VMID_SEL_MASK, 0);
984 }
985
986 pm_runtime_put(component->dev);
987 }
988
vmid_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)989 static int vmid_event(struct snd_soc_dapm_widget *w,
990 struct snd_kcontrol *kcontrol, int event)
991 {
992 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
993
994 switch (event) {
995 case SND_SOC_DAPM_PRE_PMU:
996 vmid_reference(component);
997 break;
998
999 case SND_SOC_DAPM_POST_PMD:
1000 vmid_dereference(component);
1001 break;
1002 }
1003
1004 return 0;
1005 }
1006
wm8994_check_class_w_digital(struct snd_soc_component * component)1007 static bool wm8994_check_class_w_digital(struct snd_soc_component *component)
1008 {
1009 int source = 0; /* GCC flow analysis can't track enable */
1010 int reg, reg_r;
1011
1012 /* We also need the same AIF source for L/R and only one path */
1013 reg = snd_soc_component_read32(component, WM8994_DAC1_LEFT_MIXER_ROUTING);
1014 switch (reg) {
1015 case WM8994_AIF2DACL_TO_DAC1L:
1016 dev_vdbg(component->dev, "Class W source AIF2DAC\n");
1017 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1018 break;
1019 case WM8994_AIF1DAC2L_TO_DAC1L:
1020 dev_vdbg(component->dev, "Class W source AIF1DAC2\n");
1021 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1022 break;
1023 case WM8994_AIF1DAC1L_TO_DAC1L:
1024 dev_vdbg(component->dev, "Class W source AIF1DAC1\n");
1025 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1026 break;
1027 default:
1028 dev_vdbg(component->dev, "DAC mixer setting: %x\n", reg);
1029 return false;
1030 }
1031
1032 reg_r = snd_soc_component_read32(component, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1033 if (reg_r != reg) {
1034 dev_vdbg(component->dev, "Left and right DAC mixers different\n");
1035 return false;
1036 }
1037
1038 /* Set the source up */
1039 snd_soc_component_update_bits(component, WM8994_CLASS_W_1,
1040 WM8994_CP_DYN_SRC_SEL_MASK, source);
1041
1042 return true;
1043 }
1044
aif1clk_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1045 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1046 struct snd_kcontrol *kcontrol, int event)
1047 {
1048 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1049 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
1050 struct wm8994 *control = wm8994->wm8994;
1051 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
1052 int i;
1053 int dac;
1054 int adc;
1055 int val;
1056
1057 switch (control->type) {
1058 case WM8994:
1059 case WM8958:
1060 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1061 break;
1062 default:
1063 break;
1064 }
1065
1066 switch (event) {
1067 case SND_SOC_DAPM_PRE_PMU:
1068 /* Don't enable timeslot 2 if not in use */
1069 if (wm8994->channels[0] <= 2)
1070 mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
1071
1072 val = snd_soc_component_read32(component, WM8994_AIF1_CONTROL_1);
1073 if ((val & WM8994_AIF1ADCL_SRC) &&
1074 (val & WM8994_AIF1ADCR_SRC))
1075 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1076 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1077 !(val & WM8994_AIF1ADCR_SRC))
1078 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1079 else
1080 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1081 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1082
1083 val = snd_soc_component_read32(component, WM8994_AIF1_CONTROL_2);
1084 if ((val & WM8994_AIF1DACL_SRC) &&
1085 (val & WM8994_AIF1DACR_SRC))
1086 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1087 else if (!(val & WM8994_AIF1DACL_SRC) &&
1088 !(val & WM8994_AIF1DACR_SRC))
1089 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1090 else
1091 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1092 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1093
1094 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
1095 mask, adc);
1096 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
1097 mask, dac);
1098 snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
1099 WM8994_AIF1DSPCLK_ENA |
1100 WM8994_SYSDSPCLK_ENA,
1101 WM8994_AIF1DSPCLK_ENA |
1102 WM8994_SYSDSPCLK_ENA);
1103 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4, mask,
1104 WM8994_AIF1ADC1R_ENA |
1105 WM8994_AIF1ADC1L_ENA |
1106 WM8994_AIF1ADC2R_ENA |
1107 WM8994_AIF1ADC2L_ENA);
1108 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5, mask,
1109 WM8994_AIF1DAC1R_ENA |
1110 WM8994_AIF1DAC1L_ENA |
1111 WM8994_AIF1DAC2R_ENA |
1112 WM8994_AIF1DAC2L_ENA);
1113 break;
1114
1115 case SND_SOC_DAPM_POST_PMU:
1116 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1117 snd_soc_component_write(component, wm8994_vu_bits[i].reg,
1118 snd_soc_component_read32(component,
1119 wm8994_vu_bits[i].reg));
1120 break;
1121
1122 case SND_SOC_DAPM_PRE_PMD:
1123 case SND_SOC_DAPM_POST_PMD:
1124 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
1125 mask, 0);
1126 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
1127 mask, 0);
1128
1129 val = snd_soc_component_read32(component, WM8994_CLOCKING_1);
1130 if (val & WM8994_AIF2DSPCLK_ENA)
1131 val = WM8994_SYSDSPCLK_ENA;
1132 else
1133 val = 0;
1134 snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
1135 WM8994_SYSDSPCLK_ENA |
1136 WM8994_AIF1DSPCLK_ENA, val);
1137 break;
1138 }
1139
1140 return 0;
1141 }
1142
aif2clk_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1143 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1144 struct snd_kcontrol *kcontrol, int event)
1145 {
1146 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1147 int i;
1148 int dac;
1149 int adc;
1150 int val;
1151
1152 switch (event) {
1153 case SND_SOC_DAPM_PRE_PMU:
1154 val = snd_soc_component_read32(component, WM8994_AIF2_CONTROL_1);
1155 if ((val & WM8994_AIF2ADCL_SRC) &&
1156 (val & WM8994_AIF2ADCR_SRC))
1157 adc = WM8994_AIF2ADCR_ENA;
1158 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1159 !(val & WM8994_AIF2ADCR_SRC))
1160 adc = WM8994_AIF2ADCL_ENA;
1161 else
1162 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1163
1164
1165 val = snd_soc_component_read32(component, WM8994_AIF2_CONTROL_2);
1166 if ((val & WM8994_AIF2DACL_SRC) &&
1167 (val & WM8994_AIF2DACR_SRC))
1168 dac = WM8994_AIF2DACR_ENA;
1169 else if (!(val & WM8994_AIF2DACL_SRC) &&
1170 !(val & WM8994_AIF2DACR_SRC))
1171 dac = WM8994_AIF2DACL_ENA;
1172 else
1173 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1174
1175 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
1176 WM8994_AIF2ADCL_ENA |
1177 WM8994_AIF2ADCR_ENA, adc);
1178 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
1179 WM8994_AIF2DACL_ENA |
1180 WM8994_AIF2DACR_ENA, dac);
1181 snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
1182 WM8994_AIF2DSPCLK_ENA |
1183 WM8994_SYSDSPCLK_ENA,
1184 WM8994_AIF2DSPCLK_ENA |
1185 WM8994_SYSDSPCLK_ENA);
1186 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
1187 WM8994_AIF2ADCL_ENA |
1188 WM8994_AIF2ADCR_ENA,
1189 WM8994_AIF2ADCL_ENA |
1190 WM8994_AIF2ADCR_ENA);
1191 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
1192 WM8994_AIF2DACL_ENA |
1193 WM8994_AIF2DACR_ENA,
1194 WM8994_AIF2DACL_ENA |
1195 WM8994_AIF2DACR_ENA);
1196 break;
1197
1198 case SND_SOC_DAPM_POST_PMU:
1199 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1200 snd_soc_component_write(component, wm8994_vu_bits[i].reg,
1201 snd_soc_component_read32(component,
1202 wm8994_vu_bits[i].reg));
1203 break;
1204
1205 case SND_SOC_DAPM_PRE_PMD:
1206 case SND_SOC_DAPM_POST_PMD:
1207 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
1208 WM8994_AIF2DACL_ENA |
1209 WM8994_AIF2DACR_ENA, 0);
1210 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
1211 WM8994_AIF2ADCL_ENA |
1212 WM8994_AIF2ADCR_ENA, 0);
1213
1214 val = snd_soc_component_read32(component, WM8994_CLOCKING_1);
1215 if (val & WM8994_AIF1DSPCLK_ENA)
1216 val = WM8994_SYSDSPCLK_ENA;
1217 else
1218 val = 0;
1219 snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
1220 WM8994_SYSDSPCLK_ENA |
1221 WM8994_AIF2DSPCLK_ENA, val);
1222 break;
1223 }
1224
1225 return 0;
1226 }
1227
aif1clk_late_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1228 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1229 struct snd_kcontrol *kcontrol, int event)
1230 {
1231 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1232 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
1233
1234 switch (event) {
1235 case SND_SOC_DAPM_PRE_PMU:
1236 wm8994->aif1clk_enable = 1;
1237 break;
1238 case SND_SOC_DAPM_POST_PMD:
1239 wm8994->aif1clk_disable = 1;
1240 break;
1241 }
1242
1243 return 0;
1244 }
1245
aif2clk_late_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1246 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1247 struct snd_kcontrol *kcontrol, int event)
1248 {
1249 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1250 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
1251
1252 switch (event) {
1253 case SND_SOC_DAPM_PRE_PMU:
1254 wm8994->aif2clk_enable = 1;
1255 break;
1256 case SND_SOC_DAPM_POST_PMD:
1257 wm8994->aif2clk_disable = 1;
1258 break;
1259 }
1260
1261 return 0;
1262 }
1263
late_enable_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1264 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1265 struct snd_kcontrol *kcontrol, int event)
1266 {
1267 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1268 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
1269
1270 switch (event) {
1271 case SND_SOC_DAPM_PRE_PMU:
1272 if (wm8994->aif1clk_enable) {
1273 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1274 snd_soc_component_update_bits(component, WM8994_AIF1_CLOCKING_1,
1275 WM8994_AIF1CLK_ENA_MASK,
1276 WM8994_AIF1CLK_ENA);
1277 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1278 wm8994->aif1clk_enable = 0;
1279 }
1280 if (wm8994->aif2clk_enable) {
1281 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1282 snd_soc_component_update_bits(component, WM8994_AIF2_CLOCKING_1,
1283 WM8994_AIF2CLK_ENA_MASK,
1284 WM8994_AIF2CLK_ENA);
1285 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1286 wm8994->aif2clk_enable = 0;
1287 }
1288 break;
1289 }
1290
1291 /* We may also have postponed startup of DSP, handle that. */
1292 wm8958_aif_ev(w, kcontrol, event);
1293
1294 return 0;
1295 }
1296
late_disable_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1297 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1298 struct snd_kcontrol *kcontrol, int event)
1299 {
1300 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1301 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
1302
1303 switch (event) {
1304 case SND_SOC_DAPM_POST_PMD:
1305 if (wm8994->aif1clk_disable) {
1306 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1307 snd_soc_component_update_bits(component, WM8994_AIF1_CLOCKING_1,
1308 WM8994_AIF1CLK_ENA_MASK, 0);
1309 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1310 wm8994->aif1clk_disable = 0;
1311 }
1312 if (wm8994->aif2clk_disable) {
1313 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1314 snd_soc_component_update_bits(component, WM8994_AIF2_CLOCKING_1,
1315 WM8994_AIF2CLK_ENA_MASK, 0);
1316 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1317 wm8994->aif2clk_disable = 0;
1318 }
1319 break;
1320 }
1321
1322 return 0;
1323 }
1324
adc_mux_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1325 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1326 struct snd_kcontrol *kcontrol, int event)
1327 {
1328 late_enable_ev(w, kcontrol, event);
1329 return 0;
1330 }
1331
micbias_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1332 static int micbias_ev(struct snd_soc_dapm_widget *w,
1333 struct snd_kcontrol *kcontrol, int event)
1334 {
1335 late_enable_ev(w, kcontrol, event);
1336 return 0;
1337 }
1338
dac_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1339 static int dac_ev(struct snd_soc_dapm_widget *w,
1340 struct snd_kcontrol *kcontrol, int event)
1341 {
1342 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1343 unsigned int mask = 1 << w->shift;
1344
1345 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
1346 mask, mask);
1347 return 0;
1348 }
1349
1350 static const char *adc_mux_text[] = {
1351 "ADC",
1352 "DMIC",
1353 };
1354
1355 static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text);
1356
1357 static const struct snd_kcontrol_new adcl_mux =
1358 SOC_DAPM_ENUM("ADCL Mux", adc_enum);
1359
1360 static const struct snd_kcontrol_new adcr_mux =
1361 SOC_DAPM_ENUM("ADCR Mux", adc_enum);
1362
1363 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1364 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1365 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1366 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1367 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1368 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1369 };
1370
1371 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1372 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1373 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1374 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1375 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1376 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1377 };
1378
1379 /* Debugging; dump chip status after DAPM transitions */
post_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1380 static int post_ev(struct snd_soc_dapm_widget *w,
1381 struct snd_kcontrol *kcontrol, int event)
1382 {
1383 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1384 dev_dbg(component->dev, "SRC status: %x\n",
1385 snd_soc_component_read32(component,
1386 WM8994_RATE_STATUS));
1387 return 0;
1388 }
1389
1390 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1391 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1392 1, 1, 0),
1393 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1394 0, 1, 0),
1395 };
1396
1397 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1398 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1399 1, 1, 0),
1400 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1401 0, 1, 0),
1402 };
1403
1404 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1405 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1406 1, 1, 0),
1407 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1408 0, 1, 0),
1409 };
1410
1411 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1412 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1413 1, 1, 0),
1414 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1415 0, 1, 0),
1416 };
1417
1418 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1419 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1420 5, 1, 0),
1421 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1422 4, 1, 0),
1423 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1424 2, 1, 0),
1425 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1426 1, 1, 0),
1427 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1428 0, 1, 0),
1429 };
1430
1431 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1432 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1433 5, 1, 0),
1434 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1435 4, 1, 0),
1436 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1437 2, 1, 0),
1438 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1439 1, 1, 0),
1440 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1441 0, 1, 0),
1442 };
1443
1444 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1445 SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
1446 snd_soc_dapm_get_volsw, wm8994_put_class_w)
1447
wm8994_put_class_w(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1448 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1449 struct snd_ctl_elem_value *ucontrol)
1450 {
1451 struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
1452 int ret;
1453
1454 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1455
1456 wm_hubs_update_class_w(component);
1457
1458 return ret;
1459 }
1460
1461 static const struct snd_kcontrol_new dac1l_mix[] = {
1462 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1463 5, 1, 0),
1464 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1465 4, 1, 0),
1466 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1467 2, 1, 0),
1468 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1469 1, 1, 0),
1470 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1471 0, 1, 0),
1472 };
1473
1474 static const struct snd_kcontrol_new dac1r_mix[] = {
1475 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1476 5, 1, 0),
1477 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1478 4, 1, 0),
1479 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1480 2, 1, 0),
1481 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1482 1, 1, 0),
1483 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1484 0, 1, 0),
1485 };
1486
1487 static const char *sidetone_text[] = {
1488 "ADC/DMIC1", "DMIC2",
1489 };
1490
1491 static SOC_ENUM_SINGLE_DECL(sidetone1_enum,
1492 WM8994_SIDETONE, 0, sidetone_text);
1493
1494 static const struct snd_kcontrol_new sidetone1_mux =
1495 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1496
1497 static SOC_ENUM_SINGLE_DECL(sidetone2_enum,
1498 WM8994_SIDETONE, 1, sidetone_text);
1499
1500 static const struct snd_kcontrol_new sidetone2_mux =
1501 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1502
1503 static const char *aif1dac_text[] = {
1504 "AIF1DACDAT", "AIF3DACDAT",
1505 };
1506
1507 static const char *loopback_text[] = {
1508 "None", "ADCDAT",
1509 };
1510
1511 static SOC_ENUM_SINGLE_DECL(aif1_loopback_enum,
1512 WM8994_AIF1_CONTROL_2,
1513 WM8994_AIF1_LOOPBACK_SHIFT,
1514 loopback_text);
1515
1516 static const struct snd_kcontrol_new aif1_loopback =
1517 SOC_DAPM_ENUM("AIF1 Loopback", aif1_loopback_enum);
1518
1519 static SOC_ENUM_SINGLE_DECL(aif2_loopback_enum,
1520 WM8994_AIF2_CONTROL_2,
1521 WM8994_AIF2_LOOPBACK_SHIFT,
1522 loopback_text);
1523
1524 static const struct snd_kcontrol_new aif2_loopback =
1525 SOC_DAPM_ENUM("AIF2 Loopback", aif2_loopback_enum);
1526
1527 static SOC_ENUM_SINGLE_DECL(aif1dac_enum,
1528 WM8994_POWER_MANAGEMENT_6, 0, aif1dac_text);
1529
1530 static const struct snd_kcontrol_new aif1dac_mux =
1531 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1532
1533 static const char *aif2dac_text[] = {
1534 "AIF2DACDAT", "AIF3DACDAT",
1535 };
1536
1537 static SOC_ENUM_SINGLE_DECL(aif2dac_enum,
1538 WM8994_POWER_MANAGEMENT_6, 1, aif2dac_text);
1539
1540 static const struct snd_kcontrol_new aif2dac_mux =
1541 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1542
1543 static const char *aif2adc_text[] = {
1544 "AIF2ADCDAT", "AIF3DACDAT",
1545 };
1546
1547 static SOC_ENUM_SINGLE_DECL(aif2adc_enum,
1548 WM8994_POWER_MANAGEMENT_6, 2, aif2adc_text);
1549
1550 static const struct snd_kcontrol_new aif2adc_mux =
1551 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1552
1553 static const char *aif3adc_text[] = {
1554 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1555 };
1556
1557 static SOC_ENUM_SINGLE_DECL(wm8994_aif3adc_enum,
1558 WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text);
1559
1560 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1561 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1562
1563 static SOC_ENUM_SINGLE_DECL(wm8958_aif3adc_enum,
1564 WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text);
1565
1566 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1567 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1568
1569 static const char *mono_pcm_out_text[] = {
1570 "None", "AIF2ADCL", "AIF2ADCR",
1571 };
1572
1573 static SOC_ENUM_SINGLE_DECL(mono_pcm_out_enum,
1574 WM8994_POWER_MANAGEMENT_6, 9, mono_pcm_out_text);
1575
1576 static const struct snd_kcontrol_new mono_pcm_out_mux =
1577 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1578
1579 static const char *aif2dac_src_text[] = {
1580 "AIF2", "AIF3",
1581 };
1582
1583 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1584 static SOC_ENUM_SINGLE_DECL(aif2dacl_src_enum,
1585 WM8994_POWER_MANAGEMENT_6, 7, aif2dac_src_text);
1586
1587 static const struct snd_kcontrol_new aif2dacl_src_mux =
1588 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1589
1590 static SOC_ENUM_SINGLE_DECL(aif2dacr_src_enum,
1591 WM8994_POWER_MANAGEMENT_6, 8, aif2dac_src_text);
1592
1593 static const struct snd_kcontrol_new aif2dacr_src_mux =
1594 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1595
1596 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1597 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
1598 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1599 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
1600 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1601
1602 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1603 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1604 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1605 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1606 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1607 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1608 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1609 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1610 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1611 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1612
1613 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1614 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1615 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1616 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1617 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1618 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1619 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
1620 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1621 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
1622 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1623
1624 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1625 };
1626
1627 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1628 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
1629 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1630 SND_SOC_DAPM_PRE_PMD),
1631 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
1632 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1633 SND_SOC_DAPM_PRE_PMD),
1634 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1635 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1636 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1637 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1638 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1639 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1640 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
1641 };
1642
1643 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1644 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1645 dac_ev, SND_SOC_DAPM_PRE_PMU),
1646 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1647 dac_ev, SND_SOC_DAPM_PRE_PMU),
1648 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1649 dac_ev, SND_SOC_DAPM_PRE_PMU),
1650 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1651 dac_ev, SND_SOC_DAPM_PRE_PMU),
1652 };
1653
1654 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1655 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1656 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1657 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1658 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1659 };
1660
1661 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1662 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1663 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1664 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1665 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1666 };
1667
1668 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1669 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1670 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1671 };
1672
1673 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1674 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1675 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1676 SND_SOC_DAPM_INPUT("Clock"),
1677
1678 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1679 SND_SOC_DAPM_PRE_PMU),
1680 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1681 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1682
1683 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1684 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1685 SND_SOC_DAPM_PRE_PMD),
1686
1687 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1688 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1689 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
1690
1691 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1692 0, SND_SOC_NOPM, 9, 0),
1693 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1694 0, SND_SOC_NOPM, 8, 0),
1695 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1696 SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
1697 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1698 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1699 SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
1700 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1701
1702 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1703 0, SND_SOC_NOPM, 11, 0),
1704 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1705 0, SND_SOC_NOPM, 10, 0),
1706 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1707 SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
1708 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1709 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1710 SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
1711 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1712
1713 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1714 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1715 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1716 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1717
1718 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1719 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1720 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1721 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1722
1723 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1724 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1725 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1726 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1727
1728 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1729 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1730
1731 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1732 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1733 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1734 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1735
1736 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1737 SND_SOC_NOPM, 13, 0),
1738 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1739 SND_SOC_NOPM, 12, 0),
1740 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1741 SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
1742 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1743 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1744 SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
1745 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1746
1747 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1748 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1749 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1750 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1751
1752 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1753 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1754 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1755
1756 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1757 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1758
1759 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1760
1761 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1762 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1763 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1764 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1765
1766 /* Power is done with the muxes since the ADC power also controls the
1767 * downsampling chain, the chip will automatically manage the analogue
1768 * specific portions.
1769 */
1770 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1771 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1772
1773 SND_SOC_DAPM_MUX("AIF1 Loopback", SND_SOC_NOPM, 0, 0, &aif1_loopback),
1774 SND_SOC_DAPM_MUX("AIF2 Loopback", SND_SOC_NOPM, 0, 0, &aif2_loopback),
1775
1776 SND_SOC_DAPM_POST("Debug log", post_ev),
1777 };
1778
1779 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1780 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1781 };
1782
1783 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1784 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
1785 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1786 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1787 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1788 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1789 };
1790
1791 static const struct snd_soc_dapm_route intercon[] = {
1792 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1793 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1794
1795 { "DSP1CLK", NULL, "CLK_SYS" },
1796 { "DSP2CLK", NULL, "CLK_SYS" },
1797 { "DSPINTCLK", NULL, "CLK_SYS" },
1798
1799 { "AIF1ADC1L", NULL, "AIF1CLK" },
1800 { "AIF1ADC1L", NULL, "DSP1CLK" },
1801 { "AIF1ADC1R", NULL, "AIF1CLK" },
1802 { "AIF1ADC1R", NULL, "DSP1CLK" },
1803 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1804
1805 { "AIF1DAC1L", NULL, "AIF1CLK" },
1806 { "AIF1DAC1L", NULL, "DSP1CLK" },
1807 { "AIF1DAC1R", NULL, "AIF1CLK" },
1808 { "AIF1DAC1R", NULL, "DSP1CLK" },
1809 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1810
1811 { "AIF1ADC2L", NULL, "AIF1CLK" },
1812 { "AIF1ADC2L", NULL, "DSP1CLK" },
1813 { "AIF1ADC2R", NULL, "AIF1CLK" },
1814 { "AIF1ADC2R", NULL, "DSP1CLK" },
1815 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1816
1817 { "AIF1DAC2L", NULL, "AIF1CLK" },
1818 { "AIF1DAC2L", NULL, "DSP1CLK" },
1819 { "AIF1DAC2R", NULL, "AIF1CLK" },
1820 { "AIF1DAC2R", NULL, "DSP1CLK" },
1821 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1822
1823 { "AIF2ADCL", NULL, "AIF2CLK" },
1824 { "AIF2ADCL", NULL, "DSP2CLK" },
1825 { "AIF2ADCR", NULL, "AIF2CLK" },
1826 { "AIF2ADCR", NULL, "DSP2CLK" },
1827 { "AIF2ADCR", NULL, "DSPINTCLK" },
1828
1829 { "AIF2DACL", NULL, "AIF2CLK" },
1830 { "AIF2DACL", NULL, "DSP2CLK" },
1831 { "AIF2DACR", NULL, "AIF2CLK" },
1832 { "AIF2DACR", NULL, "DSP2CLK" },
1833 { "AIF2DACR", NULL, "DSPINTCLK" },
1834
1835 { "DMIC1L", NULL, "DMIC1DAT" },
1836 { "DMIC1L", NULL, "CLK_SYS" },
1837 { "DMIC1R", NULL, "DMIC1DAT" },
1838 { "DMIC1R", NULL, "CLK_SYS" },
1839 { "DMIC2L", NULL, "DMIC2DAT" },
1840 { "DMIC2L", NULL, "CLK_SYS" },
1841 { "DMIC2R", NULL, "DMIC2DAT" },
1842 { "DMIC2R", NULL, "CLK_SYS" },
1843
1844 { "ADCL", NULL, "AIF1CLK" },
1845 { "ADCL", NULL, "DSP1CLK" },
1846 { "ADCL", NULL, "DSPINTCLK" },
1847
1848 { "ADCR", NULL, "AIF1CLK" },
1849 { "ADCR", NULL, "DSP1CLK" },
1850 { "ADCR", NULL, "DSPINTCLK" },
1851
1852 { "ADCL Mux", "ADC", "ADCL" },
1853 { "ADCL Mux", "DMIC", "DMIC1L" },
1854 { "ADCR Mux", "ADC", "ADCR" },
1855 { "ADCR Mux", "DMIC", "DMIC1R" },
1856
1857 { "DAC1L", NULL, "AIF1CLK" },
1858 { "DAC1L", NULL, "DSP1CLK" },
1859 { "DAC1L", NULL, "DSPINTCLK" },
1860
1861 { "DAC1R", NULL, "AIF1CLK" },
1862 { "DAC1R", NULL, "DSP1CLK" },
1863 { "DAC1R", NULL, "DSPINTCLK" },
1864
1865 { "DAC2L", NULL, "AIF2CLK" },
1866 { "DAC2L", NULL, "DSP2CLK" },
1867 { "DAC2L", NULL, "DSPINTCLK" },
1868
1869 { "DAC2R", NULL, "AIF2DACR" },
1870 { "DAC2R", NULL, "AIF2CLK" },
1871 { "DAC2R", NULL, "DSP2CLK" },
1872 { "DAC2R", NULL, "DSPINTCLK" },
1873
1874 { "TOCLK", NULL, "CLK_SYS" },
1875
1876 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1877 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1878 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1879
1880 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1881 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1882 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1883
1884 /* AIF1 outputs */
1885 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1886 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1887 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1888
1889 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1890 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1891 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1892
1893 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1894 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1895 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1896
1897 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1898 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1899 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1900
1901 /* Pin level routing for AIF3 */
1902 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1903 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1904 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1905 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1906
1907 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1 Loopback" },
1908 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1909 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2 Loopback" },
1910 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1911 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1912 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1913 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1914
1915 /* DAC1 inputs */
1916 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1917 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1918 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1919 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1920 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1921
1922 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1923 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1924 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1925 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1926 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1927
1928 /* DAC2/AIF2 outputs */
1929 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1930 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1931 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1932 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1933 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1934 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1935
1936 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1937 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1938 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1939 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1940 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1941 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1942
1943 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1944 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1945 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1946 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1947
1948 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1949
1950 /* AIF3 output */
1951 { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC1L" },
1952 { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC1R" },
1953 { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC2L" },
1954 { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC2R" },
1955 { "AIF3ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1956 { "AIF3ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1957 { "AIF3ADC Mux", "AIF2DACDAT", "AIF2DACL" },
1958 { "AIF3ADC Mux", "AIF2DACDAT", "AIF2DACR" },
1959
1960 { "AIF3ADCDAT", NULL, "AIF3ADC Mux" },
1961
1962 /* Loopback */
1963 { "AIF1 Loopback", "ADCDAT", "AIF1ADCDAT" },
1964 { "AIF1 Loopback", "None", "AIF1DACDAT" },
1965 { "AIF2 Loopback", "ADCDAT", "AIF2ADCDAT" },
1966 { "AIF2 Loopback", "None", "AIF2DACDAT" },
1967
1968 /* Sidetone */
1969 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1970 { "Left Sidetone", "DMIC2", "DMIC2L" },
1971 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1972 { "Right Sidetone", "DMIC2", "DMIC2R" },
1973
1974 /* Output stages */
1975 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1976 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1977
1978 { "SPKL", "DAC1 Switch", "DAC1L" },
1979 { "SPKL", "DAC2 Switch", "DAC2L" },
1980
1981 { "SPKR", "DAC1 Switch", "DAC1R" },
1982 { "SPKR", "DAC2 Switch", "DAC2R" },
1983
1984 { "Left Headphone Mux", "DAC", "DAC1L" },
1985 { "Right Headphone Mux", "DAC", "DAC1R" },
1986 };
1987
1988 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1989 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1990 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1991 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1992 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1993 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1994 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1995 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1996 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1997 };
1998
1999 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
2000 { "DAC1L", NULL, "DAC1L Mixer" },
2001 { "DAC1R", NULL, "DAC1R Mixer" },
2002 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
2003 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
2004 };
2005
2006 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
2007 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
2008 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
2009 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
2010 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
2011 { "MICBIAS1", NULL, "CLK_SYS" },
2012 { "MICBIAS1", NULL, "MICBIAS Supply" },
2013 { "MICBIAS2", NULL, "CLK_SYS" },
2014 { "MICBIAS2", NULL, "MICBIAS Supply" },
2015 };
2016
2017 static const struct snd_soc_dapm_route wm8994_intercon[] = {
2018 { "AIF2DACL", NULL, "AIF2DAC Mux" },
2019 { "AIF2DACR", NULL, "AIF2DAC Mux" },
2020 { "MICBIAS1", NULL, "VMID" },
2021 { "MICBIAS2", NULL, "VMID" },
2022 };
2023
2024 static const struct snd_soc_dapm_route wm8958_intercon[] = {
2025 { "AIF2DACL", NULL, "AIF2DACL Mux" },
2026 { "AIF2DACR", NULL, "AIF2DACR Mux" },
2027
2028 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
2029 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
2030 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
2031 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
2032
2033 { "AIF3DACDAT", NULL, "AIF3" },
2034 { "AIF3ADCDAT", NULL, "AIF3" },
2035
2036 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
2037 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
2038
2039 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
2040 };
2041
2042 /* The size in bits of the FLL divide multiplied by 10
2043 * to allow rounding later */
2044 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2045
2046 struct fll_div {
2047 u16 outdiv;
2048 u16 n;
2049 u16 k;
2050 u16 lambda;
2051 u16 clk_ref_div;
2052 u16 fll_fratio;
2053 };
2054
wm8994_get_fll_config(struct wm8994 * control,struct fll_div * fll,int freq_in,int freq_out)2055 static int wm8994_get_fll_config(struct wm8994 *control, struct fll_div *fll,
2056 int freq_in, int freq_out)
2057 {
2058 u64 Kpart;
2059 unsigned int K, Ndiv, Nmod, gcd_fll;
2060
2061 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2062
2063 /* Scale the input frequency down to <= 13.5MHz */
2064 fll->clk_ref_div = 0;
2065 while (freq_in > 13500000) {
2066 fll->clk_ref_div++;
2067 freq_in /= 2;
2068
2069 if (fll->clk_ref_div > 3)
2070 return -EINVAL;
2071 }
2072 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2073
2074 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2075 fll->outdiv = 3;
2076 while (freq_out * (fll->outdiv + 1) < 90000000) {
2077 fll->outdiv++;
2078 if (fll->outdiv > 63)
2079 return -EINVAL;
2080 }
2081 freq_out *= fll->outdiv + 1;
2082 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2083
2084 if (freq_in > 1000000) {
2085 fll->fll_fratio = 0;
2086 } else if (freq_in > 256000) {
2087 fll->fll_fratio = 1;
2088 freq_in *= 2;
2089 } else if (freq_in > 128000) {
2090 fll->fll_fratio = 2;
2091 freq_in *= 4;
2092 } else if (freq_in > 64000) {
2093 fll->fll_fratio = 3;
2094 freq_in *= 8;
2095 } else {
2096 fll->fll_fratio = 4;
2097 freq_in *= 16;
2098 }
2099 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2100
2101 /* Now, calculate N.K */
2102 Ndiv = freq_out / freq_in;
2103
2104 fll->n = Ndiv;
2105 Nmod = freq_out % freq_in;
2106 pr_debug("Nmod=%d\n", Nmod);
2107
2108 switch (control->type) {
2109 case WM8994:
2110 /* Calculate fractional part - scale up so we can round. */
2111 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2112
2113 do_div(Kpart, freq_in);
2114
2115 K = Kpart & 0xFFFFFFFF;
2116
2117 if ((K % 10) >= 5)
2118 K += 5;
2119
2120 /* Move down to proper range now rounding is done */
2121 fll->k = K / 10;
2122 fll->lambda = 0;
2123
2124 pr_debug("N=%x K=%x\n", fll->n, fll->k);
2125 break;
2126
2127 default:
2128 gcd_fll = gcd(freq_out, freq_in);
2129
2130 fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll;
2131 fll->lambda = freq_in / gcd_fll;
2132
2133 }
2134
2135 return 0;
2136 }
2137
_wm8994_set_fll(struct snd_soc_component * component,int id,int src,unsigned int freq_in,unsigned int freq_out)2138 static int _wm8994_set_fll(struct snd_soc_component *component, int id, int src,
2139 unsigned int freq_in, unsigned int freq_out)
2140 {
2141 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
2142 struct wm8994 *control = wm8994->wm8994;
2143 int reg_offset, ret;
2144 struct fll_div fll;
2145 u16 reg, clk1, aif_reg, aif_src;
2146 unsigned long timeout;
2147 bool was_enabled;
2148
2149 switch (id) {
2150 case WM8994_FLL1:
2151 reg_offset = 0;
2152 id = 0;
2153 aif_src = 0x10;
2154 break;
2155 case WM8994_FLL2:
2156 reg_offset = 0x20;
2157 id = 1;
2158 aif_src = 0x18;
2159 break;
2160 default:
2161 return -EINVAL;
2162 }
2163
2164 reg = snd_soc_component_read32(component, WM8994_FLL1_CONTROL_1 + reg_offset);
2165 was_enabled = reg & WM8994_FLL1_ENA;
2166
2167 switch (src) {
2168 case 0:
2169 /* Allow no source specification when stopping */
2170 if (freq_out)
2171 return -EINVAL;
2172 src = wm8994->fll[id].src;
2173 break;
2174 case WM8994_FLL_SRC_MCLK1:
2175 case WM8994_FLL_SRC_MCLK2:
2176 case WM8994_FLL_SRC_LRCLK:
2177 case WM8994_FLL_SRC_BCLK:
2178 break;
2179 case WM8994_FLL_SRC_INTERNAL:
2180 freq_in = 12000000;
2181 freq_out = 12000000;
2182 break;
2183 default:
2184 return -EINVAL;
2185 }
2186
2187 /* Are we changing anything? */
2188 if (wm8994->fll[id].src == src &&
2189 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2190 return 0;
2191
2192 /* If we're stopping the FLL redo the old config - no
2193 * registers will actually be written but we avoid GCC flow
2194 * analysis bugs spewing warnings.
2195 */
2196 if (freq_out)
2197 ret = wm8994_get_fll_config(control, &fll, freq_in, freq_out);
2198 else
2199 ret = wm8994_get_fll_config(control, &fll, wm8994->fll[id].in,
2200 wm8994->fll[id].out);
2201 if (ret < 0)
2202 return ret;
2203
2204 /* Make sure that we're not providing SYSCLK right now */
2205 clk1 = snd_soc_component_read32(component, WM8994_CLOCKING_1);
2206 if (clk1 & WM8994_SYSCLK_SRC)
2207 aif_reg = WM8994_AIF2_CLOCKING_1;
2208 else
2209 aif_reg = WM8994_AIF1_CLOCKING_1;
2210 reg = snd_soc_component_read32(component, aif_reg);
2211
2212 if ((reg & WM8994_AIF1CLK_ENA) &&
2213 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2214 dev_err(component->dev, "FLL%d is currently providing SYSCLK\n",
2215 id + 1);
2216 return -EBUSY;
2217 }
2218
2219 /* We always need to disable the FLL while reconfiguring */
2220 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_1 + reg_offset,
2221 WM8994_FLL1_ENA, 0);
2222
2223 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
2224 freq_in == freq_out && freq_out) {
2225 dev_dbg(component->dev, "Bypassing FLL%d\n", id + 1);
2226 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_5 + reg_offset,
2227 WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2228 goto out;
2229 }
2230
2231 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2232 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2233 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_2 + reg_offset,
2234 WM8994_FLL1_OUTDIV_MASK |
2235 WM8994_FLL1_FRATIO_MASK, reg);
2236
2237 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_3 + reg_offset,
2238 WM8994_FLL1_K_MASK, fll.k);
2239
2240 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_4 + reg_offset,
2241 WM8994_FLL1_N_MASK,
2242 fll.n << WM8994_FLL1_N_SHIFT);
2243
2244 if (fll.lambda) {
2245 snd_soc_component_update_bits(component, WM8958_FLL1_EFS_1 + reg_offset,
2246 WM8958_FLL1_LAMBDA_MASK,
2247 fll.lambda);
2248 snd_soc_component_update_bits(component, WM8958_FLL1_EFS_2 + reg_offset,
2249 WM8958_FLL1_EFS_ENA, WM8958_FLL1_EFS_ENA);
2250 } else {
2251 snd_soc_component_update_bits(component, WM8958_FLL1_EFS_2 + reg_offset,
2252 WM8958_FLL1_EFS_ENA, 0);
2253 }
2254
2255 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_5 + reg_offset,
2256 WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
2257 WM8994_FLL1_REFCLK_DIV_MASK |
2258 WM8994_FLL1_REFCLK_SRC_MASK,
2259 ((src == WM8994_FLL_SRC_INTERNAL)
2260 << WM8994_FLL1_FRC_NCO_SHIFT) |
2261 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2262 (src - 1));
2263
2264 /* Clear any pending completion from a previous failure */
2265 try_wait_for_completion(&wm8994->fll_locked[id]);
2266
2267 /* Enable (with fractional mode if required) */
2268 if (freq_out) {
2269 /* Enable VMID if we need it */
2270 if (!was_enabled) {
2271 active_reference(component);
2272
2273 switch (control->type) {
2274 case WM8994:
2275 vmid_reference(component);
2276 break;
2277 case WM8958:
2278 if (control->revision < 1)
2279 vmid_reference(component);
2280 break;
2281 default:
2282 break;
2283 }
2284 }
2285
2286 reg = WM8994_FLL1_ENA;
2287
2288 if (fll.k)
2289 reg |= WM8994_FLL1_FRAC;
2290 if (src == WM8994_FLL_SRC_INTERNAL)
2291 reg |= WM8994_FLL1_OSC_ENA;
2292
2293 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_1 + reg_offset,
2294 WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2295 WM8994_FLL1_FRAC, reg);
2296
2297 if (wm8994->fll_locked_irq) {
2298 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2299 msecs_to_jiffies(10));
2300 if (timeout == 0)
2301 dev_warn(component->dev,
2302 "Timed out waiting for FLL lock\n");
2303 } else {
2304 msleep(5);
2305 }
2306 } else {
2307 if (was_enabled) {
2308 switch (control->type) {
2309 case WM8994:
2310 vmid_dereference(component);
2311 break;
2312 case WM8958:
2313 if (control->revision < 1)
2314 vmid_dereference(component);
2315 break;
2316 default:
2317 break;
2318 }
2319
2320 active_dereference(component);
2321 }
2322 }
2323
2324 out:
2325 wm8994->fll[id].in = freq_in;
2326 wm8994->fll[id].out = freq_out;
2327 wm8994->fll[id].src = src;
2328
2329 configure_clock(component);
2330
2331 /*
2332 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2333 * for detection.
2334 */
2335 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2336 dev_dbg(component->dev, "Configuring AIFs for 128fs\n");
2337
2338 wm8994->aifdiv[0] = snd_soc_component_read32(component, WM8994_AIF1_RATE)
2339 & WM8994_AIF1CLK_RATE_MASK;
2340 wm8994->aifdiv[1] = snd_soc_component_read32(component, WM8994_AIF2_RATE)
2341 & WM8994_AIF1CLK_RATE_MASK;
2342
2343 snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
2344 WM8994_AIF1CLK_RATE_MASK, 0x1);
2345 snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
2346 WM8994_AIF2CLK_RATE_MASK, 0x1);
2347 } else if (wm8994->aifdiv[0]) {
2348 snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
2349 WM8994_AIF1CLK_RATE_MASK,
2350 wm8994->aifdiv[0]);
2351 snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
2352 WM8994_AIF2CLK_RATE_MASK,
2353 wm8994->aifdiv[1]);
2354
2355 wm8994->aifdiv[0] = 0;
2356 wm8994->aifdiv[1] = 0;
2357 }
2358
2359 return 0;
2360 }
2361
wm8994_fll_locked_irq(int irq,void * data)2362 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2363 {
2364 struct completion *completion = data;
2365
2366 complete(completion);
2367
2368 return IRQ_HANDLED;
2369 }
2370
2371 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2372
wm8994_set_fll(struct snd_soc_dai * dai,int id,int src,unsigned int freq_in,unsigned int freq_out)2373 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2374 unsigned int freq_in, unsigned int freq_out)
2375 {
2376 return _wm8994_set_fll(dai->component, id, src, freq_in, freq_out);
2377 }
2378
wm8994_set_dai_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)2379 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2380 int clk_id, unsigned int freq, int dir)
2381 {
2382 struct snd_soc_component *component = dai->component;
2383 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
2384 int i;
2385
2386 switch (dai->id) {
2387 case 1:
2388 case 2:
2389 break;
2390
2391 default:
2392 /* AIF3 shares clocking with AIF1/2 */
2393 return -EINVAL;
2394 }
2395
2396 switch (clk_id) {
2397 case WM8994_SYSCLK_MCLK1:
2398 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2399 wm8994->mclk[0] = freq;
2400 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2401 dai->id, freq);
2402 break;
2403
2404 case WM8994_SYSCLK_MCLK2:
2405 /* TODO: Set GPIO AF */
2406 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2407 wm8994->mclk[1] = freq;
2408 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2409 dai->id, freq);
2410 break;
2411
2412 case WM8994_SYSCLK_FLL1:
2413 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2414 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2415 break;
2416
2417 case WM8994_SYSCLK_FLL2:
2418 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2419 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2420 break;
2421
2422 case WM8994_SYSCLK_OPCLK:
2423 /* Special case - a division (times 10) is given and
2424 * no effect on main clocking.
2425 */
2426 if (freq) {
2427 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2428 if (opclk_divs[i] == freq)
2429 break;
2430 if (i == ARRAY_SIZE(opclk_divs))
2431 return -EINVAL;
2432 snd_soc_component_update_bits(component, WM8994_CLOCKING_2,
2433 WM8994_OPCLK_DIV_MASK, i);
2434 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_2,
2435 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2436 } else {
2437 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_2,
2438 WM8994_OPCLK_ENA, 0);
2439 }
2440 break;
2441
2442 default:
2443 return -EINVAL;
2444 }
2445
2446 configure_clock(component);
2447
2448 /*
2449 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2450 * for detection.
2451 */
2452 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2453 dev_dbg(component->dev, "Configuring AIFs for 128fs\n");
2454
2455 wm8994->aifdiv[0] = snd_soc_component_read32(component, WM8994_AIF1_RATE)
2456 & WM8994_AIF1CLK_RATE_MASK;
2457 wm8994->aifdiv[1] = snd_soc_component_read32(component, WM8994_AIF2_RATE)
2458 & WM8994_AIF1CLK_RATE_MASK;
2459
2460 snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
2461 WM8994_AIF1CLK_RATE_MASK, 0x1);
2462 snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
2463 WM8994_AIF2CLK_RATE_MASK, 0x1);
2464 } else if (wm8994->aifdiv[0]) {
2465 snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
2466 WM8994_AIF1CLK_RATE_MASK,
2467 wm8994->aifdiv[0]);
2468 snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
2469 WM8994_AIF2CLK_RATE_MASK,
2470 wm8994->aifdiv[1]);
2471
2472 wm8994->aifdiv[0] = 0;
2473 wm8994->aifdiv[1] = 0;
2474 }
2475
2476 return 0;
2477 }
2478
wm8994_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)2479 static int wm8994_set_bias_level(struct snd_soc_component *component,
2480 enum snd_soc_bias_level level)
2481 {
2482 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
2483 struct wm8994 *control = wm8994->wm8994;
2484
2485 wm_hubs_set_bias_level(component, level);
2486
2487 switch (level) {
2488 case SND_SOC_BIAS_ON:
2489 break;
2490
2491 case SND_SOC_BIAS_PREPARE:
2492 /* MICBIAS into regulating mode */
2493 switch (control->type) {
2494 case WM8958:
2495 case WM1811:
2496 snd_soc_component_update_bits(component, WM8958_MICBIAS1,
2497 WM8958_MICB1_MODE, 0);
2498 snd_soc_component_update_bits(component, WM8958_MICBIAS2,
2499 WM8958_MICB2_MODE, 0);
2500 break;
2501 default:
2502 break;
2503 }
2504
2505 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY)
2506 active_reference(component);
2507 break;
2508
2509 case SND_SOC_BIAS_STANDBY:
2510 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
2511 switch (control->type) {
2512 case WM8958:
2513 if (control->revision == 0) {
2514 /* Optimise performance for rev A */
2515 snd_soc_component_update_bits(component,
2516 WM8958_CHARGE_PUMP_2,
2517 WM8958_CP_DISCH,
2518 WM8958_CP_DISCH);
2519 }
2520 break;
2521
2522 default:
2523 break;
2524 }
2525
2526 /* Discharge LINEOUT1 & 2 */
2527 snd_soc_component_update_bits(component, WM8994_ANTIPOP_1,
2528 WM8994_LINEOUT1_DISCH |
2529 WM8994_LINEOUT2_DISCH,
2530 WM8994_LINEOUT1_DISCH |
2531 WM8994_LINEOUT2_DISCH);
2532 }
2533
2534 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE)
2535 active_dereference(component);
2536
2537 /* MICBIAS into bypass mode on newer devices */
2538 switch (control->type) {
2539 case WM8958:
2540 case WM1811:
2541 snd_soc_component_update_bits(component, WM8958_MICBIAS1,
2542 WM8958_MICB1_MODE,
2543 WM8958_MICB1_MODE);
2544 snd_soc_component_update_bits(component, WM8958_MICBIAS2,
2545 WM8958_MICB2_MODE,
2546 WM8958_MICB2_MODE);
2547 break;
2548 default:
2549 break;
2550 }
2551 break;
2552
2553 case SND_SOC_BIAS_OFF:
2554 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY)
2555 wm8994->cur_fw = NULL;
2556 break;
2557 }
2558
2559 return 0;
2560 }
2561
wm8994_vmid_mode(struct snd_soc_component * component,enum wm8994_vmid_mode mode)2562 int wm8994_vmid_mode(struct snd_soc_component *component, enum wm8994_vmid_mode mode)
2563 {
2564 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
2565 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2566
2567 switch (mode) {
2568 case WM8994_VMID_NORMAL:
2569 snd_soc_dapm_mutex_lock(dapm);
2570
2571 if (wm8994->hubs.lineout1_se) {
2572 snd_soc_dapm_disable_pin_unlocked(dapm,
2573 "LINEOUT1N Driver");
2574 snd_soc_dapm_disable_pin_unlocked(dapm,
2575 "LINEOUT1P Driver");
2576 }
2577 if (wm8994->hubs.lineout2_se) {
2578 snd_soc_dapm_disable_pin_unlocked(dapm,
2579 "LINEOUT2N Driver");
2580 snd_soc_dapm_disable_pin_unlocked(dapm,
2581 "LINEOUT2P Driver");
2582 }
2583
2584 /* Do the sync with the old mode to allow it to clean up */
2585 snd_soc_dapm_sync_unlocked(dapm);
2586 wm8994->vmid_mode = mode;
2587
2588 snd_soc_dapm_mutex_unlock(dapm);
2589 break;
2590
2591 case WM8994_VMID_FORCE:
2592 snd_soc_dapm_mutex_lock(dapm);
2593
2594 if (wm8994->hubs.lineout1_se) {
2595 snd_soc_dapm_force_enable_pin_unlocked(dapm,
2596 "LINEOUT1N Driver");
2597 snd_soc_dapm_force_enable_pin_unlocked(dapm,
2598 "LINEOUT1P Driver");
2599 }
2600 if (wm8994->hubs.lineout2_se) {
2601 snd_soc_dapm_force_enable_pin_unlocked(dapm,
2602 "LINEOUT2N Driver");
2603 snd_soc_dapm_force_enable_pin_unlocked(dapm,
2604 "LINEOUT2P Driver");
2605 }
2606
2607 wm8994->vmid_mode = mode;
2608 snd_soc_dapm_sync_unlocked(dapm);
2609
2610 snd_soc_dapm_mutex_unlock(dapm);
2611 break;
2612
2613 default:
2614 return -EINVAL;
2615 }
2616
2617 return 0;
2618 }
2619
wm8994_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)2620 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2621 {
2622 struct snd_soc_component *component = dai->component;
2623 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
2624 struct wm8994 *control = wm8994->wm8994;
2625 int ms_reg;
2626 int aif1_reg;
2627 int dac_reg;
2628 int adc_reg;
2629 int ms = 0;
2630 int aif1 = 0;
2631 int lrclk = 0;
2632
2633 switch (dai->id) {
2634 case 1:
2635 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2636 aif1_reg = WM8994_AIF1_CONTROL_1;
2637 dac_reg = WM8994_AIF1DAC_LRCLK;
2638 adc_reg = WM8994_AIF1ADC_LRCLK;
2639 break;
2640 case 2:
2641 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2642 aif1_reg = WM8994_AIF2_CONTROL_1;
2643 dac_reg = WM8994_AIF1DAC_LRCLK;
2644 adc_reg = WM8994_AIF1ADC_LRCLK;
2645 break;
2646 default:
2647 return -EINVAL;
2648 }
2649
2650 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2651 case SND_SOC_DAIFMT_CBS_CFS:
2652 break;
2653 case SND_SOC_DAIFMT_CBM_CFM:
2654 ms = WM8994_AIF1_MSTR;
2655 break;
2656 default:
2657 return -EINVAL;
2658 }
2659
2660 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2661 case SND_SOC_DAIFMT_DSP_B:
2662 aif1 |= WM8994_AIF1_LRCLK_INV;
2663 lrclk |= WM8958_AIF1_LRCLK_INV;
2664 /* fall through */
2665 case SND_SOC_DAIFMT_DSP_A:
2666 aif1 |= 0x18;
2667 break;
2668 case SND_SOC_DAIFMT_I2S:
2669 aif1 |= 0x10;
2670 break;
2671 case SND_SOC_DAIFMT_RIGHT_J:
2672 break;
2673 case SND_SOC_DAIFMT_LEFT_J:
2674 aif1 |= 0x8;
2675 break;
2676 default:
2677 return -EINVAL;
2678 }
2679
2680 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2681 case SND_SOC_DAIFMT_DSP_A:
2682 case SND_SOC_DAIFMT_DSP_B:
2683 /* frame inversion not valid for DSP modes */
2684 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2685 case SND_SOC_DAIFMT_NB_NF:
2686 break;
2687 case SND_SOC_DAIFMT_IB_NF:
2688 aif1 |= WM8994_AIF1_BCLK_INV;
2689 break;
2690 default:
2691 return -EINVAL;
2692 }
2693 break;
2694
2695 case SND_SOC_DAIFMT_I2S:
2696 case SND_SOC_DAIFMT_RIGHT_J:
2697 case SND_SOC_DAIFMT_LEFT_J:
2698 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2699 case SND_SOC_DAIFMT_NB_NF:
2700 break;
2701 case SND_SOC_DAIFMT_IB_IF:
2702 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2703 lrclk |= WM8958_AIF1_LRCLK_INV;
2704 break;
2705 case SND_SOC_DAIFMT_IB_NF:
2706 aif1 |= WM8994_AIF1_BCLK_INV;
2707 break;
2708 case SND_SOC_DAIFMT_NB_IF:
2709 aif1 |= WM8994_AIF1_LRCLK_INV;
2710 lrclk |= WM8958_AIF1_LRCLK_INV;
2711 break;
2712 default:
2713 return -EINVAL;
2714 }
2715 break;
2716 default:
2717 return -EINVAL;
2718 }
2719
2720 /* The AIF2 format configuration needs to be mirrored to AIF3
2721 * on WM8958 if it's in use so just do it all the time. */
2722 switch (control->type) {
2723 case WM1811:
2724 case WM8958:
2725 if (dai->id == 2)
2726 snd_soc_component_update_bits(component, WM8958_AIF3_CONTROL_1,
2727 WM8994_AIF1_LRCLK_INV |
2728 WM8958_AIF3_FMT_MASK, aif1);
2729 break;
2730
2731 default:
2732 break;
2733 }
2734
2735 snd_soc_component_update_bits(component, aif1_reg,
2736 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2737 WM8994_AIF1_FMT_MASK,
2738 aif1);
2739 snd_soc_component_update_bits(component, ms_reg, WM8994_AIF1_MSTR,
2740 ms);
2741 snd_soc_component_update_bits(component, dac_reg,
2742 WM8958_AIF1_LRCLK_INV, lrclk);
2743 snd_soc_component_update_bits(component, adc_reg,
2744 WM8958_AIF1_LRCLK_INV, lrclk);
2745
2746 return 0;
2747 }
2748
2749 static struct {
2750 int val, rate;
2751 } srs[] = {
2752 { 0, 8000 },
2753 { 1, 11025 },
2754 { 2, 12000 },
2755 { 3, 16000 },
2756 { 4, 22050 },
2757 { 5, 24000 },
2758 { 6, 32000 },
2759 { 7, 44100 },
2760 { 8, 48000 },
2761 { 9, 88200 },
2762 { 10, 96000 },
2763 };
2764
2765 static int fs_ratios[] = {
2766 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536
2767 };
2768
2769 static int bclk_divs[] = {
2770 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2771 640, 880, 960, 1280, 1760, 1920
2772 };
2773
wm8994_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)2774 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2775 struct snd_pcm_hw_params *params,
2776 struct snd_soc_dai *dai)
2777 {
2778 struct snd_soc_component *component = dai->component;
2779 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
2780 struct wm8994 *control = wm8994->wm8994;
2781 struct wm8994_pdata *pdata = &control->pdata;
2782 int aif1_reg;
2783 int aif2_reg;
2784 int bclk_reg;
2785 int lrclk_reg;
2786 int rate_reg;
2787 int aif1 = 0;
2788 int aif2 = 0;
2789 int bclk = 0;
2790 int lrclk = 0;
2791 int rate_val = 0;
2792 int id = dai->id - 1;
2793
2794 int i, cur_val, best_val, bclk_rate, best;
2795
2796 switch (dai->id) {
2797 case 1:
2798 aif1_reg = WM8994_AIF1_CONTROL_1;
2799 aif2_reg = WM8994_AIF1_CONTROL_2;
2800 bclk_reg = WM8994_AIF1_BCLK;
2801 rate_reg = WM8994_AIF1_RATE;
2802 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2803 wm8994->lrclk_shared[0]) {
2804 lrclk_reg = WM8994_AIF1DAC_LRCLK;
2805 } else {
2806 lrclk_reg = WM8994_AIF1ADC_LRCLK;
2807 dev_dbg(component->dev, "AIF1 using split LRCLK\n");
2808 }
2809 break;
2810 case 2:
2811 aif1_reg = WM8994_AIF2_CONTROL_1;
2812 aif2_reg = WM8994_AIF2_CONTROL_2;
2813 bclk_reg = WM8994_AIF2_BCLK;
2814 rate_reg = WM8994_AIF2_RATE;
2815 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2816 wm8994->lrclk_shared[1]) {
2817 lrclk_reg = WM8994_AIF2DAC_LRCLK;
2818 } else {
2819 lrclk_reg = WM8994_AIF2ADC_LRCLK;
2820 dev_dbg(component->dev, "AIF2 using split LRCLK\n");
2821 }
2822 break;
2823 default:
2824 return -EINVAL;
2825 }
2826
2827 bclk_rate = params_rate(params);
2828 switch (params_width(params)) {
2829 case 16:
2830 bclk_rate *= 16;
2831 break;
2832 case 20:
2833 bclk_rate *= 20;
2834 aif1 |= 0x20;
2835 break;
2836 case 24:
2837 bclk_rate *= 24;
2838 aif1 |= 0x40;
2839 break;
2840 case 32:
2841 bclk_rate *= 32;
2842 aif1 |= 0x60;
2843 break;
2844 default:
2845 return -EINVAL;
2846 }
2847
2848 wm8994->channels[id] = params_channels(params);
2849 if (pdata->max_channels_clocked[id] &&
2850 wm8994->channels[id] > pdata->max_channels_clocked[id]) {
2851 dev_dbg(dai->dev, "Constraining channels to %d from %d\n",
2852 pdata->max_channels_clocked[id], wm8994->channels[id]);
2853 wm8994->channels[id] = pdata->max_channels_clocked[id];
2854 }
2855
2856 switch (wm8994->channels[id]) {
2857 case 1:
2858 case 2:
2859 bclk_rate *= 2;
2860 break;
2861 default:
2862 bclk_rate *= 4;
2863 break;
2864 }
2865
2866 /* Try to find an appropriate sample rate; look for an exact match. */
2867 for (i = 0; i < ARRAY_SIZE(srs); i++)
2868 if (srs[i].rate == params_rate(params))
2869 break;
2870 if (i == ARRAY_SIZE(srs))
2871 return -EINVAL;
2872 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2873
2874 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2875 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2876 dai->id, wm8994->aifclk[id], bclk_rate);
2877
2878 if (wm8994->channels[id] == 1 &&
2879 (snd_soc_component_read32(component, aif1_reg) & 0x18) == 0x18)
2880 aif2 |= WM8994_AIF1_MONO;
2881
2882 if (wm8994->aifclk[id] == 0) {
2883 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2884 return -EINVAL;
2885 }
2886
2887 /* AIFCLK/fs ratio; look for a close match in either direction */
2888 best = 0;
2889 best_val = abs((fs_ratios[0] * params_rate(params))
2890 - wm8994->aifclk[id]);
2891 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2892 cur_val = abs((fs_ratios[i] * params_rate(params))
2893 - wm8994->aifclk[id]);
2894 if (cur_val >= best_val)
2895 continue;
2896 best = i;
2897 best_val = cur_val;
2898 }
2899 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2900 dai->id, fs_ratios[best]);
2901 rate_val |= best;
2902
2903 /* We may not get quite the right frequency if using
2904 * approximate clocks so look for the closest match that is
2905 * higher than the target (we need to ensure that there enough
2906 * BCLKs to clock out the samples).
2907 */
2908 best = 0;
2909 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2910 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2911 if (cur_val < 0) /* BCLK table is sorted */
2912 break;
2913 best = i;
2914 }
2915 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2916 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2917 bclk_divs[best], bclk_rate);
2918 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2919
2920 lrclk = bclk_rate / params_rate(params);
2921 if (!lrclk) {
2922 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2923 bclk_rate);
2924 return -EINVAL;
2925 }
2926 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2927 lrclk, bclk_rate / lrclk);
2928
2929 snd_soc_component_update_bits(component, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2930 snd_soc_component_update_bits(component, aif2_reg, WM8994_AIF1_MONO, aif2);
2931 snd_soc_component_update_bits(component, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2932 snd_soc_component_update_bits(component, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2933 lrclk);
2934 snd_soc_component_update_bits(component, rate_reg, WM8994_AIF1_SR_MASK |
2935 WM8994_AIF1CLK_RATE_MASK, rate_val);
2936
2937 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2938 switch (dai->id) {
2939 case 1:
2940 wm8994->dac_rates[0] = params_rate(params);
2941 wm8994_set_retune_mobile(component, 0);
2942 wm8994_set_retune_mobile(component, 1);
2943 break;
2944 case 2:
2945 wm8994->dac_rates[1] = params_rate(params);
2946 wm8994_set_retune_mobile(component, 2);
2947 break;
2948 }
2949 }
2950
2951 return 0;
2952 }
2953
wm8994_aif3_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)2954 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2955 struct snd_pcm_hw_params *params,
2956 struct snd_soc_dai *dai)
2957 {
2958 struct snd_soc_component *component = dai->component;
2959 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
2960 struct wm8994 *control = wm8994->wm8994;
2961 int aif1_reg;
2962 int aif1 = 0;
2963
2964 switch (dai->id) {
2965 case 3:
2966 switch (control->type) {
2967 case WM1811:
2968 case WM8958:
2969 aif1_reg = WM8958_AIF3_CONTROL_1;
2970 break;
2971 default:
2972 return 0;
2973 }
2974 break;
2975 default:
2976 return 0;
2977 }
2978
2979 switch (params_width(params)) {
2980 case 16:
2981 break;
2982 case 20:
2983 aif1 |= 0x20;
2984 break;
2985 case 24:
2986 aif1 |= 0x40;
2987 break;
2988 case 32:
2989 aif1 |= 0x60;
2990 break;
2991 default:
2992 return -EINVAL;
2993 }
2994
2995 return snd_soc_component_update_bits(component, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2996 }
2997
wm8994_aif_mute(struct snd_soc_dai * codec_dai,int mute)2998 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2999 {
3000 struct snd_soc_component *component = codec_dai->component;
3001 int mute_reg;
3002 int reg;
3003
3004 switch (codec_dai->id) {
3005 case 1:
3006 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
3007 break;
3008 case 2:
3009 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
3010 break;
3011 default:
3012 return -EINVAL;
3013 }
3014
3015 if (mute)
3016 reg = WM8994_AIF1DAC1_MUTE;
3017 else
3018 reg = 0;
3019
3020 snd_soc_component_update_bits(component, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
3021
3022 return 0;
3023 }
3024
wm8994_set_tristate(struct snd_soc_dai * codec_dai,int tristate)3025 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
3026 {
3027 struct snd_soc_component *component = codec_dai->component;
3028 int reg, val, mask;
3029
3030 switch (codec_dai->id) {
3031 case 1:
3032 reg = WM8994_AIF1_MASTER_SLAVE;
3033 mask = WM8994_AIF1_TRI;
3034 break;
3035 case 2:
3036 reg = WM8994_AIF2_MASTER_SLAVE;
3037 mask = WM8994_AIF2_TRI;
3038 break;
3039 default:
3040 return -EINVAL;
3041 }
3042
3043 if (tristate)
3044 val = mask;
3045 else
3046 val = 0;
3047
3048 return snd_soc_component_update_bits(component, reg, mask, val);
3049 }
3050
wm8994_aif2_probe(struct snd_soc_dai * dai)3051 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
3052 {
3053 struct snd_soc_component *component = dai->component;
3054
3055 /* Disable the pulls on the AIF if we're using it to save power. */
3056 snd_soc_component_update_bits(component, WM8994_GPIO_3,
3057 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3058 snd_soc_component_update_bits(component, WM8994_GPIO_4,
3059 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3060 snd_soc_component_update_bits(component, WM8994_GPIO_5,
3061 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3062
3063 return 0;
3064 }
3065
3066 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
3067
3068 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3069 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
3070
3071 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
3072 .set_sysclk = wm8994_set_dai_sysclk,
3073 .set_fmt = wm8994_set_dai_fmt,
3074 .hw_params = wm8994_hw_params,
3075 .digital_mute = wm8994_aif_mute,
3076 .set_pll = wm8994_set_fll,
3077 .set_tristate = wm8994_set_tristate,
3078 };
3079
3080 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
3081 .set_sysclk = wm8994_set_dai_sysclk,
3082 .set_fmt = wm8994_set_dai_fmt,
3083 .hw_params = wm8994_hw_params,
3084 .digital_mute = wm8994_aif_mute,
3085 .set_pll = wm8994_set_fll,
3086 .set_tristate = wm8994_set_tristate,
3087 };
3088
3089 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
3090 .hw_params = wm8994_aif3_hw_params,
3091 };
3092
3093 static struct snd_soc_dai_driver wm8994_dai[] = {
3094 {
3095 .name = "wm8994-aif1",
3096 .id = 1,
3097 .playback = {
3098 .stream_name = "AIF1 Playback",
3099 .channels_min = 1,
3100 .channels_max = 2,
3101 .rates = WM8994_RATES,
3102 .formats = WM8994_FORMATS,
3103 .sig_bits = 24,
3104 },
3105 .capture = {
3106 .stream_name = "AIF1 Capture",
3107 .channels_min = 1,
3108 .channels_max = 2,
3109 .rates = WM8994_RATES,
3110 .formats = WM8994_FORMATS,
3111 .sig_bits = 24,
3112 },
3113 .ops = &wm8994_aif1_dai_ops,
3114 },
3115 {
3116 .name = "wm8994-aif2",
3117 .id = 2,
3118 .playback = {
3119 .stream_name = "AIF2 Playback",
3120 .channels_min = 1,
3121 .channels_max = 2,
3122 .rates = WM8994_RATES,
3123 .formats = WM8994_FORMATS,
3124 .sig_bits = 24,
3125 },
3126 .capture = {
3127 .stream_name = "AIF2 Capture",
3128 .channels_min = 1,
3129 .channels_max = 2,
3130 .rates = WM8994_RATES,
3131 .formats = WM8994_FORMATS,
3132 .sig_bits = 24,
3133 },
3134 .probe = wm8994_aif2_probe,
3135 .ops = &wm8994_aif2_dai_ops,
3136 },
3137 {
3138 .name = "wm8994-aif3",
3139 .id = 3,
3140 .playback = {
3141 .stream_name = "AIF3 Playback",
3142 .channels_min = 1,
3143 .channels_max = 2,
3144 .rates = WM8994_RATES,
3145 .formats = WM8994_FORMATS,
3146 .sig_bits = 24,
3147 },
3148 .capture = {
3149 .stream_name = "AIF3 Capture",
3150 .channels_min = 1,
3151 .channels_max = 2,
3152 .rates = WM8994_RATES,
3153 .formats = WM8994_FORMATS,
3154 .sig_bits = 24,
3155 },
3156 .ops = &wm8994_aif3_dai_ops,
3157 }
3158 };
3159
3160 #ifdef CONFIG_PM
wm8994_component_suspend(struct snd_soc_component * component)3161 static int wm8994_component_suspend(struct snd_soc_component *component)
3162 {
3163 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3164 int i, ret;
3165
3166 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3167 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
3168 sizeof(struct wm8994_fll_config));
3169 ret = _wm8994_set_fll(component, i + 1, 0, 0, 0);
3170 if (ret < 0)
3171 dev_warn(component->dev, "Failed to stop FLL%d: %d\n",
3172 i + 1, ret);
3173 }
3174
3175 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
3176
3177 return 0;
3178 }
3179
wm8994_component_resume(struct snd_soc_component * component)3180 static int wm8994_component_resume(struct snd_soc_component *component)
3181 {
3182 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3183 int i, ret;
3184
3185 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3186 if (!wm8994->fll_suspend[i].out)
3187 continue;
3188
3189 ret = _wm8994_set_fll(component, i + 1,
3190 wm8994->fll_suspend[i].src,
3191 wm8994->fll_suspend[i].in,
3192 wm8994->fll_suspend[i].out);
3193 if (ret < 0)
3194 dev_warn(component->dev, "Failed to restore FLL%d: %d\n",
3195 i + 1, ret);
3196 }
3197
3198 return 0;
3199 }
3200 #else
3201 #define wm8994_component_suspend NULL
3202 #define wm8994_component_resume NULL
3203 #endif
3204
wm8994_handle_retune_mobile_pdata(struct wm8994_priv * wm8994)3205 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3206 {
3207 struct snd_soc_component *component = wm8994->hubs.component;
3208 struct wm8994 *control = wm8994->wm8994;
3209 struct wm8994_pdata *pdata = &control->pdata;
3210 struct snd_kcontrol_new controls[] = {
3211 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3212 wm8994->retune_mobile_enum,
3213 wm8994_get_retune_mobile_enum,
3214 wm8994_put_retune_mobile_enum),
3215 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3216 wm8994->retune_mobile_enum,
3217 wm8994_get_retune_mobile_enum,
3218 wm8994_put_retune_mobile_enum),
3219 SOC_ENUM_EXT("AIF2 EQ Mode",
3220 wm8994->retune_mobile_enum,
3221 wm8994_get_retune_mobile_enum,
3222 wm8994_put_retune_mobile_enum),
3223 };
3224 int ret, i, j;
3225 const char **t;
3226
3227 /* We need an array of texts for the enum API but the number
3228 * of texts is likely to be less than the number of
3229 * configurations due to the sample rate dependency of the
3230 * configurations. */
3231 wm8994->num_retune_mobile_texts = 0;
3232 wm8994->retune_mobile_texts = NULL;
3233 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3234 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3235 if (strcmp(pdata->retune_mobile_cfgs[i].name,
3236 wm8994->retune_mobile_texts[j]) == 0)
3237 break;
3238 }
3239
3240 if (j != wm8994->num_retune_mobile_texts)
3241 continue;
3242
3243 /* Expand the array... */
3244 t = krealloc(wm8994->retune_mobile_texts,
3245 sizeof(char *) *
3246 (wm8994->num_retune_mobile_texts + 1),
3247 GFP_KERNEL);
3248 if (t == NULL)
3249 continue;
3250
3251 /* ...store the new entry... */
3252 t[wm8994->num_retune_mobile_texts] =
3253 pdata->retune_mobile_cfgs[i].name;
3254
3255 /* ...and remember the new version. */
3256 wm8994->num_retune_mobile_texts++;
3257 wm8994->retune_mobile_texts = t;
3258 }
3259
3260 dev_dbg(component->dev, "Allocated %d unique ReTune Mobile names\n",
3261 wm8994->num_retune_mobile_texts);
3262
3263 wm8994->retune_mobile_enum.items = wm8994->num_retune_mobile_texts;
3264 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3265
3266 ret = snd_soc_add_component_controls(wm8994->hubs.component, controls,
3267 ARRAY_SIZE(controls));
3268 if (ret != 0)
3269 dev_err(wm8994->hubs.component->dev,
3270 "Failed to add ReTune Mobile controls: %d\n", ret);
3271 }
3272
wm8994_handle_pdata(struct wm8994_priv * wm8994)3273 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3274 {
3275 struct snd_soc_component *component = wm8994->hubs.component;
3276 struct wm8994 *control = wm8994->wm8994;
3277 struct wm8994_pdata *pdata = &control->pdata;
3278 int ret, i;
3279
3280 if (!pdata)
3281 return;
3282
3283 wm_hubs_handle_analogue_pdata(component, pdata->lineout1_diff,
3284 pdata->lineout2_diff,
3285 pdata->lineout1fb,
3286 pdata->lineout2fb,
3287 pdata->jd_scthr,
3288 pdata->jd_thr,
3289 pdata->micb1_delay,
3290 pdata->micb2_delay,
3291 pdata->micbias1_lvl,
3292 pdata->micbias2_lvl);
3293
3294 dev_dbg(component->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3295
3296 if (pdata->num_drc_cfgs) {
3297 struct snd_kcontrol_new controls[] = {
3298 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3299 wm8994_get_drc_enum, wm8994_put_drc_enum),
3300 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3301 wm8994_get_drc_enum, wm8994_put_drc_enum),
3302 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3303 wm8994_get_drc_enum, wm8994_put_drc_enum),
3304 };
3305
3306 /* We need an array of texts for the enum API */
3307 wm8994->drc_texts = devm_kcalloc(wm8994->hubs.component->dev,
3308 pdata->num_drc_cfgs, sizeof(char *), GFP_KERNEL);
3309 if (!wm8994->drc_texts)
3310 return;
3311
3312 for (i = 0; i < pdata->num_drc_cfgs; i++)
3313 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3314
3315 wm8994->drc_enum.items = pdata->num_drc_cfgs;
3316 wm8994->drc_enum.texts = wm8994->drc_texts;
3317
3318 ret = snd_soc_add_component_controls(wm8994->hubs.component, controls,
3319 ARRAY_SIZE(controls));
3320 for (i = 0; i < WM8994_NUM_DRC; i++)
3321 wm8994_set_drc(component, i);
3322 } else {
3323 ret = snd_soc_add_component_controls(wm8994->hubs.component,
3324 wm8994_drc_controls,
3325 ARRAY_SIZE(wm8994_drc_controls));
3326 }
3327
3328 if (ret != 0)
3329 dev_err(wm8994->hubs.component->dev,
3330 "Failed to add DRC mode controls: %d\n", ret);
3331
3332
3333 dev_dbg(component->dev, "%d ReTune Mobile configurations\n",
3334 pdata->num_retune_mobile_cfgs);
3335
3336 if (pdata->num_retune_mobile_cfgs)
3337 wm8994_handle_retune_mobile_pdata(wm8994);
3338 else
3339 snd_soc_add_component_controls(wm8994->hubs.component, wm8994_eq_controls,
3340 ARRAY_SIZE(wm8994_eq_controls));
3341
3342 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3343 if (pdata->micbias[i]) {
3344 snd_soc_component_write(component, WM8958_MICBIAS1 + i,
3345 pdata->micbias[i] & 0xffff);
3346 }
3347 }
3348 }
3349
3350 /**
3351 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3352 *
3353 * @component: WM8994 component
3354 * @jack: jack to report detection events on
3355 * @micbias: microphone bias to detect on
3356 *
3357 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3358 * being used to bring out signals to the processor then only platform
3359 * data configuration is needed for WM8994 and processor GPIOs should
3360 * be configured using snd_soc_jack_add_gpios() instead.
3361 *
3362 * Configuration of detection levels is available via the micbias1_lvl
3363 * and micbias2_lvl platform data members.
3364 */
wm8994_mic_detect(struct snd_soc_component * component,struct snd_soc_jack * jack,int micbias)3365 int wm8994_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack,
3366 int micbias)
3367 {
3368 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3369 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3370 struct wm8994_micdet *micdet;
3371 struct wm8994 *control = wm8994->wm8994;
3372 int reg, ret;
3373
3374 if (control->type != WM8994) {
3375 dev_warn(component->dev, "Not a WM8994\n");
3376 return -EINVAL;
3377 }
3378
3379 pm_runtime_get_sync(component->dev);
3380
3381 switch (micbias) {
3382 case 1:
3383 micdet = &wm8994->micdet[0];
3384 if (jack)
3385 ret = snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
3386 else
3387 ret = snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
3388 break;
3389 case 2:
3390 micdet = &wm8994->micdet[1];
3391 if (jack)
3392 ret = snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
3393 else
3394 ret = snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
3395 break;
3396 default:
3397 dev_warn(component->dev, "Invalid MICBIAS %d\n", micbias);
3398 return -EINVAL;
3399 }
3400
3401 if (ret != 0)
3402 dev_warn(component->dev, "Failed to configure MICBIAS%d: %d\n",
3403 micbias, ret);
3404
3405 dev_dbg(component->dev, "Configuring microphone detection on %d %p\n",
3406 micbias, jack);
3407
3408 /* Store the configuration */
3409 micdet->jack = jack;
3410 micdet->detecting = true;
3411
3412 /* If either of the jacks is set up then enable detection */
3413 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3414 reg = WM8994_MICD_ENA;
3415 else
3416 reg = 0;
3417
3418 snd_soc_component_update_bits(component, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3419
3420 /* enable MICDET and MICSHRT deboune */
3421 snd_soc_component_update_bits(component, WM8994_IRQ_DEBOUNCE,
3422 WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
3423 WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
3424 WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
3425
3426 snd_soc_dapm_sync(dapm);
3427
3428 pm_runtime_put(component->dev);
3429
3430 return 0;
3431 }
3432 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3433
wm8994_mic_work(struct work_struct * work)3434 static void wm8994_mic_work(struct work_struct *work)
3435 {
3436 struct wm8994_priv *priv = container_of(work,
3437 struct wm8994_priv,
3438 mic_work.work);
3439 struct regmap *regmap = priv->wm8994->regmap;
3440 struct device *dev = priv->wm8994->dev;
3441 unsigned int reg;
3442 int ret;
3443 int report;
3444
3445 pm_runtime_get_sync(dev);
3446
3447 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, ®);
3448 if (ret < 0) {
3449 dev_err(dev, "Failed to read microphone status: %d\n",
3450 ret);
3451 pm_runtime_put(dev);
3452 return;
3453 }
3454
3455 dev_dbg(dev, "Microphone status: %x\n", reg);
3456
3457 report = 0;
3458 if (reg & WM8994_MIC1_DET_STS) {
3459 if (priv->micdet[0].detecting)
3460 report = SND_JACK_HEADSET;
3461 }
3462 if (reg & WM8994_MIC1_SHRT_STS) {
3463 if (priv->micdet[0].detecting)
3464 report = SND_JACK_HEADPHONE;
3465 else
3466 report |= SND_JACK_BTN_0;
3467 }
3468 if (report)
3469 priv->micdet[0].detecting = false;
3470 else
3471 priv->micdet[0].detecting = true;
3472
3473 snd_soc_jack_report(priv->micdet[0].jack, report,
3474 SND_JACK_HEADSET | SND_JACK_BTN_0);
3475
3476 report = 0;
3477 if (reg & WM8994_MIC2_DET_STS) {
3478 if (priv->micdet[1].detecting)
3479 report = SND_JACK_HEADSET;
3480 }
3481 if (reg & WM8994_MIC2_SHRT_STS) {
3482 if (priv->micdet[1].detecting)
3483 report = SND_JACK_HEADPHONE;
3484 else
3485 report |= SND_JACK_BTN_0;
3486 }
3487 if (report)
3488 priv->micdet[1].detecting = false;
3489 else
3490 priv->micdet[1].detecting = true;
3491
3492 snd_soc_jack_report(priv->micdet[1].jack, report,
3493 SND_JACK_HEADSET | SND_JACK_BTN_0);
3494
3495 pm_runtime_put(dev);
3496 }
3497
wm8994_mic_irq(int irq,void * data)3498 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3499 {
3500 struct wm8994_priv *priv = data;
3501 struct snd_soc_component *component = priv->hubs.component;
3502
3503 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3504 trace_snd_soc_jack_irq(dev_name(component->dev));
3505 #endif
3506
3507 pm_wakeup_event(component->dev, 300);
3508
3509 queue_delayed_work(system_power_efficient_wq,
3510 &priv->mic_work, msecs_to_jiffies(250));
3511
3512 return IRQ_HANDLED;
3513 }
3514
3515 /* Should be called with accdet_lock held */
wm1811_micd_stop(struct snd_soc_component * component)3516 static void wm1811_micd_stop(struct snd_soc_component *component)
3517 {
3518 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3519 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3520
3521 if (!wm8994->jackdet)
3522 return;
3523
3524 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0);
3525
3526 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_JACK);
3527
3528 if (wm8994->wm8994->pdata.jd_ext_cap)
3529 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
3530 }
3531
wm8958_button_det(struct snd_soc_component * component,u16 status)3532 static void wm8958_button_det(struct snd_soc_component *component, u16 status)
3533 {
3534 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3535 int report;
3536
3537 report = 0;
3538 if (status & 0x4)
3539 report |= SND_JACK_BTN_0;
3540
3541 if (status & 0x8)
3542 report |= SND_JACK_BTN_1;
3543
3544 if (status & 0x10)
3545 report |= SND_JACK_BTN_2;
3546
3547 if (status & 0x20)
3548 report |= SND_JACK_BTN_3;
3549
3550 if (status & 0x40)
3551 report |= SND_JACK_BTN_4;
3552
3553 if (status & 0x80)
3554 report |= SND_JACK_BTN_5;
3555
3556 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3557 wm8994->btn_mask);
3558 }
3559
wm8958_open_circuit_work(struct work_struct * work)3560 static void wm8958_open_circuit_work(struct work_struct *work)
3561 {
3562 struct wm8994_priv *wm8994 = container_of(work,
3563 struct wm8994_priv,
3564 open_circuit_work.work);
3565 struct device *dev = wm8994->wm8994->dev;
3566
3567 mutex_lock(&wm8994->accdet_lock);
3568
3569 wm1811_micd_stop(wm8994->hubs.component);
3570
3571 dev_dbg(dev, "Reporting open circuit\n");
3572
3573 wm8994->jack_mic = false;
3574 wm8994->mic_detecting = true;
3575
3576 wm8958_micd_set_rate(wm8994->hubs.component);
3577
3578 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3579 wm8994->btn_mask |
3580 SND_JACK_HEADSET);
3581
3582 mutex_unlock(&wm8994->accdet_lock);
3583 }
3584
wm8958_mic_id(void * data,u16 status)3585 static void wm8958_mic_id(void *data, u16 status)
3586 {
3587 struct snd_soc_component *component = data;
3588 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3589
3590 /* Either nothing present or just starting detection */
3591 if (!(status & WM8958_MICD_STS)) {
3592 /* If nothing present then clear our statuses */
3593 dev_dbg(component->dev, "Detected open circuit\n");
3594
3595 queue_delayed_work(system_power_efficient_wq,
3596 &wm8994->open_circuit_work,
3597 msecs_to_jiffies(2500));
3598 return;
3599 }
3600
3601 /* If the measurement is showing a high impedence we've got a
3602 * microphone.
3603 */
3604 if (status & 0x600) {
3605 dev_dbg(component->dev, "Detected microphone\n");
3606
3607 wm8994->mic_detecting = false;
3608 wm8994->jack_mic = true;
3609
3610 wm8958_micd_set_rate(component);
3611
3612 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3613 SND_JACK_HEADSET);
3614 }
3615
3616
3617 if (status & 0xfc) {
3618 dev_dbg(component->dev, "Detected headphone\n");
3619 wm8994->mic_detecting = false;
3620
3621 wm8958_micd_set_rate(component);
3622
3623 /* If we have jackdet that will detect removal */
3624 wm1811_micd_stop(component);
3625
3626 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3627 SND_JACK_HEADSET);
3628 }
3629 }
3630
3631 /* Deferred mic detection to allow for extra settling time */
wm1811_mic_work(struct work_struct * work)3632 static void wm1811_mic_work(struct work_struct *work)
3633 {
3634 struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
3635 mic_work.work);
3636 struct wm8994 *control = wm8994->wm8994;
3637 struct snd_soc_component *component = wm8994->hubs.component;
3638 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3639
3640 pm_runtime_get_sync(component->dev);
3641
3642 /* If required for an external cap force MICBIAS on */
3643 if (control->pdata.jd_ext_cap) {
3644 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2");
3645 snd_soc_dapm_sync(dapm);
3646 }
3647
3648 mutex_lock(&wm8994->accdet_lock);
3649
3650 dev_dbg(component->dev, "Starting mic detection\n");
3651
3652 /* Use a user-supplied callback if we have one */
3653 if (wm8994->micd_cb) {
3654 wm8994->micd_cb(wm8994->micd_cb_data);
3655 } else {
3656 /*
3657 * Start off measument of microphone impedence to find out
3658 * what's actually there.
3659 */
3660 wm8994->mic_detecting = true;
3661 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_MIC);
3662
3663 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
3664 WM8958_MICD_ENA, WM8958_MICD_ENA);
3665 }
3666
3667 mutex_unlock(&wm8994->accdet_lock);
3668
3669 pm_runtime_put(component->dev);
3670 }
3671
wm1811_jackdet_irq(int irq,void * data)3672 static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3673 {
3674 struct wm8994_priv *wm8994 = data;
3675 struct wm8994 *control = wm8994->wm8994;
3676 struct snd_soc_component *component = wm8994->hubs.component;
3677 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3678 int reg, delay;
3679 bool present;
3680
3681 pm_runtime_get_sync(component->dev);
3682
3683 cancel_delayed_work_sync(&wm8994->mic_complete_work);
3684
3685 mutex_lock(&wm8994->accdet_lock);
3686
3687 reg = snd_soc_component_read32(component, WM1811_JACKDET_CTRL);
3688 if (reg < 0) {
3689 dev_err(component->dev, "Failed to read jack status: %d\n", reg);
3690 mutex_unlock(&wm8994->accdet_lock);
3691 pm_runtime_put(component->dev);
3692 return IRQ_NONE;
3693 }
3694
3695 dev_dbg(component->dev, "JACKDET %x\n", reg);
3696
3697 present = reg & WM1811_JACKDET_LVL;
3698
3699 if (present) {
3700 dev_dbg(component->dev, "Jack detected\n");
3701
3702 wm8958_micd_set_rate(component);
3703
3704 snd_soc_component_update_bits(component, WM8958_MICBIAS2,
3705 WM8958_MICB2_DISCH, 0);
3706
3707 /* Disable debounce while inserted */
3708 snd_soc_component_update_bits(component, WM1811_JACKDET_CTRL,
3709 WM1811_JACKDET_DB, 0);
3710
3711 delay = control->pdata.micdet_delay;
3712 queue_delayed_work(system_power_efficient_wq,
3713 &wm8994->mic_work,
3714 msecs_to_jiffies(delay));
3715 } else {
3716 dev_dbg(component->dev, "Jack not detected\n");
3717
3718 cancel_delayed_work_sync(&wm8994->mic_work);
3719
3720 snd_soc_component_update_bits(component, WM8958_MICBIAS2,
3721 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3722
3723 /* Enable debounce while removed */
3724 snd_soc_component_update_bits(component, WM1811_JACKDET_CTRL,
3725 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3726
3727 wm8994->mic_detecting = false;
3728 wm8994->jack_mic = false;
3729 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
3730 WM8958_MICD_ENA, 0);
3731 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_JACK);
3732 }
3733
3734 mutex_unlock(&wm8994->accdet_lock);
3735
3736 /* Turn off MICBIAS if it was on for an external cap */
3737 if (control->pdata.jd_ext_cap && !present)
3738 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
3739
3740 if (present)
3741 snd_soc_jack_report(wm8994->micdet[0].jack,
3742 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3743 else
3744 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3745 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3746 wm8994->btn_mask);
3747
3748 /* Since we only report deltas force an update, ensures we
3749 * avoid bootstrapping issues with the core. */
3750 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
3751
3752 pm_runtime_put(component->dev);
3753 return IRQ_HANDLED;
3754 }
3755
wm1811_jackdet_bootstrap(struct work_struct * work)3756 static void wm1811_jackdet_bootstrap(struct work_struct *work)
3757 {
3758 struct wm8994_priv *wm8994 = container_of(work,
3759 struct wm8994_priv,
3760 jackdet_bootstrap.work);
3761 wm1811_jackdet_irq(0, wm8994);
3762 }
3763
3764 /**
3765 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3766 *
3767 * @component: WM8958 component
3768 * @jack: jack to report detection events on
3769 *
3770 * Enable microphone detection functionality for the WM8958. By
3771 * default simple detection which supports the detection of up to 6
3772 * buttons plus video and microphone functionality is supported.
3773 *
3774 * The WM8958 has an advanced jack detection facility which is able to
3775 * support complex accessory detection, especially when used in
3776 * conjunction with external circuitry. In order to provide maximum
3777 * flexiblity a callback is provided which allows a completely custom
3778 * detection algorithm.
3779 */
wm8958_mic_detect(struct snd_soc_component * component,struct snd_soc_jack * jack,wm1811_micdet_cb det_cb,void * det_cb_data,wm1811_mic_id_cb id_cb,void * id_cb_data)3780 int wm8958_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack,
3781 wm1811_micdet_cb det_cb, void *det_cb_data,
3782 wm1811_mic_id_cb id_cb, void *id_cb_data)
3783 {
3784 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3785 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3786 struct wm8994 *control = wm8994->wm8994;
3787 u16 micd_lvl_sel;
3788
3789 switch (control->type) {
3790 case WM1811:
3791 case WM8958:
3792 break;
3793 default:
3794 return -EINVAL;
3795 }
3796
3797 pm_runtime_get_sync(component->dev);
3798
3799 if (jack) {
3800 snd_soc_dapm_force_enable_pin(dapm, "CLK_SYS");
3801 snd_soc_dapm_sync(dapm);
3802
3803 wm8994->micdet[0].jack = jack;
3804
3805 if (det_cb) {
3806 wm8994->micd_cb = det_cb;
3807 wm8994->micd_cb_data = det_cb_data;
3808 } else {
3809 wm8994->mic_detecting = true;
3810 wm8994->jack_mic = false;
3811 }
3812
3813 if (id_cb) {
3814 wm8994->mic_id_cb = id_cb;
3815 wm8994->mic_id_cb_data = id_cb_data;
3816 } else {
3817 wm8994->mic_id_cb = wm8958_mic_id;
3818 wm8994->mic_id_cb_data = component;
3819 }
3820
3821 wm8958_micd_set_rate(component);
3822
3823 /* Detect microphones and short circuits by default */
3824 if (control->pdata.micd_lvl_sel)
3825 micd_lvl_sel = control->pdata.micd_lvl_sel;
3826 else
3827 micd_lvl_sel = 0x41;
3828
3829 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3830 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3831 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3832
3833 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_2,
3834 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3835
3836 WARN_ON(snd_soc_component_get_bias_level(component) > SND_SOC_BIAS_STANDBY);
3837
3838 /*
3839 * If we can use jack detection start off with that,
3840 * otherwise jump straight to microphone detection.
3841 */
3842 if (wm8994->jackdet) {
3843 /* Disable debounce for the initial detect */
3844 snd_soc_component_update_bits(component, WM1811_JACKDET_CTRL,
3845 WM1811_JACKDET_DB, 0);
3846
3847 snd_soc_component_update_bits(component, WM8958_MICBIAS2,
3848 WM8958_MICB2_DISCH,
3849 WM8958_MICB2_DISCH);
3850 snd_soc_component_update_bits(component, WM8994_LDO_1,
3851 WM8994_LDO1_DISCH, 0);
3852 wm1811_jackdet_set_mode(component,
3853 WM1811_JACKDET_MODE_JACK);
3854 } else {
3855 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
3856 WM8958_MICD_ENA, WM8958_MICD_ENA);
3857 }
3858
3859 } else {
3860 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
3861 WM8958_MICD_ENA, 0);
3862 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_NONE);
3863 snd_soc_dapm_disable_pin(dapm, "CLK_SYS");
3864 snd_soc_dapm_sync(dapm);
3865 }
3866
3867 pm_runtime_put(component->dev);
3868
3869 return 0;
3870 }
3871 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3872
wm8958_mic_work(struct work_struct * work)3873 static void wm8958_mic_work(struct work_struct *work)
3874 {
3875 struct wm8994_priv *wm8994 = container_of(work,
3876 struct wm8994_priv,
3877 mic_complete_work.work);
3878 struct snd_soc_component *component = wm8994->hubs.component;
3879
3880 pm_runtime_get_sync(component->dev);
3881
3882 mutex_lock(&wm8994->accdet_lock);
3883
3884 wm8994->mic_id_cb(wm8994->mic_id_cb_data, wm8994->mic_status);
3885
3886 mutex_unlock(&wm8994->accdet_lock);
3887
3888 pm_runtime_put(component->dev);
3889 }
3890
wm8958_mic_irq(int irq,void * data)3891 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3892 {
3893 struct wm8994_priv *wm8994 = data;
3894 struct snd_soc_component *component = wm8994->hubs.component;
3895 int reg, count, ret, id_delay;
3896
3897 /*
3898 * Jack detection may have detected a removal simulataneously
3899 * with an update of the MICDET status; if so it will have
3900 * stopped detection and we can ignore this interrupt.
3901 */
3902 if (!(snd_soc_component_read32(component, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
3903 return IRQ_HANDLED;
3904
3905 cancel_delayed_work_sync(&wm8994->mic_complete_work);
3906 cancel_delayed_work_sync(&wm8994->open_circuit_work);
3907
3908 pm_runtime_get_sync(component->dev);
3909
3910 /* We may occasionally read a detection without an impedence
3911 * range being provided - if that happens loop again.
3912 */
3913 count = 10;
3914 do {
3915 reg = snd_soc_component_read32(component, WM8958_MIC_DETECT_3);
3916 if (reg < 0) {
3917 dev_err(component->dev,
3918 "Failed to read mic detect status: %d\n",
3919 reg);
3920 pm_runtime_put(component->dev);
3921 return IRQ_NONE;
3922 }
3923
3924 if (!(reg & WM8958_MICD_VALID)) {
3925 dev_dbg(component->dev, "Mic detect data not valid\n");
3926 goto out;
3927 }
3928
3929 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3930 break;
3931
3932 msleep(1);
3933 } while (count--);
3934
3935 if (count == 0)
3936 dev_warn(component->dev, "No impedance range reported for jack\n");
3937
3938 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3939 trace_snd_soc_jack_irq(dev_name(component->dev));
3940 #endif
3941
3942 /* Avoid a transient report when the accessory is being removed */
3943 if (wm8994->jackdet) {
3944 ret = snd_soc_component_read32(component, WM1811_JACKDET_CTRL);
3945 if (ret < 0) {
3946 dev_err(component->dev, "Failed to read jack status: %d\n",
3947 ret);
3948 } else if (!(ret & WM1811_JACKDET_LVL)) {
3949 dev_dbg(component->dev, "Ignoring removed jack\n");
3950 goto out;
3951 }
3952 } else if (!(reg & WM8958_MICD_STS)) {
3953 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3954 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3955 wm8994->btn_mask);
3956 wm8994->mic_detecting = true;
3957 goto out;
3958 }
3959
3960 wm8994->mic_status = reg;
3961 id_delay = wm8994->wm8994->pdata.mic_id_delay;
3962
3963 if (wm8994->mic_detecting)
3964 queue_delayed_work(system_power_efficient_wq,
3965 &wm8994->mic_complete_work,
3966 msecs_to_jiffies(id_delay));
3967 else
3968 wm8958_button_det(component, reg);
3969
3970 out:
3971 pm_runtime_put(component->dev);
3972 return IRQ_HANDLED;
3973 }
3974
wm8994_fifo_error(int irq,void * data)3975 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3976 {
3977 struct snd_soc_component *component = data;
3978
3979 dev_err(component->dev, "FIFO error\n");
3980
3981 return IRQ_HANDLED;
3982 }
3983
wm8994_temp_warn(int irq,void * data)3984 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3985 {
3986 struct snd_soc_component *component = data;
3987
3988 dev_err(component->dev, "Thermal warning\n");
3989
3990 return IRQ_HANDLED;
3991 }
3992
wm8994_temp_shut(int irq,void * data)3993 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3994 {
3995 struct snd_soc_component *component = data;
3996
3997 dev_crit(component->dev, "Thermal shutdown\n");
3998
3999 return IRQ_HANDLED;
4000 }
4001
wm8994_component_probe(struct snd_soc_component * component)4002 static int wm8994_component_probe(struct snd_soc_component *component)
4003 {
4004 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
4005 struct wm8994 *control = dev_get_drvdata(component->dev->parent);
4006 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
4007 unsigned int reg;
4008 int ret, i;
4009
4010 snd_soc_component_init_regmap(component, control->regmap);
4011
4012 wm8994->hubs.component = component;
4013
4014 mutex_init(&wm8994->accdet_lock);
4015 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
4016 wm1811_jackdet_bootstrap);
4017 INIT_DELAYED_WORK(&wm8994->open_circuit_work,
4018 wm8958_open_circuit_work);
4019
4020 switch (control->type) {
4021 case WM8994:
4022 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
4023 break;
4024 case WM1811:
4025 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
4026 break;
4027 default:
4028 break;
4029 }
4030
4031 INIT_DELAYED_WORK(&wm8994->mic_complete_work, wm8958_mic_work);
4032
4033 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4034 init_completion(&wm8994->fll_locked[i]);
4035
4036 wm8994->micdet_irq = control->pdata.micdet_irq;
4037
4038 /* By default use idle_bias_off, will override for WM8994 */
4039 dapm->idle_bias_off = 1;
4040
4041 /* Set revision-specific configuration */
4042 switch (control->type) {
4043 case WM8994:
4044 /* Single ended line outputs should have VMID on. */
4045 if (!control->pdata.lineout1_diff ||
4046 !control->pdata.lineout2_diff)
4047 dapm->idle_bias_off = 0;
4048
4049 switch (control->revision) {
4050 case 2:
4051 case 3:
4052 wm8994->hubs.dcs_codes_l = -5;
4053 wm8994->hubs.dcs_codes_r = -5;
4054 wm8994->hubs.hp_startup_mode = 1;
4055 wm8994->hubs.dcs_readback_mode = 1;
4056 wm8994->hubs.series_startup = 1;
4057 break;
4058 default:
4059 wm8994->hubs.dcs_readback_mode = 2;
4060 break;
4061 }
4062 wm8994->hubs.micd_scthr = true;
4063 break;
4064
4065 case WM8958:
4066 wm8994->hubs.dcs_readback_mode = 1;
4067 wm8994->hubs.hp_startup_mode = 1;
4068 wm8994->hubs.micd_scthr = true;
4069
4070 switch (control->revision) {
4071 case 0:
4072 break;
4073 default:
4074 wm8994->fll_byp = true;
4075 break;
4076 }
4077 break;
4078
4079 case WM1811:
4080 wm8994->hubs.dcs_readback_mode = 2;
4081 wm8994->hubs.no_series_update = 1;
4082 wm8994->hubs.hp_startup_mode = 1;
4083 wm8994->hubs.no_cache_dac_hp_direct = true;
4084 wm8994->fll_byp = true;
4085
4086 wm8994->hubs.dcs_codes_l = -9;
4087 wm8994->hubs.dcs_codes_r = -7;
4088
4089 snd_soc_component_update_bits(component, WM8994_ANALOGUE_HP_1,
4090 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
4091 break;
4092
4093 default:
4094 break;
4095 }
4096
4097 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
4098 wm8994_fifo_error, "FIFO error", component);
4099 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
4100 wm8994_temp_warn, "Thermal warning", component);
4101 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
4102 wm8994_temp_shut, "Thermal shutdown", component);
4103
4104 switch (control->type) {
4105 case WM8994:
4106 if (wm8994->micdet_irq)
4107 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4108 wm8994_mic_irq,
4109 IRQF_TRIGGER_RISING |
4110 IRQF_ONESHOT,
4111 "Mic1 detect",
4112 wm8994);
4113 else
4114 ret = wm8994_request_irq(wm8994->wm8994,
4115 WM8994_IRQ_MIC1_DET,
4116 wm8994_mic_irq, "Mic 1 detect",
4117 wm8994);
4118
4119 if (ret != 0)
4120 dev_warn(component->dev,
4121 "Failed to request Mic1 detect IRQ: %d\n",
4122 ret);
4123
4124
4125 ret = wm8994_request_irq(wm8994->wm8994,
4126 WM8994_IRQ_MIC1_SHRT,
4127 wm8994_mic_irq, "Mic 1 short",
4128 wm8994);
4129 if (ret != 0)
4130 dev_warn(component->dev,
4131 "Failed to request Mic1 short IRQ: %d\n",
4132 ret);
4133
4134 ret = wm8994_request_irq(wm8994->wm8994,
4135 WM8994_IRQ_MIC2_DET,
4136 wm8994_mic_irq, "Mic 2 detect",
4137 wm8994);
4138 if (ret != 0)
4139 dev_warn(component->dev,
4140 "Failed to request Mic2 detect IRQ: %d\n",
4141 ret);
4142
4143 ret = wm8994_request_irq(wm8994->wm8994,
4144 WM8994_IRQ_MIC2_SHRT,
4145 wm8994_mic_irq, "Mic 2 short",
4146 wm8994);
4147 if (ret != 0)
4148 dev_warn(component->dev,
4149 "Failed to request Mic2 short IRQ: %d\n",
4150 ret);
4151 break;
4152
4153 case WM8958:
4154 case WM1811:
4155 if (wm8994->micdet_irq) {
4156 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4157 wm8958_mic_irq,
4158 IRQF_TRIGGER_RISING |
4159 IRQF_ONESHOT,
4160 "Mic detect",
4161 wm8994);
4162 if (ret != 0)
4163 dev_warn(component->dev,
4164 "Failed to request Mic detect IRQ: %d\n",
4165 ret);
4166 } else {
4167 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4168 wm8958_mic_irq, "Mic detect",
4169 wm8994);
4170 }
4171 }
4172
4173 switch (control->type) {
4174 case WM1811:
4175 if (control->cust_id > 1 || control->revision > 1) {
4176 ret = wm8994_request_irq(wm8994->wm8994,
4177 WM8994_IRQ_GPIO(6),
4178 wm1811_jackdet_irq, "JACKDET",
4179 wm8994);
4180 if (ret == 0)
4181 wm8994->jackdet = true;
4182 }
4183 break;
4184 default:
4185 break;
4186 }
4187
4188 wm8994->fll_locked_irq = true;
4189 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
4190 ret = wm8994_request_irq(wm8994->wm8994,
4191 WM8994_IRQ_FLL1_LOCK + i,
4192 wm8994_fll_locked_irq, "FLL lock",
4193 &wm8994->fll_locked[i]);
4194 if (ret != 0)
4195 wm8994->fll_locked_irq = false;
4196 }
4197
4198 /* Make sure we can read from the GPIOs if they're inputs */
4199 pm_runtime_get_sync(component->dev);
4200
4201 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
4202 * configured on init - if a system wants to do this dynamically
4203 * at runtime we can deal with that then.
4204 */
4205 ret = regmap_read(control->regmap, WM8994_GPIO_1, ®);
4206 if (ret < 0) {
4207 dev_err(component->dev, "Failed to read GPIO1 state: %d\n", ret);
4208 goto err_irq;
4209 }
4210 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4211 wm8994->lrclk_shared[0] = 1;
4212 wm8994_dai[0].symmetric_rates = 1;
4213 } else {
4214 wm8994->lrclk_shared[0] = 0;
4215 }
4216
4217 ret = regmap_read(control->regmap, WM8994_GPIO_6, ®);
4218 if (ret < 0) {
4219 dev_err(component->dev, "Failed to read GPIO6 state: %d\n", ret);
4220 goto err_irq;
4221 }
4222 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4223 wm8994->lrclk_shared[1] = 1;
4224 wm8994_dai[1].symmetric_rates = 1;
4225 } else {
4226 wm8994->lrclk_shared[1] = 0;
4227 }
4228
4229 pm_runtime_put(component->dev);
4230
4231 /* Latch volume update bits */
4232 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
4233 snd_soc_component_update_bits(component, wm8994_vu_bits[i].reg,
4234 wm8994_vu_bits[i].mask,
4235 wm8994_vu_bits[i].mask);
4236
4237 /* Set the low bit of the 3D stereo depth so TLV matches */
4238 snd_soc_component_update_bits(component, WM8994_AIF1_DAC1_FILTERS_2,
4239 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
4240 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
4241 snd_soc_component_update_bits(component, WM8994_AIF1_DAC2_FILTERS_2,
4242 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
4243 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
4244 snd_soc_component_update_bits(component, WM8994_AIF2_DAC_FILTERS_2,
4245 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
4246 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
4247
4248 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4249 * use this; it only affects behaviour on idle TDM clock
4250 * cycles. */
4251 switch (control->type) {
4252 case WM8994:
4253 case WM8958:
4254 snd_soc_component_update_bits(component, WM8994_AIF1_CONTROL_1,
4255 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4256 break;
4257 default:
4258 break;
4259 }
4260
4261 /* Put MICBIAS into bypass mode by default on newer devices */
4262 switch (control->type) {
4263 case WM8958:
4264 case WM1811:
4265 snd_soc_component_update_bits(component, WM8958_MICBIAS1,
4266 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
4267 snd_soc_component_update_bits(component, WM8958_MICBIAS2,
4268 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
4269 break;
4270 default:
4271 break;
4272 }
4273
4274 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
4275 wm_hubs_update_class_w(component);
4276
4277 wm8994_handle_pdata(wm8994);
4278
4279 wm_hubs_add_analogue_controls(component);
4280 snd_soc_add_component_controls(component, wm8994_common_snd_controls,
4281 ARRAY_SIZE(wm8994_common_snd_controls));
4282 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
4283 ARRAY_SIZE(wm8994_dapm_widgets));
4284
4285 switch (control->type) {
4286 case WM8994:
4287 snd_soc_add_component_controls(component, wm8994_snd_controls,
4288 ARRAY_SIZE(wm8994_snd_controls));
4289 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4290 ARRAY_SIZE(wm8994_specific_dapm_widgets));
4291 if (control->revision < 4) {
4292 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4293 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4294 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4295 ARRAY_SIZE(wm8994_adc_revd_widgets));
4296 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4297 ARRAY_SIZE(wm8994_dac_revd_widgets));
4298 } else {
4299 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4300 ARRAY_SIZE(wm8994_lateclk_widgets));
4301 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4302 ARRAY_SIZE(wm8994_adc_widgets));
4303 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4304 ARRAY_SIZE(wm8994_dac_widgets));
4305 }
4306 break;
4307 case WM8958:
4308 snd_soc_add_component_controls(component, wm8994_snd_controls,
4309 ARRAY_SIZE(wm8994_snd_controls));
4310 snd_soc_add_component_controls(component, wm8958_snd_controls,
4311 ARRAY_SIZE(wm8958_snd_controls));
4312 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4313 ARRAY_SIZE(wm8958_dapm_widgets));
4314 if (control->revision < 1) {
4315 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4316 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4317 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4318 ARRAY_SIZE(wm8994_adc_revd_widgets));
4319 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4320 ARRAY_SIZE(wm8994_dac_revd_widgets));
4321 } else {
4322 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4323 ARRAY_SIZE(wm8994_lateclk_widgets));
4324 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4325 ARRAY_SIZE(wm8994_adc_widgets));
4326 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4327 ARRAY_SIZE(wm8994_dac_widgets));
4328 }
4329 break;
4330
4331 case WM1811:
4332 snd_soc_add_component_controls(component, wm8958_snd_controls,
4333 ARRAY_SIZE(wm8958_snd_controls));
4334 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4335 ARRAY_SIZE(wm8958_dapm_widgets));
4336 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4337 ARRAY_SIZE(wm8994_lateclk_widgets));
4338 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4339 ARRAY_SIZE(wm8994_adc_widgets));
4340 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4341 ARRAY_SIZE(wm8994_dac_widgets));
4342 break;
4343 }
4344
4345 wm_hubs_add_analogue_routes(component, 0, 0);
4346 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4347 wm_hubs_dcs_done, "DC servo done",
4348 &wm8994->hubs);
4349 if (ret == 0)
4350 wm8994->hubs.dcs_done_irq = true;
4351 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
4352
4353 switch (control->type) {
4354 case WM8994:
4355 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4356 ARRAY_SIZE(wm8994_intercon));
4357
4358 if (control->revision < 4) {
4359 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4360 ARRAY_SIZE(wm8994_revd_intercon));
4361 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4362 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4363 } else {
4364 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4365 ARRAY_SIZE(wm8994_lateclk_intercon));
4366 }
4367 break;
4368 case WM8958:
4369 if (control->revision < 1) {
4370 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4371 ARRAY_SIZE(wm8994_intercon));
4372 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4373 ARRAY_SIZE(wm8994_revd_intercon));
4374 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4375 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4376 } else {
4377 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4378 ARRAY_SIZE(wm8994_lateclk_intercon));
4379 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4380 ARRAY_SIZE(wm8958_intercon));
4381 }
4382
4383 wm8958_dsp2_init(component);
4384 break;
4385 case WM1811:
4386 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4387 ARRAY_SIZE(wm8994_lateclk_intercon));
4388 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4389 ARRAY_SIZE(wm8958_intercon));
4390 break;
4391 }
4392
4393 return 0;
4394
4395 err_irq:
4396 if (wm8994->jackdet)
4397 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4398 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4399 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4400 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
4401 if (wm8994->micdet_irq)
4402 free_irq(wm8994->micdet_irq, wm8994);
4403 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4404 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4405 &wm8994->fll_locked[i]);
4406 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4407 &wm8994->hubs);
4408 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, component);
4409 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, component);
4410 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, component);
4411
4412 return ret;
4413 }
4414
wm8994_component_remove(struct snd_soc_component * component)4415 static void wm8994_component_remove(struct snd_soc_component *component)
4416 {
4417 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
4418 struct wm8994 *control = wm8994->wm8994;
4419 int i;
4420
4421 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4422 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4423 &wm8994->fll_locked[i]);
4424
4425 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4426 &wm8994->hubs);
4427 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, component);
4428 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, component);
4429 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, component);
4430
4431 if (wm8994->jackdet)
4432 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4433
4434 switch (control->type) {
4435 case WM8994:
4436 if (wm8994->micdet_irq)
4437 free_irq(wm8994->micdet_irq, wm8994);
4438 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
4439 wm8994);
4440 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
4441 wm8994);
4442 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4443 wm8994);
4444 break;
4445
4446 case WM1811:
4447 case WM8958:
4448 if (wm8994->micdet_irq)
4449 free_irq(wm8994->micdet_irq, wm8994);
4450 break;
4451 }
4452 release_firmware(wm8994->mbc);
4453 release_firmware(wm8994->mbc_vss);
4454 release_firmware(wm8994->enh_eq);
4455 kfree(wm8994->retune_mobile_texts);
4456 }
4457
4458 static const struct snd_soc_component_driver soc_component_dev_wm8994 = {
4459 .probe = wm8994_component_probe,
4460 .remove = wm8994_component_remove,
4461 .suspend = wm8994_component_suspend,
4462 .resume = wm8994_component_resume,
4463 .set_bias_level = wm8994_set_bias_level,
4464 .idle_bias_on = 1,
4465 .use_pmdown_time = 1,
4466 .endianness = 1,
4467 .non_legacy_dai_naming = 1,
4468 };
4469
wm8994_probe(struct platform_device * pdev)4470 static int wm8994_probe(struct platform_device *pdev)
4471 {
4472 struct wm8994_priv *wm8994;
4473
4474 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4475 GFP_KERNEL);
4476 if (wm8994 == NULL)
4477 return -ENOMEM;
4478 platform_set_drvdata(pdev, wm8994);
4479
4480 mutex_init(&wm8994->fw_lock);
4481
4482 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4483
4484 pm_runtime_enable(&pdev->dev);
4485 pm_runtime_idle(&pdev->dev);
4486
4487 return devm_snd_soc_register_component(&pdev->dev, &soc_component_dev_wm8994,
4488 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4489 }
4490
wm8994_remove(struct platform_device * pdev)4491 static int wm8994_remove(struct platform_device *pdev)
4492 {
4493 pm_runtime_disable(&pdev->dev);
4494
4495 return 0;
4496 }
4497
4498 #ifdef CONFIG_PM_SLEEP
wm8994_suspend(struct device * dev)4499 static int wm8994_suspend(struct device *dev)
4500 {
4501 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4502
4503 /* Drop down to power saving mode when system is suspended */
4504 if (wm8994->jackdet && !wm8994->active_refcount)
4505 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4506 WM1811_JACKDET_MODE_MASK,
4507 wm8994->jackdet_mode);
4508
4509 return 0;
4510 }
4511
wm8994_resume(struct device * dev)4512 static int wm8994_resume(struct device *dev)
4513 {
4514 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4515
4516 if (wm8994->jackdet && wm8994->jackdet_mode)
4517 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4518 WM1811_JACKDET_MODE_MASK,
4519 WM1811_JACKDET_MODE_AUDIO);
4520
4521 return 0;
4522 }
4523 #endif
4524
4525 static const struct dev_pm_ops wm8994_pm_ops = {
4526 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4527 };
4528
4529 static struct platform_driver wm8994_codec_driver = {
4530 .driver = {
4531 .name = "wm8994-codec",
4532 .pm = &wm8994_pm_ops,
4533 },
4534 .probe = wm8994_probe,
4535 .remove = wm8994_remove,
4536 };
4537
4538 module_platform_driver(wm8994_codec_driver);
4539
4540 MODULE_DESCRIPTION("ASoC WM8994 driver");
4541 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4542 MODULE_LICENSE("GPL");
4543 MODULE_ALIAS("platform:wm8994-codec");
4544