1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * linux/arch/arm/kernel/entry-armv.S 4 * 5 * Copyright (C) 1996,1997,1998 Russell King. 6 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) 7 * nommu support by Hyok S. Choi (hyok.choi@samsung.com) 8 * 9 * Low-level vector interface routines 10 * 11 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction 12 * that causes it to save wrong values... Be aware! 13 */ 14 15#include <linux/init.h> 16 17#include <asm/assembler.h> 18#include <asm/extable.h> 19#include <asm/memory.h> 20#include <asm/glue-df.h> 21#include <asm/glue-pf.h> 22#include <asm/vfpmacros.h> 23#ifndef CONFIG_GENERIC_IRQ_MULTI_HANDLER 24#include <mach/entry-macro.S> 25#endif 26#include <asm/thread_notify.h> 27#include <asm/unwind.h> 28#include <asm/unistd.h> 29#include <asm/tls.h> 30#include <asm/system_info.h> 31#include <asm/uaccess-asm.h> 32 33#include "entry-header.S" 34#include <asm/entry-macro-multi.S> 35#include <asm/probes.h> 36 37/* 38 * Interrupt handling. 39 */ 40 .macro irq_handler 41#ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER 42 ldr r1, =handle_arch_irq 43 mov r0, sp 44 badr lr, 9997f 45 ldr pc, [r1] 46#else 47 arch_irq_handler_default 48#endif 499997: 50 .endm 51 52 .macro pabt_helper 53 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5 54#ifdef MULTI_PABORT 55 ldr ip, .LCprocfns 56 mov lr, pc 57 ldr pc, [ip, #PROCESSOR_PABT_FUNC] 58#else 59 bl CPU_PABORT_HANDLER 60#endif 61 .endm 62 63 .macro dabt_helper 64 65 @ 66 @ Call the processor-specific abort handler: 67 @ 68 @ r2 - pt_regs 69 @ r4 - aborted context pc 70 @ r5 - aborted context psr 71 @ 72 @ The abort handler must return the aborted address in r0, and 73 @ the fault status register in r1. r9 must be preserved. 74 @ 75#ifdef MULTI_DABORT 76 ldr ip, .LCprocfns 77 mov lr, pc 78 ldr pc, [ip, #PROCESSOR_DABT_FUNC] 79#else 80 bl CPU_DABORT_HANDLER 81#endif 82 .endm 83 84 .section .entry.text,"ax",%progbits 85 86/* 87 * Invalid mode handlers 88 */ 89 .macro inv_entry, reason 90 sub sp, sp, #PT_REGS_SIZE 91 ARM( stmib sp, {r1 - lr} ) 92 THUMB( stmia sp, {r0 - r12} ) 93 THUMB( str sp, [sp, #S_SP] ) 94 THUMB( str lr, [sp, #S_LR] ) 95 mov r1, #\reason 96 .endm 97 98__pabt_invalid: 99 inv_entry BAD_PREFETCH 100 b common_invalid 101ENDPROC(__pabt_invalid) 102 103__dabt_invalid: 104 inv_entry BAD_DATA 105 b common_invalid 106ENDPROC(__dabt_invalid) 107 108__irq_invalid: 109 inv_entry BAD_IRQ 110 b common_invalid 111ENDPROC(__irq_invalid) 112 113__und_invalid: 114 inv_entry BAD_UNDEFINSTR 115 116 @ 117 @ XXX fall through to common_invalid 118 @ 119 120@ 121@ common_invalid - generic code for failed exception (re-entrant version of handlers) 122@ 123common_invalid: 124 zero_fp 125 126 ldmia r0, {r4 - r6} 127 add r0, sp, #S_PC @ here for interlock avoidance 128 mov r7, #-1 @ "" "" "" "" 129 str r4, [sp] @ save preserved r0 130 stmia r0, {r5 - r7} @ lr_<exception>, 131 @ cpsr_<exception>, "old_r0" 132 133 mov r0, sp 134 b bad_mode 135ENDPROC(__und_invalid) 136 137/* 138 * SVC mode handlers 139 */ 140 141#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) 142#define SPFIX(code...) code 143#else 144#define SPFIX(code...) 145#endif 146 147 .macro svc_entry, stack_hole=0, trace=1, uaccess=1 148 UNWIND(.fnstart ) 149 UNWIND(.save {r0 - pc} ) 150 sub sp, sp, #(SVC_REGS_SIZE + \stack_hole - 4) 151#ifdef CONFIG_THUMB2_KERNEL 152 SPFIX( str r0, [sp] ) @ temporarily saved 153 SPFIX( mov r0, sp ) 154 SPFIX( tst r0, #4 ) @ test original stack alignment 155 SPFIX( ldr r0, [sp] ) @ restored 156#else 157 SPFIX( tst sp, #4 ) 158#endif 159 SPFIX( subeq sp, sp, #4 ) 160 stmia sp, {r1 - r12} 161 162 ldmia r0, {r3 - r5} 163 add r7, sp, #S_SP - 4 @ here for interlock avoidance 164 mov r6, #-1 @ "" "" "" "" 165 add r2, sp, #(SVC_REGS_SIZE + \stack_hole - 4) 166 SPFIX( addeq r2, r2, #4 ) 167 str r3, [sp, #-4]! @ save the "real" r0 copied 168 @ from the exception stack 169 170 mov r3, lr 171 172 @ 173 @ We are now ready to fill in the remaining blanks on the stack: 174 @ 175 @ r2 - sp_svc 176 @ r3 - lr_svc 177 @ r4 - lr_<exception>, already fixed up for correct return/restart 178 @ r5 - spsr_<exception> 179 @ r6 - orig_r0 (see pt_regs definition in ptrace.h) 180 @ 181 stmia r7, {r2 - r6} 182 183 get_thread_info tsk 184 uaccess_entry tsk, r0, r1, r2, \uaccess 185 186 .if \trace 187#ifdef CONFIG_TRACE_IRQFLAGS 188 bl trace_hardirqs_off 189#endif 190 .endif 191 .endm 192 193 .align 5 194__dabt_svc: 195 svc_entry uaccess=0 196 mov r2, sp 197 dabt_helper 198 THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR 199 svc_exit r5 @ return from exception 200 UNWIND(.fnend ) 201ENDPROC(__dabt_svc) 202 203 .align 5 204__irq_svc: 205 svc_entry 206 irq_handler 207 208#ifdef CONFIG_PREEMPTION 209 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 210 ldr r0, [tsk, #TI_FLAGS] @ get flags 211 teq r8, #0 @ if preempt count != 0 212 movne r0, #0 @ force flags to 0 213 tst r0, #_TIF_NEED_RESCHED 214 blne svc_preempt 215#endif 216 217 svc_exit r5, irq = 1 @ return from exception 218 UNWIND(.fnend ) 219ENDPROC(__irq_svc) 220 221 .ltorg 222 223#ifdef CONFIG_PREEMPTION 224svc_preempt: 225 mov r8, lr 2261: bl preempt_schedule_irq @ irq en/disable is done inside 227 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS 228 tst r0, #_TIF_NEED_RESCHED 229 reteq r8 @ go again 230 b 1b 231#endif 232 233__und_fault: 234 @ Correct the PC such that it is pointing at the instruction 235 @ which caused the fault. If the faulting instruction was ARM 236 @ the PC will be pointing at the next instruction, and have to 237 @ subtract 4. Otherwise, it is Thumb, and the PC will be 238 @ pointing at the second half of the Thumb instruction. We 239 @ have to subtract 2. 240 ldr r2, [r0, #S_PC] 241 sub r2, r2, r1 242 str r2, [r0, #S_PC] 243 b do_undefinstr 244ENDPROC(__und_fault) 245 246 .align 5 247__und_svc: 248#ifdef CONFIG_KPROBES 249 @ If a kprobe is about to simulate a "stmdb sp..." instruction, 250 @ it obviously needs free stack space which then will belong to 251 @ the saved context. 252 svc_entry MAX_STACK_SIZE 253#else 254 svc_entry 255#endif 256 257 mov r1, #4 @ PC correction to apply 258 THUMB( tst r5, #PSR_T_BIT ) @ exception taken in Thumb mode? 259 THUMB( movne r1, #2 ) @ if so, fix up PC correction 260 mov r0, sp @ struct pt_regs *regs 261 bl __und_fault 262 263__und_svc_finish: 264 get_thread_info tsk 265 ldr r5, [sp, #S_PSR] @ Get SVC cpsr 266 svc_exit r5 @ return from exception 267 UNWIND(.fnend ) 268ENDPROC(__und_svc) 269 270 .align 5 271__pabt_svc: 272 svc_entry 273 mov r2, sp @ regs 274 pabt_helper 275 svc_exit r5 @ return from exception 276 UNWIND(.fnend ) 277ENDPROC(__pabt_svc) 278 279 .align 5 280__fiq_svc: 281 svc_entry trace=0 282 mov r0, sp @ struct pt_regs *regs 283 bl handle_fiq_as_nmi 284 svc_exit_via_fiq 285 UNWIND(.fnend ) 286ENDPROC(__fiq_svc) 287 288 .align 5 289.LCcralign: 290 .word cr_alignment 291#ifdef MULTI_DABORT 292.LCprocfns: 293 .word processor 294#endif 295.LCfp: 296 .word fp_enter 297 298/* 299 * Abort mode handlers 300 */ 301 302@ 303@ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode 304@ and reuses the same macros. However in abort mode we must also 305@ save/restore lr_abt and spsr_abt to make nested aborts safe. 306@ 307 .align 5 308__fiq_abt: 309 svc_entry trace=0 310 311 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 312 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 313 THUMB( msr cpsr_c, r0 ) 314 mov r1, lr @ Save lr_abt 315 mrs r2, spsr @ Save spsr_abt, abort is now safe 316 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 317 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 318 THUMB( msr cpsr_c, r0 ) 319 stmfd sp!, {r1 - r2} 320 321 add r0, sp, #8 @ struct pt_regs *regs 322 bl handle_fiq_as_nmi 323 324 ldmfd sp!, {r1 - r2} 325 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 326 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 327 THUMB( msr cpsr_c, r0 ) 328 mov lr, r1 @ Restore lr_abt, abort is unsafe 329 msr spsr_cxsf, r2 @ Restore spsr_abt 330 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 331 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 332 THUMB( msr cpsr_c, r0 ) 333 334 svc_exit_via_fiq 335 UNWIND(.fnend ) 336ENDPROC(__fiq_abt) 337 338/* 339 * User mode handlers 340 * 341 * EABI note: sp_svc is always 64-bit aligned here, so should PT_REGS_SIZE 342 */ 343 344#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (PT_REGS_SIZE & 7) 345#error "sizeof(struct pt_regs) must be a multiple of 8" 346#endif 347 348 .macro usr_entry, trace=1, uaccess=1 349 UNWIND(.fnstart ) 350 UNWIND(.cantunwind ) @ don't unwind the user space 351 sub sp, sp, #PT_REGS_SIZE 352 ARM( stmib sp, {r1 - r12} ) 353 THUMB( stmia sp, {r0 - r12} ) 354 355 ATRAP( mrc p15, 0, r7, c1, c0, 0) 356 ATRAP( ldr r8, .LCcralign) 357 358 ldmia r0, {r3 - r5} 359 add r0, sp, #S_PC @ here for interlock avoidance 360 mov r6, #-1 @ "" "" "" "" 361 362 str r3, [sp] @ save the "real" r0 copied 363 @ from the exception stack 364 365 ATRAP( ldr r8, [r8, #0]) 366 367 @ 368 @ We are now ready to fill in the remaining blanks on the stack: 369 @ 370 @ r4 - lr_<exception>, already fixed up for correct return/restart 371 @ r5 - spsr_<exception> 372 @ r6 - orig_r0 (see pt_regs definition in ptrace.h) 373 @ 374 @ Also, separately save sp_usr and lr_usr 375 @ 376 stmia r0, {r4 - r6} 377 ARM( stmdb r0, {sp, lr}^ ) 378 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) 379 380 .if \uaccess 381 uaccess_disable ip 382 .endif 383 384 @ Enable the alignment trap while in kernel mode 385 ATRAP( teq r8, r7) 386 ATRAP( mcrne p15, 0, r8, c1, c0, 0) 387 388 @ 389 @ Clear FP to mark the first stack frame 390 @ 391 zero_fp 392 393 .if \trace 394#ifdef CONFIG_TRACE_IRQFLAGS 395 bl trace_hardirqs_off 396#endif 397 ct_user_exit save = 0 398 .endif 399 .endm 400 401 .macro kuser_cmpxchg_check 402#if !defined(CONFIG_CPU_32v6K) && defined(CONFIG_KUSER_HELPERS) 403#ifndef CONFIG_MMU 404#warning "NPTL on non MMU needs fixing" 405#else 406 @ Make sure our user space atomic helper is restarted 407 @ if it was interrupted in a critical region. Here we 408 @ perform a quick test inline since it should be false 409 @ 99.9999% of the time. The rest is done out of line. 410 ldr r0, =TASK_SIZE 411 cmp r4, r0 412 blhs kuser_cmpxchg64_fixup 413#endif 414#endif 415 .endm 416 417 .align 5 418__dabt_usr: 419 usr_entry uaccess=0 420 kuser_cmpxchg_check 421 mov r2, sp 422 dabt_helper 423 b ret_from_exception 424 UNWIND(.fnend ) 425ENDPROC(__dabt_usr) 426 427 .align 5 428__irq_usr: 429 usr_entry 430 kuser_cmpxchg_check 431 irq_handler 432 get_thread_info tsk 433 mov why, #0 434 b ret_to_user_from_irq 435 UNWIND(.fnend ) 436ENDPROC(__irq_usr) 437 438 .ltorg 439 440 .align 5 441__und_usr: 442 usr_entry uaccess=0 443 444 mov r2, r4 445 mov r3, r5 446 447 @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the 448 @ faulting instruction depending on Thumb mode. 449 @ r3 = regs->ARM_cpsr 450 @ 451 @ The emulation code returns using r9 if it has emulated the 452 @ instruction, or the more conventional lr if we are to treat 453 @ this as a real undefined instruction 454 @ 455 badr r9, ret_from_exception 456 457 @ IRQs must be enabled before attempting to read the instruction from 458 @ user space since that could cause a page/translation fault if the 459 @ page table was modified by another CPU. 460 enable_irq 461 462 tst r3, #PSR_T_BIT @ Thumb mode? 463 bne __und_usr_thumb 464 sub r4, r2, #4 @ ARM instr at LR - 4 4651: ldrt r0, [r4] 466 ARM_BE8(rev r0, r0) @ little endian instruction 467 468 uaccess_disable ip 469 470 @ r0 = 32-bit ARM instruction which caused the exception 471 @ r2 = PC value for the following instruction (:= regs->ARM_pc) 472 @ r4 = PC value for the faulting instruction 473 @ lr = 32-bit undefined instruction function 474 badr lr, __und_usr_fault_32 475 b call_fpe 476 477__und_usr_thumb: 478 @ Thumb instruction 479 sub r4, r2, #2 @ First half of thumb instr at LR - 2 480#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 481/* 482 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms 483 * can never be supported in a single kernel, this code is not applicable at 484 * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be 485 * made about .arch directives. 486 */ 487#if __LINUX_ARM_ARCH__ < 7 488/* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */ 489#define NEED_CPU_ARCHITECTURE 490 ldr r5, .LCcpu_architecture 491 ldr r5, [r5] 492 cmp r5, #CPU_ARCH_ARMv7 493 blo __und_usr_fault_16 @ 16bit undefined instruction 494/* 495 * The following code won't get run unless the running CPU really is v7, so 496 * coding round the lack of ldrht on older arches is pointless. Temporarily 497 * override the assembler target arch with the minimum required instead: 498 */ 499 .arch armv6t2 500#endif 5012: ldrht r5, [r4] 502ARM_BE8(rev16 r5, r5) @ little endian instruction 503 cmp r5, #0xe800 @ 32bit instruction if xx != 0 504 blo __und_usr_fault_16_pan @ 16bit undefined instruction 5053: ldrht r0, [r2] 506ARM_BE8(rev16 r0, r0) @ little endian instruction 507 uaccess_disable ip 508 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 509 str r2, [sp, #S_PC] @ it's a 2x16bit instr, update 510 orr r0, r0, r5, lsl #16 511 badr lr, __und_usr_fault_32 512 @ r0 = the two 16-bit Thumb instructions which caused the exception 513 @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc) 514 @ r4 = PC value for the first 16-bit Thumb instruction 515 @ lr = 32bit undefined instruction function 516 517#if __LINUX_ARM_ARCH__ < 7 518/* If the target arch was overridden, change it back: */ 519#ifdef CONFIG_CPU_32v6K 520 .arch armv6k 521#else 522 .arch armv6 523#endif 524#endif /* __LINUX_ARM_ARCH__ < 7 */ 525#else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */ 526 b __und_usr_fault_16 527#endif 528 UNWIND(.fnend) 529ENDPROC(__und_usr) 530 531/* 532 * The out of line fixup for the ldrt instructions above. 533 */ 534 .pushsection .text.fixup, "ax" 535 .align 2 5364: str r4, [sp, #S_PC] @ retry current instruction 537 ret r9 538 .popsection 539 ex_entry 1b, 4b 540#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 541 ex_entry 2b, 4b 542 ex_entry 3b, 4b 543#endif 544 545/* 546 * Check whether the instruction is a co-processor instruction. 547 * If yes, we need to call the relevant co-processor handler. 548 * 549 * Note that we don't do a full check here for the co-processor 550 * instructions; all instructions with bit 27 set are well 551 * defined. The only instructions that should fault are the 552 * co-processor instructions. However, we have to watch out 553 * for the ARM6/ARM7 SWI bug. 554 * 555 * NEON is a special case that has to be handled here. Not all 556 * NEON instructions are co-processor instructions, so we have 557 * to make a special case of checking for them. Plus, there's 558 * five groups of them, so we have a table of mask/opcode pairs 559 * to check against, and if any match then we branch off into the 560 * NEON handler code. 561 * 562 * Emulators may wish to make use of the following registers: 563 * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb) 564 * r2 = PC value to resume execution after successful emulation 565 * r9 = normal "successful" return address 566 * r10 = this threads thread_info structure 567 * lr = unrecognised instruction return address 568 * IRQs enabled, FIQs enabled. 569 */ 570 @ 571 @ Fall-through from Thumb-2 __und_usr 572 @ 573#ifdef CONFIG_NEON 574 get_thread_info r10 @ get current thread 575 adr r6, .LCneon_thumb_opcodes 576 b 2f 577#endif 578call_fpe: 579 get_thread_info r10 @ get current thread 580#ifdef CONFIG_NEON 581 adr r6, .LCneon_arm_opcodes 5822: ldr r5, [r6], #4 @ mask value 583 ldr r7, [r6], #4 @ opcode bits matching in mask 584 cmp r5, #0 @ end mask? 585 beq 1f 586 and r8, r0, r5 587 cmp r8, r7 @ NEON instruction? 588 bne 2b 589 mov r7, #1 590 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used 591 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used 592 b do_vfp @ let VFP handler handle this 5931: 594#endif 595 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 596 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 597 reteq lr 598 and r8, r0, #0x00000f00 @ mask out CP number 599 THUMB( lsr r8, r8, #8 ) 600 mov r7, #1 601 add r6, r10, #TI_USED_CP 602 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[] 603 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[] 604#ifdef CONFIG_IWMMXT 605 @ Test if we need to give access to iWMMXt coprocessors 606 ldr r5, [r10, #TI_FLAGS] 607 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only 608 movscs r7, r5, lsr #(TIF_USING_IWMMXT + 1) 609 bcs iwmmxt_task_enable 610#endif 611 ARM( add pc, pc, r8, lsr #6 ) 612 THUMB( lsl r8, r8, #2 ) 613 THUMB( add pc, r8 ) 614 nop 615 616 ret.w lr @ CP#0 617 W(b) do_fpe @ CP#1 (FPE) 618 W(b) do_fpe @ CP#2 (FPE) 619 ret.w lr @ CP#3 620#ifdef CONFIG_CRUNCH 621 b crunch_task_enable @ CP#4 (MaverickCrunch) 622 b crunch_task_enable @ CP#5 (MaverickCrunch) 623 b crunch_task_enable @ CP#6 (MaverickCrunch) 624#else 625 ret.w lr @ CP#4 626 ret.w lr @ CP#5 627 ret.w lr @ CP#6 628#endif 629 ret.w lr @ CP#7 630 ret.w lr @ CP#8 631 ret.w lr @ CP#9 632#ifdef CONFIG_VFP 633 W(b) do_vfp @ CP#10 (VFP) 634 W(b) do_vfp @ CP#11 (VFP) 635#else 636 ret.w lr @ CP#10 (VFP) 637 ret.w lr @ CP#11 (VFP) 638#endif 639 ret.w lr @ CP#12 640 ret.w lr @ CP#13 641 ret.w lr @ CP#14 (Debug) 642 ret.w lr @ CP#15 (Control) 643 644#ifdef NEED_CPU_ARCHITECTURE 645 .align 2 646.LCcpu_architecture: 647 .word __cpu_architecture 648#endif 649 650#ifdef CONFIG_NEON 651 .align 6 652 653.LCneon_arm_opcodes: 654 .word 0xfe000000 @ mask 655 .word 0xf2000000 @ opcode 656 657 .word 0xff100000 @ mask 658 .word 0xf4000000 @ opcode 659 660 .word 0x00000000 @ mask 661 .word 0x00000000 @ opcode 662 663.LCneon_thumb_opcodes: 664 .word 0xef000000 @ mask 665 .word 0xef000000 @ opcode 666 667 .word 0xff100000 @ mask 668 .word 0xf9000000 @ opcode 669 670 .word 0x00000000 @ mask 671 .word 0x00000000 @ opcode 672#endif 673 674do_fpe: 675 ldr r4, .LCfp 676 add r10, r10, #TI_FPSTATE @ r10 = workspace 677 ldr pc, [r4] @ Call FP module USR entry point 678 679/* 680 * The FP module is called with these registers set: 681 * r0 = instruction 682 * r2 = PC+4 683 * r9 = normal "successful" return address 684 * r10 = FP workspace 685 * lr = unrecognised FP instruction return address 686 */ 687 688 .pushsection .data 689 .align 2 690ENTRY(fp_enter) 691 .word no_fp 692 .popsection 693 694ENTRY(no_fp) 695 ret lr 696ENDPROC(no_fp) 697 698__und_usr_fault_32: 699 mov r1, #4 700 b 1f 701__und_usr_fault_16_pan: 702 uaccess_disable ip 703__und_usr_fault_16: 704 mov r1, #2 7051: mov r0, sp 706 badr lr, ret_from_exception 707 b __und_fault 708ENDPROC(__und_usr_fault_32) 709ENDPROC(__und_usr_fault_16) 710 711 .align 5 712__pabt_usr: 713 usr_entry 714 mov r2, sp @ regs 715 pabt_helper 716 UNWIND(.fnend ) 717 /* fall through */ 718/* 719 * This is the return code to user mode for abort handlers 720 */ 721ENTRY(ret_from_exception) 722 UNWIND(.fnstart ) 723 UNWIND(.cantunwind ) 724 get_thread_info tsk 725 mov why, #0 726 b ret_to_user 727 UNWIND(.fnend ) 728ENDPROC(__pabt_usr) 729ENDPROC(ret_from_exception) 730 731 .align 5 732__fiq_usr: 733 usr_entry trace=0 734 kuser_cmpxchg_check 735 mov r0, sp @ struct pt_regs *regs 736 bl handle_fiq_as_nmi 737 get_thread_info tsk 738 restore_user_regs fast = 0, offset = 0 739 UNWIND(.fnend ) 740ENDPROC(__fiq_usr) 741 742/* 743 * Register switch for ARMv3 and ARMv4 processors 744 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info 745 * previous and next are guaranteed not to be the same. 746 */ 747ENTRY(__switch_to) 748 UNWIND(.fnstart ) 749 UNWIND(.cantunwind ) 750 add ip, r1, #TI_CPU_SAVE 751 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack 752 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack 753 THUMB( str sp, [ip], #4 ) 754 THUMB( str lr, [ip], #4 ) 755 ldr r4, [r2, #TI_TP_VALUE] 756 ldr r5, [r2, #TI_TP_VALUE + 4] 757#ifdef CONFIG_CPU_USE_DOMAINS 758 mrc p15, 0, r6, c3, c0, 0 @ Get domain register 759 str r6, [r1, #TI_CPU_DOMAIN] @ Save old domain register 760 ldr r6, [r2, #TI_CPU_DOMAIN] 761#endif 762 switch_tls r1, r4, r5, r3, r7 763#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP) 764 ldr r7, [r2, #TI_TASK] 765 ldr r8, =__stack_chk_guard 766 .if (TSK_STACK_CANARY > IMM12_MASK) 767 add r7, r7, #TSK_STACK_CANARY & ~IMM12_MASK 768 .endif 769 ldr r7, [r7, #TSK_STACK_CANARY & IMM12_MASK] 770#endif 771#ifdef CONFIG_CPU_USE_DOMAINS 772 mcr p15, 0, r6, c3, c0, 0 @ Set domain register 773#endif 774 mov r5, r0 775 add r4, r2, #TI_CPU_SAVE 776 ldr r0, =thread_notify_head 777 mov r1, #THREAD_NOTIFY_SWITCH 778 bl atomic_notifier_call_chain 779#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP) 780 str r7, [r8] 781#endif 782 THUMB( mov ip, r4 ) 783 mov r0, r5 784 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously 785 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously 786 THUMB( ldr sp, [ip], #4 ) 787 THUMB( ldr pc, [ip] ) 788 UNWIND(.fnend ) 789ENDPROC(__switch_to) 790 791 __INIT 792 793/* 794 * User helpers. 795 * 796 * Each segment is 32-byte aligned and will be moved to the top of the high 797 * vector page. New segments (if ever needed) must be added in front of 798 * existing ones. This mechanism should be used only for things that are 799 * really small and justified, and not be abused freely. 800 * 801 * See Documentation/arm/kernel_user_helpers.rst for formal definitions. 802 */ 803 THUMB( .arm ) 804 805 .macro usr_ret, reg 806#ifdef CONFIG_ARM_THUMB 807 bx \reg 808#else 809 ret \reg 810#endif 811 .endm 812 813 .macro kuser_pad, sym, size 814 .if (. - \sym) & 3 815 .rept 4 - (. - \sym) & 3 816 .byte 0 817 .endr 818 .endif 819 .rept (\size - (. - \sym)) / 4 820 .word 0xe7fddef1 821 .endr 822 .endm 823 824#ifdef CONFIG_KUSER_HELPERS 825 .align 5 826 .globl __kuser_helper_start 827__kuser_helper_start: 828 829/* 830 * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular 831 * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point. 832 */ 833 834__kuser_cmpxchg64: @ 0xffff0f60 835 836#if defined(CONFIG_CPU_32v6K) 837 838 stmfd sp!, {r4, r5, r6, r7} 839 ldrd r4, r5, [r0] @ load old val 840 ldrd r6, r7, [r1] @ load new val 841 smp_dmb arm 8421: ldrexd r0, r1, [r2] @ load current val 843 eors r3, r0, r4 @ compare with oldval (1) 844 eorseq r3, r1, r5 @ compare with oldval (2) 845 strexdeq r3, r6, r7, [r2] @ store newval if eq 846 teqeq r3, #1 @ success? 847 beq 1b @ if no then retry 848 smp_dmb arm 849 rsbs r0, r3, #0 @ set returned val and C flag 850 ldmfd sp!, {r4, r5, r6, r7} 851 usr_ret lr 852 853#elif !defined(CONFIG_SMP) 854 855#ifdef CONFIG_MMU 856 857 /* 858 * The only thing that can break atomicity in this cmpxchg64 859 * implementation is either an IRQ or a data abort exception 860 * causing another process/thread to be scheduled in the middle of 861 * the critical sequence. The same strategy as for cmpxchg is used. 862 */ 863 stmfd sp!, {r4, r5, r6, lr} 864 ldmia r0, {r4, r5} @ load old val 865 ldmia r1, {r6, lr} @ load new val 8661: ldmia r2, {r0, r1} @ load current val 867 eors r3, r0, r4 @ compare with oldval (1) 868 eorseq r3, r1, r5 @ compare with oldval (2) 8692: stmiaeq r2, {r6, lr} @ store newval if eq 870 rsbs r0, r3, #0 @ set return val and C flag 871 ldmfd sp!, {r4, r5, r6, pc} 872 873 .text 874kuser_cmpxchg64_fixup: 875 @ Called from kuser_cmpxchg_fixup. 876 @ r4 = address of interrupted insn (must be preserved). 877 @ sp = saved regs. r7 and r8 are clobbered. 878 @ 1b = first critical insn, 2b = last critical insn. 879 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. 880 mov r7, #0xffff0fff 881 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64))) 882 subs r8, r4, r7 883 rsbscs r8, r8, #(2b - 1b) 884 strcs r7, [sp, #S_PC] 885#if __LINUX_ARM_ARCH__ < 6 886 bcc kuser_cmpxchg32_fixup 887#endif 888 ret lr 889 .previous 890 891#else 892#warning "NPTL on non MMU needs fixing" 893 mov r0, #-1 894 adds r0, r0, #0 895 usr_ret lr 896#endif 897 898#else 899#error "incoherent kernel configuration" 900#endif 901 902 kuser_pad __kuser_cmpxchg64, 64 903 904__kuser_memory_barrier: @ 0xffff0fa0 905 smp_dmb arm 906 usr_ret lr 907 908 kuser_pad __kuser_memory_barrier, 32 909 910__kuser_cmpxchg: @ 0xffff0fc0 911 912#if __LINUX_ARM_ARCH__ < 6 913 914#ifdef CONFIG_MMU 915 916 /* 917 * The only thing that can break atomicity in this cmpxchg 918 * implementation is either an IRQ or a data abort exception 919 * causing another process/thread to be scheduled in the middle 920 * of the critical sequence. To prevent this, code is added to 921 * the IRQ and data abort exception handlers to set the pc back 922 * to the beginning of the critical section if it is found to be 923 * within that critical section (see kuser_cmpxchg_fixup). 924 */ 9251: ldr r3, [r2] @ load current val 926 subs r3, r3, r0 @ compare with oldval 9272: streq r1, [r2] @ store newval if eq 928 rsbs r0, r3, #0 @ set return val and C flag 929 usr_ret lr 930 931 .text 932kuser_cmpxchg32_fixup: 933 @ Called from kuser_cmpxchg_check macro. 934 @ r4 = address of interrupted insn (must be preserved). 935 @ sp = saved regs. r7 and r8 are clobbered. 936 @ 1b = first critical insn, 2b = last critical insn. 937 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. 938 mov r7, #0xffff0fff 939 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) 940 subs r8, r4, r7 941 rsbscs r8, r8, #(2b - 1b) 942 strcs r7, [sp, #S_PC] 943 ret lr 944 .previous 945 946#else 947#warning "NPTL on non MMU needs fixing" 948 mov r0, #-1 949 adds r0, r0, #0 950 usr_ret lr 951#endif 952 953#else 954 955 smp_dmb arm 9561: ldrex r3, [r2] 957 subs r3, r3, r0 958 strexeq r3, r1, [r2] 959 teqeq r3, #1 960 beq 1b 961 rsbs r0, r3, #0 962 /* beware -- each __kuser slot must be 8 instructions max */ 963 ALT_SMP(b __kuser_memory_barrier) 964 ALT_UP(usr_ret lr) 965 966#endif 967 968 kuser_pad __kuser_cmpxchg, 32 969 970__kuser_get_tls: @ 0xffff0fe0 971 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init 972 usr_ret lr 973 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code 974 kuser_pad __kuser_get_tls, 16 975 .rep 3 976 .word 0 @ 0xffff0ff0 software TLS value, then 977 .endr @ pad up to __kuser_helper_version 978 979__kuser_helper_version: @ 0xffff0ffc 980 .word ((__kuser_helper_end - __kuser_helper_start) >> 5) 981 982 .globl __kuser_helper_end 983__kuser_helper_end: 984 985#endif 986 987 THUMB( .thumb ) 988 989/* 990 * Vector stubs. 991 * 992 * This code is copied to 0xffff1000 so we can use branches in the 993 * vectors, rather than ldr's. Note that this code must not exceed 994 * a page size. 995 * 996 * Common stub entry macro: 997 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 998 * 999 * SP points to a minimal amount of processor-private memory, the address 1000 * of which is copied into r0 for the mode specific abort handler. 1001 */ 1002 .macro vector_stub, name, mode, correction=0 1003 .align 5 1004 1005.Lvector_\name: 1006 .if \correction 1007 sub lr, lr, #\correction 1008 .endif 1009 1010 @ Save r0, lr_<exception> (parent PC) 1011 stmia sp, {r0, lr} @ save r0, lr 1012 1013 @ Save spsr_<exception> (parent CPSR) 10142: mrs lr, spsr 1015 str lr, [sp, #8] @ save spsr 1016 1017 @ 1018 @ Prepare for SVC32 mode. IRQs remain disabled. 1019 @ 1020 mrs r0, cpsr 1021 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) 1022 msr spsr_cxsf, r0 1023 1024 @ 1025 @ the branch table must immediately follow this code 1026 @ 1027 and lr, lr, #0x0f 1028 THUMB( adr r0, 1f ) 1029 THUMB( ldr lr, [r0, lr, lsl #2] ) 1030 mov r0, sp 1031 ARM( ldr lr, [pc, lr, lsl #2] ) 1032 movs pc, lr @ branch to handler in SVC mode 1033ENDPROC(.Lvector_\name) 1034 1035#ifdef CONFIG_HARDEN_BRANCH_HISTORY 1036 .subsection 1 1037 .align 5 1038vector_bhb_loop8_\name: 1039 .if \correction 1040 sub lr, lr, #\correction 1041 .endif 1042 1043 @ Save r0, lr_<exception> (parent PC) 1044 stmia sp, {r0, lr} 1045 1046 @ bhb workaround 1047 mov r0, #8 10483: b . + 4 1049 subs r0, r0, #1 1050 bne 3b 1051 dsb 1052 isb 1053 b 2b 1054ENDPROC(vector_bhb_loop8_\name) 1055 1056vector_bhb_bpiall_\name: 1057 .if \correction 1058 sub lr, lr, #\correction 1059 .endif 1060 1061 @ Save r0, lr_<exception> (parent PC) 1062 stmia sp, {r0, lr} 1063 1064 @ bhb workaround 1065 mcr p15, 0, r0, c7, c5, 6 @ BPIALL 1066 @ isb not needed due to "movs pc, lr" in the vector stub 1067 @ which gives a "context synchronisation". 1068 b 2b 1069ENDPROC(vector_bhb_bpiall_\name) 1070 .previous 1071#endif 1072 1073 .align 2 1074 @ handler addresses follow this label 10751: 1076 .endm 1077 1078 .section .stubs, "ax", %progbits 1079#ifdef CONFIG_FIQ 1080 .global vector_fiq_offset 1081 .set vector_fiq_offset, .Lvector_fiq - . + 0x1000 1082#endif 1083 @ This must be the first word 1084 .word vector_swi 1085#ifdef CONFIG_HARDEN_BRANCH_HISTORY 1086 .word vector_bhb_loop8_swi 1087 .word vector_bhb_bpiall_swi 1088#endif 1089 1090.Lvector_rst: 1091 ARM( swi SYS_ERROR0 ) 1092 THUMB( svc #0 ) 1093 THUMB( nop ) 1094 b .Lvector_und 1095 1096/* 1097 * Interrupt dispatcher 1098 */ 1099 vector_stub irq, IRQ_MODE, 4 1100 1101 .long __irq_usr @ 0 (USR_26 / USR_32) 1102 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) 1103 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) 1104 .long __irq_svc @ 3 (SVC_26 / SVC_32) 1105 .long __irq_invalid @ 4 1106 .long __irq_invalid @ 5 1107 .long __irq_invalid @ 6 1108 .long __irq_invalid @ 7 1109 .long __irq_invalid @ 8 1110 .long __irq_invalid @ 9 1111 .long __irq_invalid @ a 1112 .long __irq_invalid @ b 1113 .long __irq_invalid @ c 1114 .long __irq_invalid @ d 1115 .long __irq_invalid @ e 1116 .long __irq_invalid @ f 1117 1118/* 1119 * Data abort dispatcher 1120 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1121 */ 1122 vector_stub dabt, ABT_MODE, 8 1123 1124 .long __dabt_usr @ 0 (USR_26 / USR_32) 1125 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) 1126 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) 1127 .long __dabt_svc @ 3 (SVC_26 / SVC_32) 1128 .long __dabt_invalid @ 4 1129 .long __dabt_invalid @ 5 1130 .long __dabt_invalid @ 6 1131 .long __dabt_invalid @ 7 1132 .long __dabt_invalid @ 8 1133 .long __dabt_invalid @ 9 1134 .long __dabt_invalid @ a 1135 .long __dabt_invalid @ b 1136 .long __dabt_invalid @ c 1137 .long __dabt_invalid @ d 1138 .long __dabt_invalid @ e 1139 .long __dabt_invalid @ f 1140 1141/* 1142 * Prefetch abort dispatcher 1143 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1144 */ 1145 vector_stub pabt, ABT_MODE, 4 1146 1147 .long __pabt_usr @ 0 (USR_26 / USR_32) 1148 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) 1149 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) 1150 .long __pabt_svc @ 3 (SVC_26 / SVC_32) 1151 .long __pabt_invalid @ 4 1152 .long __pabt_invalid @ 5 1153 .long __pabt_invalid @ 6 1154 .long __pabt_invalid @ 7 1155 .long __pabt_invalid @ 8 1156 .long __pabt_invalid @ 9 1157 .long __pabt_invalid @ a 1158 .long __pabt_invalid @ b 1159 .long __pabt_invalid @ c 1160 .long __pabt_invalid @ d 1161 .long __pabt_invalid @ e 1162 .long __pabt_invalid @ f 1163 1164/* 1165 * Undef instr entry dispatcher 1166 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1167 */ 1168 vector_stub und, UND_MODE 1169 1170 .long __und_usr @ 0 (USR_26 / USR_32) 1171 .long __und_invalid @ 1 (FIQ_26 / FIQ_32) 1172 .long __und_invalid @ 2 (IRQ_26 / IRQ_32) 1173 .long __und_svc @ 3 (SVC_26 / SVC_32) 1174 .long __und_invalid @ 4 1175 .long __und_invalid @ 5 1176 .long __und_invalid @ 6 1177 .long __und_invalid @ 7 1178 .long __und_invalid @ 8 1179 .long __und_invalid @ 9 1180 .long __und_invalid @ a 1181 .long __und_invalid @ b 1182 .long __und_invalid @ c 1183 .long __und_invalid @ d 1184 .long __und_invalid @ e 1185 .long __und_invalid @ f 1186 1187 .align 5 1188 1189/*============================================================================= 1190 * Address exception handler 1191 *----------------------------------------------------------------------------- 1192 * These aren't too critical. 1193 * (they're not supposed to happen, and won't happen in 32-bit data mode). 1194 */ 1195 1196.Lvector_addrexcptn: 1197 b .Lvector_addrexcptn 1198 1199/*============================================================================= 1200 * FIQ "NMI" handler 1201 *----------------------------------------------------------------------------- 1202 * Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86 1203 * systems. This must be the last vector stub, so lets place it in its own 1204 * subsection. 1205 */ 1206 .subsection 2 1207 vector_stub fiq, FIQ_MODE, 4 1208 1209 .long __fiq_usr @ 0 (USR_26 / USR_32) 1210 .long __fiq_svc @ 1 (FIQ_26 / FIQ_32) 1211 .long __fiq_svc @ 2 (IRQ_26 / IRQ_32) 1212 .long __fiq_svc @ 3 (SVC_26 / SVC_32) 1213 .long __fiq_svc @ 4 1214 .long __fiq_svc @ 5 1215 .long __fiq_svc @ 6 1216 .long __fiq_abt @ 7 1217 .long __fiq_svc @ 8 1218 .long __fiq_svc @ 9 1219 .long __fiq_svc @ a 1220 .long __fiq_svc @ b 1221 .long __fiq_svc @ c 1222 .long __fiq_svc @ d 1223 .long __fiq_svc @ e 1224 .long __fiq_svc @ f 1225 1226 .section .vectors, "ax", %progbits 1227.L__vectors_start: 1228 W(b) .Lvector_rst 1229 W(b) .Lvector_und 1230 W(ldr) pc, .L__vectors_start + 0x1000 1231 W(b) .Lvector_pabt 1232 W(b) .Lvector_dabt 1233 W(b) .Lvector_addrexcptn 1234 W(b) .Lvector_irq 1235 W(b) .Lvector_fiq 1236 1237#ifdef CONFIG_HARDEN_BRANCH_HISTORY 1238 .section .vectors.bhb.loop8, "ax", %progbits 1239.L__vectors_bhb_loop8_start: 1240 W(b) .Lvector_rst 1241 W(b) vector_bhb_loop8_und 1242 W(ldr) pc, .L__vectors_bhb_loop8_start + 0x1004 1243 W(b) vector_bhb_loop8_pabt 1244 W(b) vector_bhb_loop8_dabt 1245 W(b) .Lvector_addrexcptn 1246 W(b) vector_bhb_loop8_irq 1247 W(b) vector_bhb_loop8_fiq 1248 1249 .section .vectors.bhb.bpiall, "ax", %progbits 1250.L__vectors_bhb_bpiall_start: 1251 W(b) .Lvector_rst 1252 W(b) vector_bhb_bpiall_und 1253 W(ldr) pc, .L__vectors_bhb_bpiall_start + 0x1008 1254 W(b) vector_bhb_bpiall_pabt 1255 W(b) vector_bhb_bpiall_dabt 1256 W(b) .Lvector_addrexcptn 1257 W(b) vector_bhb_bpiall_irq 1258 W(b) vector_bhb_bpiall_fiq 1259#endif 1260 1261 .data 1262 .align 2 1263 1264 .globl cr_alignment 1265cr_alignment: 1266 .space 4 1267