1 /*
2 * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
3 *
4 * Copyright (C) {2012} Texas Instruments Incorporated - https://www.ti.com/
5 *
6 * This file is automatically generated from the AM33XX hardware databases.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include "omap_hwmod.h"
18 #include "omap_hwmod_common_data.h"
19
20 #include "control.h"
21 #include "cm33xx.h"
22 #include "prm33xx.h"
23 #include "prm-regbits-33xx.h"
24 #include "omap_hwmod_33xx_43xx_common_data.h"
25
26 /*
27 * IP blocks
28 */
29
30 /* emif */
31 static struct omap_hwmod am33xx_emif_hwmod = {
32 .name = "emif",
33 .class = &am33xx_emif_hwmod_class,
34 .clkdm_name = "l3_clkdm",
35 .flags = HWMOD_INIT_NO_IDLE,
36 .main_clk = "dpll_ddr_m2_div2_ck",
37 .prcm = {
38 .omap4 = {
39 .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
40 .modulemode = MODULEMODE_SWCTRL,
41 },
42 },
43 };
44
45 /* l4_hs */
46 static struct omap_hwmod am33xx_l4_hs_hwmod = {
47 .name = "l4_hs",
48 .class = &am33xx_l4_hwmod_class,
49 .clkdm_name = "l4hs_clkdm",
50 .flags = HWMOD_INIT_NO_IDLE,
51 .main_clk = "l4hs_gclk",
52 .prcm = {
53 .omap4 = {
54 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
55 .modulemode = MODULEMODE_SWCTRL,
56 },
57 },
58 };
59
60 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
61 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
62 };
63
64 /* wkup_m3 */
65 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
66 .name = "wkup_m3",
67 .class = &am33xx_wkup_m3_hwmod_class,
68 .clkdm_name = "l4_wkup_aon_clkdm",
69 /* Keep hardreset asserted */
70 .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
71 .main_clk = "dpll_core_m4_div2_ck",
72 .prcm = {
73 .omap4 = {
74 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
75 .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
76 .rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET,
77 .modulemode = MODULEMODE_SWCTRL,
78 },
79 },
80 .rst_lines = am33xx_wkup_m3_resets,
81 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
82 };
83
84
85 /*
86 * Modules omap_hwmod structures
87 *
88 * The following IPs are excluded for the moment because:
89 * - They do not need an explicit SW control using omap_hwmod API.
90 * - They still need to be validated with the driver
91 * properly adapted to omap_hwmod / omap_device
92 *
93 * - cEFUSE (doesn't fall under any ocp_if)
94 * - clkdiv32k
95 * - ocp watch point
96 */
97 #if 0
98 /*
99 * 'cefuse' class
100 */
101 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
102 .name = "cefuse",
103 };
104
105 static struct omap_hwmod am33xx_cefuse_hwmod = {
106 .name = "cefuse",
107 .class = &am33xx_cefuse_hwmod_class,
108 .clkdm_name = "l4_cefuse_clkdm",
109 .main_clk = "cefuse_fck",
110 .prcm = {
111 .omap4 = {
112 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
113 .modulemode = MODULEMODE_SWCTRL,
114 },
115 },
116 };
117
118 /*
119 * 'clkdiv32k' class
120 */
121 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
122 .name = "clkdiv32k",
123 };
124
125 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
126 .name = "clkdiv32k",
127 .class = &am33xx_clkdiv32k_hwmod_class,
128 .clkdm_name = "clk_24mhz_clkdm",
129 .main_clk = "clkdiv32k_ick",
130 .prcm = {
131 .omap4 = {
132 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
133 .modulemode = MODULEMODE_SWCTRL,
134 },
135 },
136 };
137
138 /* ocpwp */
139 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
140 .name = "ocpwp",
141 };
142
143 static struct omap_hwmod am33xx_ocpwp_hwmod = {
144 .name = "ocpwp",
145 .class = &am33xx_ocpwp_hwmod_class,
146 .clkdm_name = "l4ls_clkdm",
147 .main_clk = "l4ls_gclk",
148 .prcm = {
149 .omap4 = {
150 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
151 .modulemode = MODULEMODE_SWCTRL,
152 },
153 },
154 };
155 #endif
156
157 /*
158 * 'debugss' class
159 * debug sub system
160 */
161 static struct omap_hwmod_opt_clk debugss_opt_clks[] = {
162 { .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" },
163 { .role = "dbg_clka", .clk = "dbg_clka_ck" },
164 };
165
166 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
167 .name = "debugss",
168 };
169
170 static struct omap_hwmod am33xx_debugss_hwmod = {
171 .name = "debugss",
172 .class = &am33xx_debugss_hwmod_class,
173 .clkdm_name = "l3_aon_clkdm",
174 .main_clk = "trace_clk_div_ck",
175 .prcm = {
176 .omap4 = {
177 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
178 .modulemode = MODULEMODE_SWCTRL,
179 },
180 },
181 .opt_clks = debugss_opt_clks,
182 .opt_clks_cnt = ARRAY_SIZE(debugss_opt_clks),
183 };
184
185 static struct omap_hwmod am33xx_control_hwmod = {
186 .name = "control",
187 .class = &am33xx_control_hwmod_class,
188 .clkdm_name = "l4_wkup_clkdm",
189 .flags = HWMOD_INIT_NO_IDLE,
190 .main_clk = "dpll_core_m4_div2_ck",
191 .prcm = {
192 .omap4 = {
193 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
194 .modulemode = MODULEMODE_SWCTRL,
195 },
196 },
197 };
198
199
200 /*
201 * Interfaces
202 */
203
204 /* l3 main -> emif */
205 static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
206 .master = &am33xx_l3_main_hwmod,
207 .slave = &am33xx_emif_hwmod,
208 .clk = "dpll_core_m4_ck",
209 .user = OCP_USER_MPU | OCP_USER_SDMA,
210 };
211
212 /* l3 main -> l4 hs */
213 static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
214 .master = &am33xx_l3_main_hwmod,
215 .slave = &am33xx_l4_hs_hwmod,
216 .clk = "l3s_gclk",
217 .user = OCP_USER_MPU | OCP_USER_SDMA,
218 };
219
220 /* wkup m3 -> l4 wkup */
221 static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
222 .master = &am33xx_wkup_m3_hwmod,
223 .slave = &am33xx_l4_wkup_hwmod,
224 .clk = "dpll_core_m4_div2_ck",
225 .user = OCP_USER_MPU | OCP_USER_SDMA,
226 };
227
228 /* l4 wkup -> wkup m3 */
229 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
230 .master = &am33xx_l4_wkup_hwmod,
231 .slave = &am33xx_wkup_m3_hwmod,
232 .clk = "dpll_core_m4_div2_ck",
233 .user = OCP_USER_MPU | OCP_USER_SDMA,
234 };
235
236 /* l3_main -> debugss */
237 static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
238 .master = &am33xx_l3_main_hwmod,
239 .slave = &am33xx_debugss_hwmod,
240 .clk = "dpll_core_m4_ck",
241 .user = OCP_USER_MPU,
242 };
243
244 /* l4 wkup -> smartreflex0 */
245 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
246 .master = &am33xx_l4_wkup_hwmod,
247 .slave = &am33xx_smartreflex0_hwmod,
248 .clk = "dpll_core_m4_div2_ck",
249 .user = OCP_USER_MPU,
250 };
251
252 /* l4 wkup -> smartreflex1 */
253 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
254 .master = &am33xx_l4_wkup_hwmod,
255 .slave = &am33xx_smartreflex1_hwmod,
256 .clk = "dpll_core_m4_div2_ck",
257 .user = OCP_USER_MPU,
258 };
259
260 /* l4 wkup -> control */
261 static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
262 .master = &am33xx_l4_wkup_hwmod,
263 .slave = &am33xx_control_hwmod,
264 .clk = "dpll_core_m4_div2_ck",
265 .user = OCP_USER_MPU,
266 };
267
268 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
269 &am33xx_l3_main__emif,
270 &am33xx_mpu__l3_main,
271 &am33xx_mpu__prcm,
272 &am33xx_l3_s__l4_ls,
273 &am33xx_l3_s__l4_wkup,
274 &am33xx_l3_main__l4_hs,
275 &am33xx_l3_main__l3_s,
276 &am33xx_l3_main__l3_instr,
277 &am33xx_l3_s__l3_main,
278 &am33xx_wkup_m3__l4_wkup,
279 &am33xx_l3_main__debugss,
280 &am33xx_l4_wkup__wkup_m3,
281 &am33xx_l4_wkup__control,
282 &am33xx_l4_wkup__smartreflex0,
283 &am33xx_l4_wkup__smartreflex1,
284 &am33xx_l3_s__gpmc,
285 &am33xx_l3_main__ocmc,
286 NULL,
287 };
288
am33xx_hwmod_init(void)289 int __init am33xx_hwmod_init(void)
290 {
291 omap_hwmod_am33xx_reg();
292 omap_hwmod_init();
293 return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
294 }
295