1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Per core/cpu state
4 *
5 * Used to coordinate shared registers between HT threads or
6 * among events on a single PMU.
7 */
8
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11 #include <linux/stddef.h>
12 #include <linux/types.h>
13 #include <linux/init.h>
14 #include <linux/slab.h>
15 #include <linux/export.h>
16 #include <linux/nmi.h>
17
18 #include <asm/cpufeature.h>
19 #include <asm/hardirq.h>
20 #include <asm/intel-family.h>
21 #include <asm/intel_pt.h>
22 #include <asm/apic.h>
23 #include <asm/cpu_device_id.h>
24
25 #include "../perf_event.h"
26
27 /*
28 * Intel PerfMon, used on Core and later.
29 */
30 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
31 {
32 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
33 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
34 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
35 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
36 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
37 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
38 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
39 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
40 };
41
42 static struct event_constraint intel_core_event_constraints[] __read_mostly =
43 {
44 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
45 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
46 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
47 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
48 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
49 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
50 EVENT_CONSTRAINT_END
51 };
52
53 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
54 {
55 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
56 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
57 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
58 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
59 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
60 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
61 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
62 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
63 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
64 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
65 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
66 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
67 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
68 EVENT_CONSTRAINT_END
69 };
70
71 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
72 {
73 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
74 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
75 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
76 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
77 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
78 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
79 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
80 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
81 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
82 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
83 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
84 EVENT_CONSTRAINT_END
85 };
86
87 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
88 {
89 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
90 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
91 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
92 EVENT_EXTRA_END
93 };
94
95 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
96 {
97 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
98 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
99 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
100 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
101 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
102 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
103 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
104 EVENT_CONSTRAINT_END
105 };
106
107 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
108 {
109 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
110 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
111 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
112 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
113 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
114 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
115 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
116 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
117 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
118 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
119 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
120 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
121
122 /*
123 * When HT is off these events can only run on the bottom 4 counters
124 * When HT is on, they are impacted by the HT bug and require EXCL access
125 */
126 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
127 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
128 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
129 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
130
131 EVENT_CONSTRAINT_END
132 };
133
134 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
135 {
136 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
137 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
138 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
139 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
140 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
141 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
142 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
143 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
144 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
145 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
146 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
147 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
148 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
149
150 /*
151 * When HT is off these events can only run on the bottom 4 counters
152 * When HT is on, they are impacted by the HT bug and require EXCL access
153 */
154 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
155 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
156 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
157 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
158
159 EVENT_CONSTRAINT_END
160 };
161
162 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
163 {
164 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
165 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
166 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
167 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
168 EVENT_EXTRA_END
169 };
170
171 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
172 {
173 EVENT_CONSTRAINT_END
174 };
175
176 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
177 {
178 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
179 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
180 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
181 EVENT_CONSTRAINT_END
182 };
183
184 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
185 {
186 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
187 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
188 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
189 EVENT_CONSTRAINT_END
190 };
191
192 static struct event_constraint intel_skl_event_constraints[] = {
193 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
194 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
195 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
196 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
197
198 /*
199 * when HT is off, these can only run on the bottom 4 counters
200 */
201 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
202 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
203 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
204 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
205 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */
206
207 EVENT_CONSTRAINT_END
208 };
209
210 static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
211 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
212 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
213 EVENT_EXTRA_END
214 };
215
216 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
217 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
218 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
219 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
220 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
221 EVENT_EXTRA_END
222 };
223
224 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
225 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
226 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
227 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
228 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
229 EVENT_EXTRA_END
230 };
231
232 static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
233 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
234 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
235 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
236 /*
237 * Note the low 8 bits eventsel code is not a continuous field, containing
238 * some #GPing bits. These are masked out.
239 */
240 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
241 EVENT_EXTRA_END
242 };
243
244 static struct event_constraint intel_icl_event_constraints[] = {
245 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
246 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* INST_RETIRED.PREC_DIST */
247 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
248 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
249 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
250 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
251 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
252 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
253 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
254 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf),
255 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf),
256 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */
257 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x54, 0xf),
258 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf),
259 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */
260 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */
261 INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */
262 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */
263 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf),
264 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf),
265 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf),
266 INTEL_EVENT_CONSTRAINT(0xef, 0xf),
267 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf),
268 EVENT_CONSTRAINT_END
269 };
270
271 static struct extra_reg intel_icl_extra_regs[] __read_mostly = {
272 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0),
273 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1),
274 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
275 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
276 EVENT_EXTRA_END
277 };
278
279 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
280 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
281 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
282
283 static struct attribute *nhm_mem_events_attrs[] = {
284 EVENT_PTR(mem_ld_nhm),
285 NULL,
286 };
287
288 /*
289 * topdown events for Intel Core CPUs.
290 *
291 * The events are all in slots, which is a free slot in a 4 wide
292 * pipeline. Some events are already reported in slots, for cycle
293 * events we multiply by the pipeline width (4).
294 *
295 * With Hyper Threading on, topdown metrics are either summed or averaged
296 * between the threads of a core: (count_t0 + count_t1).
297 *
298 * For the average case the metric is always scaled to pipeline width,
299 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4)
300 */
301
302 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots,
303 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */
304 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */
305 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2");
306 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued,
307 "event=0xe,umask=0x1"); /* uops_issued.any */
308 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired,
309 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */
310 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles,
311 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */
312 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles,
313 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */
314 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */
315 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale,
316 "4", "2");
317
318 EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4");
319 EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80");
320 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81");
321 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82");
322 EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83");
323
324 static struct attribute *snb_events_attrs[] = {
325 EVENT_PTR(td_slots_issued),
326 EVENT_PTR(td_slots_retired),
327 EVENT_PTR(td_fetch_bubbles),
328 EVENT_PTR(td_total_slots),
329 EVENT_PTR(td_total_slots_scale),
330 EVENT_PTR(td_recovery_bubbles),
331 EVENT_PTR(td_recovery_bubbles_scale),
332 NULL,
333 };
334
335 static struct attribute *snb_mem_events_attrs[] = {
336 EVENT_PTR(mem_ld_snb),
337 EVENT_PTR(mem_st_snb),
338 NULL,
339 };
340
341 static struct event_constraint intel_hsw_event_constraints[] = {
342 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
343 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
344 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
345 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
346 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
347 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
348 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
349 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
350 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
351 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
352 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
353 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
354
355 /*
356 * When HT is off these events can only run on the bottom 4 counters
357 * When HT is on, they are impacted by the HT bug and require EXCL access
358 */
359 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
360 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
361 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
362 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
363
364 EVENT_CONSTRAINT_END
365 };
366
367 static struct event_constraint intel_bdw_event_constraints[] = {
368 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
369 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
370 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
371 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
372 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
373 /*
374 * when HT is off, these can only run on the bottom 4 counters
375 */
376 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
377 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
378 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
379 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
380 EVENT_CONSTRAINT_END
381 };
382
intel_pmu_event_map(int hw_event)383 static u64 intel_pmu_event_map(int hw_event)
384 {
385 return intel_perfmon_event_map[hw_event];
386 }
387
388 /*
389 * Notes on the events:
390 * - data reads do not include code reads (comparable to earlier tables)
391 * - data counts include speculative execution (except L1 write, dtlb, bpu)
392 * - remote node access includes remote memory, remote cache, remote mmio.
393 * - prefetches are not included in the counts.
394 * - icache miss does not include decoded icache
395 */
396
397 #define SKL_DEMAND_DATA_RD BIT_ULL(0)
398 #define SKL_DEMAND_RFO BIT_ULL(1)
399 #define SKL_ANY_RESPONSE BIT_ULL(16)
400 #define SKL_SUPPLIER_NONE BIT_ULL(17)
401 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
402 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
403 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
404 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
405 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
406 SKL_L3_MISS_REMOTE_HOP0_DRAM| \
407 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
408 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
409 #define SKL_SPL_HIT BIT_ULL(30)
410 #define SKL_SNOOP_NONE BIT_ULL(31)
411 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
412 #define SKL_SNOOP_MISS BIT_ULL(33)
413 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
414 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
415 #define SKL_SNOOP_HITM BIT_ULL(36)
416 #define SKL_SNOOP_NON_DRAM BIT_ULL(37)
417 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
418 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
419 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
420 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
421 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
422 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
423 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
424 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
425 SKL_SNOOP_HITM|SKL_SPL_HIT)
426 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO
427 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE
428 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
429 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
430 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
431
432 static __initconst const u64 skl_hw_cache_event_ids
433 [PERF_COUNT_HW_CACHE_MAX]
434 [PERF_COUNT_HW_CACHE_OP_MAX]
435 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
436 {
437 [ C(L1D ) ] = {
438 [ C(OP_READ) ] = {
439 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
440 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
441 },
442 [ C(OP_WRITE) ] = {
443 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
444 [ C(RESULT_MISS) ] = 0x0,
445 },
446 [ C(OP_PREFETCH) ] = {
447 [ C(RESULT_ACCESS) ] = 0x0,
448 [ C(RESULT_MISS) ] = 0x0,
449 },
450 },
451 [ C(L1I ) ] = {
452 [ C(OP_READ) ] = {
453 [ C(RESULT_ACCESS) ] = 0x0,
454 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
455 },
456 [ C(OP_WRITE) ] = {
457 [ C(RESULT_ACCESS) ] = -1,
458 [ C(RESULT_MISS) ] = -1,
459 },
460 [ C(OP_PREFETCH) ] = {
461 [ C(RESULT_ACCESS) ] = 0x0,
462 [ C(RESULT_MISS) ] = 0x0,
463 },
464 },
465 [ C(LL ) ] = {
466 [ C(OP_READ) ] = {
467 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
468 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
469 },
470 [ C(OP_WRITE) ] = {
471 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
472 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
473 },
474 [ C(OP_PREFETCH) ] = {
475 [ C(RESULT_ACCESS) ] = 0x0,
476 [ C(RESULT_MISS) ] = 0x0,
477 },
478 },
479 [ C(DTLB) ] = {
480 [ C(OP_READ) ] = {
481 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
482 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
483 },
484 [ C(OP_WRITE) ] = {
485 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
486 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
487 },
488 [ C(OP_PREFETCH) ] = {
489 [ C(RESULT_ACCESS) ] = 0x0,
490 [ C(RESULT_MISS) ] = 0x0,
491 },
492 },
493 [ C(ITLB) ] = {
494 [ C(OP_READ) ] = {
495 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
496 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
497 },
498 [ C(OP_WRITE) ] = {
499 [ C(RESULT_ACCESS) ] = -1,
500 [ C(RESULT_MISS) ] = -1,
501 },
502 [ C(OP_PREFETCH) ] = {
503 [ C(RESULT_ACCESS) ] = -1,
504 [ C(RESULT_MISS) ] = -1,
505 },
506 },
507 [ C(BPU ) ] = {
508 [ C(OP_READ) ] = {
509 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
510 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
511 },
512 [ C(OP_WRITE) ] = {
513 [ C(RESULT_ACCESS) ] = -1,
514 [ C(RESULT_MISS) ] = -1,
515 },
516 [ C(OP_PREFETCH) ] = {
517 [ C(RESULT_ACCESS) ] = -1,
518 [ C(RESULT_MISS) ] = -1,
519 },
520 },
521 [ C(NODE) ] = {
522 [ C(OP_READ) ] = {
523 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
524 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
525 },
526 [ C(OP_WRITE) ] = {
527 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
528 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
529 },
530 [ C(OP_PREFETCH) ] = {
531 [ C(RESULT_ACCESS) ] = 0x0,
532 [ C(RESULT_MISS) ] = 0x0,
533 },
534 },
535 };
536
537 static __initconst const u64 skl_hw_cache_extra_regs
538 [PERF_COUNT_HW_CACHE_MAX]
539 [PERF_COUNT_HW_CACHE_OP_MAX]
540 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
541 {
542 [ C(LL ) ] = {
543 [ C(OP_READ) ] = {
544 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
545 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
546 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
547 SKL_L3_MISS|SKL_ANY_SNOOP|
548 SKL_SUPPLIER_NONE,
549 },
550 [ C(OP_WRITE) ] = {
551 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
552 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
553 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
554 SKL_L3_MISS|SKL_ANY_SNOOP|
555 SKL_SUPPLIER_NONE,
556 },
557 [ C(OP_PREFETCH) ] = {
558 [ C(RESULT_ACCESS) ] = 0x0,
559 [ C(RESULT_MISS) ] = 0x0,
560 },
561 },
562 [ C(NODE) ] = {
563 [ C(OP_READ) ] = {
564 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
565 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
566 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
567 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
568 },
569 [ C(OP_WRITE) ] = {
570 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
571 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
572 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
573 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
574 },
575 [ C(OP_PREFETCH) ] = {
576 [ C(RESULT_ACCESS) ] = 0x0,
577 [ C(RESULT_MISS) ] = 0x0,
578 },
579 },
580 };
581
582 #define SNB_DMND_DATA_RD (1ULL << 0)
583 #define SNB_DMND_RFO (1ULL << 1)
584 #define SNB_DMND_IFETCH (1ULL << 2)
585 #define SNB_DMND_WB (1ULL << 3)
586 #define SNB_PF_DATA_RD (1ULL << 4)
587 #define SNB_PF_RFO (1ULL << 5)
588 #define SNB_PF_IFETCH (1ULL << 6)
589 #define SNB_LLC_DATA_RD (1ULL << 7)
590 #define SNB_LLC_RFO (1ULL << 8)
591 #define SNB_LLC_IFETCH (1ULL << 9)
592 #define SNB_BUS_LOCKS (1ULL << 10)
593 #define SNB_STRM_ST (1ULL << 11)
594 #define SNB_OTHER (1ULL << 15)
595 #define SNB_RESP_ANY (1ULL << 16)
596 #define SNB_NO_SUPP (1ULL << 17)
597 #define SNB_LLC_HITM (1ULL << 18)
598 #define SNB_LLC_HITE (1ULL << 19)
599 #define SNB_LLC_HITS (1ULL << 20)
600 #define SNB_LLC_HITF (1ULL << 21)
601 #define SNB_LOCAL (1ULL << 22)
602 #define SNB_REMOTE (0xffULL << 23)
603 #define SNB_SNP_NONE (1ULL << 31)
604 #define SNB_SNP_NOT_NEEDED (1ULL << 32)
605 #define SNB_SNP_MISS (1ULL << 33)
606 #define SNB_NO_FWD (1ULL << 34)
607 #define SNB_SNP_FWD (1ULL << 35)
608 #define SNB_HITM (1ULL << 36)
609 #define SNB_NON_DRAM (1ULL << 37)
610
611 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
612 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
613 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
614
615 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
616 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
617 SNB_HITM)
618
619 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
620 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
621
622 #define SNB_L3_ACCESS SNB_RESP_ANY
623 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
624
625 static __initconst const u64 snb_hw_cache_extra_regs
626 [PERF_COUNT_HW_CACHE_MAX]
627 [PERF_COUNT_HW_CACHE_OP_MAX]
628 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
629 {
630 [ C(LL ) ] = {
631 [ C(OP_READ) ] = {
632 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
633 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
634 },
635 [ C(OP_WRITE) ] = {
636 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
637 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
638 },
639 [ C(OP_PREFETCH) ] = {
640 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
641 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
642 },
643 },
644 [ C(NODE) ] = {
645 [ C(OP_READ) ] = {
646 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
647 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
648 },
649 [ C(OP_WRITE) ] = {
650 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
651 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
652 },
653 [ C(OP_PREFETCH) ] = {
654 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
655 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
656 },
657 },
658 };
659
660 static __initconst const u64 snb_hw_cache_event_ids
661 [PERF_COUNT_HW_CACHE_MAX]
662 [PERF_COUNT_HW_CACHE_OP_MAX]
663 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
664 {
665 [ C(L1D) ] = {
666 [ C(OP_READ) ] = {
667 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
668 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
669 },
670 [ C(OP_WRITE) ] = {
671 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
672 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
673 },
674 [ C(OP_PREFETCH) ] = {
675 [ C(RESULT_ACCESS) ] = 0x0,
676 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
677 },
678 },
679 [ C(L1I ) ] = {
680 [ C(OP_READ) ] = {
681 [ C(RESULT_ACCESS) ] = 0x0,
682 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
683 },
684 [ C(OP_WRITE) ] = {
685 [ C(RESULT_ACCESS) ] = -1,
686 [ C(RESULT_MISS) ] = -1,
687 },
688 [ C(OP_PREFETCH) ] = {
689 [ C(RESULT_ACCESS) ] = 0x0,
690 [ C(RESULT_MISS) ] = 0x0,
691 },
692 },
693 [ C(LL ) ] = {
694 [ C(OP_READ) ] = {
695 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
696 [ C(RESULT_ACCESS) ] = 0x01b7,
697 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
698 [ C(RESULT_MISS) ] = 0x01b7,
699 },
700 [ C(OP_WRITE) ] = {
701 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
702 [ C(RESULT_ACCESS) ] = 0x01b7,
703 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
704 [ C(RESULT_MISS) ] = 0x01b7,
705 },
706 [ C(OP_PREFETCH) ] = {
707 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
708 [ C(RESULT_ACCESS) ] = 0x01b7,
709 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
710 [ C(RESULT_MISS) ] = 0x01b7,
711 },
712 },
713 [ C(DTLB) ] = {
714 [ C(OP_READ) ] = {
715 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
716 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
717 },
718 [ C(OP_WRITE) ] = {
719 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
720 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
721 },
722 [ C(OP_PREFETCH) ] = {
723 [ C(RESULT_ACCESS) ] = 0x0,
724 [ C(RESULT_MISS) ] = 0x0,
725 },
726 },
727 [ C(ITLB) ] = {
728 [ C(OP_READ) ] = {
729 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
730 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
731 },
732 [ C(OP_WRITE) ] = {
733 [ C(RESULT_ACCESS) ] = -1,
734 [ C(RESULT_MISS) ] = -1,
735 },
736 [ C(OP_PREFETCH) ] = {
737 [ C(RESULT_ACCESS) ] = -1,
738 [ C(RESULT_MISS) ] = -1,
739 },
740 },
741 [ C(BPU ) ] = {
742 [ C(OP_READ) ] = {
743 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
744 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
745 },
746 [ C(OP_WRITE) ] = {
747 [ C(RESULT_ACCESS) ] = -1,
748 [ C(RESULT_MISS) ] = -1,
749 },
750 [ C(OP_PREFETCH) ] = {
751 [ C(RESULT_ACCESS) ] = -1,
752 [ C(RESULT_MISS) ] = -1,
753 },
754 },
755 [ C(NODE) ] = {
756 [ C(OP_READ) ] = {
757 [ C(RESULT_ACCESS) ] = 0x01b7,
758 [ C(RESULT_MISS) ] = 0x01b7,
759 },
760 [ C(OP_WRITE) ] = {
761 [ C(RESULT_ACCESS) ] = 0x01b7,
762 [ C(RESULT_MISS) ] = 0x01b7,
763 },
764 [ C(OP_PREFETCH) ] = {
765 [ C(RESULT_ACCESS) ] = 0x01b7,
766 [ C(RESULT_MISS) ] = 0x01b7,
767 },
768 },
769
770 };
771
772 /*
773 * Notes on the events:
774 * - data reads do not include code reads (comparable to earlier tables)
775 * - data counts include speculative execution (except L1 write, dtlb, bpu)
776 * - remote node access includes remote memory, remote cache, remote mmio.
777 * - prefetches are not included in the counts because they are not
778 * reliably counted.
779 */
780
781 #define HSW_DEMAND_DATA_RD BIT_ULL(0)
782 #define HSW_DEMAND_RFO BIT_ULL(1)
783 #define HSW_ANY_RESPONSE BIT_ULL(16)
784 #define HSW_SUPPLIER_NONE BIT_ULL(17)
785 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
786 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
787 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
788 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
789 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
790 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
791 HSW_L3_MISS_REMOTE_HOP2P)
792 #define HSW_SNOOP_NONE BIT_ULL(31)
793 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
794 #define HSW_SNOOP_MISS BIT_ULL(33)
795 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
796 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
797 #define HSW_SNOOP_HITM BIT_ULL(36)
798 #define HSW_SNOOP_NON_DRAM BIT_ULL(37)
799 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
800 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
801 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
802 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
803 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
804 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
805 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO
806 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
807 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
808 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE
809
810 #define BDW_L3_MISS_LOCAL BIT(26)
811 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
812 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
813 HSW_L3_MISS_REMOTE_HOP2P)
814
815
816 static __initconst const u64 hsw_hw_cache_event_ids
817 [PERF_COUNT_HW_CACHE_MAX]
818 [PERF_COUNT_HW_CACHE_OP_MAX]
819 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
820 {
821 [ C(L1D ) ] = {
822 [ C(OP_READ) ] = {
823 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
824 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
825 },
826 [ C(OP_WRITE) ] = {
827 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
828 [ C(RESULT_MISS) ] = 0x0,
829 },
830 [ C(OP_PREFETCH) ] = {
831 [ C(RESULT_ACCESS) ] = 0x0,
832 [ C(RESULT_MISS) ] = 0x0,
833 },
834 },
835 [ C(L1I ) ] = {
836 [ C(OP_READ) ] = {
837 [ C(RESULT_ACCESS) ] = 0x0,
838 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
839 },
840 [ C(OP_WRITE) ] = {
841 [ C(RESULT_ACCESS) ] = -1,
842 [ C(RESULT_MISS) ] = -1,
843 },
844 [ C(OP_PREFETCH) ] = {
845 [ C(RESULT_ACCESS) ] = 0x0,
846 [ C(RESULT_MISS) ] = 0x0,
847 },
848 },
849 [ C(LL ) ] = {
850 [ C(OP_READ) ] = {
851 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
852 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
853 },
854 [ C(OP_WRITE) ] = {
855 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
856 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
857 },
858 [ C(OP_PREFETCH) ] = {
859 [ C(RESULT_ACCESS) ] = 0x0,
860 [ C(RESULT_MISS) ] = 0x0,
861 },
862 },
863 [ C(DTLB) ] = {
864 [ C(OP_READ) ] = {
865 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
866 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
867 },
868 [ C(OP_WRITE) ] = {
869 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
870 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
871 },
872 [ C(OP_PREFETCH) ] = {
873 [ C(RESULT_ACCESS) ] = 0x0,
874 [ C(RESULT_MISS) ] = 0x0,
875 },
876 },
877 [ C(ITLB) ] = {
878 [ C(OP_READ) ] = {
879 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
880 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
881 },
882 [ C(OP_WRITE) ] = {
883 [ C(RESULT_ACCESS) ] = -1,
884 [ C(RESULT_MISS) ] = -1,
885 },
886 [ C(OP_PREFETCH) ] = {
887 [ C(RESULT_ACCESS) ] = -1,
888 [ C(RESULT_MISS) ] = -1,
889 },
890 },
891 [ C(BPU ) ] = {
892 [ C(OP_READ) ] = {
893 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
894 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
895 },
896 [ C(OP_WRITE) ] = {
897 [ C(RESULT_ACCESS) ] = -1,
898 [ C(RESULT_MISS) ] = -1,
899 },
900 [ C(OP_PREFETCH) ] = {
901 [ C(RESULT_ACCESS) ] = -1,
902 [ C(RESULT_MISS) ] = -1,
903 },
904 },
905 [ C(NODE) ] = {
906 [ C(OP_READ) ] = {
907 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
908 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
909 },
910 [ C(OP_WRITE) ] = {
911 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
912 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
913 },
914 [ C(OP_PREFETCH) ] = {
915 [ C(RESULT_ACCESS) ] = 0x0,
916 [ C(RESULT_MISS) ] = 0x0,
917 },
918 },
919 };
920
921 static __initconst const u64 hsw_hw_cache_extra_regs
922 [PERF_COUNT_HW_CACHE_MAX]
923 [PERF_COUNT_HW_CACHE_OP_MAX]
924 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
925 {
926 [ C(LL ) ] = {
927 [ C(OP_READ) ] = {
928 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
929 HSW_LLC_ACCESS,
930 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
931 HSW_L3_MISS|HSW_ANY_SNOOP,
932 },
933 [ C(OP_WRITE) ] = {
934 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
935 HSW_LLC_ACCESS,
936 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
937 HSW_L3_MISS|HSW_ANY_SNOOP,
938 },
939 [ C(OP_PREFETCH) ] = {
940 [ C(RESULT_ACCESS) ] = 0x0,
941 [ C(RESULT_MISS) ] = 0x0,
942 },
943 },
944 [ C(NODE) ] = {
945 [ C(OP_READ) ] = {
946 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
947 HSW_L3_MISS_LOCAL_DRAM|
948 HSW_SNOOP_DRAM,
949 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
950 HSW_L3_MISS_REMOTE|
951 HSW_SNOOP_DRAM,
952 },
953 [ C(OP_WRITE) ] = {
954 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
955 HSW_L3_MISS_LOCAL_DRAM|
956 HSW_SNOOP_DRAM,
957 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
958 HSW_L3_MISS_REMOTE|
959 HSW_SNOOP_DRAM,
960 },
961 [ C(OP_PREFETCH) ] = {
962 [ C(RESULT_ACCESS) ] = 0x0,
963 [ C(RESULT_MISS) ] = 0x0,
964 },
965 },
966 };
967
968 static __initconst const u64 westmere_hw_cache_event_ids
969 [PERF_COUNT_HW_CACHE_MAX]
970 [PERF_COUNT_HW_CACHE_OP_MAX]
971 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
972 {
973 [ C(L1D) ] = {
974 [ C(OP_READ) ] = {
975 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
976 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
977 },
978 [ C(OP_WRITE) ] = {
979 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
980 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
981 },
982 [ C(OP_PREFETCH) ] = {
983 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
984 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
985 },
986 },
987 [ C(L1I ) ] = {
988 [ C(OP_READ) ] = {
989 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
990 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
991 },
992 [ C(OP_WRITE) ] = {
993 [ C(RESULT_ACCESS) ] = -1,
994 [ C(RESULT_MISS) ] = -1,
995 },
996 [ C(OP_PREFETCH) ] = {
997 [ C(RESULT_ACCESS) ] = 0x0,
998 [ C(RESULT_MISS) ] = 0x0,
999 },
1000 },
1001 [ C(LL ) ] = {
1002 [ C(OP_READ) ] = {
1003 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1004 [ C(RESULT_ACCESS) ] = 0x01b7,
1005 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1006 [ C(RESULT_MISS) ] = 0x01b7,
1007 },
1008 /*
1009 * Use RFO, not WRITEBACK, because a write miss would typically occur
1010 * on RFO.
1011 */
1012 [ C(OP_WRITE) ] = {
1013 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1014 [ C(RESULT_ACCESS) ] = 0x01b7,
1015 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1016 [ C(RESULT_MISS) ] = 0x01b7,
1017 },
1018 [ C(OP_PREFETCH) ] = {
1019 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1020 [ C(RESULT_ACCESS) ] = 0x01b7,
1021 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1022 [ C(RESULT_MISS) ] = 0x01b7,
1023 },
1024 },
1025 [ C(DTLB) ] = {
1026 [ C(OP_READ) ] = {
1027 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1028 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1029 },
1030 [ C(OP_WRITE) ] = {
1031 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1032 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1033 },
1034 [ C(OP_PREFETCH) ] = {
1035 [ C(RESULT_ACCESS) ] = 0x0,
1036 [ C(RESULT_MISS) ] = 0x0,
1037 },
1038 },
1039 [ C(ITLB) ] = {
1040 [ C(OP_READ) ] = {
1041 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1042 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
1043 },
1044 [ C(OP_WRITE) ] = {
1045 [ C(RESULT_ACCESS) ] = -1,
1046 [ C(RESULT_MISS) ] = -1,
1047 },
1048 [ C(OP_PREFETCH) ] = {
1049 [ C(RESULT_ACCESS) ] = -1,
1050 [ C(RESULT_MISS) ] = -1,
1051 },
1052 },
1053 [ C(BPU ) ] = {
1054 [ C(OP_READ) ] = {
1055 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1056 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1057 },
1058 [ C(OP_WRITE) ] = {
1059 [ C(RESULT_ACCESS) ] = -1,
1060 [ C(RESULT_MISS) ] = -1,
1061 },
1062 [ C(OP_PREFETCH) ] = {
1063 [ C(RESULT_ACCESS) ] = -1,
1064 [ C(RESULT_MISS) ] = -1,
1065 },
1066 },
1067 [ C(NODE) ] = {
1068 [ C(OP_READ) ] = {
1069 [ C(RESULT_ACCESS) ] = 0x01b7,
1070 [ C(RESULT_MISS) ] = 0x01b7,
1071 },
1072 [ C(OP_WRITE) ] = {
1073 [ C(RESULT_ACCESS) ] = 0x01b7,
1074 [ C(RESULT_MISS) ] = 0x01b7,
1075 },
1076 [ C(OP_PREFETCH) ] = {
1077 [ C(RESULT_ACCESS) ] = 0x01b7,
1078 [ C(RESULT_MISS) ] = 0x01b7,
1079 },
1080 },
1081 };
1082
1083 /*
1084 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
1085 * See IA32 SDM Vol 3B 30.6.1.3
1086 */
1087
1088 #define NHM_DMND_DATA_RD (1 << 0)
1089 #define NHM_DMND_RFO (1 << 1)
1090 #define NHM_DMND_IFETCH (1 << 2)
1091 #define NHM_DMND_WB (1 << 3)
1092 #define NHM_PF_DATA_RD (1 << 4)
1093 #define NHM_PF_DATA_RFO (1 << 5)
1094 #define NHM_PF_IFETCH (1 << 6)
1095 #define NHM_OFFCORE_OTHER (1 << 7)
1096 #define NHM_UNCORE_HIT (1 << 8)
1097 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
1098 #define NHM_OTHER_CORE_HITM (1 << 10)
1099 /* reserved */
1100 #define NHM_REMOTE_CACHE_FWD (1 << 12)
1101 #define NHM_REMOTE_DRAM (1 << 13)
1102 #define NHM_LOCAL_DRAM (1 << 14)
1103 #define NHM_NON_DRAM (1 << 15)
1104
1105 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
1106 #define NHM_REMOTE (NHM_REMOTE_DRAM)
1107
1108 #define NHM_DMND_READ (NHM_DMND_DATA_RD)
1109 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
1110 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
1111
1112 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
1113 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
1114 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
1115
1116 static __initconst const u64 nehalem_hw_cache_extra_regs
1117 [PERF_COUNT_HW_CACHE_MAX]
1118 [PERF_COUNT_HW_CACHE_OP_MAX]
1119 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1120 {
1121 [ C(LL ) ] = {
1122 [ C(OP_READ) ] = {
1123 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1124 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
1125 },
1126 [ C(OP_WRITE) ] = {
1127 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1128 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
1129 },
1130 [ C(OP_PREFETCH) ] = {
1131 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1132 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1133 },
1134 },
1135 [ C(NODE) ] = {
1136 [ C(OP_READ) ] = {
1137 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1138 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
1139 },
1140 [ C(OP_WRITE) ] = {
1141 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1142 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
1143 },
1144 [ C(OP_PREFETCH) ] = {
1145 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1146 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1147 },
1148 },
1149 };
1150
1151 static __initconst const u64 nehalem_hw_cache_event_ids
1152 [PERF_COUNT_HW_CACHE_MAX]
1153 [PERF_COUNT_HW_CACHE_OP_MAX]
1154 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1155 {
1156 [ C(L1D) ] = {
1157 [ C(OP_READ) ] = {
1158 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1159 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1160 },
1161 [ C(OP_WRITE) ] = {
1162 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1163 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1164 },
1165 [ C(OP_PREFETCH) ] = {
1166 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1167 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1168 },
1169 },
1170 [ C(L1I ) ] = {
1171 [ C(OP_READ) ] = {
1172 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1173 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1174 },
1175 [ C(OP_WRITE) ] = {
1176 [ C(RESULT_ACCESS) ] = -1,
1177 [ C(RESULT_MISS) ] = -1,
1178 },
1179 [ C(OP_PREFETCH) ] = {
1180 [ C(RESULT_ACCESS) ] = 0x0,
1181 [ C(RESULT_MISS) ] = 0x0,
1182 },
1183 },
1184 [ C(LL ) ] = {
1185 [ C(OP_READ) ] = {
1186 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1187 [ C(RESULT_ACCESS) ] = 0x01b7,
1188 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1189 [ C(RESULT_MISS) ] = 0x01b7,
1190 },
1191 /*
1192 * Use RFO, not WRITEBACK, because a write miss would typically occur
1193 * on RFO.
1194 */
1195 [ C(OP_WRITE) ] = {
1196 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1197 [ C(RESULT_ACCESS) ] = 0x01b7,
1198 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1199 [ C(RESULT_MISS) ] = 0x01b7,
1200 },
1201 [ C(OP_PREFETCH) ] = {
1202 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1203 [ C(RESULT_ACCESS) ] = 0x01b7,
1204 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1205 [ C(RESULT_MISS) ] = 0x01b7,
1206 },
1207 },
1208 [ C(DTLB) ] = {
1209 [ C(OP_READ) ] = {
1210 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1211 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1212 },
1213 [ C(OP_WRITE) ] = {
1214 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1215 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1216 },
1217 [ C(OP_PREFETCH) ] = {
1218 [ C(RESULT_ACCESS) ] = 0x0,
1219 [ C(RESULT_MISS) ] = 0x0,
1220 },
1221 },
1222 [ C(ITLB) ] = {
1223 [ C(OP_READ) ] = {
1224 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1225 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1226 },
1227 [ C(OP_WRITE) ] = {
1228 [ C(RESULT_ACCESS) ] = -1,
1229 [ C(RESULT_MISS) ] = -1,
1230 },
1231 [ C(OP_PREFETCH) ] = {
1232 [ C(RESULT_ACCESS) ] = -1,
1233 [ C(RESULT_MISS) ] = -1,
1234 },
1235 },
1236 [ C(BPU ) ] = {
1237 [ C(OP_READ) ] = {
1238 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1239 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1240 },
1241 [ C(OP_WRITE) ] = {
1242 [ C(RESULT_ACCESS) ] = -1,
1243 [ C(RESULT_MISS) ] = -1,
1244 },
1245 [ C(OP_PREFETCH) ] = {
1246 [ C(RESULT_ACCESS) ] = -1,
1247 [ C(RESULT_MISS) ] = -1,
1248 },
1249 },
1250 [ C(NODE) ] = {
1251 [ C(OP_READ) ] = {
1252 [ C(RESULT_ACCESS) ] = 0x01b7,
1253 [ C(RESULT_MISS) ] = 0x01b7,
1254 },
1255 [ C(OP_WRITE) ] = {
1256 [ C(RESULT_ACCESS) ] = 0x01b7,
1257 [ C(RESULT_MISS) ] = 0x01b7,
1258 },
1259 [ C(OP_PREFETCH) ] = {
1260 [ C(RESULT_ACCESS) ] = 0x01b7,
1261 [ C(RESULT_MISS) ] = 0x01b7,
1262 },
1263 },
1264 };
1265
1266 static __initconst const u64 core2_hw_cache_event_ids
1267 [PERF_COUNT_HW_CACHE_MAX]
1268 [PERF_COUNT_HW_CACHE_OP_MAX]
1269 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1270 {
1271 [ C(L1D) ] = {
1272 [ C(OP_READ) ] = {
1273 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1274 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1275 },
1276 [ C(OP_WRITE) ] = {
1277 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1278 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1279 },
1280 [ C(OP_PREFETCH) ] = {
1281 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1282 [ C(RESULT_MISS) ] = 0,
1283 },
1284 },
1285 [ C(L1I ) ] = {
1286 [ C(OP_READ) ] = {
1287 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1288 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1289 },
1290 [ C(OP_WRITE) ] = {
1291 [ C(RESULT_ACCESS) ] = -1,
1292 [ C(RESULT_MISS) ] = -1,
1293 },
1294 [ C(OP_PREFETCH) ] = {
1295 [ C(RESULT_ACCESS) ] = 0,
1296 [ C(RESULT_MISS) ] = 0,
1297 },
1298 },
1299 [ C(LL ) ] = {
1300 [ C(OP_READ) ] = {
1301 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1302 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1303 },
1304 [ C(OP_WRITE) ] = {
1305 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1306 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1307 },
1308 [ C(OP_PREFETCH) ] = {
1309 [ C(RESULT_ACCESS) ] = 0,
1310 [ C(RESULT_MISS) ] = 0,
1311 },
1312 },
1313 [ C(DTLB) ] = {
1314 [ C(OP_READ) ] = {
1315 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1316 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1317 },
1318 [ C(OP_WRITE) ] = {
1319 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1320 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1321 },
1322 [ C(OP_PREFETCH) ] = {
1323 [ C(RESULT_ACCESS) ] = 0,
1324 [ C(RESULT_MISS) ] = 0,
1325 },
1326 },
1327 [ C(ITLB) ] = {
1328 [ C(OP_READ) ] = {
1329 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1330 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1331 },
1332 [ C(OP_WRITE) ] = {
1333 [ C(RESULT_ACCESS) ] = -1,
1334 [ C(RESULT_MISS) ] = -1,
1335 },
1336 [ C(OP_PREFETCH) ] = {
1337 [ C(RESULT_ACCESS) ] = -1,
1338 [ C(RESULT_MISS) ] = -1,
1339 },
1340 },
1341 [ C(BPU ) ] = {
1342 [ C(OP_READ) ] = {
1343 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1344 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1345 },
1346 [ C(OP_WRITE) ] = {
1347 [ C(RESULT_ACCESS) ] = -1,
1348 [ C(RESULT_MISS) ] = -1,
1349 },
1350 [ C(OP_PREFETCH) ] = {
1351 [ C(RESULT_ACCESS) ] = -1,
1352 [ C(RESULT_MISS) ] = -1,
1353 },
1354 },
1355 };
1356
1357 static __initconst const u64 atom_hw_cache_event_ids
1358 [PERF_COUNT_HW_CACHE_MAX]
1359 [PERF_COUNT_HW_CACHE_OP_MAX]
1360 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1361 {
1362 [ C(L1D) ] = {
1363 [ C(OP_READ) ] = {
1364 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1365 [ C(RESULT_MISS) ] = 0,
1366 },
1367 [ C(OP_WRITE) ] = {
1368 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1369 [ C(RESULT_MISS) ] = 0,
1370 },
1371 [ C(OP_PREFETCH) ] = {
1372 [ C(RESULT_ACCESS) ] = 0x0,
1373 [ C(RESULT_MISS) ] = 0,
1374 },
1375 },
1376 [ C(L1I ) ] = {
1377 [ C(OP_READ) ] = {
1378 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1379 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1380 },
1381 [ C(OP_WRITE) ] = {
1382 [ C(RESULT_ACCESS) ] = -1,
1383 [ C(RESULT_MISS) ] = -1,
1384 },
1385 [ C(OP_PREFETCH) ] = {
1386 [ C(RESULT_ACCESS) ] = 0,
1387 [ C(RESULT_MISS) ] = 0,
1388 },
1389 },
1390 [ C(LL ) ] = {
1391 [ C(OP_READ) ] = {
1392 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1393 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1394 },
1395 [ C(OP_WRITE) ] = {
1396 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1397 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1398 },
1399 [ C(OP_PREFETCH) ] = {
1400 [ C(RESULT_ACCESS) ] = 0,
1401 [ C(RESULT_MISS) ] = 0,
1402 },
1403 },
1404 [ C(DTLB) ] = {
1405 [ C(OP_READ) ] = {
1406 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1407 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1408 },
1409 [ C(OP_WRITE) ] = {
1410 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1411 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1412 },
1413 [ C(OP_PREFETCH) ] = {
1414 [ C(RESULT_ACCESS) ] = 0,
1415 [ C(RESULT_MISS) ] = 0,
1416 },
1417 },
1418 [ C(ITLB) ] = {
1419 [ C(OP_READ) ] = {
1420 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1421 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1422 },
1423 [ C(OP_WRITE) ] = {
1424 [ C(RESULT_ACCESS) ] = -1,
1425 [ C(RESULT_MISS) ] = -1,
1426 },
1427 [ C(OP_PREFETCH) ] = {
1428 [ C(RESULT_ACCESS) ] = -1,
1429 [ C(RESULT_MISS) ] = -1,
1430 },
1431 },
1432 [ C(BPU ) ] = {
1433 [ C(OP_READ) ] = {
1434 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1435 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1436 },
1437 [ C(OP_WRITE) ] = {
1438 [ C(RESULT_ACCESS) ] = -1,
1439 [ C(RESULT_MISS) ] = -1,
1440 },
1441 [ C(OP_PREFETCH) ] = {
1442 [ C(RESULT_ACCESS) ] = -1,
1443 [ C(RESULT_MISS) ] = -1,
1444 },
1445 },
1446 };
1447
1448 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c");
1449 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2");
1450 /* no_alloc_cycles.not_delivered */
1451 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
1452 "event=0xca,umask=0x50");
1453 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
1454 /* uops_retired.all */
1455 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm,
1456 "event=0xc2,umask=0x10");
1457 /* uops_retired.all */
1458 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm,
1459 "event=0xc2,umask=0x10");
1460
1461 static struct attribute *slm_events_attrs[] = {
1462 EVENT_PTR(td_total_slots_slm),
1463 EVENT_PTR(td_total_slots_scale_slm),
1464 EVENT_PTR(td_fetch_bubbles_slm),
1465 EVENT_PTR(td_fetch_bubbles_scale_slm),
1466 EVENT_PTR(td_slots_issued_slm),
1467 EVENT_PTR(td_slots_retired_slm),
1468 NULL
1469 };
1470
1471 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1472 {
1473 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1474 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1475 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1476 EVENT_EXTRA_END
1477 };
1478
1479 #define SLM_DMND_READ SNB_DMND_DATA_RD
1480 #define SLM_DMND_WRITE SNB_DMND_RFO
1481 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1482
1483 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1484 #define SLM_LLC_ACCESS SNB_RESP_ANY
1485 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1486
1487 static __initconst const u64 slm_hw_cache_extra_regs
1488 [PERF_COUNT_HW_CACHE_MAX]
1489 [PERF_COUNT_HW_CACHE_OP_MAX]
1490 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1491 {
1492 [ C(LL ) ] = {
1493 [ C(OP_READ) ] = {
1494 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1495 [ C(RESULT_MISS) ] = 0,
1496 },
1497 [ C(OP_WRITE) ] = {
1498 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1499 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1500 },
1501 [ C(OP_PREFETCH) ] = {
1502 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1503 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1504 },
1505 },
1506 };
1507
1508 static __initconst const u64 slm_hw_cache_event_ids
1509 [PERF_COUNT_HW_CACHE_MAX]
1510 [PERF_COUNT_HW_CACHE_OP_MAX]
1511 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1512 {
1513 [ C(L1D) ] = {
1514 [ C(OP_READ) ] = {
1515 [ C(RESULT_ACCESS) ] = 0,
1516 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1517 },
1518 [ C(OP_WRITE) ] = {
1519 [ C(RESULT_ACCESS) ] = 0,
1520 [ C(RESULT_MISS) ] = 0,
1521 },
1522 [ C(OP_PREFETCH) ] = {
1523 [ C(RESULT_ACCESS) ] = 0,
1524 [ C(RESULT_MISS) ] = 0,
1525 },
1526 },
1527 [ C(L1I ) ] = {
1528 [ C(OP_READ) ] = {
1529 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1530 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1531 },
1532 [ C(OP_WRITE) ] = {
1533 [ C(RESULT_ACCESS) ] = -1,
1534 [ C(RESULT_MISS) ] = -1,
1535 },
1536 [ C(OP_PREFETCH) ] = {
1537 [ C(RESULT_ACCESS) ] = 0,
1538 [ C(RESULT_MISS) ] = 0,
1539 },
1540 },
1541 [ C(LL ) ] = {
1542 [ C(OP_READ) ] = {
1543 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1544 [ C(RESULT_ACCESS) ] = 0x01b7,
1545 [ C(RESULT_MISS) ] = 0,
1546 },
1547 [ C(OP_WRITE) ] = {
1548 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1549 [ C(RESULT_ACCESS) ] = 0x01b7,
1550 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1551 [ C(RESULT_MISS) ] = 0x01b7,
1552 },
1553 [ C(OP_PREFETCH) ] = {
1554 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1555 [ C(RESULT_ACCESS) ] = 0x01b7,
1556 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1557 [ C(RESULT_MISS) ] = 0x01b7,
1558 },
1559 },
1560 [ C(DTLB) ] = {
1561 [ C(OP_READ) ] = {
1562 [ C(RESULT_ACCESS) ] = 0,
1563 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1564 },
1565 [ C(OP_WRITE) ] = {
1566 [ C(RESULT_ACCESS) ] = 0,
1567 [ C(RESULT_MISS) ] = 0,
1568 },
1569 [ C(OP_PREFETCH) ] = {
1570 [ C(RESULT_ACCESS) ] = 0,
1571 [ C(RESULT_MISS) ] = 0,
1572 },
1573 },
1574 [ C(ITLB) ] = {
1575 [ C(OP_READ) ] = {
1576 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1577 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1578 },
1579 [ C(OP_WRITE) ] = {
1580 [ C(RESULT_ACCESS) ] = -1,
1581 [ C(RESULT_MISS) ] = -1,
1582 },
1583 [ C(OP_PREFETCH) ] = {
1584 [ C(RESULT_ACCESS) ] = -1,
1585 [ C(RESULT_MISS) ] = -1,
1586 },
1587 },
1588 [ C(BPU ) ] = {
1589 [ C(OP_READ) ] = {
1590 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1591 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1592 },
1593 [ C(OP_WRITE) ] = {
1594 [ C(RESULT_ACCESS) ] = -1,
1595 [ C(RESULT_MISS) ] = -1,
1596 },
1597 [ C(OP_PREFETCH) ] = {
1598 [ C(RESULT_ACCESS) ] = -1,
1599 [ C(RESULT_MISS) ] = -1,
1600 },
1601 },
1602 };
1603
1604 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
1605 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
1606 /* UOPS_NOT_DELIVERED.ANY */
1607 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c");
1608 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
1609 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02");
1610 /* UOPS_RETIRED.ANY */
1611 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2");
1612 /* UOPS_ISSUED.ANY */
1613 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e");
1614
1615 static struct attribute *glm_events_attrs[] = {
1616 EVENT_PTR(td_total_slots_glm),
1617 EVENT_PTR(td_total_slots_scale_glm),
1618 EVENT_PTR(td_fetch_bubbles_glm),
1619 EVENT_PTR(td_recovery_bubbles_glm),
1620 EVENT_PTR(td_slots_issued_glm),
1621 EVENT_PTR(td_slots_retired_glm),
1622 NULL
1623 };
1624
1625 static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
1626 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1627 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
1628 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
1629 EVENT_EXTRA_END
1630 };
1631
1632 #define GLM_DEMAND_DATA_RD BIT_ULL(0)
1633 #define GLM_DEMAND_RFO BIT_ULL(1)
1634 #define GLM_ANY_RESPONSE BIT_ULL(16)
1635 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33)
1636 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD
1637 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO
1638 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1639 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE
1640 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)
1641 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM)
1642
1643 static __initconst const u64 glm_hw_cache_event_ids
1644 [PERF_COUNT_HW_CACHE_MAX]
1645 [PERF_COUNT_HW_CACHE_OP_MAX]
1646 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1647 [C(L1D)] = {
1648 [C(OP_READ)] = {
1649 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1650 [C(RESULT_MISS)] = 0x0,
1651 },
1652 [C(OP_WRITE)] = {
1653 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1654 [C(RESULT_MISS)] = 0x0,
1655 },
1656 [C(OP_PREFETCH)] = {
1657 [C(RESULT_ACCESS)] = 0x0,
1658 [C(RESULT_MISS)] = 0x0,
1659 },
1660 },
1661 [C(L1I)] = {
1662 [C(OP_READ)] = {
1663 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1664 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1665 },
1666 [C(OP_WRITE)] = {
1667 [C(RESULT_ACCESS)] = -1,
1668 [C(RESULT_MISS)] = -1,
1669 },
1670 [C(OP_PREFETCH)] = {
1671 [C(RESULT_ACCESS)] = 0x0,
1672 [C(RESULT_MISS)] = 0x0,
1673 },
1674 },
1675 [C(LL)] = {
1676 [C(OP_READ)] = {
1677 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1678 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1679 },
1680 [C(OP_WRITE)] = {
1681 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1682 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1683 },
1684 [C(OP_PREFETCH)] = {
1685 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1686 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1687 },
1688 },
1689 [C(DTLB)] = {
1690 [C(OP_READ)] = {
1691 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1692 [C(RESULT_MISS)] = 0x0,
1693 },
1694 [C(OP_WRITE)] = {
1695 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1696 [C(RESULT_MISS)] = 0x0,
1697 },
1698 [C(OP_PREFETCH)] = {
1699 [C(RESULT_ACCESS)] = 0x0,
1700 [C(RESULT_MISS)] = 0x0,
1701 },
1702 },
1703 [C(ITLB)] = {
1704 [C(OP_READ)] = {
1705 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1706 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1707 },
1708 [C(OP_WRITE)] = {
1709 [C(RESULT_ACCESS)] = -1,
1710 [C(RESULT_MISS)] = -1,
1711 },
1712 [C(OP_PREFETCH)] = {
1713 [C(RESULT_ACCESS)] = -1,
1714 [C(RESULT_MISS)] = -1,
1715 },
1716 },
1717 [C(BPU)] = {
1718 [C(OP_READ)] = {
1719 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1720 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1721 },
1722 [C(OP_WRITE)] = {
1723 [C(RESULT_ACCESS)] = -1,
1724 [C(RESULT_MISS)] = -1,
1725 },
1726 [C(OP_PREFETCH)] = {
1727 [C(RESULT_ACCESS)] = -1,
1728 [C(RESULT_MISS)] = -1,
1729 },
1730 },
1731 };
1732
1733 static __initconst const u64 glm_hw_cache_extra_regs
1734 [PERF_COUNT_HW_CACHE_MAX]
1735 [PERF_COUNT_HW_CACHE_OP_MAX]
1736 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1737 [C(LL)] = {
1738 [C(OP_READ)] = {
1739 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1740 GLM_LLC_ACCESS,
1741 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1742 GLM_LLC_MISS,
1743 },
1744 [C(OP_WRITE)] = {
1745 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1746 GLM_LLC_ACCESS,
1747 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1748 GLM_LLC_MISS,
1749 },
1750 [C(OP_PREFETCH)] = {
1751 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH|
1752 GLM_LLC_ACCESS,
1753 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH|
1754 GLM_LLC_MISS,
1755 },
1756 },
1757 };
1758
1759 static __initconst const u64 glp_hw_cache_event_ids
1760 [PERF_COUNT_HW_CACHE_MAX]
1761 [PERF_COUNT_HW_CACHE_OP_MAX]
1762 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1763 [C(L1D)] = {
1764 [C(OP_READ)] = {
1765 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1766 [C(RESULT_MISS)] = 0x0,
1767 },
1768 [C(OP_WRITE)] = {
1769 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1770 [C(RESULT_MISS)] = 0x0,
1771 },
1772 [C(OP_PREFETCH)] = {
1773 [C(RESULT_ACCESS)] = 0x0,
1774 [C(RESULT_MISS)] = 0x0,
1775 },
1776 },
1777 [C(L1I)] = {
1778 [C(OP_READ)] = {
1779 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1780 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1781 },
1782 [C(OP_WRITE)] = {
1783 [C(RESULT_ACCESS)] = -1,
1784 [C(RESULT_MISS)] = -1,
1785 },
1786 [C(OP_PREFETCH)] = {
1787 [C(RESULT_ACCESS)] = 0x0,
1788 [C(RESULT_MISS)] = 0x0,
1789 },
1790 },
1791 [C(LL)] = {
1792 [C(OP_READ)] = {
1793 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1794 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1795 },
1796 [C(OP_WRITE)] = {
1797 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1798 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1799 },
1800 [C(OP_PREFETCH)] = {
1801 [C(RESULT_ACCESS)] = 0x0,
1802 [C(RESULT_MISS)] = 0x0,
1803 },
1804 },
1805 [C(DTLB)] = {
1806 [C(OP_READ)] = {
1807 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1808 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
1809 },
1810 [C(OP_WRITE)] = {
1811 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1812 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
1813 },
1814 [C(OP_PREFETCH)] = {
1815 [C(RESULT_ACCESS)] = 0x0,
1816 [C(RESULT_MISS)] = 0x0,
1817 },
1818 },
1819 [C(ITLB)] = {
1820 [C(OP_READ)] = {
1821 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1822 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1823 },
1824 [C(OP_WRITE)] = {
1825 [C(RESULT_ACCESS)] = -1,
1826 [C(RESULT_MISS)] = -1,
1827 },
1828 [C(OP_PREFETCH)] = {
1829 [C(RESULT_ACCESS)] = -1,
1830 [C(RESULT_MISS)] = -1,
1831 },
1832 },
1833 [C(BPU)] = {
1834 [C(OP_READ)] = {
1835 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1836 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1837 },
1838 [C(OP_WRITE)] = {
1839 [C(RESULT_ACCESS)] = -1,
1840 [C(RESULT_MISS)] = -1,
1841 },
1842 [C(OP_PREFETCH)] = {
1843 [C(RESULT_ACCESS)] = -1,
1844 [C(RESULT_MISS)] = -1,
1845 },
1846 },
1847 };
1848
1849 static __initconst const u64 glp_hw_cache_extra_regs
1850 [PERF_COUNT_HW_CACHE_MAX]
1851 [PERF_COUNT_HW_CACHE_OP_MAX]
1852 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1853 [C(LL)] = {
1854 [C(OP_READ)] = {
1855 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1856 GLM_LLC_ACCESS,
1857 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1858 GLM_LLC_MISS,
1859 },
1860 [C(OP_WRITE)] = {
1861 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1862 GLM_LLC_ACCESS,
1863 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1864 GLM_LLC_MISS,
1865 },
1866 [C(OP_PREFETCH)] = {
1867 [C(RESULT_ACCESS)] = 0x0,
1868 [C(RESULT_MISS)] = 0x0,
1869 },
1870 },
1871 };
1872
1873 #define TNT_LOCAL_DRAM BIT_ULL(26)
1874 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD
1875 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO
1876 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE
1877 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \
1878 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM)
1879 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM)
1880
1881 static __initconst const u64 tnt_hw_cache_extra_regs
1882 [PERF_COUNT_HW_CACHE_MAX]
1883 [PERF_COUNT_HW_CACHE_OP_MAX]
1884 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1885 [C(LL)] = {
1886 [C(OP_READ)] = {
1887 [C(RESULT_ACCESS)] = TNT_DEMAND_READ|
1888 TNT_LLC_ACCESS,
1889 [C(RESULT_MISS)] = TNT_DEMAND_READ|
1890 TNT_LLC_MISS,
1891 },
1892 [C(OP_WRITE)] = {
1893 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE|
1894 TNT_LLC_ACCESS,
1895 [C(RESULT_MISS)] = TNT_DEMAND_WRITE|
1896 TNT_LLC_MISS,
1897 },
1898 [C(OP_PREFETCH)] = {
1899 [C(RESULT_ACCESS)] = 0x0,
1900 [C(RESULT_MISS)] = 0x0,
1901 },
1902 },
1903 };
1904
1905 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = {
1906 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1907 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0),
1908 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1),
1909 EVENT_EXTRA_END
1910 };
1911
1912 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */
1913 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */
1914 #define KNL_MCDRAM_LOCAL BIT_ULL(21)
1915 #define KNL_MCDRAM_FAR BIT_ULL(22)
1916 #define KNL_DDR_LOCAL BIT_ULL(23)
1917 #define KNL_DDR_FAR BIT_ULL(24)
1918 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
1919 KNL_DDR_LOCAL | KNL_DDR_FAR)
1920 #define KNL_L2_READ SLM_DMND_READ
1921 #define KNL_L2_WRITE SLM_DMND_WRITE
1922 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH
1923 #define KNL_L2_ACCESS SLM_LLC_ACCESS
1924 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
1925 KNL_DRAM_ANY | SNB_SNP_ANY | \
1926 SNB_NON_DRAM)
1927
1928 static __initconst const u64 knl_hw_cache_extra_regs
1929 [PERF_COUNT_HW_CACHE_MAX]
1930 [PERF_COUNT_HW_CACHE_OP_MAX]
1931 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1932 [C(LL)] = {
1933 [C(OP_READ)] = {
1934 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
1935 [C(RESULT_MISS)] = 0,
1936 },
1937 [C(OP_WRITE)] = {
1938 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
1939 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
1940 },
1941 [C(OP_PREFETCH)] = {
1942 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
1943 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
1944 },
1945 },
1946 };
1947
1948 /*
1949 * Used from PMIs where the LBRs are already disabled.
1950 *
1951 * This function could be called consecutively. It is required to remain in
1952 * disabled state if called consecutively.
1953 *
1954 * During consecutive calls, the same disable value will be written to related
1955 * registers, so the PMU state remains unchanged.
1956 *
1957 * intel_bts events don't coexist with intel PMU's BTS events because of
1958 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them
1959 * disabled around intel PMU's event batching etc, only inside the PMI handler.
1960 *
1961 * Avoid PEBS_ENABLE MSR access in PMIs.
1962 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore.
1963 * It doesn't matter if the PEBS is enabled or not.
1964 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to
1965 * access PEBS_ENABLE MSR in disable_all()/enable_all().
1966 * However, there are some cases which may change PEBS status, e.g. PMI
1967 * throttle. The PEBS_ENABLE should be updated where the status changes.
1968 */
__intel_pmu_disable_all(void)1969 static void __intel_pmu_disable_all(void)
1970 {
1971 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1972
1973 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1974
1975 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
1976 intel_pmu_disable_bts();
1977 }
1978
intel_pmu_disable_all(void)1979 static void intel_pmu_disable_all(void)
1980 {
1981 __intel_pmu_disable_all();
1982 intel_pmu_pebs_disable_all();
1983 intel_pmu_lbr_disable_all();
1984 }
1985
__intel_pmu_enable_all(int added,bool pmi)1986 static void __intel_pmu_enable_all(int added, bool pmi)
1987 {
1988 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1989
1990 intel_pmu_lbr_enable_all(pmi);
1991 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
1992 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
1993
1994 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
1995 struct perf_event *event =
1996 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
1997
1998 if (WARN_ON_ONCE(!event))
1999 return;
2000
2001 intel_pmu_enable_bts(event->hw.config);
2002 }
2003 }
2004
intel_pmu_enable_all(int added)2005 static void intel_pmu_enable_all(int added)
2006 {
2007 intel_pmu_pebs_enable_all();
2008 __intel_pmu_enable_all(added, false);
2009 }
2010
2011 /*
2012 * Workaround for:
2013 * Intel Errata AAK100 (model 26)
2014 * Intel Errata AAP53 (model 30)
2015 * Intel Errata BD53 (model 44)
2016 *
2017 * The official story:
2018 * These chips need to be 'reset' when adding counters by programming the
2019 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
2020 * in sequence on the same PMC or on different PMCs.
2021 *
2022 * In practise it appears some of these events do in fact count, and
2023 * we need to program all 4 events.
2024 */
intel_pmu_nhm_workaround(void)2025 static void intel_pmu_nhm_workaround(void)
2026 {
2027 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2028 static const unsigned long nhm_magic[4] = {
2029 0x4300B5,
2030 0x4300D2,
2031 0x4300B1,
2032 0x4300B1
2033 };
2034 struct perf_event *event;
2035 int i;
2036
2037 /*
2038 * The Errata requires below steps:
2039 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
2040 * 2) Configure 4 PERFEVTSELx with the magic events and clear
2041 * the corresponding PMCx;
2042 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
2043 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
2044 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
2045 */
2046
2047 /*
2048 * The real steps we choose are a little different from above.
2049 * A) To reduce MSR operations, we don't run step 1) as they
2050 * are already cleared before this function is called;
2051 * B) Call x86_perf_event_update to save PMCx before configuring
2052 * PERFEVTSELx with magic number;
2053 * C) With step 5), we do clear only when the PERFEVTSELx is
2054 * not used currently.
2055 * D) Call x86_perf_event_set_period to restore PMCx;
2056 */
2057
2058 /* We always operate 4 pairs of PERF Counters */
2059 for (i = 0; i < 4; i++) {
2060 event = cpuc->events[i];
2061 if (event)
2062 x86_perf_event_update(event);
2063 }
2064
2065 for (i = 0; i < 4; i++) {
2066 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
2067 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
2068 }
2069
2070 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
2071 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
2072
2073 for (i = 0; i < 4; i++) {
2074 event = cpuc->events[i];
2075
2076 if (event) {
2077 x86_perf_event_set_period(event);
2078 __x86_pmu_enable_event(&event->hw,
2079 ARCH_PERFMON_EVENTSEL_ENABLE);
2080 } else
2081 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
2082 }
2083 }
2084
intel_pmu_nhm_enable_all(int added)2085 static void intel_pmu_nhm_enable_all(int added)
2086 {
2087 if (added)
2088 intel_pmu_nhm_workaround();
2089 intel_pmu_enable_all(added);
2090 }
2091
intel_set_tfa(struct cpu_hw_events * cpuc,bool on)2092 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on)
2093 {
2094 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0;
2095
2096 if (cpuc->tfa_shadow != val) {
2097 cpuc->tfa_shadow = val;
2098 wrmsrl(MSR_TSX_FORCE_ABORT, val);
2099 }
2100 }
2101
intel_tfa_commit_scheduling(struct cpu_hw_events * cpuc,int idx,int cntr)2102 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2103 {
2104 /*
2105 * We're going to use PMC3, make sure TFA is set before we touch it.
2106 */
2107 if (cntr == 3)
2108 intel_set_tfa(cpuc, true);
2109 }
2110
intel_tfa_pmu_enable_all(int added)2111 static void intel_tfa_pmu_enable_all(int added)
2112 {
2113 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2114
2115 /*
2116 * If we find PMC3 is no longer used when we enable the PMU, we can
2117 * clear TFA.
2118 */
2119 if (!test_bit(3, cpuc->active_mask))
2120 intel_set_tfa(cpuc, false);
2121
2122 intel_pmu_enable_all(added);
2123 }
2124
enable_counter_freeze(void)2125 static void enable_counter_freeze(void)
2126 {
2127 update_debugctlmsr(get_debugctlmsr() |
2128 DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI);
2129 }
2130
disable_counter_freeze(void)2131 static void disable_counter_freeze(void)
2132 {
2133 update_debugctlmsr(get_debugctlmsr() &
2134 ~DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI);
2135 }
2136
intel_pmu_get_status(void)2137 static inline u64 intel_pmu_get_status(void)
2138 {
2139 u64 status;
2140
2141 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
2142
2143 return status;
2144 }
2145
intel_pmu_ack_status(u64 ack)2146 static inline void intel_pmu_ack_status(u64 ack)
2147 {
2148 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
2149 }
2150
event_is_checkpointed(struct perf_event * event)2151 static inline bool event_is_checkpointed(struct perf_event *event)
2152 {
2153 return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
2154 }
2155
intel_set_masks(struct perf_event * event,int idx)2156 static inline void intel_set_masks(struct perf_event *event, int idx)
2157 {
2158 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2159
2160 if (event->attr.exclude_host)
2161 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2162 if (event->attr.exclude_guest)
2163 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2164 if (event_is_checkpointed(event))
2165 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2166 }
2167
intel_clear_masks(struct perf_event * event,int idx)2168 static inline void intel_clear_masks(struct perf_event *event, int idx)
2169 {
2170 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2171
2172 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2173 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2174 __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2175 }
2176
intel_pmu_disable_fixed(struct perf_event * event)2177 static void intel_pmu_disable_fixed(struct perf_event *event)
2178 {
2179 struct hw_perf_event *hwc = &event->hw;
2180 u64 ctrl_val, mask;
2181 int idx = hwc->idx;
2182
2183 if (is_topdown_idx(idx)) {
2184 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2185
2186 /*
2187 * When there are other active TopDown events,
2188 * don't disable the fixed counter 3.
2189 */
2190 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
2191 return;
2192 idx = INTEL_PMC_IDX_FIXED_SLOTS;
2193 }
2194
2195 intel_clear_masks(event, idx);
2196
2197 mask = 0xfULL << ((idx - INTEL_PMC_IDX_FIXED) * 4);
2198 rdmsrl(hwc->config_base, ctrl_val);
2199 ctrl_val &= ~mask;
2200 wrmsrl(hwc->config_base, ctrl_val);
2201 }
2202
intel_pmu_disable_event(struct perf_event * event)2203 static void intel_pmu_disable_event(struct perf_event *event)
2204 {
2205 struct hw_perf_event *hwc = &event->hw;
2206 int idx = hwc->idx;
2207
2208 switch (idx) {
2209 case 0 ... INTEL_PMC_IDX_FIXED - 1:
2210 intel_clear_masks(event, idx);
2211 x86_pmu_disable_event(event);
2212 break;
2213 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
2214 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
2215 intel_pmu_disable_fixed(event);
2216 break;
2217 case INTEL_PMC_IDX_FIXED_BTS:
2218 intel_pmu_disable_bts();
2219 intel_pmu_drain_bts_buffer();
2220 return;
2221 case INTEL_PMC_IDX_FIXED_VLBR:
2222 intel_clear_masks(event, idx);
2223 break;
2224 default:
2225 intel_clear_masks(event, idx);
2226 pr_warn("Failed to disable the event with invalid index %d\n",
2227 idx);
2228 return;
2229 }
2230
2231 /*
2232 * Needs to be called after x86_pmu_disable_event,
2233 * so we don't trigger the event without PEBS bit set.
2234 */
2235 if (unlikely(event->attr.precise_ip))
2236 intel_pmu_pebs_disable(event);
2237 }
2238
intel_pmu_del_event(struct perf_event * event)2239 static void intel_pmu_del_event(struct perf_event *event)
2240 {
2241 if (needs_branch_stack(event))
2242 intel_pmu_lbr_del(event);
2243 if (event->attr.precise_ip)
2244 intel_pmu_pebs_del(event);
2245 }
2246
icl_set_topdown_event_period(struct perf_event * event)2247 static int icl_set_topdown_event_period(struct perf_event *event)
2248 {
2249 struct hw_perf_event *hwc = &event->hw;
2250 s64 left = local64_read(&hwc->period_left);
2251
2252 /*
2253 * The values in PERF_METRICS MSR are derived from fixed counter 3.
2254 * Software should start both registers, PERF_METRICS and fixed
2255 * counter 3, from zero.
2256 * Clear PERF_METRICS and Fixed counter 3 in initialization.
2257 * After that, both MSRs will be cleared for each read.
2258 * Don't need to clear them again.
2259 */
2260 if (left == x86_pmu.max_period) {
2261 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0);
2262 wrmsrl(MSR_PERF_METRICS, 0);
2263 hwc->saved_slots = 0;
2264 hwc->saved_metric = 0;
2265 }
2266
2267 if ((hwc->saved_slots) && is_slots_event(event)) {
2268 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots);
2269 wrmsrl(MSR_PERF_METRICS, hwc->saved_metric);
2270 }
2271
2272 perf_event_update_userpage(event);
2273
2274 return 0;
2275 }
2276
icl_get_metrics_event_value(u64 metric,u64 slots,int idx)2277 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx)
2278 {
2279 u32 val;
2280
2281 /*
2282 * The metric is reported as an 8bit integer fraction
2283 * suming up to 0xff.
2284 * slots-in-metric = (Metric / 0xff) * slots
2285 */
2286 val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff;
2287 return mul_u64_u32_div(slots, val, 0xff);
2288 }
2289
icl_get_topdown_value(struct perf_event * event,u64 slots,u64 metrics)2290 static u64 icl_get_topdown_value(struct perf_event *event,
2291 u64 slots, u64 metrics)
2292 {
2293 int idx = event->hw.idx;
2294 u64 delta;
2295
2296 if (is_metric_idx(idx))
2297 delta = icl_get_metrics_event_value(metrics, slots, idx);
2298 else
2299 delta = slots;
2300
2301 return delta;
2302 }
2303
__icl_update_topdown_event(struct perf_event * event,u64 slots,u64 metrics,u64 last_slots,u64 last_metrics)2304 static void __icl_update_topdown_event(struct perf_event *event,
2305 u64 slots, u64 metrics,
2306 u64 last_slots, u64 last_metrics)
2307 {
2308 u64 delta, last = 0;
2309
2310 delta = icl_get_topdown_value(event, slots, metrics);
2311 if (last_slots)
2312 last = icl_get_topdown_value(event, last_slots, last_metrics);
2313
2314 /*
2315 * The 8bit integer fraction of metric may be not accurate,
2316 * especially when the changes is very small.
2317 * For example, if only a few bad_spec happens, the fraction
2318 * may be reduced from 1 to 0. If so, the bad_spec event value
2319 * will be 0 which is definitely less than the last value.
2320 * Avoid update event->count for this case.
2321 */
2322 if (delta > last) {
2323 delta -= last;
2324 local64_add(delta, &event->count);
2325 }
2326 }
2327
update_saved_topdown_regs(struct perf_event * event,u64 slots,u64 metrics)2328 static void update_saved_topdown_regs(struct perf_event *event,
2329 u64 slots, u64 metrics)
2330 {
2331 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2332 struct perf_event *other;
2333 int idx;
2334
2335 event->hw.saved_slots = slots;
2336 event->hw.saved_metric = metrics;
2337
2338 for_each_set_bit(idx, cpuc->active_mask, INTEL_PMC_IDX_TD_BE_BOUND + 1) {
2339 if (!is_topdown_idx(idx))
2340 continue;
2341 other = cpuc->events[idx];
2342 other->hw.saved_slots = slots;
2343 other->hw.saved_metric = metrics;
2344 }
2345 }
2346
2347 /*
2348 * Update all active Topdown events.
2349 *
2350 * The PERF_METRICS and Fixed counter 3 are read separately. The values may be
2351 * modify by a NMI. PMU has to be disabled before calling this function.
2352 */
icl_update_topdown_event(struct perf_event * event)2353 static u64 icl_update_topdown_event(struct perf_event *event)
2354 {
2355 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2356 struct perf_event *other;
2357 u64 slots, metrics;
2358 bool reset = true;
2359 int idx;
2360
2361 /* read Fixed counter 3 */
2362 rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots);
2363 if (!slots)
2364 return 0;
2365
2366 /* read PERF_METRICS */
2367 rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics);
2368
2369 for_each_set_bit(idx, cpuc->active_mask, INTEL_PMC_IDX_TD_BE_BOUND + 1) {
2370 if (!is_topdown_idx(idx))
2371 continue;
2372 other = cpuc->events[idx];
2373 __icl_update_topdown_event(other, slots, metrics,
2374 event ? event->hw.saved_slots : 0,
2375 event ? event->hw.saved_metric : 0);
2376 }
2377
2378 /*
2379 * Check and update this event, which may have been cleared
2380 * in active_mask e.g. x86_pmu_stop()
2381 */
2382 if (event && !test_bit(event->hw.idx, cpuc->active_mask)) {
2383 __icl_update_topdown_event(event, slots, metrics,
2384 event->hw.saved_slots,
2385 event->hw.saved_metric);
2386
2387 /*
2388 * In x86_pmu_stop(), the event is cleared in active_mask first,
2389 * then drain the delta, which indicates context switch for
2390 * counting.
2391 * Save metric and slots for context switch.
2392 * Don't need to reset the PERF_METRICS and Fixed counter 3.
2393 * Because the values will be restored in next schedule in.
2394 */
2395 update_saved_topdown_regs(event, slots, metrics);
2396 reset = false;
2397 }
2398
2399 if (reset) {
2400 /* The fixed counter 3 has to be written before the PERF_METRICS. */
2401 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0);
2402 wrmsrl(MSR_PERF_METRICS, 0);
2403 if (event)
2404 update_saved_topdown_regs(event, 0, 0);
2405 }
2406
2407 return slots;
2408 }
2409
intel_pmu_read_topdown_event(struct perf_event * event)2410 static void intel_pmu_read_topdown_event(struct perf_event *event)
2411 {
2412 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2413
2414 /* Only need to call update_topdown_event() once for group read. */
2415 if ((cpuc->txn_flags & PERF_PMU_TXN_READ) &&
2416 !is_slots_event(event))
2417 return;
2418
2419 perf_pmu_disable(event->pmu);
2420 x86_pmu.update_topdown_event(event);
2421 perf_pmu_enable(event->pmu);
2422 }
2423
intel_pmu_read_event(struct perf_event * event)2424 static void intel_pmu_read_event(struct perf_event *event)
2425 {
2426 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
2427 intel_pmu_auto_reload_read(event);
2428 else if (is_topdown_count(event) && x86_pmu.update_topdown_event)
2429 intel_pmu_read_topdown_event(event);
2430 else
2431 x86_perf_event_update(event);
2432 }
2433
intel_pmu_enable_fixed(struct perf_event * event)2434 static void intel_pmu_enable_fixed(struct perf_event *event)
2435 {
2436 struct hw_perf_event *hwc = &event->hw;
2437 u64 ctrl_val, mask, bits = 0;
2438 int idx = hwc->idx;
2439
2440 if (is_topdown_idx(idx)) {
2441 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2442 /*
2443 * When there are other active TopDown events,
2444 * don't enable the fixed counter 3 again.
2445 */
2446 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
2447 return;
2448
2449 idx = INTEL_PMC_IDX_FIXED_SLOTS;
2450 }
2451
2452 intel_set_masks(event, idx);
2453
2454 /*
2455 * Enable IRQ generation (0x8), if not PEBS,
2456 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
2457 * if requested:
2458 */
2459 if (!event->attr.precise_ip)
2460 bits |= 0x8;
2461 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
2462 bits |= 0x2;
2463 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
2464 bits |= 0x1;
2465
2466 /*
2467 * ANY bit is supported in v3 and up
2468 */
2469 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
2470 bits |= 0x4;
2471
2472 idx -= INTEL_PMC_IDX_FIXED;
2473 bits <<= (idx * 4);
2474 mask = 0xfULL << (idx * 4);
2475
2476 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) {
2477 bits |= ICL_FIXED_0_ADAPTIVE << (idx * 4);
2478 mask |= ICL_FIXED_0_ADAPTIVE << (idx * 4);
2479 }
2480
2481 rdmsrl(hwc->config_base, ctrl_val);
2482 ctrl_val &= ~mask;
2483 ctrl_val |= bits;
2484 wrmsrl(hwc->config_base, ctrl_val);
2485 }
2486
intel_pmu_enable_event(struct perf_event * event)2487 static void intel_pmu_enable_event(struct perf_event *event)
2488 {
2489 struct hw_perf_event *hwc = &event->hw;
2490 int idx = hwc->idx;
2491
2492 if (unlikely(event->attr.precise_ip))
2493 intel_pmu_pebs_enable(event);
2494
2495 switch (idx) {
2496 case 0 ... INTEL_PMC_IDX_FIXED - 1:
2497 intel_set_masks(event, idx);
2498 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2499 break;
2500 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
2501 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
2502 intel_pmu_enable_fixed(event);
2503 break;
2504 case INTEL_PMC_IDX_FIXED_BTS:
2505 if (!__this_cpu_read(cpu_hw_events.enabled))
2506 return;
2507 intel_pmu_enable_bts(hwc->config);
2508 break;
2509 case INTEL_PMC_IDX_FIXED_VLBR:
2510 intel_set_masks(event, idx);
2511 break;
2512 default:
2513 pr_warn("Failed to enable the event with invalid index %d\n",
2514 idx);
2515 }
2516 }
2517
intel_pmu_add_event(struct perf_event * event)2518 static void intel_pmu_add_event(struct perf_event *event)
2519 {
2520 if (event->attr.precise_ip)
2521 intel_pmu_pebs_add(event);
2522 if (needs_branch_stack(event))
2523 intel_pmu_lbr_add(event);
2524 }
2525
2526 /*
2527 * Save and restart an expired event. Called by NMI contexts,
2528 * so it has to be careful about preempting normal event ops:
2529 */
intel_pmu_save_and_restart(struct perf_event * event)2530 int intel_pmu_save_and_restart(struct perf_event *event)
2531 {
2532 x86_perf_event_update(event);
2533 /*
2534 * For a checkpointed counter always reset back to 0. This
2535 * avoids a situation where the counter overflows, aborts the
2536 * transaction and is then set back to shortly before the
2537 * overflow, and overflows and aborts again.
2538 */
2539 if (unlikely(event_is_checkpointed(event))) {
2540 /* No race with NMIs because the counter should not be armed */
2541 wrmsrl(event->hw.event_base, 0);
2542 local64_set(&event->hw.prev_count, 0);
2543 }
2544 return x86_perf_event_set_period(event);
2545 }
2546
intel_pmu_reset(void)2547 static void intel_pmu_reset(void)
2548 {
2549 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
2550 unsigned long flags;
2551 int idx;
2552
2553 if (!x86_pmu.num_counters)
2554 return;
2555
2556 local_irq_save(flags);
2557
2558 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
2559
2560 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2561 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
2562 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
2563 }
2564 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
2565 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
2566
2567 if (ds)
2568 ds->bts_index = ds->bts_buffer_base;
2569
2570 /* Ack all overflows and disable fixed counters */
2571 if (x86_pmu.version >= 2) {
2572 intel_pmu_ack_status(intel_pmu_get_status());
2573 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2574 }
2575
2576 /* Reset LBRs and LBR freezing */
2577 if (x86_pmu.lbr_nr) {
2578 update_debugctlmsr(get_debugctlmsr() &
2579 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
2580 }
2581
2582 local_irq_restore(flags);
2583 }
2584
handle_pmi_common(struct pt_regs * regs,u64 status)2585 static int handle_pmi_common(struct pt_regs *regs, u64 status)
2586 {
2587 struct perf_sample_data data;
2588 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2589 int bit;
2590 int handled = 0;
2591
2592 inc_irq_stat(apic_perf_irqs);
2593
2594 /*
2595 * Ignore a range of extra bits in status that do not indicate
2596 * overflow by themselves.
2597 */
2598 status &= ~(GLOBAL_STATUS_COND_CHG |
2599 GLOBAL_STATUS_ASIF |
2600 GLOBAL_STATUS_LBRS_FROZEN);
2601 if (!status)
2602 return 0;
2603 /*
2604 * In case multiple PEBS events are sampled at the same time,
2605 * it is possible to have GLOBAL_STATUS bit 62 set indicating
2606 * PEBS buffer overflow and also seeing at most 3 PEBS counters
2607 * having their bits set in the status register. This is a sign
2608 * that there was at least one PEBS record pending at the time
2609 * of the PMU interrupt. PEBS counters must only be processed
2610 * via the drain_pebs() calls and not via the regular sample
2611 * processing loop coming after that the function, otherwise
2612 * phony regular samples may be generated in the sampling buffer
2613 * not marked with the EXACT tag. Another possibility is to have
2614 * one PEBS event and at least one non-PEBS event whic hoverflows
2615 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will
2616 * not be set, yet the overflow status bit for the PEBS counter will
2617 * be on Skylake.
2618 *
2619 * To avoid this problem, we systematically ignore the PEBS-enabled
2620 * counters from the GLOBAL_STATUS mask and we always process PEBS
2621 * events via drain_pebs().
2622 */
2623 if (x86_pmu.flags & PMU_FL_PEBS_ALL)
2624 status &= ~cpuc->pebs_enabled;
2625 else
2626 status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
2627
2628 /*
2629 * PEBS overflow sets bit 62 in the global status register
2630 */
2631 if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) {
2632 u64 pebs_enabled = cpuc->pebs_enabled;
2633
2634 handled++;
2635 x86_pmu.drain_pebs(regs, &data);
2636 status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
2637
2638 /*
2639 * PMI throttle may be triggered, which stops the PEBS event.
2640 * Although cpuc->pebs_enabled is updated accordingly, the
2641 * MSR_IA32_PEBS_ENABLE is not updated. Because the
2642 * cpuc->enabled has been forced to 0 in PMI.
2643 * Update the MSR if pebs_enabled is changed.
2644 */
2645 if (pebs_enabled != cpuc->pebs_enabled)
2646 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
2647 }
2648
2649 /*
2650 * Intel PT
2651 */
2652 if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) {
2653 handled++;
2654 if (unlikely(perf_guest_cbs && perf_guest_cbs->is_in_guest() &&
2655 perf_guest_cbs->handle_intel_pt_intr))
2656 perf_guest_cbs->handle_intel_pt_intr();
2657 else
2658 intel_pt_interrupt();
2659 }
2660
2661 /*
2662 * Intel Perf mertrics
2663 */
2664 if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) {
2665 handled++;
2666 if (x86_pmu.update_topdown_event)
2667 x86_pmu.update_topdown_event(NULL);
2668 }
2669
2670 /*
2671 * Checkpointed counters can lead to 'spurious' PMIs because the
2672 * rollback caused by the PMI will have cleared the overflow status
2673 * bit. Therefore always force probe these counters.
2674 */
2675 status |= cpuc->intel_cp_status;
2676
2677 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
2678 struct perf_event *event = cpuc->events[bit];
2679
2680 handled++;
2681
2682 if (!test_bit(bit, cpuc->active_mask))
2683 continue;
2684
2685 if (!intel_pmu_save_and_restart(event))
2686 continue;
2687
2688 perf_sample_data_init(&data, 0, event->hw.last_period);
2689
2690 if (has_branch_stack(event))
2691 data.br_stack = &cpuc->lbr_stack;
2692
2693 if (perf_event_overflow(event, &data, regs))
2694 x86_pmu_stop(event, 0);
2695 }
2696
2697 return handled;
2698 }
2699
2700 static bool disable_counter_freezing = true;
intel_perf_counter_freezing_setup(char * s)2701 static int __init intel_perf_counter_freezing_setup(char *s)
2702 {
2703 bool res;
2704
2705 if (kstrtobool(s, &res))
2706 return -EINVAL;
2707
2708 disable_counter_freezing = !res;
2709 return 1;
2710 }
2711 __setup("perf_v4_pmi=", intel_perf_counter_freezing_setup);
2712
2713 /*
2714 * Simplified handler for Arch Perfmon v4:
2715 * - We rely on counter freezing/unfreezing to enable/disable the PMU.
2716 * This is done automatically on PMU ack.
2717 * - Ack the PMU only after the APIC.
2718 */
2719
intel_pmu_handle_irq_v4(struct pt_regs * regs)2720 static int intel_pmu_handle_irq_v4(struct pt_regs *regs)
2721 {
2722 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2723 int handled = 0;
2724 bool bts = false;
2725 u64 status;
2726 int pmu_enabled = cpuc->enabled;
2727 int loops = 0;
2728
2729 /* PMU has been disabled because of counter freezing */
2730 cpuc->enabled = 0;
2731 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
2732 bts = true;
2733 intel_bts_disable_local();
2734 handled = intel_pmu_drain_bts_buffer();
2735 handled += intel_bts_interrupt();
2736 }
2737 status = intel_pmu_get_status();
2738 if (!status)
2739 goto done;
2740 again:
2741 intel_pmu_lbr_read();
2742 if (++loops > 100) {
2743 static bool warned;
2744
2745 if (!warned) {
2746 WARN(1, "perfevents: irq loop stuck!\n");
2747 perf_event_print_debug();
2748 warned = true;
2749 }
2750 intel_pmu_reset();
2751 goto done;
2752 }
2753
2754
2755 handled += handle_pmi_common(regs, status);
2756 done:
2757 /* Ack the PMI in the APIC */
2758 apic_write(APIC_LVTPC, APIC_DM_NMI);
2759
2760 /*
2761 * The counters start counting immediately while ack the status.
2762 * Make it as close as possible to IRET. This avoids bogus
2763 * freezing on Skylake CPUs.
2764 */
2765 if (status) {
2766 intel_pmu_ack_status(status);
2767 } else {
2768 /*
2769 * CPU may issues two PMIs very close to each other.
2770 * When the PMI handler services the first one, the
2771 * GLOBAL_STATUS is already updated to reflect both.
2772 * When it IRETs, the second PMI is immediately
2773 * handled and it sees clear status. At the meantime,
2774 * there may be a third PMI, because the freezing bit
2775 * isn't set since the ack in first PMI handlers.
2776 * Double check if there is more work to be done.
2777 */
2778 status = intel_pmu_get_status();
2779 if (status)
2780 goto again;
2781 }
2782
2783 if (bts)
2784 intel_bts_enable_local();
2785 cpuc->enabled = pmu_enabled;
2786 return handled;
2787 }
2788
2789 /*
2790 * This handler is triggered by the local APIC, so the APIC IRQ handling
2791 * rules apply:
2792 */
intel_pmu_handle_irq(struct pt_regs * regs)2793 static int intel_pmu_handle_irq(struct pt_regs *regs)
2794 {
2795 struct cpu_hw_events *cpuc;
2796 int loops;
2797 u64 status;
2798 int handled;
2799 int pmu_enabled;
2800
2801 cpuc = this_cpu_ptr(&cpu_hw_events);
2802
2803 /*
2804 * Save the PMU state.
2805 * It needs to be restored when leaving the handler.
2806 */
2807 pmu_enabled = cpuc->enabled;
2808 /*
2809 * No known reason to not always do late ACK,
2810 * but just in case do it opt-in.
2811 */
2812 if (!x86_pmu.late_ack)
2813 apic_write(APIC_LVTPC, APIC_DM_NMI);
2814 intel_bts_disable_local();
2815 cpuc->enabled = 0;
2816 __intel_pmu_disable_all();
2817 handled = intel_pmu_drain_bts_buffer();
2818 handled += intel_bts_interrupt();
2819 status = intel_pmu_get_status();
2820 if (!status)
2821 goto done;
2822
2823 loops = 0;
2824 again:
2825 intel_pmu_lbr_read();
2826 intel_pmu_ack_status(status);
2827 if (++loops > 100) {
2828 static bool warned;
2829
2830 if (!warned) {
2831 WARN(1, "perfevents: irq loop stuck!\n");
2832 perf_event_print_debug();
2833 warned = true;
2834 }
2835 intel_pmu_reset();
2836 goto done;
2837 }
2838
2839 handled += handle_pmi_common(regs, status);
2840
2841 /*
2842 * Repeat if there is more work to be done:
2843 */
2844 status = intel_pmu_get_status();
2845 if (status)
2846 goto again;
2847
2848 done:
2849 /* Only restore PMU state when it's active. See x86_pmu_disable(). */
2850 cpuc->enabled = pmu_enabled;
2851 if (pmu_enabled)
2852 __intel_pmu_enable_all(0, true);
2853 intel_bts_enable_local();
2854
2855 /*
2856 * Only unmask the NMI after the overflow counters
2857 * have been reset. This avoids spurious NMIs on
2858 * Haswell CPUs.
2859 */
2860 if (x86_pmu.late_ack)
2861 apic_write(APIC_LVTPC, APIC_DM_NMI);
2862 return handled;
2863 }
2864
2865 static struct event_constraint *
intel_bts_constraints(struct perf_event * event)2866 intel_bts_constraints(struct perf_event *event)
2867 {
2868 if (unlikely(intel_pmu_has_bts(event)))
2869 return &bts_constraint;
2870
2871 return NULL;
2872 }
2873
2874 /*
2875 * Note: matches a fake event, like Fixed2.
2876 */
2877 static struct event_constraint *
intel_vlbr_constraints(struct perf_event * event)2878 intel_vlbr_constraints(struct perf_event *event)
2879 {
2880 struct event_constraint *c = &vlbr_constraint;
2881
2882 if (unlikely(constraint_match(c, event->hw.config)))
2883 return c;
2884
2885 return NULL;
2886 }
2887
intel_alt_er(int idx,u64 config)2888 static int intel_alt_er(int idx, u64 config)
2889 {
2890 int alt_idx = idx;
2891
2892 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
2893 return idx;
2894
2895 if (idx == EXTRA_REG_RSP_0)
2896 alt_idx = EXTRA_REG_RSP_1;
2897
2898 if (idx == EXTRA_REG_RSP_1)
2899 alt_idx = EXTRA_REG_RSP_0;
2900
2901 if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask)
2902 return idx;
2903
2904 return alt_idx;
2905 }
2906
intel_fixup_er(struct perf_event * event,int idx)2907 static void intel_fixup_er(struct perf_event *event, int idx)
2908 {
2909 event->hw.extra_reg.idx = idx;
2910
2911 if (idx == EXTRA_REG_RSP_0) {
2912 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
2913 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
2914 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
2915 } else if (idx == EXTRA_REG_RSP_1) {
2916 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
2917 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
2918 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
2919 }
2920 }
2921
2922 /*
2923 * manage allocation of shared extra msr for certain events
2924 *
2925 * sharing can be:
2926 * per-cpu: to be shared between the various events on a single PMU
2927 * per-core: per-cpu + shared by HT threads
2928 */
2929 static struct event_constraint *
__intel_shared_reg_get_constraints(struct cpu_hw_events * cpuc,struct perf_event * event,struct hw_perf_event_extra * reg)2930 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
2931 struct perf_event *event,
2932 struct hw_perf_event_extra *reg)
2933 {
2934 struct event_constraint *c = &emptyconstraint;
2935 struct er_account *era;
2936 unsigned long flags;
2937 int idx = reg->idx;
2938
2939 /*
2940 * reg->alloc can be set due to existing state, so for fake cpuc we
2941 * need to ignore this, otherwise we might fail to allocate proper fake
2942 * state for this extra reg constraint. Also see the comment below.
2943 */
2944 if (reg->alloc && !cpuc->is_fake)
2945 return NULL; /* call x86_get_event_constraint() */
2946
2947 again:
2948 era = &cpuc->shared_regs->regs[idx];
2949 /*
2950 * we use spin_lock_irqsave() to avoid lockdep issues when
2951 * passing a fake cpuc
2952 */
2953 raw_spin_lock_irqsave(&era->lock, flags);
2954
2955 if (!atomic_read(&era->ref) || era->config == reg->config) {
2956
2957 /*
2958 * If its a fake cpuc -- as per validate_{group,event}() we
2959 * shouldn't touch event state and we can avoid doing so
2960 * since both will only call get_event_constraints() once
2961 * on each event, this avoids the need for reg->alloc.
2962 *
2963 * Not doing the ER fixup will only result in era->reg being
2964 * wrong, but since we won't actually try and program hardware
2965 * this isn't a problem either.
2966 */
2967 if (!cpuc->is_fake) {
2968 if (idx != reg->idx)
2969 intel_fixup_er(event, idx);
2970
2971 /*
2972 * x86_schedule_events() can call get_event_constraints()
2973 * multiple times on events in the case of incremental
2974 * scheduling(). reg->alloc ensures we only do the ER
2975 * allocation once.
2976 */
2977 reg->alloc = 1;
2978 }
2979
2980 /* lock in msr value */
2981 era->config = reg->config;
2982 era->reg = reg->reg;
2983
2984 /* one more user */
2985 atomic_inc(&era->ref);
2986
2987 /*
2988 * need to call x86_get_event_constraint()
2989 * to check if associated event has constraints
2990 */
2991 c = NULL;
2992 } else {
2993 idx = intel_alt_er(idx, reg->config);
2994 if (idx != reg->idx) {
2995 raw_spin_unlock_irqrestore(&era->lock, flags);
2996 goto again;
2997 }
2998 }
2999 raw_spin_unlock_irqrestore(&era->lock, flags);
3000
3001 return c;
3002 }
3003
3004 static void
__intel_shared_reg_put_constraints(struct cpu_hw_events * cpuc,struct hw_perf_event_extra * reg)3005 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
3006 struct hw_perf_event_extra *reg)
3007 {
3008 struct er_account *era;
3009
3010 /*
3011 * Only put constraint if extra reg was actually allocated. Also takes
3012 * care of event which do not use an extra shared reg.
3013 *
3014 * Also, if this is a fake cpuc we shouldn't touch any event state
3015 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
3016 * either since it'll be thrown out.
3017 */
3018 if (!reg->alloc || cpuc->is_fake)
3019 return;
3020
3021 era = &cpuc->shared_regs->regs[reg->idx];
3022
3023 /* one fewer user */
3024 atomic_dec(&era->ref);
3025
3026 /* allocate again next time */
3027 reg->alloc = 0;
3028 }
3029
3030 static struct event_constraint *
intel_shared_regs_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)3031 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
3032 struct perf_event *event)
3033 {
3034 struct event_constraint *c = NULL, *d;
3035 struct hw_perf_event_extra *xreg, *breg;
3036
3037 xreg = &event->hw.extra_reg;
3038 if (xreg->idx != EXTRA_REG_NONE) {
3039 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
3040 if (c == &emptyconstraint)
3041 return c;
3042 }
3043 breg = &event->hw.branch_reg;
3044 if (breg->idx != EXTRA_REG_NONE) {
3045 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
3046 if (d == &emptyconstraint) {
3047 __intel_shared_reg_put_constraints(cpuc, xreg);
3048 c = d;
3049 }
3050 }
3051 return c;
3052 }
3053
3054 struct event_constraint *
x86_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3055 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3056 struct perf_event *event)
3057 {
3058 struct event_constraint *c;
3059
3060 if (x86_pmu.event_constraints) {
3061 for_each_event_constraint(c, x86_pmu.event_constraints) {
3062 if (constraint_match(c, event->hw.config)) {
3063 event->hw.flags |= c->flags;
3064 return c;
3065 }
3066 }
3067 }
3068
3069 return &unconstrained;
3070 }
3071
3072 static struct event_constraint *
__intel_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3073 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3074 struct perf_event *event)
3075 {
3076 struct event_constraint *c;
3077
3078 c = intel_vlbr_constraints(event);
3079 if (c)
3080 return c;
3081
3082 c = intel_bts_constraints(event);
3083 if (c)
3084 return c;
3085
3086 c = intel_shared_regs_constraints(cpuc, event);
3087 if (c)
3088 return c;
3089
3090 c = intel_pebs_constraints(event);
3091 if (c)
3092 return c;
3093
3094 return x86_get_event_constraints(cpuc, idx, event);
3095 }
3096
3097 static void
intel_start_scheduling(struct cpu_hw_events * cpuc)3098 intel_start_scheduling(struct cpu_hw_events *cpuc)
3099 {
3100 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3101 struct intel_excl_states *xl;
3102 int tid = cpuc->excl_thread_id;
3103
3104 /*
3105 * nothing needed if in group validation mode
3106 */
3107 if (cpuc->is_fake || !is_ht_workaround_enabled())
3108 return;
3109
3110 /*
3111 * no exclusion needed
3112 */
3113 if (WARN_ON_ONCE(!excl_cntrs))
3114 return;
3115
3116 xl = &excl_cntrs->states[tid];
3117
3118 xl->sched_started = true;
3119 /*
3120 * lock shared state until we are done scheduling
3121 * in stop_event_scheduling()
3122 * makes scheduling appear as a transaction
3123 */
3124 raw_spin_lock(&excl_cntrs->lock);
3125 }
3126
intel_commit_scheduling(struct cpu_hw_events * cpuc,int idx,int cntr)3127 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
3128 {
3129 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3130 struct event_constraint *c = cpuc->event_constraint[idx];
3131 struct intel_excl_states *xl;
3132 int tid = cpuc->excl_thread_id;
3133
3134 if (cpuc->is_fake || !is_ht_workaround_enabled())
3135 return;
3136
3137 if (WARN_ON_ONCE(!excl_cntrs))
3138 return;
3139
3140 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
3141 return;
3142
3143 xl = &excl_cntrs->states[tid];
3144
3145 lockdep_assert_held(&excl_cntrs->lock);
3146
3147 if (c->flags & PERF_X86_EVENT_EXCL)
3148 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
3149 else
3150 xl->state[cntr] = INTEL_EXCL_SHARED;
3151 }
3152
3153 static void
intel_stop_scheduling(struct cpu_hw_events * cpuc)3154 intel_stop_scheduling(struct cpu_hw_events *cpuc)
3155 {
3156 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3157 struct intel_excl_states *xl;
3158 int tid = cpuc->excl_thread_id;
3159
3160 /*
3161 * nothing needed if in group validation mode
3162 */
3163 if (cpuc->is_fake || !is_ht_workaround_enabled())
3164 return;
3165 /*
3166 * no exclusion needed
3167 */
3168 if (WARN_ON_ONCE(!excl_cntrs))
3169 return;
3170
3171 xl = &excl_cntrs->states[tid];
3172
3173 xl->sched_started = false;
3174 /*
3175 * release shared state lock (acquired in intel_start_scheduling())
3176 */
3177 raw_spin_unlock(&excl_cntrs->lock);
3178 }
3179
3180 static struct event_constraint *
dyn_constraint(struct cpu_hw_events * cpuc,struct event_constraint * c,int idx)3181 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx)
3182 {
3183 WARN_ON_ONCE(!cpuc->constraint_list);
3184
3185 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
3186 struct event_constraint *cx;
3187
3188 /*
3189 * grab pre-allocated constraint entry
3190 */
3191 cx = &cpuc->constraint_list[idx];
3192
3193 /*
3194 * initialize dynamic constraint
3195 * with static constraint
3196 */
3197 *cx = *c;
3198
3199 /*
3200 * mark constraint as dynamic
3201 */
3202 cx->flags |= PERF_X86_EVENT_DYNAMIC;
3203 c = cx;
3204 }
3205
3206 return c;
3207 }
3208
3209 static struct event_constraint *
intel_get_excl_constraints(struct cpu_hw_events * cpuc,struct perf_event * event,int idx,struct event_constraint * c)3210 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
3211 int idx, struct event_constraint *c)
3212 {
3213 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3214 struct intel_excl_states *xlo;
3215 int tid = cpuc->excl_thread_id;
3216 int is_excl, i, w;
3217
3218 /*
3219 * validating a group does not require
3220 * enforcing cross-thread exclusion
3221 */
3222 if (cpuc->is_fake || !is_ht_workaround_enabled())
3223 return c;
3224
3225 /*
3226 * no exclusion needed
3227 */
3228 if (WARN_ON_ONCE(!excl_cntrs))
3229 return c;
3230
3231 /*
3232 * because we modify the constraint, we need
3233 * to make a copy. Static constraints come
3234 * from static const tables.
3235 *
3236 * only needed when constraint has not yet
3237 * been cloned (marked dynamic)
3238 */
3239 c = dyn_constraint(cpuc, c, idx);
3240
3241 /*
3242 * From here on, the constraint is dynamic.
3243 * Either it was just allocated above, or it
3244 * was allocated during a earlier invocation
3245 * of this function
3246 */
3247
3248 /*
3249 * state of sibling HT
3250 */
3251 xlo = &excl_cntrs->states[tid ^ 1];
3252
3253 /*
3254 * event requires exclusive counter access
3255 * across HT threads
3256 */
3257 is_excl = c->flags & PERF_X86_EVENT_EXCL;
3258 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
3259 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
3260 if (!cpuc->n_excl++)
3261 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
3262 }
3263
3264 /*
3265 * Modify static constraint with current dynamic
3266 * state of thread
3267 *
3268 * EXCLUSIVE: sibling counter measuring exclusive event
3269 * SHARED : sibling counter measuring non-exclusive event
3270 * UNUSED : sibling counter unused
3271 */
3272 w = c->weight;
3273 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
3274 /*
3275 * exclusive event in sibling counter
3276 * our corresponding counter cannot be used
3277 * regardless of our event
3278 */
3279 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) {
3280 __clear_bit(i, c->idxmsk);
3281 w--;
3282 continue;
3283 }
3284 /*
3285 * if measuring an exclusive event, sibling
3286 * measuring non-exclusive, then counter cannot
3287 * be used
3288 */
3289 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) {
3290 __clear_bit(i, c->idxmsk);
3291 w--;
3292 continue;
3293 }
3294 }
3295
3296 /*
3297 * if we return an empty mask, then switch
3298 * back to static empty constraint to avoid
3299 * the cost of freeing later on
3300 */
3301 if (!w)
3302 c = &emptyconstraint;
3303
3304 c->weight = w;
3305
3306 return c;
3307 }
3308
3309 static struct event_constraint *
intel_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3310 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3311 struct perf_event *event)
3312 {
3313 struct event_constraint *c1, *c2;
3314
3315 c1 = cpuc->event_constraint[idx];
3316
3317 /*
3318 * first time only
3319 * - static constraint: no change across incremental scheduling calls
3320 * - dynamic constraint: handled by intel_get_excl_constraints()
3321 */
3322 c2 = __intel_get_event_constraints(cpuc, idx, event);
3323 if (c1) {
3324 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC));
3325 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
3326 c1->weight = c2->weight;
3327 c2 = c1;
3328 }
3329
3330 if (cpuc->excl_cntrs)
3331 return intel_get_excl_constraints(cpuc, event, idx, c2);
3332
3333 return c2;
3334 }
3335
intel_put_excl_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)3336 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
3337 struct perf_event *event)
3338 {
3339 struct hw_perf_event *hwc = &event->hw;
3340 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3341 int tid = cpuc->excl_thread_id;
3342 struct intel_excl_states *xl;
3343
3344 /*
3345 * nothing needed if in group validation mode
3346 */
3347 if (cpuc->is_fake)
3348 return;
3349
3350 if (WARN_ON_ONCE(!excl_cntrs))
3351 return;
3352
3353 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
3354 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
3355 if (!--cpuc->n_excl)
3356 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
3357 }
3358
3359 /*
3360 * If event was actually assigned, then mark the counter state as
3361 * unused now.
3362 */
3363 if (hwc->idx >= 0) {
3364 xl = &excl_cntrs->states[tid];
3365
3366 /*
3367 * put_constraint may be called from x86_schedule_events()
3368 * which already has the lock held so here make locking
3369 * conditional.
3370 */
3371 if (!xl->sched_started)
3372 raw_spin_lock(&excl_cntrs->lock);
3373
3374 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
3375
3376 if (!xl->sched_started)
3377 raw_spin_unlock(&excl_cntrs->lock);
3378 }
3379 }
3380
3381 static void
intel_put_shared_regs_event_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)3382 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
3383 struct perf_event *event)
3384 {
3385 struct hw_perf_event_extra *reg;
3386
3387 reg = &event->hw.extra_reg;
3388 if (reg->idx != EXTRA_REG_NONE)
3389 __intel_shared_reg_put_constraints(cpuc, reg);
3390
3391 reg = &event->hw.branch_reg;
3392 if (reg->idx != EXTRA_REG_NONE)
3393 __intel_shared_reg_put_constraints(cpuc, reg);
3394 }
3395
intel_put_event_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)3396 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
3397 struct perf_event *event)
3398 {
3399 intel_put_shared_regs_event_constraints(cpuc, event);
3400
3401 /*
3402 * is PMU has exclusive counter restrictions, then
3403 * all events are subject to and must call the
3404 * put_excl_constraints() routine
3405 */
3406 if (cpuc->excl_cntrs)
3407 intel_put_excl_constraints(cpuc, event);
3408 }
3409
intel_pebs_aliases_core2(struct perf_event * event)3410 static void intel_pebs_aliases_core2(struct perf_event *event)
3411 {
3412 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3413 /*
3414 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3415 * (0x003c) so that we can use it with PEBS.
3416 *
3417 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3418 * PEBS capable. However we can use INST_RETIRED.ANY_P
3419 * (0x00c0), which is a PEBS capable event, to get the same
3420 * count.
3421 *
3422 * INST_RETIRED.ANY_P counts the number of cycles that retires
3423 * CNTMASK instructions. By setting CNTMASK to a value (16)
3424 * larger than the maximum number of instructions that can be
3425 * retired per cycle (4) and then inverting the condition, we
3426 * count all cycles that retire 16 or less instructions, which
3427 * is every cycle.
3428 *
3429 * Thereby we gain a PEBS capable cycle counter.
3430 */
3431 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
3432
3433 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3434 event->hw.config = alt_config;
3435 }
3436 }
3437
intel_pebs_aliases_snb(struct perf_event * event)3438 static void intel_pebs_aliases_snb(struct perf_event *event)
3439 {
3440 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3441 /*
3442 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3443 * (0x003c) so that we can use it with PEBS.
3444 *
3445 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3446 * PEBS capable. However we can use UOPS_RETIRED.ALL
3447 * (0x01c2), which is a PEBS capable event, to get the same
3448 * count.
3449 *
3450 * UOPS_RETIRED.ALL counts the number of cycles that retires
3451 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
3452 * larger than the maximum number of micro-ops that can be
3453 * retired per cycle (4) and then inverting the condition, we
3454 * count all cycles that retire 16 or less micro-ops, which
3455 * is every cycle.
3456 *
3457 * Thereby we gain a PEBS capable cycle counter.
3458 */
3459 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
3460
3461 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3462 event->hw.config = alt_config;
3463 }
3464 }
3465
intel_pebs_aliases_precdist(struct perf_event * event)3466 static void intel_pebs_aliases_precdist(struct perf_event *event)
3467 {
3468 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3469 /*
3470 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3471 * (0x003c) so that we can use it with PEBS.
3472 *
3473 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3474 * PEBS capable. However we can use INST_RETIRED.PREC_DIST
3475 * (0x01c0), which is a PEBS capable event, to get the same
3476 * count.
3477 *
3478 * The PREC_DIST event has special support to minimize sample
3479 * shadowing effects. One drawback is that it can be
3480 * only programmed on counter 1, but that seems like an
3481 * acceptable trade off.
3482 */
3483 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
3484
3485 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3486 event->hw.config = alt_config;
3487 }
3488 }
3489
intel_pebs_aliases_ivb(struct perf_event * event)3490 static void intel_pebs_aliases_ivb(struct perf_event *event)
3491 {
3492 if (event->attr.precise_ip < 3)
3493 return intel_pebs_aliases_snb(event);
3494 return intel_pebs_aliases_precdist(event);
3495 }
3496
intel_pebs_aliases_skl(struct perf_event * event)3497 static void intel_pebs_aliases_skl(struct perf_event *event)
3498 {
3499 if (event->attr.precise_ip < 3)
3500 return intel_pebs_aliases_core2(event);
3501 return intel_pebs_aliases_precdist(event);
3502 }
3503
intel_pmu_large_pebs_flags(struct perf_event * event)3504 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
3505 {
3506 unsigned long flags = x86_pmu.large_pebs_flags;
3507
3508 if (event->attr.use_clockid)
3509 flags &= ~PERF_SAMPLE_TIME;
3510 if (!event->attr.exclude_kernel)
3511 flags &= ~PERF_SAMPLE_REGS_USER;
3512 if (event->attr.sample_regs_user & ~PEBS_GP_REGS)
3513 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
3514 return flags;
3515 }
3516
intel_pmu_bts_config(struct perf_event * event)3517 static int intel_pmu_bts_config(struct perf_event *event)
3518 {
3519 struct perf_event_attr *attr = &event->attr;
3520
3521 if (unlikely(intel_pmu_has_bts(event))) {
3522 /* BTS is not supported by this architecture. */
3523 if (!x86_pmu.bts_active)
3524 return -EOPNOTSUPP;
3525
3526 /* BTS is currently only allowed for user-mode. */
3527 if (!attr->exclude_kernel)
3528 return -EOPNOTSUPP;
3529
3530 /* BTS is not allowed for precise events. */
3531 if (attr->precise_ip)
3532 return -EOPNOTSUPP;
3533
3534 /* disallow bts if conflicting events are present */
3535 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3536 return -EBUSY;
3537
3538 event->destroy = hw_perf_lbr_event_destroy;
3539 }
3540
3541 return 0;
3542 }
3543
core_pmu_hw_config(struct perf_event * event)3544 static int core_pmu_hw_config(struct perf_event *event)
3545 {
3546 int ret = x86_pmu_hw_config(event);
3547
3548 if (ret)
3549 return ret;
3550
3551 return intel_pmu_bts_config(event);
3552 }
3553
intel_pmu_hw_config(struct perf_event * event)3554 static int intel_pmu_hw_config(struct perf_event *event)
3555 {
3556 int ret = x86_pmu_hw_config(event);
3557
3558 if (ret)
3559 return ret;
3560
3561 ret = intel_pmu_bts_config(event);
3562 if (ret)
3563 return ret;
3564
3565 if (event->attr.precise_ip) {
3566 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT)
3567 return -EINVAL;
3568
3569 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) {
3570 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
3571 if (!(event->attr.sample_type &
3572 ~intel_pmu_large_pebs_flags(event))) {
3573 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
3574 event->attach_state |= PERF_ATTACH_SCHED_CB;
3575 }
3576 }
3577 if (x86_pmu.pebs_aliases)
3578 x86_pmu.pebs_aliases(event);
3579
3580 if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN)
3581 event->attr.sample_type |= __PERF_SAMPLE_CALLCHAIN_EARLY;
3582 }
3583
3584 if (needs_branch_stack(event)) {
3585 ret = intel_pmu_setup_lbr_filter(event);
3586 if (ret)
3587 return ret;
3588 event->attach_state |= PERF_ATTACH_SCHED_CB;
3589
3590 /*
3591 * BTS is set up earlier in this path, so don't account twice
3592 */
3593 if (!unlikely(intel_pmu_has_bts(event))) {
3594 /* disallow lbr if conflicting events are present */
3595 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3596 return -EBUSY;
3597
3598 event->destroy = hw_perf_lbr_event_destroy;
3599 }
3600 }
3601
3602 if (event->attr.aux_output) {
3603 if (!event->attr.precise_ip)
3604 return -EINVAL;
3605
3606 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT;
3607 }
3608
3609 if (event->attr.type != PERF_TYPE_RAW)
3610 return 0;
3611
3612 /*
3613 * Config Topdown slots and metric events
3614 *
3615 * The slots event on Fixed Counter 3 can support sampling,
3616 * which will be handled normally in x86_perf_event_update().
3617 *
3618 * Metric events don't support sampling and require being paired
3619 * with a slots event as group leader. When the slots event
3620 * is used in a metrics group, it too cannot support sampling.
3621 */
3622 if (x86_pmu.intel_cap.perf_metrics && is_topdown_event(event)) {
3623 if (event->attr.config1 || event->attr.config2)
3624 return -EINVAL;
3625
3626 /*
3627 * The TopDown metrics events and slots event don't
3628 * support any filters.
3629 */
3630 if (event->attr.config & X86_ALL_EVENT_FLAGS)
3631 return -EINVAL;
3632
3633 if (is_metric_event(event)) {
3634 struct perf_event *leader = event->group_leader;
3635
3636 /* The metric events don't support sampling. */
3637 if (is_sampling_event(event))
3638 return -EINVAL;
3639
3640 /* The metric events require a slots group leader. */
3641 if (!is_slots_event(leader))
3642 return -EINVAL;
3643
3644 /*
3645 * The leader/SLOTS must not be a sampling event for
3646 * metric use; hardware requires it starts at 0 when used
3647 * in conjunction with MSR_PERF_METRICS.
3648 */
3649 if (is_sampling_event(leader))
3650 return -EINVAL;
3651
3652 event->event_caps |= PERF_EV_CAP_SIBLING;
3653 /*
3654 * Only once we have a METRICs sibling do we
3655 * need TopDown magic.
3656 */
3657 leader->hw.flags |= PERF_X86_EVENT_TOPDOWN;
3658 event->hw.flags |= PERF_X86_EVENT_TOPDOWN;
3659 }
3660 }
3661
3662 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
3663 return 0;
3664
3665 if (x86_pmu.version < 3)
3666 return -EINVAL;
3667
3668 ret = perf_allow_cpu(&event->attr);
3669 if (ret)
3670 return ret;
3671
3672 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
3673
3674 return 0;
3675 }
3676
3677 #ifdef CONFIG_RETPOLINE
3678 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr);
3679 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr);
3680 #endif
3681
perf_guest_get_msrs(int * nr)3682 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
3683 {
3684 #ifdef CONFIG_RETPOLINE
3685 if (x86_pmu.guest_get_msrs == intel_guest_get_msrs)
3686 return intel_guest_get_msrs(nr);
3687 else if (x86_pmu.guest_get_msrs == core_guest_get_msrs)
3688 return core_guest_get_msrs(nr);
3689 #endif
3690 if (x86_pmu.guest_get_msrs)
3691 return x86_pmu.guest_get_msrs(nr);
3692 *nr = 0;
3693 return NULL;
3694 }
3695 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
3696
intel_guest_get_msrs(int * nr)3697 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
3698 {
3699 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3700 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
3701
3702 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
3703 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
3704 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
3705 if (x86_pmu.flags & PMU_FL_PEBS_ALL)
3706 arr[0].guest &= ~cpuc->pebs_enabled;
3707 else
3708 arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
3709 *nr = 1;
3710
3711 if (x86_pmu.pebs && x86_pmu.pebs_no_isolation) {
3712 /*
3713 * If PMU counter has PEBS enabled it is not enough to
3714 * disable counter on a guest entry since PEBS memory
3715 * write can overshoot guest entry and corrupt guest
3716 * memory. Disabling PEBS solves the problem.
3717 *
3718 * Don't do this if the CPU already enforces it.
3719 */
3720 arr[1].msr = MSR_IA32_PEBS_ENABLE;
3721 arr[1].host = cpuc->pebs_enabled;
3722 arr[1].guest = 0;
3723 *nr = 2;
3724 }
3725
3726 return arr;
3727 }
3728
core_guest_get_msrs(int * nr)3729 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
3730 {
3731 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3732 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
3733 int idx;
3734
3735 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
3736 struct perf_event *event = cpuc->events[idx];
3737
3738 arr[idx].msr = x86_pmu_config_addr(idx);
3739 arr[idx].host = arr[idx].guest = 0;
3740
3741 if (!test_bit(idx, cpuc->active_mask))
3742 continue;
3743
3744 arr[idx].host = arr[idx].guest =
3745 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
3746
3747 if (event->attr.exclude_host)
3748 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
3749 else if (event->attr.exclude_guest)
3750 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
3751 }
3752
3753 *nr = x86_pmu.num_counters;
3754 return arr;
3755 }
3756
core_pmu_enable_event(struct perf_event * event)3757 static void core_pmu_enable_event(struct perf_event *event)
3758 {
3759 if (!event->attr.exclude_host)
3760 x86_pmu_enable_event(event);
3761 }
3762
core_pmu_enable_all(int added)3763 static void core_pmu_enable_all(int added)
3764 {
3765 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3766 int idx;
3767
3768 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
3769 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
3770
3771 if (!test_bit(idx, cpuc->active_mask) ||
3772 cpuc->events[idx]->attr.exclude_host)
3773 continue;
3774
3775 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
3776 }
3777 }
3778
hsw_hw_config(struct perf_event * event)3779 static int hsw_hw_config(struct perf_event *event)
3780 {
3781 int ret = intel_pmu_hw_config(event);
3782
3783 if (ret)
3784 return ret;
3785 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
3786 return 0;
3787 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
3788
3789 /*
3790 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
3791 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
3792 * this combination.
3793 */
3794 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
3795 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
3796 event->attr.precise_ip > 0))
3797 return -EOPNOTSUPP;
3798
3799 if (event_is_checkpointed(event)) {
3800 /*
3801 * Sampling of checkpointed events can cause situations where
3802 * the CPU constantly aborts because of a overflow, which is
3803 * then checkpointed back and ignored. Forbid checkpointing
3804 * for sampling.
3805 *
3806 * But still allow a long sampling period, so that perf stat
3807 * from KVM works.
3808 */
3809 if (event->attr.sample_period > 0 &&
3810 event->attr.sample_period < 0x7fffffff)
3811 return -EOPNOTSUPP;
3812 }
3813 return 0;
3814 }
3815
3816 static struct event_constraint counter0_constraint =
3817 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1);
3818
3819 static struct event_constraint counter2_constraint =
3820 EVENT_CONSTRAINT(0, 0x4, 0);
3821
3822 static struct event_constraint fixed0_constraint =
3823 FIXED_EVENT_CONSTRAINT(0x00c0, 0);
3824
3825 static struct event_constraint fixed0_counter0_constraint =
3826 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL);
3827
3828 static struct event_constraint *
hsw_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3829 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3830 struct perf_event *event)
3831 {
3832 struct event_constraint *c;
3833
3834 c = intel_get_event_constraints(cpuc, idx, event);
3835
3836 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
3837 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
3838 if (c->idxmsk64 & (1U << 2))
3839 return &counter2_constraint;
3840 return &emptyconstraint;
3841 }
3842
3843 return c;
3844 }
3845
3846 static struct event_constraint *
icl_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3847 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3848 struct perf_event *event)
3849 {
3850 /*
3851 * Fixed counter 0 has less skid.
3852 * Force instruction:ppp in Fixed counter 0
3853 */
3854 if ((event->attr.precise_ip == 3) &&
3855 constraint_match(&fixed0_constraint, event->hw.config))
3856 return &fixed0_constraint;
3857
3858 return hsw_get_event_constraints(cpuc, idx, event);
3859 }
3860
3861 static struct event_constraint *
glp_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3862 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3863 struct perf_event *event)
3864 {
3865 struct event_constraint *c;
3866
3867 /* :ppp means to do reduced skid PEBS which is PMC0 only. */
3868 if (event->attr.precise_ip == 3)
3869 return &counter0_constraint;
3870
3871 c = intel_get_event_constraints(cpuc, idx, event);
3872
3873 return c;
3874 }
3875
3876 static struct event_constraint *
tnt_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3877 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3878 struct perf_event *event)
3879 {
3880 struct event_constraint *c;
3881
3882 /*
3883 * :ppp means to do reduced skid PEBS,
3884 * which is available on PMC0 and fixed counter 0.
3885 */
3886 if (event->attr.precise_ip == 3) {
3887 /* Force instruction:ppp on PMC0 and Fixed counter 0 */
3888 if (constraint_match(&fixed0_constraint, event->hw.config))
3889 return &fixed0_counter0_constraint;
3890
3891 return &counter0_constraint;
3892 }
3893
3894 c = intel_get_event_constraints(cpuc, idx, event);
3895
3896 return c;
3897 }
3898
3899 static bool allow_tsx_force_abort = true;
3900
3901 static struct event_constraint *
tfa_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3902 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3903 struct perf_event *event)
3904 {
3905 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event);
3906
3907 /*
3908 * Without TFA we must not use PMC3.
3909 */
3910 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) {
3911 c = dyn_constraint(cpuc, c, idx);
3912 c->idxmsk64 &= ~(1ULL << 3);
3913 c->weight--;
3914 }
3915
3916 return c;
3917 }
3918
3919 /*
3920 * Broadwell:
3921 *
3922 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
3923 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
3924 * the two to enforce a minimum period of 128 (the smallest value that has bits
3925 * 0-5 cleared and >= 100).
3926 *
3927 * Because of how the code in x86_perf_event_set_period() works, the truncation
3928 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
3929 * to make up for the 'lost' events due to carrying the 'error' in period_left.
3930 *
3931 * Therefore the effective (average) period matches the requested period,
3932 * despite coarser hardware granularity.
3933 */
bdw_limit_period(struct perf_event * event,u64 left)3934 static u64 bdw_limit_period(struct perf_event *event, u64 left)
3935 {
3936 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
3937 X86_CONFIG(.event=0xc0, .umask=0x01)) {
3938 if (left < 128)
3939 left = 128;
3940 left &= ~0x3fULL;
3941 }
3942 return left;
3943 }
3944
nhm_limit_period(struct perf_event * event,u64 left)3945 static u64 nhm_limit_period(struct perf_event *event, u64 left)
3946 {
3947 return max(left, 32ULL);
3948 }
3949
3950 PMU_FORMAT_ATTR(event, "config:0-7" );
3951 PMU_FORMAT_ATTR(umask, "config:8-15" );
3952 PMU_FORMAT_ATTR(edge, "config:18" );
3953 PMU_FORMAT_ATTR(pc, "config:19" );
3954 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
3955 PMU_FORMAT_ATTR(inv, "config:23" );
3956 PMU_FORMAT_ATTR(cmask, "config:24-31" );
3957 PMU_FORMAT_ATTR(in_tx, "config:32");
3958 PMU_FORMAT_ATTR(in_tx_cp, "config:33");
3959
3960 static struct attribute *intel_arch_formats_attr[] = {
3961 &format_attr_event.attr,
3962 &format_attr_umask.attr,
3963 &format_attr_edge.attr,
3964 &format_attr_pc.attr,
3965 &format_attr_inv.attr,
3966 &format_attr_cmask.attr,
3967 NULL,
3968 };
3969
intel_event_sysfs_show(char * page,u64 config)3970 ssize_t intel_event_sysfs_show(char *page, u64 config)
3971 {
3972 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
3973
3974 return x86_event_sysfs_show(page, config, event);
3975 }
3976
allocate_shared_regs(int cpu)3977 static struct intel_shared_regs *allocate_shared_regs(int cpu)
3978 {
3979 struct intel_shared_regs *regs;
3980 int i;
3981
3982 regs = kzalloc_node(sizeof(struct intel_shared_regs),
3983 GFP_KERNEL, cpu_to_node(cpu));
3984 if (regs) {
3985 /*
3986 * initialize the locks to keep lockdep happy
3987 */
3988 for (i = 0; i < EXTRA_REG_MAX; i++)
3989 raw_spin_lock_init(®s->regs[i].lock);
3990
3991 regs->core_id = -1;
3992 }
3993 return regs;
3994 }
3995
allocate_excl_cntrs(int cpu)3996 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
3997 {
3998 struct intel_excl_cntrs *c;
3999
4000 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
4001 GFP_KERNEL, cpu_to_node(cpu));
4002 if (c) {
4003 raw_spin_lock_init(&c->lock);
4004 c->core_id = -1;
4005 }
4006 return c;
4007 }
4008
4009
intel_cpuc_prepare(struct cpu_hw_events * cpuc,int cpu)4010 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
4011 {
4012 cpuc->pebs_record_size = x86_pmu.pebs_record_size;
4013
4014 if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
4015 cpuc->shared_regs = allocate_shared_regs(cpu);
4016 if (!cpuc->shared_regs)
4017 goto err;
4018 }
4019
4020 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) {
4021 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
4022
4023 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu));
4024 if (!cpuc->constraint_list)
4025 goto err_shared_regs;
4026 }
4027
4028 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
4029 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
4030 if (!cpuc->excl_cntrs)
4031 goto err_constraint_list;
4032
4033 cpuc->excl_thread_id = 0;
4034 }
4035
4036 return 0;
4037
4038 err_constraint_list:
4039 kfree(cpuc->constraint_list);
4040 cpuc->constraint_list = NULL;
4041
4042 err_shared_regs:
4043 kfree(cpuc->shared_regs);
4044 cpuc->shared_regs = NULL;
4045
4046 err:
4047 return -ENOMEM;
4048 }
4049
intel_pmu_cpu_prepare(int cpu)4050 static int intel_pmu_cpu_prepare(int cpu)
4051 {
4052 return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu);
4053 }
4054
flip_smm_bit(void * data)4055 static void flip_smm_bit(void *data)
4056 {
4057 unsigned long set = *(unsigned long *)data;
4058
4059 if (set > 0) {
4060 msr_set_bit(MSR_IA32_DEBUGCTLMSR,
4061 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
4062 } else {
4063 msr_clear_bit(MSR_IA32_DEBUGCTLMSR,
4064 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
4065 }
4066 }
4067
intel_pmu_cpu_starting(int cpu)4068 static void intel_pmu_cpu_starting(int cpu)
4069 {
4070 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
4071 int core_id = topology_core_id(cpu);
4072 int i;
4073
4074 init_debug_store_on_cpu(cpu);
4075 /*
4076 * Deal with CPUs that don't clear their LBRs on power-up.
4077 */
4078 intel_pmu_lbr_reset();
4079
4080 cpuc->lbr_sel = NULL;
4081
4082 if (x86_pmu.flags & PMU_FL_TFA) {
4083 WARN_ON_ONCE(cpuc->tfa_shadow);
4084 cpuc->tfa_shadow = ~0ULL;
4085 intel_set_tfa(cpuc, false);
4086 }
4087
4088 if (x86_pmu.version > 1)
4089 flip_smm_bit(&x86_pmu.attr_freeze_on_smi);
4090
4091 if (x86_pmu.counter_freezing)
4092 enable_counter_freeze();
4093
4094 /* Disable perf metrics if any added CPU doesn't support it. */
4095 if (x86_pmu.intel_cap.perf_metrics) {
4096 union perf_capabilities perf_cap;
4097
4098 rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities);
4099 if (!perf_cap.perf_metrics) {
4100 x86_pmu.intel_cap.perf_metrics = 0;
4101 x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS);
4102 }
4103 }
4104
4105 if (!cpuc->shared_regs)
4106 return;
4107
4108 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
4109 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
4110 struct intel_shared_regs *pc;
4111
4112 pc = per_cpu(cpu_hw_events, i).shared_regs;
4113 if (pc && pc->core_id == core_id) {
4114 cpuc->kfree_on_online[0] = cpuc->shared_regs;
4115 cpuc->shared_regs = pc;
4116 break;
4117 }
4118 }
4119 cpuc->shared_regs->core_id = core_id;
4120 cpuc->shared_regs->refcnt++;
4121 }
4122
4123 if (x86_pmu.lbr_sel_map)
4124 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
4125
4126 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
4127 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
4128 struct cpu_hw_events *sibling;
4129 struct intel_excl_cntrs *c;
4130
4131 sibling = &per_cpu(cpu_hw_events, i);
4132 c = sibling->excl_cntrs;
4133 if (c && c->core_id == core_id) {
4134 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
4135 cpuc->excl_cntrs = c;
4136 if (!sibling->excl_thread_id)
4137 cpuc->excl_thread_id = 1;
4138 break;
4139 }
4140 }
4141 cpuc->excl_cntrs->core_id = core_id;
4142 cpuc->excl_cntrs->refcnt++;
4143 }
4144 }
4145
free_excl_cntrs(struct cpu_hw_events * cpuc)4146 static void free_excl_cntrs(struct cpu_hw_events *cpuc)
4147 {
4148 struct intel_excl_cntrs *c;
4149
4150 c = cpuc->excl_cntrs;
4151 if (c) {
4152 if (c->core_id == -1 || --c->refcnt == 0)
4153 kfree(c);
4154 cpuc->excl_cntrs = NULL;
4155 }
4156
4157 kfree(cpuc->constraint_list);
4158 cpuc->constraint_list = NULL;
4159 }
4160
intel_pmu_cpu_dying(int cpu)4161 static void intel_pmu_cpu_dying(int cpu)
4162 {
4163 fini_debug_store_on_cpu(cpu);
4164
4165 if (x86_pmu.counter_freezing)
4166 disable_counter_freeze();
4167 }
4168
intel_cpuc_finish(struct cpu_hw_events * cpuc)4169 void intel_cpuc_finish(struct cpu_hw_events *cpuc)
4170 {
4171 struct intel_shared_regs *pc;
4172
4173 pc = cpuc->shared_regs;
4174 if (pc) {
4175 if (pc->core_id == -1 || --pc->refcnt == 0)
4176 kfree(pc);
4177 cpuc->shared_regs = NULL;
4178 }
4179
4180 free_excl_cntrs(cpuc);
4181 }
4182
intel_pmu_cpu_dead(int cpu)4183 static void intel_pmu_cpu_dead(int cpu)
4184 {
4185 intel_cpuc_finish(&per_cpu(cpu_hw_events, cpu));
4186 }
4187
intel_pmu_sched_task(struct perf_event_context * ctx,bool sched_in)4188 static void intel_pmu_sched_task(struct perf_event_context *ctx,
4189 bool sched_in)
4190 {
4191 intel_pmu_pebs_sched_task(ctx, sched_in);
4192 intel_pmu_lbr_sched_task(ctx, sched_in);
4193 }
4194
intel_pmu_swap_task_ctx(struct perf_event_context * prev,struct perf_event_context * next)4195 static void intel_pmu_swap_task_ctx(struct perf_event_context *prev,
4196 struct perf_event_context *next)
4197 {
4198 intel_pmu_lbr_swap_task_ctx(prev, next);
4199 }
4200
intel_pmu_check_period(struct perf_event * event,u64 value)4201 static int intel_pmu_check_period(struct perf_event *event, u64 value)
4202 {
4203 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0;
4204 }
4205
intel_pmu_aux_output_match(struct perf_event * event)4206 static int intel_pmu_aux_output_match(struct perf_event *event)
4207 {
4208 if (!x86_pmu.intel_cap.pebs_output_pt_available)
4209 return 0;
4210
4211 return is_intel_pt_event(event);
4212 }
4213
4214 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
4215
4216 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
4217
4218 PMU_FORMAT_ATTR(frontend, "config1:0-23");
4219
4220 static struct attribute *intel_arch3_formats_attr[] = {
4221 &format_attr_event.attr,
4222 &format_attr_umask.attr,
4223 &format_attr_edge.attr,
4224 &format_attr_pc.attr,
4225 &format_attr_any.attr,
4226 &format_attr_inv.attr,
4227 &format_attr_cmask.attr,
4228 NULL,
4229 };
4230
4231 static struct attribute *hsw_format_attr[] = {
4232 &format_attr_in_tx.attr,
4233 &format_attr_in_tx_cp.attr,
4234 &format_attr_offcore_rsp.attr,
4235 &format_attr_ldlat.attr,
4236 NULL
4237 };
4238
4239 static struct attribute *nhm_format_attr[] = {
4240 &format_attr_offcore_rsp.attr,
4241 &format_attr_ldlat.attr,
4242 NULL
4243 };
4244
4245 static struct attribute *slm_format_attr[] = {
4246 &format_attr_offcore_rsp.attr,
4247 NULL
4248 };
4249
4250 static struct attribute *skl_format_attr[] = {
4251 &format_attr_frontend.attr,
4252 NULL,
4253 };
4254
4255 static __initconst const struct x86_pmu core_pmu = {
4256 .name = "core",
4257 .handle_irq = x86_pmu_handle_irq,
4258 .disable_all = x86_pmu_disable_all,
4259 .enable_all = core_pmu_enable_all,
4260 .enable = core_pmu_enable_event,
4261 .disable = x86_pmu_disable_event,
4262 .hw_config = core_pmu_hw_config,
4263 .schedule_events = x86_schedule_events,
4264 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
4265 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
4266 .event_map = intel_pmu_event_map,
4267 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
4268 .apic = 1,
4269 .large_pebs_flags = LARGE_PEBS_FLAGS,
4270
4271 /*
4272 * Intel PMCs cannot be accessed sanely above 32-bit width,
4273 * so we install an artificial 1<<31 period regardless of
4274 * the generic event period:
4275 */
4276 .max_period = (1ULL<<31) - 1,
4277 .get_event_constraints = intel_get_event_constraints,
4278 .put_event_constraints = intel_put_event_constraints,
4279 .event_constraints = intel_core_event_constraints,
4280 .guest_get_msrs = core_guest_get_msrs,
4281 .format_attrs = intel_arch_formats_attr,
4282 .events_sysfs_show = intel_event_sysfs_show,
4283
4284 /*
4285 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
4286 * together with PMU version 1 and thus be using core_pmu with
4287 * shared_regs. We need following callbacks here to allocate
4288 * it properly.
4289 */
4290 .cpu_prepare = intel_pmu_cpu_prepare,
4291 .cpu_starting = intel_pmu_cpu_starting,
4292 .cpu_dying = intel_pmu_cpu_dying,
4293 .cpu_dead = intel_pmu_cpu_dead,
4294
4295 .check_period = intel_pmu_check_period,
4296
4297 .lbr_reset = intel_pmu_lbr_reset_64,
4298 .lbr_read = intel_pmu_lbr_read_64,
4299 .lbr_save = intel_pmu_lbr_save,
4300 .lbr_restore = intel_pmu_lbr_restore,
4301 };
4302
4303 static __initconst const struct x86_pmu intel_pmu = {
4304 .name = "Intel",
4305 .handle_irq = intel_pmu_handle_irq,
4306 .disable_all = intel_pmu_disable_all,
4307 .enable_all = intel_pmu_enable_all,
4308 .enable = intel_pmu_enable_event,
4309 .disable = intel_pmu_disable_event,
4310 .add = intel_pmu_add_event,
4311 .del = intel_pmu_del_event,
4312 .read = intel_pmu_read_event,
4313 .hw_config = intel_pmu_hw_config,
4314 .schedule_events = x86_schedule_events,
4315 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
4316 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
4317 .event_map = intel_pmu_event_map,
4318 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
4319 .apic = 1,
4320 .large_pebs_flags = LARGE_PEBS_FLAGS,
4321 /*
4322 * Intel PMCs cannot be accessed sanely above 32 bit width,
4323 * so we install an artificial 1<<31 period regardless of
4324 * the generic event period:
4325 */
4326 .max_period = (1ULL << 31) - 1,
4327 .get_event_constraints = intel_get_event_constraints,
4328 .put_event_constraints = intel_put_event_constraints,
4329 .pebs_aliases = intel_pebs_aliases_core2,
4330
4331 .format_attrs = intel_arch3_formats_attr,
4332 .events_sysfs_show = intel_event_sysfs_show,
4333
4334 .cpu_prepare = intel_pmu_cpu_prepare,
4335 .cpu_starting = intel_pmu_cpu_starting,
4336 .cpu_dying = intel_pmu_cpu_dying,
4337 .cpu_dead = intel_pmu_cpu_dead,
4338
4339 .guest_get_msrs = intel_guest_get_msrs,
4340 .sched_task = intel_pmu_sched_task,
4341 .swap_task_ctx = intel_pmu_swap_task_ctx,
4342
4343 .check_period = intel_pmu_check_period,
4344
4345 .aux_output_match = intel_pmu_aux_output_match,
4346
4347 .lbr_reset = intel_pmu_lbr_reset_64,
4348 .lbr_read = intel_pmu_lbr_read_64,
4349 .lbr_save = intel_pmu_lbr_save,
4350 .lbr_restore = intel_pmu_lbr_restore,
4351 };
4352
intel_clovertown_quirk(void)4353 static __init void intel_clovertown_quirk(void)
4354 {
4355 /*
4356 * PEBS is unreliable due to:
4357 *
4358 * AJ67 - PEBS may experience CPL leaks
4359 * AJ68 - PEBS PMI may be delayed by one event
4360 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
4361 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
4362 *
4363 * AJ67 could be worked around by restricting the OS/USR flags.
4364 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
4365 *
4366 * AJ106 could possibly be worked around by not allowing LBR
4367 * usage from PEBS, including the fixup.
4368 * AJ68 could possibly be worked around by always programming
4369 * a pebs_event_reset[0] value and coping with the lost events.
4370 *
4371 * But taken together it might just make sense to not enable PEBS on
4372 * these chips.
4373 */
4374 pr_warn("PEBS disabled due to CPU errata\n");
4375 x86_pmu.pebs = 0;
4376 x86_pmu.pebs_constraints = NULL;
4377 }
4378
4379 static const struct x86_cpu_desc isolation_ucodes[] = {
4380 INTEL_CPU_DESC(INTEL_FAM6_HASWELL, 3, 0x0000001f),
4381 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L, 1, 0x0000001e),
4382 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G, 1, 0x00000015),
4383 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 2, 0x00000037),
4384 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 4, 0x0000000a),
4385 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL, 4, 0x00000023),
4386 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G, 1, 0x00000014),
4387 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 2, 0x00000010),
4388 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 3, 0x07000009),
4389 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 4, 0x0f000009),
4390 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 5, 0x0e000002),
4391 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X, 1, 0x0b000014),
4392 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 3, 0x00000021),
4393 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 4, 0x00000000),
4394 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 5, 0x00000000),
4395 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 6, 0x00000000),
4396 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 7, 0x00000000),
4397 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_L, 3, 0x0000007c),
4398 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE, 3, 0x0000007c),
4399 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 9, 0x0000004e),
4400 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 9, 0x0000004e),
4401 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 10, 0x0000004e),
4402 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 11, 0x0000004e),
4403 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 12, 0x0000004e),
4404 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 10, 0x0000004e),
4405 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 11, 0x0000004e),
4406 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 12, 0x0000004e),
4407 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 13, 0x0000004e),
4408 {}
4409 };
4410
intel_check_pebs_isolation(void)4411 static void intel_check_pebs_isolation(void)
4412 {
4413 x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes);
4414 }
4415
intel_pebs_isolation_quirk(void)4416 static __init void intel_pebs_isolation_quirk(void)
4417 {
4418 WARN_ON_ONCE(x86_pmu.check_microcode);
4419 x86_pmu.check_microcode = intel_check_pebs_isolation;
4420 intel_check_pebs_isolation();
4421 }
4422
4423 static const struct x86_cpu_desc pebs_ucodes[] = {
4424 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE, 7, 0x00000028),
4425 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 6, 0x00000618),
4426 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 7, 0x0000070c),
4427 {}
4428 };
4429
intel_snb_pebs_broken(void)4430 static bool intel_snb_pebs_broken(void)
4431 {
4432 return !x86_cpu_has_min_microcode_rev(pebs_ucodes);
4433 }
4434
intel_snb_check_microcode(void)4435 static void intel_snb_check_microcode(void)
4436 {
4437 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken)
4438 return;
4439
4440 /*
4441 * Serialized by the microcode lock..
4442 */
4443 if (x86_pmu.pebs_broken) {
4444 pr_info("PEBS enabled due to microcode update\n");
4445 x86_pmu.pebs_broken = 0;
4446 } else {
4447 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
4448 x86_pmu.pebs_broken = 1;
4449 }
4450 }
4451
is_lbr_from(unsigned long msr)4452 static bool is_lbr_from(unsigned long msr)
4453 {
4454 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr;
4455
4456 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr;
4457 }
4458
4459 /*
4460 * Under certain circumstances, access certain MSR may cause #GP.
4461 * The function tests if the input MSR can be safely accessed.
4462 */
check_msr(unsigned long msr,u64 mask)4463 static bool check_msr(unsigned long msr, u64 mask)
4464 {
4465 u64 val_old, val_new, val_tmp;
4466
4467 /*
4468 * Disable the check for real HW, so we don't
4469 * mess with potentionaly enabled registers:
4470 */
4471 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
4472 return true;
4473
4474 /*
4475 * Read the current value, change it and read it back to see if it
4476 * matches, this is needed to detect certain hardware emulators
4477 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
4478 */
4479 if (rdmsrl_safe(msr, &val_old))
4480 return false;
4481
4482 /*
4483 * Only change the bits which can be updated by wrmsrl.
4484 */
4485 val_tmp = val_old ^ mask;
4486
4487 if (is_lbr_from(msr))
4488 val_tmp = lbr_from_signext_quirk_wr(val_tmp);
4489
4490 if (wrmsrl_safe(msr, val_tmp) ||
4491 rdmsrl_safe(msr, &val_new))
4492 return false;
4493
4494 /*
4495 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value
4496 * should equal rdmsrl()'s even with the quirk.
4497 */
4498 if (val_new != val_tmp)
4499 return false;
4500
4501 if (is_lbr_from(msr))
4502 val_old = lbr_from_signext_quirk_wr(val_old);
4503
4504 /* Here it's sure that the MSR can be safely accessed.
4505 * Restore the old value and return.
4506 */
4507 wrmsrl(msr, val_old);
4508
4509 return true;
4510 }
4511
intel_sandybridge_quirk(void)4512 static __init void intel_sandybridge_quirk(void)
4513 {
4514 x86_pmu.check_microcode = intel_snb_check_microcode;
4515 cpus_read_lock();
4516 intel_snb_check_microcode();
4517 cpus_read_unlock();
4518 }
4519
4520 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
4521 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
4522 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
4523 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
4524 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
4525 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
4526 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
4527 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
4528 };
4529
intel_arch_events_quirk(void)4530 static __init void intel_arch_events_quirk(void)
4531 {
4532 int bit;
4533
4534 /* disable event that reported as not presend by cpuid */
4535 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
4536 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
4537 pr_warn("CPUID marked event: \'%s\' unavailable\n",
4538 intel_arch_events_map[bit].name);
4539 }
4540 }
4541
intel_nehalem_quirk(void)4542 static __init void intel_nehalem_quirk(void)
4543 {
4544 union cpuid10_ebx ebx;
4545
4546 ebx.full = x86_pmu.events_maskl;
4547 if (ebx.split.no_branch_misses_retired) {
4548 /*
4549 * Erratum AAJ80 detected, we work it around by using
4550 * the BR_MISP_EXEC.ANY event. This will over-count
4551 * branch-misses, but it's still much better than the
4552 * architectural event which is often completely bogus:
4553 */
4554 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
4555 ebx.split.no_branch_misses_retired = 0;
4556 x86_pmu.events_maskl = ebx.full;
4557 pr_info("CPU erratum AAJ80 worked around\n");
4558 }
4559 }
4560
4561 static const struct x86_cpu_desc counter_freezing_ucodes[] = {
4562 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 2, 0x0000000e),
4563 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 9, 0x0000002e),
4564 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 10, 0x00000008),
4565 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_D, 1, 0x00000028),
4566 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 1, 0x00000028),
4567 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 8, 0x00000006),
4568 {}
4569 };
4570
intel_counter_freezing_broken(void)4571 static bool intel_counter_freezing_broken(void)
4572 {
4573 return !x86_cpu_has_min_microcode_rev(counter_freezing_ucodes);
4574 }
4575
intel_counter_freezing_quirk(void)4576 static __init void intel_counter_freezing_quirk(void)
4577 {
4578 /* Check if it's already disabled */
4579 if (disable_counter_freezing)
4580 return;
4581
4582 /*
4583 * If the system starts with the wrong ucode, leave the
4584 * counter-freezing feature permanently disabled.
4585 */
4586 if (intel_counter_freezing_broken()) {
4587 pr_info("PMU counter freezing disabled due to CPU errata,"
4588 "please upgrade microcode\n");
4589 x86_pmu.counter_freezing = false;
4590 x86_pmu.handle_irq = intel_pmu_handle_irq;
4591 }
4592 }
4593
4594 /*
4595 * enable software workaround for errata:
4596 * SNB: BJ122
4597 * IVB: BV98
4598 * HSW: HSD29
4599 *
4600 * Only needed when HT is enabled. However detecting
4601 * if HT is enabled is difficult (model specific). So instead,
4602 * we enable the workaround in the early boot, and verify if
4603 * it is needed in a later initcall phase once we have valid
4604 * topology information to check if HT is actually enabled
4605 */
intel_ht_bug(void)4606 static __init void intel_ht_bug(void)
4607 {
4608 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
4609
4610 x86_pmu.start_scheduling = intel_start_scheduling;
4611 x86_pmu.commit_scheduling = intel_commit_scheduling;
4612 x86_pmu.stop_scheduling = intel_stop_scheduling;
4613 }
4614
4615 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
4616 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
4617
4618 /* Haswell special events */
4619 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
4620 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
4621 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
4622 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
4623 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
4624 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
4625 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
4626 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
4627 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
4628 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
4629 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
4630 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
4631
4632 static struct attribute *hsw_events_attrs[] = {
4633 EVENT_PTR(td_slots_issued),
4634 EVENT_PTR(td_slots_retired),
4635 EVENT_PTR(td_fetch_bubbles),
4636 EVENT_PTR(td_total_slots),
4637 EVENT_PTR(td_total_slots_scale),
4638 EVENT_PTR(td_recovery_bubbles),
4639 EVENT_PTR(td_recovery_bubbles_scale),
4640 NULL
4641 };
4642
4643 static struct attribute *hsw_mem_events_attrs[] = {
4644 EVENT_PTR(mem_ld_hsw),
4645 EVENT_PTR(mem_st_hsw),
4646 NULL,
4647 };
4648
4649 static struct attribute *hsw_tsx_events_attrs[] = {
4650 EVENT_PTR(tx_start),
4651 EVENT_PTR(tx_commit),
4652 EVENT_PTR(tx_abort),
4653 EVENT_PTR(tx_capacity),
4654 EVENT_PTR(tx_conflict),
4655 EVENT_PTR(el_start),
4656 EVENT_PTR(el_commit),
4657 EVENT_PTR(el_abort),
4658 EVENT_PTR(el_capacity),
4659 EVENT_PTR(el_conflict),
4660 EVENT_PTR(cycles_t),
4661 EVENT_PTR(cycles_ct),
4662 NULL
4663 };
4664
4665 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80");
4666 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2");
4667 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80");
4668 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2");
4669
4670 static struct attribute *icl_events_attrs[] = {
4671 EVENT_PTR(mem_ld_hsw),
4672 EVENT_PTR(mem_st_hsw),
4673 NULL,
4674 };
4675
4676 static struct attribute *icl_td_events_attrs[] = {
4677 EVENT_PTR(slots),
4678 EVENT_PTR(td_retiring),
4679 EVENT_PTR(td_bad_spec),
4680 EVENT_PTR(td_fe_bound),
4681 EVENT_PTR(td_be_bound),
4682 NULL,
4683 };
4684
4685 static struct attribute *icl_tsx_events_attrs[] = {
4686 EVENT_PTR(tx_start),
4687 EVENT_PTR(tx_abort),
4688 EVENT_PTR(tx_commit),
4689 EVENT_PTR(tx_capacity_read),
4690 EVENT_PTR(tx_capacity_write),
4691 EVENT_PTR(tx_conflict),
4692 EVENT_PTR(el_start),
4693 EVENT_PTR(el_abort),
4694 EVENT_PTR(el_commit),
4695 EVENT_PTR(el_capacity_read),
4696 EVENT_PTR(el_capacity_write),
4697 EVENT_PTR(el_conflict),
4698 EVENT_PTR(cycles_t),
4699 EVENT_PTR(cycles_ct),
4700 NULL,
4701 };
4702
freeze_on_smi_show(struct device * cdev,struct device_attribute * attr,char * buf)4703 static ssize_t freeze_on_smi_show(struct device *cdev,
4704 struct device_attribute *attr,
4705 char *buf)
4706 {
4707 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi);
4708 }
4709
4710 static DEFINE_MUTEX(freeze_on_smi_mutex);
4711
freeze_on_smi_store(struct device * cdev,struct device_attribute * attr,const char * buf,size_t count)4712 static ssize_t freeze_on_smi_store(struct device *cdev,
4713 struct device_attribute *attr,
4714 const char *buf, size_t count)
4715 {
4716 unsigned long val;
4717 ssize_t ret;
4718
4719 ret = kstrtoul(buf, 0, &val);
4720 if (ret)
4721 return ret;
4722
4723 if (val > 1)
4724 return -EINVAL;
4725
4726 mutex_lock(&freeze_on_smi_mutex);
4727
4728 if (x86_pmu.attr_freeze_on_smi == val)
4729 goto done;
4730
4731 x86_pmu.attr_freeze_on_smi = val;
4732
4733 get_online_cpus();
4734 on_each_cpu(flip_smm_bit, &val, 1);
4735 put_online_cpus();
4736 done:
4737 mutex_unlock(&freeze_on_smi_mutex);
4738
4739 return count;
4740 }
4741
update_tfa_sched(void * ignored)4742 static void update_tfa_sched(void *ignored)
4743 {
4744 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4745
4746 /*
4747 * check if PMC3 is used
4748 * and if so force schedule out for all event types all contexts
4749 */
4750 if (test_bit(3, cpuc->active_mask))
4751 perf_pmu_resched(x86_get_pmu(smp_processor_id()));
4752 }
4753
show_sysctl_tfa(struct device * cdev,struct device_attribute * attr,char * buf)4754 static ssize_t show_sysctl_tfa(struct device *cdev,
4755 struct device_attribute *attr,
4756 char *buf)
4757 {
4758 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort);
4759 }
4760
set_sysctl_tfa(struct device * cdev,struct device_attribute * attr,const char * buf,size_t count)4761 static ssize_t set_sysctl_tfa(struct device *cdev,
4762 struct device_attribute *attr,
4763 const char *buf, size_t count)
4764 {
4765 bool val;
4766 ssize_t ret;
4767
4768 ret = kstrtobool(buf, &val);
4769 if (ret)
4770 return ret;
4771
4772 /* no change */
4773 if (val == allow_tsx_force_abort)
4774 return count;
4775
4776 allow_tsx_force_abort = val;
4777
4778 get_online_cpus();
4779 on_each_cpu(update_tfa_sched, NULL, 1);
4780 put_online_cpus();
4781
4782 return count;
4783 }
4784
4785
4786 static DEVICE_ATTR_RW(freeze_on_smi);
4787
branches_show(struct device * cdev,struct device_attribute * attr,char * buf)4788 static ssize_t branches_show(struct device *cdev,
4789 struct device_attribute *attr,
4790 char *buf)
4791 {
4792 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr);
4793 }
4794
4795 static DEVICE_ATTR_RO(branches);
4796
4797 static struct attribute *lbr_attrs[] = {
4798 &dev_attr_branches.attr,
4799 NULL
4800 };
4801
4802 static char pmu_name_str[30];
4803
pmu_name_show(struct device * cdev,struct device_attribute * attr,char * buf)4804 static ssize_t pmu_name_show(struct device *cdev,
4805 struct device_attribute *attr,
4806 char *buf)
4807 {
4808 return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str);
4809 }
4810
4811 static DEVICE_ATTR_RO(pmu_name);
4812
4813 static struct attribute *intel_pmu_caps_attrs[] = {
4814 &dev_attr_pmu_name.attr,
4815 NULL
4816 };
4817
4818 static DEVICE_ATTR(allow_tsx_force_abort, 0644,
4819 show_sysctl_tfa,
4820 set_sysctl_tfa);
4821
4822 static struct attribute *intel_pmu_attrs[] = {
4823 &dev_attr_freeze_on_smi.attr,
4824 &dev_attr_allow_tsx_force_abort.attr,
4825 NULL,
4826 };
4827
4828 static umode_t
tsx_is_visible(struct kobject * kobj,struct attribute * attr,int i)4829 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4830 {
4831 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0;
4832 }
4833
4834 static umode_t
pebs_is_visible(struct kobject * kobj,struct attribute * attr,int i)4835 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4836 {
4837 return x86_pmu.pebs ? attr->mode : 0;
4838 }
4839
4840 static umode_t
lbr_is_visible(struct kobject * kobj,struct attribute * attr,int i)4841 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4842 {
4843 return x86_pmu.lbr_nr ? attr->mode : 0;
4844 }
4845
4846 static umode_t
exra_is_visible(struct kobject * kobj,struct attribute * attr,int i)4847 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4848 {
4849 return x86_pmu.version >= 2 ? attr->mode : 0;
4850 }
4851
4852 static umode_t
default_is_visible(struct kobject * kobj,struct attribute * attr,int i)4853 default_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4854 {
4855 if (attr == &dev_attr_allow_tsx_force_abort.attr)
4856 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0;
4857
4858 return attr->mode;
4859 }
4860
4861 static struct attribute_group group_events_td = {
4862 .name = "events",
4863 };
4864
4865 static struct attribute_group group_events_mem = {
4866 .name = "events",
4867 .is_visible = pebs_is_visible,
4868 };
4869
4870 static struct attribute_group group_events_tsx = {
4871 .name = "events",
4872 .is_visible = tsx_is_visible,
4873 };
4874
4875 static struct attribute_group group_caps_gen = {
4876 .name = "caps",
4877 .attrs = intel_pmu_caps_attrs,
4878 };
4879
4880 static struct attribute_group group_caps_lbr = {
4881 .name = "caps",
4882 .attrs = lbr_attrs,
4883 .is_visible = lbr_is_visible,
4884 };
4885
4886 static struct attribute_group group_format_extra = {
4887 .name = "format",
4888 .is_visible = exra_is_visible,
4889 };
4890
4891 static struct attribute_group group_format_extra_skl = {
4892 .name = "format",
4893 .is_visible = exra_is_visible,
4894 };
4895
4896 static struct attribute_group group_default = {
4897 .attrs = intel_pmu_attrs,
4898 .is_visible = default_is_visible,
4899 };
4900
4901 static const struct attribute_group *attr_update[] = {
4902 &group_events_td,
4903 &group_events_mem,
4904 &group_events_tsx,
4905 &group_caps_gen,
4906 &group_caps_lbr,
4907 &group_format_extra,
4908 &group_format_extra_skl,
4909 &group_default,
4910 NULL,
4911 };
4912
4913 static struct attribute *empty_attrs;
4914
intel_pmu_init(void)4915 __init int intel_pmu_init(void)
4916 {
4917 struct attribute **extra_skl_attr = &empty_attrs;
4918 struct attribute **extra_attr = &empty_attrs;
4919 struct attribute **td_attr = &empty_attrs;
4920 struct attribute **mem_attr = &empty_attrs;
4921 struct attribute **tsx_attr = &empty_attrs;
4922 union cpuid10_edx edx;
4923 union cpuid10_eax eax;
4924 union cpuid10_ebx ebx;
4925 struct event_constraint *c;
4926 unsigned int unused;
4927 struct extra_reg *er;
4928 bool pmem = false;
4929 int version, i;
4930 char *name;
4931
4932 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
4933 switch (boot_cpu_data.x86) {
4934 case 0x6:
4935 return p6_pmu_init();
4936 case 0xb:
4937 return knc_pmu_init();
4938 case 0xf:
4939 return p4_pmu_init();
4940 }
4941 return -ENODEV;
4942 }
4943
4944 /*
4945 * Check whether the Architectural PerfMon supports
4946 * Branch Misses Retired hw_event or not.
4947 */
4948 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
4949 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
4950 return -ENODEV;
4951
4952 version = eax.split.version_id;
4953 if (version < 2)
4954 x86_pmu = core_pmu;
4955 else
4956 x86_pmu = intel_pmu;
4957
4958 x86_pmu.version = version;
4959 x86_pmu.num_counters = eax.split.num_counters;
4960 x86_pmu.cntval_bits = eax.split.bit_width;
4961 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
4962
4963 x86_pmu.events_maskl = ebx.full;
4964 x86_pmu.events_mask_len = eax.split.mask_length;
4965
4966 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
4967
4968 /*
4969 * Quirk: v2 perfmon does not report fixed-purpose events, so
4970 * assume at least 3 events, when not running in a hypervisor:
4971 */
4972 if (version > 1) {
4973 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR);
4974
4975 x86_pmu.num_counters_fixed =
4976 max((int)edx.split.num_counters_fixed, assume);
4977 }
4978
4979 if (version >= 4)
4980 x86_pmu.counter_freezing = !disable_counter_freezing;
4981
4982 if (boot_cpu_has(X86_FEATURE_PDCM)) {
4983 u64 capabilities;
4984
4985 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
4986 x86_pmu.intel_cap.capabilities = capabilities;
4987 }
4988
4989 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) {
4990 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32;
4991 x86_pmu.lbr_read = intel_pmu_lbr_read_32;
4992 }
4993
4994 if (boot_cpu_has(X86_FEATURE_ARCH_LBR))
4995 intel_pmu_arch_lbr_init();
4996
4997 intel_ds_init();
4998
4999 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
5000
5001 if (version >= 5) {
5002 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated;
5003 if (x86_pmu.intel_cap.anythread_deprecated)
5004 pr_cont(" AnyThread deprecated, ");
5005 }
5006
5007 /*
5008 * Install the hw-cache-events table:
5009 */
5010 switch (boot_cpu_data.x86_model) {
5011 case INTEL_FAM6_CORE_YONAH:
5012 pr_cont("Core events, ");
5013 name = "core";
5014 break;
5015
5016 case INTEL_FAM6_CORE2_MEROM:
5017 x86_add_quirk(intel_clovertown_quirk);
5018 fallthrough;
5019
5020 case INTEL_FAM6_CORE2_MEROM_L:
5021 case INTEL_FAM6_CORE2_PENRYN:
5022 case INTEL_FAM6_CORE2_DUNNINGTON:
5023 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
5024 sizeof(hw_cache_event_ids));
5025
5026 intel_pmu_lbr_init_core();
5027
5028 x86_pmu.event_constraints = intel_core2_event_constraints;
5029 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
5030 pr_cont("Core2 events, ");
5031 name = "core2";
5032 break;
5033
5034 case INTEL_FAM6_NEHALEM:
5035 case INTEL_FAM6_NEHALEM_EP:
5036 case INTEL_FAM6_NEHALEM_EX:
5037 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
5038 sizeof(hw_cache_event_ids));
5039 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
5040 sizeof(hw_cache_extra_regs));
5041
5042 intel_pmu_lbr_init_nhm();
5043
5044 x86_pmu.event_constraints = intel_nehalem_event_constraints;
5045 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
5046 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
5047 x86_pmu.extra_regs = intel_nehalem_extra_regs;
5048 x86_pmu.limit_period = nhm_limit_period;
5049
5050 mem_attr = nhm_mem_events_attrs;
5051
5052 /* UOPS_ISSUED.STALLED_CYCLES */
5053 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5054 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5055 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
5056 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
5057 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
5058
5059 intel_pmu_pebs_data_source_nhm();
5060 x86_add_quirk(intel_nehalem_quirk);
5061 x86_pmu.pebs_no_tlb = 1;
5062 extra_attr = nhm_format_attr;
5063
5064 pr_cont("Nehalem events, ");
5065 name = "nehalem";
5066 break;
5067
5068 case INTEL_FAM6_ATOM_BONNELL:
5069 case INTEL_FAM6_ATOM_BONNELL_MID:
5070 case INTEL_FAM6_ATOM_SALTWELL:
5071 case INTEL_FAM6_ATOM_SALTWELL_MID:
5072 case INTEL_FAM6_ATOM_SALTWELL_TABLET:
5073 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
5074 sizeof(hw_cache_event_ids));
5075
5076 intel_pmu_lbr_init_atom();
5077
5078 x86_pmu.event_constraints = intel_gen_event_constraints;
5079 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
5080 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
5081 pr_cont("Atom events, ");
5082 name = "bonnell";
5083 break;
5084
5085 case INTEL_FAM6_ATOM_SILVERMONT:
5086 case INTEL_FAM6_ATOM_SILVERMONT_D:
5087 case INTEL_FAM6_ATOM_SILVERMONT_MID:
5088 case INTEL_FAM6_ATOM_AIRMONT:
5089 case INTEL_FAM6_ATOM_AIRMONT_MID:
5090 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
5091 sizeof(hw_cache_event_ids));
5092 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
5093 sizeof(hw_cache_extra_regs));
5094
5095 intel_pmu_lbr_init_slm();
5096
5097 x86_pmu.event_constraints = intel_slm_event_constraints;
5098 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
5099 x86_pmu.extra_regs = intel_slm_extra_regs;
5100 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5101 td_attr = slm_events_attrs;
5102 extra_attr = slm_format_attr;
5103 pr_cont("Silvermont events, ");
5104 name = "silvermont";
5105 break;
5106
5107 case INTEL_FAM6_ATOM_GOLDMONT:
5108 case INTEL_FAM6_ATOM_GOLDMONT_D:
5109 x86_add_quirk(intel_counter_freezing_quirk);
5110 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
5111 sizeof(hw_cache_event_ids));
5112 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
5113 sizeof(hw_cache_extra_regs));
5114
5115 intel_pmu_lbr_init_skl();
5116
5117 x86_pmu.event_constraints = intel_slm_event_constraints;
5118 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints;
5119 x86_pmu.extra_regs = intel_glm_extra_regs;
5120 /*
5121 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
5122 * for precise cycles.
5123 * :pp is identical to :ppp
5124 */
5125 x86_pmu.pebs_aliases = NULL;
5126 x86_pmu.pebs_prec_dist = true;
5127 x86_pmu.lbr_pt_coexist = true;
5128 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5129 td_attr = glm_events_attrs;
5130 extra_attr = slm_format_attr;
5131 pr_cont("Goldmont events, ");
5132 name = "goldmont";
5133 break;
5134
5135 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
5136 x86_add_quirk(intel_counter_freezing_quirk);
5137 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
5138 sizeof(hw_cache_event_ids));
5139 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs,
5140 sizeof(hw_cache_extra_regs));
5141
5142 intel_pmu_lbr_init_skl();
5143
5144 x86_pmu.event_constraints = intel_slm_event_constraints;
5145 x86_pmu.extra_regs = intel_glm_extra_regs;
5146 /*
5147 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
5148 * for precise cycles.
5149 */
5150 x86_pmu.pebs_aliases = NULL;
5151 x86_pmu.pebs_prec_dist = true;
5152 x86_pmu.lbr_pt_coexist = true;
5153 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5154 x86_pmu.flags |= PMU_FL_PEBS_ALL;
5155 x86_pmu.get_event_constraints = glp_get_event_constraints;
5156 td_attr = glm_events_attrs;
5157 /* Goldmont Plus has 4-wide pipeline */
5158 event_attr_td_total_slots_scale_glm.event_str = "4";
5159 extra_attr = slm_format_attr;
5160 pr_cont("Goldmont plus events, ");
5161 name = "goldmont_plus";
5162 break;
5163
5164 case INTEL_FAM6_ATOM_TREMONT_D:
5165 case INTEL_FAM6_ATOM_TREMONT:
5166 case INTEL_FAM6_ATOM_TREMONT_L:
5167 x86_pmu.late_ack = true;
5168 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
5169 sizeof(hw_cache_event_ids));
5170 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs,
5171 sizeof(hw_cache_extra_regs));
5172 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
5173
5174 intel_pmu_lbr_init_skl();
5175
5176 x86_pmu.event_constraints = intel_slm_event_constraints;
5177 x86_pmu.extra_regs = intel_tnt_extra_regs;
5178 /*
5179 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
5180 * for precise cycles.
5181 */
5182 x86_pmu.pebs_aliases = NULL;
5183 x86_pmu.pebs_prec_dist = true;
5184 x86_pmu.lbr_pt_coexist = true;
5185 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5186 x86_pmu.get_event_constraints = tnt_get_event_constraints;
5187 extra_attr = slm_format_attr;
5188 pr_cont("Tremont events, ");
5189 name = "Tremont";
5190 break;
5191
5192 case INTEL_FAM6_WESTMERE:
5193 case INTEL_FAM6_WESTMERE_EP:
5194 case INTEL_FAM6_WESTMERE_EX:
5195 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
5196 sizeof(hw_cache_event_ids));
5197 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
5198 sizeof(hw_cache_extra_regs));
5199
5200 intel_pmu_lbr_init_nhm();
5201
5202 x86_pmu.event_constraints = intel_westmere_event_constraints;
5203 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
5204 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
5205 x86_pmu.extra_regs = intel_westmere_extra_regs;
5206 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5207
5208 mem_attr = nhm_mem_events_attrs;
5209
5210 /* UOPS_ISSUED.STALLED_CYCLES */
5211 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5212 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5213 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
5214 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
5215 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
5216
5217 intel_pmu_pebs_data_source_nhm();
5218 extra_attr = nhm_format_attr;
5219 pr_cont("Westmere events, ");
5220 name = "westmere";
5221 break;
5222
5223 case INTEL_FAM6_SANDYBRIDGE:
5224 case INTEL_FAM6_SANDYBRIDGE_X:
5225 x86_add_quirk(intel_sandybridge_quirk);
5226 x86_add_quirk(intel_ht_bug);
5227 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
5228 sizeof(hw_cache_event_ids));
5229 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
5230 sizeof(hw_cache_extra_regs));
5231
5232 intel_pmu_lbr_init_snb();
5233
5234 x86_pmu.event_constraints = intel_snb_event_constraints;
5235 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
5236 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
5237 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X)
5238 x86_pmu.extra_regs = intel_snbep_extra_regs;
5239 else
5240 x86_pmu.extra_regs = intel_snb_extra_regs;
5241
5242
5243 /* all extra regs are per-cpu when HT is on */
5244 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5245 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5246
5247 td_attr = snb_events_attrs;
5248 mem_attr = snb_mem_events_attrs;
5249
5250 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
5251 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5252 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5253 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
5254 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
5255 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
5256
5257 extra_attr = nhm_format_attr;
5258
5259 pr_cont("SandyBridge events, ");
5260 name = "sandybridge";
5261 break;
5262
5263 case INTEL_FAM6_IVYBRIDGE:
5264 case INTEL_FAM6_IVYBRIDGE_X:
5265 x86_add_quirk(intel_ht_bug);
5266 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
5267 sizeof(hw_cache_event_ids));
5268 /* dTLB-load-misses on IVB is different than SNB */
5269 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
5270
5271 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
5272 sizeof(hw_cache_extra_regs));
5273
5274 intel_pmu_lbr_init_snb();
5275
5276 x86_pmu.event_constraints = intel_ivb_event_constraints;
5277 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
5278 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
5279 x86_pmu.pebs_prec_dist = true;
5280 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X)
5281 x86_pmu.extra_regs = intel_snbep_extra_regs;
5282 else
5283 x86_pmu.extra_regs = intel_snb_extra_regs;
5284 /* all extra regs are per-cpu when HT is on */
5285 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5286 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5287
5288 td_attr = snb_events_attrs;
5289 mem_attr = snb_mem_events_attrs;
5290
5291 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
5292 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5293 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5294
5295 extra_attr = nhm_format_attr;
5296
5297 pr_cont("IvyBridge events, ");
5298 name = "ivybridge";
5299 break;
5300
5301
5302 case INTEL_FAM6_HASWELL:
5303 case INTEL_FAM6_HASWELL_X:
5304 case INTEL_FAM6_HASWELL_L:
5305 case INTEL_FAM6_HASWELL_G:
5306 x86_add_quirk(intel_ht_bug);
5307 x86_add_quirk(intel_pebs_isolation_quirk);
5308 x86_pmu.late_ack = true;
5309 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5310 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5311
5312 intel_pmu_lbr_init_hsw();
5313
5314 x86_pmu.event_constraints = intel_hsw_event_constraints;
5315 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
5316 x86_pmu.extra_regs = intel_snbep_extra_regs;
5317 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
5318 x86_pmu.pebs_prec_dist = true;
5319 /* all extra regs are per-cpu when HT is on */
5320 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5321 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5322
5323 x86_pmu.hw_config = hsw_hw_config;
5324 x86_pmu.get_event_constraints = hsw_get_event_constraints;
5325 x86_pmu.lbr_double_abort = true;
5326 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
5327 hsw_format_attr : nhm_format_attr;
5328 td_attr = hsw_events_attrs;
5329 mem_attr = hsw_mem_events_attrs;
5330 tsx_attr = hsw_tsx_events_attrs;
5331 pr_cont("Haswell events, ");
5332 name = "haswell";
5333 break;
5334
5335 case INTEL_FAM6_BROADWELL:
5336 case INTEL_FAM6_BROADWELL_D:
5337 case INTEL_FAM6_BROADWELL_G:
5338 case INTEL_FAM6_BROADWELL_X:
5339 x86_add_quirk(intel_pebs_isolation_quirk);
5340 x86_pmu.late_ack = true;
5341 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5342 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5343
5344 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
5345 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
5346 BDW_L3_MISS|HSW_SNOOP_DRAM;
5347 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
5348 HSW_SNOOP_DRAM;
5349 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
5350 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
5351 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
5352 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
5353
5354 intel_pmu_lbr_init_hsw();
5355
5356 x86_pmu.event_constraints = intel_bdw_event_constraints;
5357 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;
5358 x86_pmu.extra_regs = intel_snbep_extra_regs;
5359 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
5360 x86_pmu.pebs_prec_dist = true;
5361 /* all extra regs are per-cpu when HT is on */
5362 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5363 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5364
5365 x86_pmu.hw_config = hsw_hw_config;
5366 x86_pmu.get_event_constraints = hsw_get_event_constraints;
5367 x86_pmu.limit_period = bdw_limit_period;
5368 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
5369 hsw_format_attr : nhm_format_attr;
5370 td_attr = hsw_events_attrs;
5371 mem_attr = hsw_mem_events_attrs;
5372 tsx_attr = hsw_tsx_events_attrs;
5373 pr_cont("Broadwell events, ");
5374 name = "broadwell";
5375 break;
5376
5377 case INTEL_FAM6_XEON_PHI_KNL:
5378 case INTEL_FAM6_XEON_PHI_KNM:
5379 memcpy(hw_cache_event_ids,
5380 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5381 memcpy(hw_cache_extra_regs,
5382 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5383 intel_pmu_lbr_init_knl();
5384
5385 x86_pmu.event_constraints = intel_slm_event_constraints;
5386 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
5387 x86_pmu.extra_regs = intel_knl_extra_regs;
5388
5389 /* all extra regs are per-cpu when HT is on */
5390 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5391 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5392 extra_attr = slm_format_attr;
5393 pr_cont("Knights Landing/Mill events, ");
5394 name = "knights-landing";
5395 break;
5396
5397 case INTEL_FAM6_SKYLAKE_X:
5398 pmem = true;
5399 fallthrough;
5400 case INTEL_FAM6_SKYLAKE_L:
5401 case INTEL_FAM6_SKYLAKE:
5402 case INTEL_FAM6_KABYLAKE_L:
5403 case INTEL_FAM6_KABYLAKE:
5404 case INTEL_FAM6_COMETLAKE_L:
5405 case INTEL_FAM6_COMETLAKE:
5406 x86_add_quirk(intel_pebs_isolation_quirk);
5407 x86_pmu.late_ack = true;
5408 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5409 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5410 intel_pmu_lbr_init_skl();
5411
5412 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */
5413 event_attr_td_recovery_bubbles.event_str_noht =
5414 "event=0xd,umask=0x1,cmask=1";
5415 event_attr_td_recovery_bubbles.event_str_ht =
5416 "event=0xd,umask=0x1,cmask=1,any=1";
5417
5418 x86_pmu.event_constraints = intel_skl_event_constraints;
5419 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
5420 x86_pmu.extra_regs = intel_skl_extra_regs;
5421 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
5422 x86_pmu.pebs_prec_dist = true;
5423 /* all extra regs are per-cpu when HT is on */
5424 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5425 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5426
5427 x86_pmu.hw_config = hsw_hw_config;
5428 x86_pmu.get_event_constraints = hsw_get_event_constraints;
5429 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
5430 hsw_format_attr : nhm_format_attr;
5431 extra_skl_attr = skl_format_attr;
5432 td_attr = hsw_events_attrs;
5433 mem_attr = hsw_mem_events_attrs;
5434 tsx_attr = hsw_tsx_events_attrs;
5435 intel_pmu_pebs_data_source_skl(pmem);
5436
5437 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) {
5438 x86_pmu.flags |= PMU_FL_TFA;
5439 x86_pmu.get_event_constraints = tfa_get_event_constraints;
5440 x86_pmu.enable_all = intel_tfa_pmu_enable_all;
5441 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling;
5442 }
5443
5444 pr_cont("Skylake events, ");
5445 name = "skylake";
5446 break;
5447
5448 case INTEL_FAM6_ICELAKE_X:
5449 case INTEL_FAM6_ICELAKE_D:
5450 pmem = true;
5451 fallthrough;
5452 case INTEL_FAM6_ICELAKE_L:
5453 case INTEL_FAM6_ICELAKE:
5454 case INTEL_FAM6_TIGERLAKE_L:
5455 case INTEL_FAM6_TIGERLAKE:
5456 x86_pmu.late_ack = true;
5457 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5458 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5459 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
5460 intel_pmu_lbr_init_skl();
5461
5462 x86_pmu.event_constraints = intel_icl_event_constraints;
5463 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints;
5464 x86_pmu.extra_regs = intel_icl_extra_regs;
5465 x86_pmu.pebs_aliases = NULL;
5466 x86_pmu.pebs_prec_dist = true;
5467 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5468 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5469
5470 x86_pmu.hw_config = hsw_hw_config;
5471 x86_pmu.get_event_constraints = icl_get_event_constraints;
5472 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
5473 hsw_format_attr : nhm_format_attr;
5474 extra_skl_attr = skl_format_attr;
5475 mem_attr = icl_events_attrs;
5476 td_attr = icl_td_events_attrs;
5477 tsx_attr = icl_tsx_events_attrs;
5478 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
5479 x86_pmu.lbr_pt_coexist = true;
5480 intel_pmu_pebs_data_source_skl(pmem);
5481 x86_pmu.update_topdown_event = icl_update_topdown_event;
5482 x86_pmu.set_topdown_event_period = icl_set_topdown_event_period;
5483 pr_cont("Icelake events, ");
5484 name = "icelake";
5485 break;
5486
5487 default:
5488 switch (x86_pmu.version) {
5489 case 1:
5490 x86_pmu.event_constraints = intel_v1_event_constraints;
5491 pr_cont("generic architected perfmon v1, ");
5492 name = "generic_arch_v1";
5493 break;
5494 default:
5495 /*
5496 * default constraints for v2 and up
5497 */
5498 x86_pmu.event_constraints = intel_gen_event_constraints;
5499 pr_cont("generic architected perfmon, ");
5500 name = "generic_arch_v2+";
5501 break;
5502 }
5503 }
5504
5505 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name);
5506
5507
5508 group_events_td.attrs = td_attr;
5509 group_events_mem.attrs = mem_attr;
5510 group_events_tsx.attrs = tsx_attr;
5511 group_format_extra.attrs = extra_attr;
5512 group_format_extra_skl.attrs = extra_skl_attr;
5513
5514 x86_pmu.attr_update = attr_update;
5515
5516 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
5517 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
5518 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
5519 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
5520 }
5521 x86_pmu.intel_ctrl = (1ULL << x86_pmu.num_counters) - 1;
5522
5523 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
5524 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
5525 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
5526 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
5527 }
5528
5529 x86_pmu.intel_ctrl |=
5530 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
5531
5532 /* AnyThread may be deprecated on arch perfmon v5 or later */
5533 if (x86_pmu.intel_cap.anythread_deprecated)
5534 x86_pmu.format_attrs = intel_arch_formats_attr;
5535
5536 if (x86_pmu.event_constraints) {
5537 /*
5538 * event on fixed counter2 (REF_CYCLES) only works on this
5539 * counter, so do not extend mask to generic counters
5540 */
5541 for_each_event_constraint(c, x86_pmu.event_constraints) {
5542 /*
5543 * Don't extend the topdown slots and metrics
5544 * events to the generic counters.
5545 */
5546 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) {
5547 c->weight = hweight64(c->idxmsk64);
5548 continue;
5549 }
5550
5551 if (c->cmask == FIXED_EVENT_FLAGS
5552 && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) {
5553 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
5554 }
5555 c->idxmsk64 &=
5556 ~(~0ULL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed));
5557 c->weight = hweight64(c->idxmsk64);
5558 }
5559 }
5560
5561 /*
5562 * Access LBR MSR may cause #GP under certain circumstances.
5563 * E.g. KVM doesn't support LBR MSR
5564 * Check all LBT MSR here.
5565 * Disable LBR access if any LBR MSRs can not be accessed.
5566 */
5567 if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL))
5568 x86_pmu.lbr_nr = 0;
5569 for (i = 0; i < x86_pmu.lbr_nr; i++) {
5570 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
5571 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
5572 x86_pmu.lbr_nr = 0;
5573 }
5574
5575 if (x86_pmu.lbr_nr)
5576 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
5577
5578 /*
5579 * Access extra MSR may cause #GP under certain circumstances.
5580 * E.g. KVM doesn't support offcore event
5581 * Check all extra_regs here.
5582 */
5583 if (x86_pmu.extra_regs) {
5584 for (er = x86_pmu.extra_regs; er->msr; er++) {
5585 er->extra_msr_access = check_msr(er->msr, 0x11UL);
5586 /* Disable LBR select mapping */
5587 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
5588 x86_pmu.lbr_sel_map = NULL;
5589 }
5590 }
5591
5592 /* Support full width counters using alternative MSR range */
5593 if (x86_pmu.intel_cap.full_width_write) {
5594 x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
5595 x86_pmu.perfctr = MSR_IA32_PMC0;
5596 pr_cont("full-width counters, ");
5597 }
5598
5599 /*
5600 * For arch perfmon 4 use counter freezing to avoid
5601 * several MSR accesses in the PMI.
5602 */
5603 if (x86_pmu.counter_freezing)
5604 x86_pmu.handle_irq = intel_pmu_handle_irq_v4;
5605
5606 if (x86_pmu.intel_cap.perf_metrics)
5607 x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS;
5608
5609 return 0;
5610 }
5611
5612 /*
5613 * HT bug: phase 2 init
5614 * Called once we have valid topology information to check
5615 * whether or not HT is enabled
5616 * If HT is off, then we disable the workaround
5617 */
fixup_ht_bug(void)5618 static __init int fixup_ht_bug(void)
5619 {
5620 int c;
5621 /*
5622 * problem not present on this CPU model, nothing to do
5623 */
5624 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
5625 return 0;
5626
5627 if (topology_max_smt_threads() > 1) {
5628 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
5629 return 0;
5630 }
5631
5632 cpus_read_lock();
5633
5634 hardlockup_detector_perf_stop();
5635
5636 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
5637
5638 x86_pmu.start_scheduling = NULL;
5639 x86_pmu.commit_scheduling = NULL;
5640 x86_pmu.stop_scheduling = NULL;
5641
5642 hardlockup_detector_perf_restart();
5643
5644 for_each_online_cpu(c)
5645 free_excl_cntrs(&per_cpu(cpu_hw_events, c));
5646
5647 cpus_read_unlock();
5648 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
5649 return 0;
5650 }
5651 subsys_initcall(fixup_ht_bug)
5652