1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ti-sysc.c - Texas Instruments sysc interconnect target driver
4 */
5
6 #include <linux/io.h>
7 #include <linux/clk.h>
8 #include <linux/clkdev.h>
9 #include <linux/delay.h>
10 #include <linux/list.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_domain.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/reset.h>
16 #include <linux/of_address.h>
17 #include <linux/of_platform.h>
18 #include <linux/slab.h>
19 #include <linux/sys_soc.h>
20 #include <linux/iopoll.h>
21
22 #include <linux/platform_data/ti-sysc.h>
23
24 #include <dt-bindings/bus/ti-sysc.h>
25
26 #define DIS_ISP BIT(2)
27 #define DIS_IVA BIT(1)
28 #define DIS_SGX BIT(0)
29
30 #define SOC_FLAG(match, flag) { .machine = match, .data = (void *)(flag), }
31
32 #define MAX_MODULE_SOFTRESET_WAIT 10000
33
34 enum sysc_soc {
35 SOC_UNKNOWN,
36 SOC_2420,
37 SOC_2430,
38 SOC_3430,
39 SOC_3630,
40 SOC_4430,
41 SOC_4460,
42 SOC_4470,
43 SOC_5430,
44 SOC_AM3,
45 SOC_AM4,
46 SOC_DRA7,
47 };
48
49 struct sysc_address {
50 unsigned long base;
51 struct list_head node;
52 };
53
54 struct sysc_soc_info {
55 unsigned long general_purpose:1;
56 enum sysc_soc soc;
57 struct mutex list_lock; /* disabled modules list lock */
58 struct list_head disabled_modules;
59 };
60
61 enum sysc_clocks {
62 SYSC_FCK,
63 SYSC_ICK,
64 SYSC_OPTFCK0,
65 SYSC_OPTFCK1,
66 SYSC_OPTFCK2,
67 SYSC_OPTFCK3,
68 SYSC_OPTFCK4,
69 SYSC_OPTFCK5,
70 SYSC_OPTFCK6,
71 SYSC_OPTFCK7,
72 SYSC_MAX_CLOCKS,
73 };
74
75 static struct sysc_soc_info *sysc_soc;
76 static const char * const reg_names[] = { "rev", "sysc", "syss", };
77 static const char * const clock_names[SYSC_MAX_CLOCKS] = {
78 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
79 "opt5", "opt6", "opt7",
80 };
81
82 #define SYSC_IDLEMODE_MASK 3
83 #define SYSC_CLOCKACTIVITY_MASK 3
84
85 /**
86 * struct sysc - TI sysc interconnect target module registers and capabilities
87 * @dev: struct device pointer
88 * @module_pa: physical address of the interconnect target module
89 * @module_size: size of the interconnect target module
90 * @module_va: virtual address of the interconnect target module
91 * @offsets: register offsets from module base
92 * @mdata: ti-sysc to hwmod translation data for a module
93 * @clocks: clocks used by the interconnect target module
94 * @clock_roles: clock role names for the found clocks
95 * @nr_clocks: number of clocks used by the interconnect target module
96 * @rsts: resets used by the interconnect target module
97 * @legacy_mode: configured for legacy mode if set
98 * @cap: interconnect target module capabilities
99 * @cfg: interconnect target module configuration
100 * @cookie: data used by legacy platform callbacks
101 * @name: name if available
102 * @revision: interconnect target module revision
103 * @reserved: target module is reserved and already in use
104 * @enabled: sysc runtime enabled status
105 * @needs_resume: runtime resume needed on resume from suspend
106 * @child_needs_resume: runtime resume needed for child on resume from suspend
107 * @disable_on_idle: status flag used for disabling modules with resets
108 * @idle_work: work structure used to perform delayed idle on a module
109 * @pre_reset_quirk: module specific pre-reset quirk
110 * @post_reset_quirk: module specific post-reset quirk
111 * @reset_done_quirk: module specific reset done quirk
112 * @module_enable_quirk: module specific enable quirk
113 * @module_disable_quirk: module specific disable quirk
114 * @module_unlock_quirk: module specific sysconfig unlock quirk
115 * @module_lock_quirk: module specific sysconfig lock quirk
116 */
117 struct sysc {
118 struct device *dev;
119 u64 module_pa;
120 u32 module_size;
121 void __iomem *module_va;
122 int offsets[SYSC_MAX_REGS];
123 struct ti_sysc_module_data *mdata;
124 struct clk **clocks;
125 const char **clock_roles;
126 int nr_clocks;
127 struct reset_control *rsts;
128 const char *legacy_mode;
129 const struct sysc_capabilities *cap;
130 struct sysc_config cfg;
131 struct ti_sysc_cookie cookie;
132 const char *name;
133 u32 revision;
134 unsigned int reserved:1;
135 unsigned int enabled:1;
136 unsigned int needs_resume:1;
137 unsigned int child_needs_resume:1;
138 struct delayed_work idle_work;
139 void (*pre_reset_quirk)(struct sysc *sysc);
140 void (*post_reset_quirk)(struct sysc *sysc);
141 void (*reset_done_quirk)(struct sysc *sysc);
142 void (*module_enable_quirk)(struct sysc *sysc);
143 void (*module_disable_quirk)(struct sysc *sysc);
144 void (*module_unlock_quirk)(struct sysc *sysc);
145 void (*module_lock_quirk)(struct sysc *sysc);
146 };
147
148 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
149 bool is_child);
150
sysc_write(struct sysc * ddata,int offset,u32 value)151 static void sysc_write(struct sysc *ddata, int offset, u32 value)
152 {
153 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
154 writew_relaxed(value & 0xffff, ddata->module_va + offset);
155
156 /* Only i2c revision has LO and HI register with stride of 4 */
157 if (ddata->offsets[SYSC_REVISION] >= 0 &&
158 offset == ddata->offsets[SYSC_REVISION]) {
159 u16 hi = value >> 16;
160
161 writew_relaxed(hi, ddata->module_va + offset + 4);
162 }
163
164 return;
165 }
166
167 writel_relaxed(value, ddata->module_va + offset);
168 }
169
sysc_read(struct sysc * ddata,int offset)170 static u32 sysc_read(struct sysc *ddata, int offset)
171 {
172 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
173 u32 val;
174
175 val = readw_relaxed(ddata->module_va + offset);
176
177 /* Only i2c revision has LO and HI register with stride of 4 */
178 if (ddata->offsets[SYSC_REVISION] >= 0 &&
179 offset == ddata->offsets[SYSC_REVISION]) {
180 u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
181
182 val |= tmp << 16;
183 }
184
185 return val;
186 }
187
188 return readl_relaxed(ddata->module_va + offset);
189 }
190
sysc_opt_clks_needed(struct sysc * ddata)191 static bool sysc_opt_clks_needed(struct sysc *ddata)
192 {
193 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
194 }
195
sysc_read_revision(struct sysc * ddata)196 static u32 sysc_read_revision(struct sysc *ddata)
197 {
198 int offset = ddata->offsets[SYSC_REVISION];
199
200 if (offset < 0)
201 return 0;
202
203 return sysc_read(ddata, offset);
204 }
205
sysc_read_sysconfig(struct sysc * ddata)206 static u32 sysc_read_sysconfig(struct sysc *ddata)
207 {
208 int offset = ddata->offsets[SYSC_SYSCONFIG];
209
210 if (offset < 0)
211 return 0;
212
213 return sysc_read(ddata, offset);
214 }
215
sysc_read_sysstatus(struct sysc * ddata)216 static u32 sysc_read_sysstatus(struct sysc *ddata)
217 {
218 int offset = ddata->offsets[SYSC_SYSSTATUS];
219
220 if (offset < 0)
221 return 0;
222
223 return sysc_read(ddata, offset);
224 }
225
226 /* Poll on reset status */
sysc_wait_softreset(struct sysc * ddata)227 static int sysc_wait_softreset(struct sysc *ddata)
228 {
229 u32 sysc_mask, syss_done, rstval;
230 int syss_offset, error = 0;
231
232 if (ddata->cap->regbits->srst_shift < 0)
233 return 0;
234
235 syss_offset = ddata->offsets[SYSC_SYSSTATUS];
236 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
237
238 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
239 syss_done = 0;
240 else
241 syss_done = ddata->cfg.syss_mask;
242
243 if (syss_offset >= 0) {
244 error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata,
245 rstval, (rstval & ddata->cfg.syss_mask) ==
246 syss_done, 100, MAX_MODULE_SOFTRESET_WAIT);
247
248 } else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) {
249 error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata,
250 rstval, !(rstval & sysc_mask),
251 100, MAX_MODULE_SOFTRESET_WAIT);
252 }
253
254 return error;
255 }
256
sysc_add_named_clock_from_child(struct sysc * ddata,const char * name,const char * optfck_name)257 static int sysc_add_named_clock_from_child(struct sysc *ddata,
258 const char *name,
259 const char *optfck_name)
260 {
261 struct device_node *np = ddata->dev->of_node;
262 struct device_node *child;
263 struct clk_lookup *cl;
264 struct clk *clock;
265 const char *n;
266
267 if (name)
268 n = name;
269 else
270 n = optfck_name;
271
272 /* Does the clock alias already exist? */
273 clock = of_clk_get_by_name(np, n);
274 if (!IS_ERR(clock)) {
275 clk_put(clock);
276
277 return 0;
278 }
279
280 child = of_get_next_available_child(np, NULL);
281 if (!child)
282 return -ENODEV;
283
284 clock = devm_get_clk_from_child(ddata->dev, child, name);
285 if (IS_ERR(clock))
286 return PTR_ERR(clock);
287
288 /*
289 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
290 * limit for clk_get(). If cl ever needs to be freed, it should be done
291 * with clkdev_drop().
292 */
293 cl = kcalloc(1, sizeof(*cl), GFP_KERNEL);
294 if (!cl)
295 return -ENOMEM;
296
297 cl->con_id = n;
298 cl->dev_id = dev_name(ddata->dev);
299 cl->clk = clock;
300 clkdev_add(cl);
301
302 clk_put(clock);
303
304 return 0;
305 }
306
sysc_init_ext_opt_clock(struct sysc * ddata,const char * name)307 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
308 {
309 const char *optfck_name;
310 int error, index;
311
312 if (ddata->nr_clocks < SYSC_OPTFCK0)
313 index = SYSC_OPTFCK0;
314 else
315 index = ddata->nr_clocks;
316
317 if (name)
318 optfck_name = name;
319 else
320 optfck_name = clock_names[index];
321
322 error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
323 if (error)
324 return error;
325
326 ddata->clock_roles[index] = optfck_name;
327 ddata->nr_clocks++;
328
329 return 0;
330 }
331
sysc_get_one_clock(struct sysc * ddata,const char * name)332 static int sysc_get_one_clock(struct sysc *ddata, const char *name)
333 {
334 int error, i, index = -ENODEV;
335
336 if (!strncmp(clock_names[SYSC_FCK], name, 3))
337 index = SYSC_FCK;
338 else if (!strncmp(clock_names[SYSC_ICK], name, 3))
339 index = SYSC_ICK;
340
341 if (index < 0) {
342 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
343 if (!ddata->clocks[i]) {
344 index = i;
345 break;
346 }
347 }
348 }
349
350 if (index < 0) {
351 dev_err(ddata->dev, "clock %s not added\n", name);
352 return index;
353 }
354
355 ddata->clocks[index] = devm_clk_get(ddata->dev, name);
356 if (IS_ERR(ddata->clocks[index])) {
357 dev_err(ddata->dev, "clock get error for %s: %li\n",
358 name, PTR_ERR(ddata->clocks[index]));
359
360 return PTR_ERR(ddata->clocks[index]);
361 }
362
363 error = clk_prepare(ddata->clocks[index]);
364 if (error) {
365 dev_err(ddata->dev, "clock prepare error for %s: %i\n",
366 name, error);
367
368 return error;
369 }
370
371 return 0;
372 }
373
sysc_get_clocks(struct sysc * ddata)374 static int sysc_get_clocks(struct sysc *ddata)
375 {
376 struct device_node *np = ddata->dev->of_node;
377 struct property *prop;
378 const char *name;
379 int nr_fck = 0, nr_ick = 0, i, error = 0;
380
381 ddata->clock_roles = devm_kcalloc(ddata->dev,
382 SYSC_MAX_CLOCKS,
383 sizeof(*ddata->clock_roles),
384 GFP_KERNEL);
385 if (!ddata->clock_roles)
386 return -ENOMEM;
387
388 of_property_for_each_string(np, "clock-names", prop, name) {
389 if (!strncmp(clock_names[SYSC_FCK], name, 3))
390 nr_fck++;
391 if (!strncmp(clock_names[SYSC_ICK], name, 3))
392 nr_ick++;
393 ddata->clock_roles[ddata->nr_clocks] = name;
394 ddata->nr_clocks++;
395 }
396
397 if (ddata->nr_clocks < 1)
398 return 0;
399
400 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
401 error = sysc_init_ext_opt_clock(ddata, NULL);
402 if (error)
403 return error;
404 }
405
406 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
407 dev_err(ddata->dev, "too many clocks for %pOF\n", np);
408
409 return -EINVAL;
410 }
411
412 if (nr_fck > 1 || nr_ick > 1) {
413 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
414
415 return -EINVAL;
416 }
417
418 /* Always add a slot for main clocks fck and ick even if unused */
419 if (!nr_fck)
420 ddata->nr_clocks++;
421 if (!nr_ick)
422 ddata->nr_clocks++;
423
424 ddata->clocks = devm_kcalloc(ddata->dev,
425 ddata->nr_clocks, sizeof(*ddata->clocks),
426 GFP_KERNEL);
427 if (!ddata->clocks)
428 return -ENOMEM;
429
430 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
431 const char *name = ddata->clock_roles[i];
432
433 if (!name)
434 continue;
435
436 error = sysc_get_one_clock(ddata, name);
437 if (error)
438 return error;
439 }
440
441 return 0;
442 }
443
sysc_enable_main_clocks(struct sysc * ddata)444 static int sysc_enable_main_clocks(struct sysc *ddata)
445 {
446 struct clk *clock;
447 int i, error;
448
449 if (!ddata->clocks)
450 return 0;
451
452 for (i = 0; i < SYSC_OPTFCK0; i++) {
453 clock = ddata->clocks[i];
454
455 /* Main clocks may not have ick */
456 if (IS_ERR_OR_NULL(clock))
457 continue;
458
459 error = clk_enable(clock);
460 if (error)
461 goto err_disable;
462 }
463
464 return 0;
465
466 err_disable:
467 for (i--; i >= 0; i--) {
468 clock = ddata->clocks[i];
469
470 /* Main clocks may not have ick */
471 if (IS_ERR_OR_NULL(clock))
472 continue;
473
474 clk_disable(clock);
475 }
476
477 return error;
478 }
479
sysc_disable_main_clocks(struct sysc * ddata)480 static void sysc_disable_main_clocks(struct sysc *ddata)
481 {
482 struct clk *clock;
483 int i;
484
485 if (!ddata->clocks)
486 return;
487
488 for (i = 0; i < SYSC_OPTFCK0; i++) {
489 clock = ddata->clocks[i];
490 if (IS_ERR_OR_NULL(clock))
491 continue;
492
493 clk_disable(clock);
494 }
495 }
496
sysc_enable_opt_clocks(struct sysc * ddata)497 static int sysc_enable_opt_clocks(struct sysc *ddata)
498 {
499 struct clk *clock;
500 int i, error;
501
502 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
503 return 0;
504
505 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
506 clock = ddata->clocks[i];
507
508 /* Assume no holes for opt clocks */
509 if (IS_ERR_OR_NULL(clock))
510 return 0;
511
512 error = clk_enable(clock);
513 if (error)
514 goto err_disable;
515 }
516
517 return 0;
518
519 err_disable:
520 for (i--; i >= 0; i--) {
521 clock = ddata->clocks[i];
522 if (IS_ERR_OR_NULL(clock))
523 continue;
524
525 clk_disable(clock);
526 }
527
528 return error;
529 }
530
sysc_disable_opt_clocks(struct sysc * ddata)531 static void sysc_disable_opt_clocks(struct sysc *ddata)
532 {
533 struct clk *clock;
534 int i;
535
536 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
537 return;
538
539 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
540 clock = ddata->clocks[i];
541
542 /* Assume no holes for opt clocks */
543 if (IS_ERR_OR_NULL(clock))
544 return;
545
546 clk_disable(clock);
547 }
548 }
549
sysc_clkdm_deny_idle(struct sysc * ddata)550 static void sysc_clkdm_deny_idle(struct sysc *ddata)
551 {
552 struct ti_sysc_platform_data *pdata;
553
554 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
555 return;
556
557 pdata = dev_get_platdata(ddata->dev);
558 if (pdata && pdata->clkdm_deny_idle)
559 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie);
560 }
561
sysc_clkdm_allow_idle(struct sysc * ddata)562 static void sysc_clkdm_allow_idle(struct sysc *ddata)
563 {
564 struct ti_sysc_platform_data *pdata;
565
566 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
567 return;
568
569 pdata = dev_get_platdata(ddata->dev);
570 if (pdata && pdata->clkdm_allow_idle)
571 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie);
572 }
573
574 /**
575 * sysc_init_resets - init rstctrl reset line if configured
576 * @ddata: device driver data
577 *
578 * See sysc_rstctrl_reset_deassert().
579 */
sysc_init_resets(struct sysc * ddata)580 static int sysc_init_resets(struct sysc *ddata)
581 {
582 ddata->rsts =
583 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl");
584
585 return PTR_ERR_OR_ZERO(ddata->rsts);
586 }
587
588 /**
589 * sysc_parse_and_check_child_range - parses module IO region from ranges
590 * @ddata: device driver data
591 *
592 * In general we only need rev, syss, and sysc registers and not the whole
593 * module range. But we do want the offsets for these registers from the
594 * module base. This allows us to check them against the legacy hwmod
595 * platform data. Let's also check the ranges are configured properly.
596 */
sysc_parse_and_check_child_range(struct sysc * ddata)597 static int sysc_parse_and_check_child_range(struct sysc *ddata)
598 {
599 struct device_node *np = ddata->dev->of_node;
600 const __be32 *ranges;
601 u32 nr_addr, nr_size;
602 int len, error;
603
604 ranges = of_get_property(np, "ranges", &len);
605 if (!ranges) {
606 dev_err(ddata->dev, "missing ranges for %pOF\n", np);
607
608 return -ENOENT;
609 }
610
611 len /= sizeof(*ranges);
612
613 if (len < 3) {
614 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
615
616 return -EINVAL;
617 }
618
619 error = of_property_read_u32(np, "#address-cells", &nr_addr);
620 if (error)
621 return -ENOENT;
622
623 error = of_property_read_u32(np, "#size-cells", &nr_size);
624 if (error)
625 return -ENOENT;
626
627 if (nr_addr != 1 || nr_size != 1) {
628 dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
629
630 return -EINVAL;
631 }
632
633 ranges++;
634 ddata->module_pa = of_translate_address(np, ranges++);
635 ddata->module_size = be32_to_cpup(ranges);
636
637 return 0;
638 }
639
640 /* Interconnect instances to probe before l4_per instances */
641 static struct resource early_bus_ranges[] = {
642 /* am3/4 l4_wkup */
643 { .start = 0x44c00000, .end = 0x44c00000 + 0x300000, },
644 /* omap4/5 and dra7 l4_cfg */
645 { .start = 0x4a000000, .end = 0x4a000000 + 0x300000, },
646 /* omap4 l4_wkup */
647 { .start = 0x4a300000, .end = 0x4a300000 + 0x30000, },
648 /* omap5 and dra7 l4_wkup without dra7 dcan segment */
649 { .start = 0x4ae00000, .end = 0x4ae00000 + 0x30000, },
650 };
651
652 static atomic_t sysc_defer = ATOMIC_INIT(10);
653
654 /**
655 * sysc_defer_non_critical - defer non_critical interconnect probing
656 * @ddata: device driver data
657 *
658 * We want to probe l4_cfg and l4_wkup interconnect instances before any
659 * l4_per instances as l4_per instances depend on resources on l4_cfg and
660 * l4_wkup interconnects.
661 */
sysc_defer_non_critical(struct sysc * ddata)662 static int sysc_defer_non_critical(struct sysc *ddata)
663 {
664 struct resource *res;
665 int i;
666
667 if (!atomic_read(&sysc_defer))
668 return 0;
669
670 for (i = 0; i < ARRAY_SIZE(early_bus_ranges); i++) {
671 res = &early_bus_ranges[i];
672 if (ddata->module_pa >= res->start &&
673 ddata->module_pa <= res->end) {
674 atomic_set(&sysc_defer, 0);
675
676 return 0;
677 }
678 }
679
680 atomic_dec_if_positive(&sysc_defer);
681
682 return -EPROBE_DEFER;
683 }
684
685 static struct device_node *stdout_path;
686
sysc_init_stdout_path(struct sysc * ddata)687 static void sysc_init_stdout_path(struct sysc *ddata)
688 {
689 struct device_node *np = NULL;
690 const char *uart;
691
692 if (IS_ERR(stdout_path))
693 return;
694
695 if (stdout_path)
696 return;
697
698 np = of_find_node_by_path("/chosen");
699 if (!np)
700 goto err;
701
702 uart = of_get_property(np, "stdout-path", NULL);
703 if (!uart)
704 goto err;
705
706 np = of_find_node_by_path(uart);
707 if (!np)
708 goto err;
709
710 stdout_path = np;
711
712 return;
713
714 err:
715 stdout_path = ERR_PTR(-ENODEV);
716 }
717
sysc_check_quirk_stdout(struct sysc * ddata,struct device_node * np)718 static void sysc_check_quirk_stdout(struct sysc *ddata,
719 struct device_node *np)
720 {
721 sysc_init_stdout_path(ddata);
722 if (np != stdout_path)
723 return;
724
725 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
726 SYSC_QUIRK_NO_RESET_ON_INIT;
727 }
728
729 /**
730 * sysc_check_one_child - check child configuration
731 * @ddata: device driver data
732 * @np: child device node
733 *
734 * Let's avoid messy situations where we have new interconnect target
735 * node but children have "ti,hwmods". These belong to the interconnect
736 * target node and are managed by this driver.
737 */
sysc_check_one_child(struct sysc * ddata,struct device_node * np)738 static void sysc_check_one_child(struct sysc *ddata,
739 struct device_node *np)
740 {
741 const char *name;
742
743 name = of_get_property(np, "ti,hwmods", NULL);
744 if (name && !of_device_is_compatible(np, "ti,sysc"))
745 dev_warn(ddata->dev, "really a child ti,hwmods property?");
746
747 sysc_check_quirk_stdout(ddata, np);
748 sysc_parse_dts_quirks(ddata, np, true);
749 }
750
sysc_check_children(struct sysc * ddata)751 static void sysc_check_children(struct sysc *ddata)
752 {
753 struct device_node *child;
754
755 for_each_child_of_node(ddata->dev->of_node, child)
756 sysc_check_one_child(ddata, child);
757 }
758
759 /*
760 * So far only I2C uses 16-bit read access with clockactivity with revision
761 * in two registers with stride of 4. We can detect this based on the rev
762 * register size to configure things far enough to be able to properly read
763 * the revision register.
764 */
sysc_check_quirk_16bit(struct sysc * ddata,struct resource * res)765 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
766 {
767 if (resource_size(res) == 8)
768 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
769 }
770
771 /**
772 * sysc_parse_one - parses the interconnect target module registers
773 * @ddata: device driver data
774 * @reg: register to parse
775 */
sysc_parse_one(struct sysc * ddata,enum sysc_registers reg)776 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
777 {
778 struct resource *res;
779 const char *name;
780
781 switch (reg) {
782 case SYSC_REVISION:
783 case SYSC_SYSCONFIG:
784 case SYSC_SYSSTATUS:
785 name = reg_names[reg];
786 break;
787 default:
788 return -EINVAL;
789 }
790
791 res = platform_get_resource_byname(to_platform_device(ddata->dev),
792 IORESOURCE_MEM, name);
793 if (!res) {
794 ddata->offsets[reg] = -ENODEV;
795
796 return 0;
797 }
798
799 ddata->offsets[reg] = res->start - ddata->module_pa;
800 if (reg == SYSC_REVISION)
801 sysc_check_quirk_16bit(ddata, res);
802
803 return 0;
804 }
805
sysc_parse_registers(struct sysc * ddata)806 static int sysc_parse_registers(struct sysc *ddata)
807 {
808 int i, error;
809
810 for (i = 0; i < SYSC_MAX_REGS; i++) {
811 error = sysc_parse_one(ddata, i);
812 if (error)
813 return error;
814 }
815
816 return 0;
817 }
818
819 /**
820 * sysc_check_registers - check for misconfigured register overlaps
821 * @ddata: device driver data
822 */
sysc_check_registers(struct sysc * ddata)823 static int sysc_check_registers(struct sysc *ddata)
824 {
825 int i, j, nr_regs = 0, nr_matches = 0;
826
827 for (i = 0; i < SYSC_MAX_REGS; i++) {
828 if (ddata->offsets[i] < 0)
829 continue;
830
831 if (ddata->offsets[i] > (ddata->module_size - 4)) {
832 dev_err(ddata->dev, "register outside module range");
833
834 return -EINVAL;
835 }
836
837 for (j = 0; j < SYSC_MAX_REGS; j++) {
838 if (ddata->offsets[j] < 0)
839 continue;
840
841 if (ddata->offsets[i] == ddata->offsets[j])
842 nr_matches++;
843 }
844 nr_regs++;
845 }
846
847 if (nr_matches > nr_regs) {
848 dev_err(ddata->dev, "overlapping registers: (%i/%i)",
849 nr_regs, nr_matches);
850
851 return -EINVAL;
852 }
853
854 return 0;
855 }
856
857 /**
858 * syc_ioremap - ioremap register space for the interconnect target module
859 * @ddata: device driver data
860 *
861 * Note that the interconnect target module registers can be anywhere
862 * within the interconnect target module range. For example, SGX has
863 * them at offset 0x1fc00 in the 32MB module address space. And cpsw
864 * has them at offset 0x1200 in the CPSW_WR child. Usually the
865 * the interconnect target module registers are at the beginning of
866 * the module range though.
867 */
sysc_ioremap(struct sysc * ddata)868 static int sysc_ioremap(struct sysc *ddata)
869 {
870 int size;
871
872 if (ddata->offsets[SYSC_REVISION] < 0 &&
873 ddata->offsets[SYSC_SYSCONFIG] < 0 &&
874 ddata->offsets[SYSC_SYSSTATUS] < 0) {
875 size = ddata->module_size;
876 } else {
877 size = max3(ddata->offsets[SYSC_REVISION],
878 ddata->offsets[SYSC_SYSCONFIG],
879 ddata->offsets[SYSC_SYSSTATUS]);
880
881 if (size < SZ_1K)
882 size = SZ_1K;
883
884 if ((size + sizeof(u32)) > ddata->module_size)
885 size = ddata->module_size;
886 }
887
888 ddata->module_va = devm_ioremap(ddata->dev,
889 ddata->module_pa,
890 size + sizeof(u32));
891 if (!ddata->module_va)
892 return -EIO;
893
894 return 0;
895 }
896
897 /**
898 * sysc_map_and_check_registers - ioremap and check device registers
899 * @ddata: device driver data
900 */
sysc_map_and_check_registers(struct sysc * ddata)901 static int sysc_map_and_check_registers(struct sysc *ddata)
902 {
903 int error;
904
905 error = sysc_parse_and_check_child_range(ddata);
906 if (error)
907 return error;
908
909 error = sysc_defer_non_critical(ddata);
910 if (error)
911 return error;
912
913 sysc_check_children(ddata);
914
915 error = sysc_parse_registers(ddata);
916 if (error)
917 return error;
918
919 error = sysc_ioremap(ddata);
920 if (error)
921 return error;
922
923 error = sysc_check_registers(ddata);
924 if (error)
925 return error;
926
927 return 0;
928 }
929
930 /**
931 * sysc_show_rev - read and show interconnect target module revision
932 * @bufp: buffer to print the information to
933 * @ddata: device driver data
934 */
sysc_show_rev(char * bufp,struct sysc * ddata)935 static int sysc_show_rev(char *bufp, struct sysc *ddata)
936 {
937 int len;
938
939 if (ddata->offsets[SYSC_REVISION] < 0)
940 return sprintf(bufp, ":NA");
941
942 len = sprintf(bufp, ":%08x", ddata->revision);
943
944 return len;
945 }
946
sysc_show_reg(struct sysc * ddata,char * bufp,enum sysc_registers reg)947 static int sysc_show_reg(struct sysc *ddata,
948 char *bufp, enum sysc_registers reg)
949 {
950 if (ddata->offsets[reg] < 0)
951 return sprintf(bufp, ":NA");
952
953 return sprintf(bufp, ":%x", ddata->offsets[reg]);
954 }
955
sysc_show_name(char * bufp,struct sysc * ddata)956 static int sysc_show_name(char *bufp, struct sysc *ddata)
957 {
958 if (!ddata->name)
959 return 0;
960
961 return sprintf(bufp, ":%s", ddata->name);
962 }
963
964 /**
965 * sysc_show_registers - show information about interconnect target module
966 * @ddata: device driver data
967 */
sysc_show_registers(struct sysc * ddata)968 static void sysc_show_registers(struct sysc *ddata)
969 {
970 char buf[128];
971 char *bufp = buf;
972 int i;
973
974 for (i = 0; i < SYSC_MAX_REGS; i++)
975 bufp += sysc_show_reg(ddata, bufp, i);
976
977 bufp += sysc_show_rev(bufp, ddata);
978 bufp += sysc_show_name(bufp, ddata);
979
980 dev_dbg(ddata->dev, "%llx:%x%s\n",
981 ddata->module_pa, ddata->module_size,
982 buf);
983 }
984
985 /**
986 * sysc_write_sysconfig - handle sysconfig quirks for register write
987 * @ddata: device driver data
988 * @value: register value
989 */
sysc_write_sysconfig(struct sysc * ddata,u32 value)990 static void sysc_write_sysconfig(struct sysc *ddata, u32 value)
991 {
992 if (ddata->module_unlock_quirk)
993 ddata->module_unlock_quirk(ddata);
994
995 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value);
996
997 if (ddata->module_lock_quirk)
998 ddata->module_lock_quirk(ddata);
999 }
1000
1001 #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
1002 #define SYSC_CLOCACT_ICK 2
1003
1004 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
sysc_enable_module(struct device * dev)1005 static int sysc_enable_module(struct device *dev)
1006 {
1007 struct sysc *ddata;
1008 const struct sysc_regbits *regbits;
1009 u32 reg, idlemodes, best_mode;
1010 int error;
1011
1012 ddata = dev_get_drvdata(dev);
1013
1014 /*
1015 * Some modules like DSS reset automatically on idle. Enable optional
1016 * reset clocks and wait for OCP softreset to complete.
1017 */
1018 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) {
1019 error = sysc_enable_opt_clocks(ddata);
1020 if (error) {
1021 dev_err(ddata->dev,
1022 "Optional clocks failed for enable: %i\n",
1023 error);
1024 return error;
1025 }
1026 }
1027 /*
1028 * Some modules like i2c and hdq1w have unusable reset status unless
1029 * the module reset quirk is enabled. Skip status check on enable.
1030 */
1031 if (!(ddata->cfg.quirks & SYSC_MODULE_QUIRK_ENA_RESETDONE)) {
1032 error = sysc_wait_softreset(ddata);
1033 if (error)
1034 dev_warn(ddata->dev, "OCP softreset timed out\n");
1035 }
1036 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET)
1037 sysc_disable_opt_clocks(ddata);
1038
1039 /*
1040 * Some subsystem private interconnects, like DSS top level module,
1041 * need only the automatic OCP softreset handling with no sysconfig
1042 * register bits to configure.
1043 */
1044 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1045 return 0;
1046
1047 regbits = ddata->cap->regbits;
1048 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1049
1050 /*
1051 * Set CLOCKACTIVITY, we only use it for ick. And we only configure it
1052 * based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware
1053 * capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag.
1054 */
1055 if (regbits->clkact_shift >= 0 &&
1056 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT))
1057 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift;
1058
1059 /* Set SIDLE mode */
1060 idlemodes = ddata->cfg.sidlemodes;
1061 if (!idlemodes || regbits->sidle_shift < 0)
1062 goto set_midle;
1063
1064 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE |
1065 SYSC_QUIRK_SWSUP_SIDLE_ACT)) {
1066 best_mode = SYSC_IDLE_NO;
1067 } else {
1068 best_mode = fls(ddata->cfg.sidlemodes) - 1;
1069 if (best_mode > SYSC_IDLE_MASK) {
1070 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1071 return -EINVAL;
1072 }
1073
1074 /* Set WAKEUP */
1075 if (regbits->enwkup_shift >= 0 &&
1076 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
1077 reg |= BIT(regbits->enwkup_shift);
1078 }
1079
1080 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1081 reg |= best_mode << regbits->sidle_shift;
1082 sysc_write_sysconfig(ddata, reg);
1083
1084 set_midle:
1085 /* Set MIDLE mode */
1086 idlemodes = ddata->cfg.midlemodes;
1087 if (!idlemodes || regbits->midle_shift < 0)
1088 goto set_autoidle;
1089
1090 best_mode = fls(ddata->cfg.midlemodes) - 1;
1091 if (best_mode > SYSC_IDLE_MASK) {
1092 dev_err(dev, "%s: invalid midlemode\n", __func__);
1093 return -EINVAL;
1094 }
1095
1096 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
1097 best_mode = SYSC_IDLE_NO;
1098
1099 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1100 reg |= best_mode << regbits->midle_shift;
1101 sysc_write_sysconfig(ddata, reg);
1102
1103 set_autoidle:
1104 /* Autoidle bit must enabled separately if available */
1105 if (regbits->autoidle_shift >= 0 &&
1106 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
1107 reg |= 1 << regbits->autoidle_shift;
1108 sysc_write_sysconfig(ddata, reg);
1109 }
1110
1111 /* Flush posted write */
1112 sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1113
1114 if (ddata->module_enable_quirk)
1115 ddata->module_enable_quirk(ddata);
1116
1117 return 0;
1118 }
1119
sysc_best_idle_mode(u32 idlemodes,u32 * best_mode)1120 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
1121 {
1122 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
1123 *best_mode = SYSC_IDLE_SMART_WKUP;
1124 else if (idlemodes & BIT(SYSC_IDLE_SMART))
1125 *best_mode = SYSC_IDLE_SMART;
1126 else if (idlemodes & BIT(SYSC_IDLE_FORCE))
1127 *best_mode = SYSC_IDLE_FORCE;
1128 else
1129 return -EINVAL;
1130
1131 return 0;
1132 }
1133
1134 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
sysc_disable_module(struct device * dev)1135 static int sysc_disable_module(struct device *dev)
1136 {
1137 struct sysc *ddata;
1138 const struct sysc_regbits *regbits;
1139 u32 reg, idlemodes, best_mode;
1140 int ret;
1141
1142 ddata = dev_get_drvdata(dev);
1143 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1144 return 0;
1145
1146 if (ddata->module_disable_quirk)
1147 ddata->module_disable_quirk(ddata);
1148
1149 regbits = ddata->cap->regbits;
1150 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1151
1152 /* Set MIDLE mode */
1153 idlemodes = ddata->cfg.midlemodes;
1154 if (!idlemodes || regbits->midle_shift < 0)
1155 goto set_sidle;
1156
1157 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1158 if (ret) {
1159 dev_err(dev, "%s: invalid midlemode\n", __func__);
1160 return ret;
1161 }
1162
1163 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) ||
1164 ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY))
1165 best_mode = SYSC_IDLE_FORCE;
1166
1167 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1168 reg |= best_mode << regbits->midle_shift;
1169 sysc_write_sysconfig(ddata, reg);
1170
1171 set_sidle:
1172 /* Set SIDLE mode */
1173 idlemodes = ddata->cfg.sidlemodes;
1174 if (!idlemodes || regbits->sidle_shift < 0)
1175 return 0;
1176
1177 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) {
1178 best_mode = SYSC_IDLE_FORCE;
1179 } else {
1180 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1181 if (ret) {
1182 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1183 return ret;
1184 }
1185 }
1186
1187 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1188 reg |= best_mode << regbits->sidle_shift;
1189 if (regbits->autoidle_shift >= 0 &&
1190 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
1191 reg |= 1 << regbits->autoidle_shift;
1192 sysc_write_sysconfig(ddata, reg);
1193
1194 /* Flush posted write */
1195 sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1196
1197 return 0;
1198 }
1199
sysc_runtime_suspend_legacy(struct device * dev,struct sysc * ddata)1200 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
1201 struct sysc *ddata)
1202 {
1203 struct ti_sysc_platform_data *pdata;
1204 int error;
1205
1206 pdata = dev_get_platdata(ddata->dev);
1207 if (!pdata)
1208 return 0;
1209
1210 if (!pdata->idle_module)
1211 return -ENODEV;
1212
1213 error = pdata->idle_module(dev, &ddata->cookie);
1214 if (error)
1215 dev_err(dev, "%s: could not idle: %i\n",
1216 __func__, error);
1217
1218 reset_control_assert(ddata->rsts);
1219
1220 return 0;
1221 }
1222
sysc_runtime_resume_legacy(struct device * dev,struct sysc * ddata)1223 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
1224 struct sysc *ddata)
1225 {
1226 struct ti_sysc_platform_data *pdata;
1227 int error;
1228
1229 pdata = dev_get_platdata(ddata->dev);
1230 if (!pdata)
1231 return 0;
1232
1233 if (!pdata->enable_module)
1234 return -ENODEV;
1235
1236 error = pdata->enable_module(dev, &ddata->cookie);
1237 if (error)
1238 dev_err(dev, "%s: could not enable: %i\n",
1239 __func__, error);
1240
1241 reset_control_deassert(ddata->rsts);
1242
1243 return 0;
1244 }
1245
sysc_runtime_suspend(struct device * dev)1246 static int __maybe_unused sysc_runtime_suspend(struct device *dev)
1247 {
1248 struct sysc *ddata;
1249 int error = 0;
1250
1251 ddata = dev_get_drvdata(dev);
1252
1253 if (!ddata->enabled)
1254 return 0;
1255
1256 sysc_clkdm_deny_idle(ddata);
1257
1258 if (ddata->legacy_mode) {
1259 error = sysc_runtime_suspend_legacy(dev, ddata);
1260 if (error)
1261 goto err_allow_idle;
1262 } else {
1263 error = sysc_disable_module(dev);
1264 if (error)
1265 goto err_allow_idle;
1266 }
1267
1268 sysc_disable_main_clocks(ddata);
1269
1270 if (sysc_opt_clks_needed(ddata))
1271 sysc_disable_opt_clocks(ddata);
1272
1273 ddata->enabled = false;
1274
1275 err_allow_idle:
1276 reset_control_assert(ddata->rsts);
1277
1278 sysc_clkdm_allow_idle(ddata);
1279
1280 return error;
1281 }
1282
sysc_runtime_resume(struct device * dev)1283 static int __maybe_unused sysc_runtime_resume(struct device *dev)
1284 {
1285 struct sysc *ddata;
1286 int error = 0;
1287
1288 ddata = dev_get_drvdata(dev);
1289
1290 if (ddata->enabled)
1291 return 0;
1292
1293
1294 sysc_clkdm_deny_idle(ddata);
1295
1296 if (sysc_opt_clks_needed(ddata)) {
1297 error = sysc_enable_opt_clocks(ddata);
1298 if (error)
1299 goto err_allow_idle;
1300 }
1301
1302 error = sysc_enable_main_clocks(ddata);
1303 if (error)
1304 goto err_opt_clocks;
1305
1306 reset_control_deassert(ddata->rsts);
1307
1308 if (ddata->legacy_mode) {
1309 error = sysc_runtime_resume_legacy(dev, ddata);
1310 if (error)
1311 goto err_main_clocks;
1312 } else {
1313 error = sysc_enable_module(dev);
1314 if (error)
1315 goto err_main_clocks;
1316 }
1317
1318 ddata->enabled = true;
1319
1320 sysc_clkdm_allow_idle(ddata);
1321
1322 return 0;
1323
1324 err_main_clocks:
1325 sysc_disable_main_clocks(ddata);
1326 err_opt_clocks:
1327 if (sysc_opt_clks_needed(ddata))
1328 sysc_disable_opt_clocks(ddata);
1329 err_allow_idle:
1330 sysc_clkdm_allow_idle(ddata);
1331
1332 return error;
1333 }
1334
sysc_reinit_module(struct sysc * ddata,bool leave_enabled)1335 static int sysc_reinit_module(struct sysc *ddata, bool leave_enabled)
1336 {
1337 struct device *dev = ddata->dev;
1338 int error;
1339
1340 /* Disable target module if it is enabled */
1341 if (ddata->enabled) {
1342 error = sysc_runtime_suspend(dev);
1343 if (error)
1344 dev_warn(dev, "reinit suspend failed: %i\n", error);
1345 }
1346
1347 /* Enable target module */
1348 error = sysc_runtime_resume(dev);
1349 if (error)
1350 dev_warn(dev, "reinit resume failed: %i\n", error);
1351
1352 if (leave_enabled)
1353 return error;
1354
1355 /* Disable target module if no leave_enabled was set */
1356 error = sysc_runtime_suspend(dev);
1357 if (error)
1358 dev_warn(dev, "reinit suspend failed: %i\n", error);
1359
1360 return error;
1361 }
1362
sysc_noirq_suspend(struct device * dev)1363 static int __maybe_unused sysc_noirq_suspend(struct device *dev)
1364 {
1365 struct sysc *ddata;
1366
1367 ddata = dev_get_drvdata(dev);
1368
1369 if (ddata->cfg.quirks &
1370 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
1371 return 0;
1372
1373 if (!ddata->enabled)
1374 return 0;
1375
1376 ddata->needs_resume = 1;
1377
1378 return sysc_runtime_suspend(dev);
1379 }
1380
sysc_noirq_resume(struct device * dev)1381 static int __maybe_unused sysc_noirq_resume(struct device *dev)
1382 {
1383 struct sysc *ddata;
1384 int error = 0;
1385
1386 ddata = dev_get_drvdata(dev);
1387
1388 if (ddata->cfg.quirks &
1389 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
1390 return 0;
1391
1392 if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_RESUME) {
1393 error = sysc_reinit_module(ddata, ddata->needs_resume);
1394 if (error)
1395 dev_warn(dev, "noirq_resume failed: %i\n", error);
1396 } else if (ddata->needs_resume) {
1397 error = sysc_runtime_resume(dev);
1398 if (error)
1399 dev_warn(dev, "noirq_resume failed: %i\n", error);
1400 }
1401
1402 ddata->needs_resume = 0;
1403
1404 return error;
1405 }
1406
1407 static const struct dev_pm_ops sysc_pm_ops = {
1408 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
1409 SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
1410 sysc_runtime_resume,
1411 NULL)
1412 };
1413
1414 /* Module revision register based quirks */
1415 struct sysc_revision_quirk {
1416 const char *name;
1417 u32 base;
1418 int rev_offset;
1419 int sysc_offset;
1420 int syss_offset;
1421 u32 revision;
1422 u32 revision_mask;
1423 u32 quirks;
1424 };
1425
1426 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
1427 optrev_val, optrevmask, optquirkmask) \
1428 { \
1429 .name = (optname), \
1430 .base = (optbase), \
1431 .rev_offset = (optrev), \
1432 .sysc_offset = (optsysc), \
1433 .syss_offset = (optsyss), \
1434 .revision = (optrev_val), \
1435 .revision_mask = (optrevmask), \
1436 .quirks = (optquirkmask), \
1437 }
1438
1439 static const struct sysc_revision_quirk sysc_revision_quirks[] = {
1440 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
1441 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
1442 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET),
1443 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
1444 SYSC_QUIRK_LEGACY_IDLE),
1445 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff,
1446 SYSC_QUIRK_LEGACY_IDLE),
1447 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff,
1448 SYSC_QUIRK_LEGACY_IDLE),
1449 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff,
1450 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1451 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
1452 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1453 /* Uarts on omap4 and later */
1454 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
1455 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1456 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
1457 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1458
1459 /* Quirks that need to be set based on the module address */
1460 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff,
1461 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
1462 SYSC_QUIRK_SWSUP_SIDLE),
1463
1464 /* Quirks that need to be set based on detected module */
1465 SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff,
1466 SYSC_MODULE_QUIRK_AESS),
1467 /* Errata i893 handling for dra7 dcan1 and 2 */
1468 SYSC_QUIRK("dcan", 0x4ae3c000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
1469 SYSC_QUIRK_CLKDM_NOAUTO),
1470 SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
1471 SYSC_QUIRK_CLKDM_NOAUTO),
1472 SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
1473 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1474 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff,
1475 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1476 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff,
1477 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1478 SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
1479 SYSC_QUIRK_CLKDM_NOAUTO),
1480 SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
1481 SYSC_QUIRK_CLKDM_NOAUTO),
1482 SYSC_QUIRK("gpmc", 0, 0, 0x10, 0x14, 0x00000060, 0xffffffff,
1483 SYSC_QUIRK_GPMC_DEBUG),
1484 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff,
1485 SYSC_QUIRK_OPT_CLKS_NEEDED),
1486 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
1487 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1488 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
1489 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1490 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff,
1491 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1492 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff,
1493 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1494 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff,
1495 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1496 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
1497 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1498 SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0),
1499 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff,
1500 SYSC_MODULE_QUIRK_SGX),
1501 SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff,
1502 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1503 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0,
1504 SYSC_MODULE_QUIRK_RTC_UNLOCK),
1505 SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff,
1506 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1507 SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff,
1508 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1509 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff,
1510 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1511 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff,
1512 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1513 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1514 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1515 SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff,
1516 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY |
1517 SYSC_QUIRK_REINIT_ON_RESUME),
1518 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1519 SYSC_MODULE_QUIRK_WDT),
1520 /* PRUSS on am3, am4 and am5 */
1521 SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV, 0x47000000, 0xff000000,
1522 SYSC_MODULE_QUIRK_PRUSS),
1523 /* Watchdog on am3 and am4 */
1524 SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1525 SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE),
1526
1527 #ifdef DEBUG
1528 SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0),
1529 SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0),
1530 SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0),
1531 SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1532 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
1533 0xffff00f0, 0),
1534 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0),
1535 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0),
1536 SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1537 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1538 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0),
1539 SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0),
1540 SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1541 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1542 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1543 SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1544 SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0),
1545 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1546 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1547 SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0),
1548 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0),
1549 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0),
1550 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0),
1551 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
1552 SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0),
1553 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff, 0),
1554 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0),
1555 SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0),
1556 SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0),
1557 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
1558 SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0),
1559 SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0),
1560 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
1561 SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0),
1562 SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0),
1563 SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0),
1564 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0),
1565 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0),
1566 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0),
1567 SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1568 SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1569 SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1570 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0),
1571 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0),
1572 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0),
1573 SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0),
1574 SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0),
1575 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
1576 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
1577 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0),
1578 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0),
1579 SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0),
1580 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0),
1581 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0),
1582 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 0),
1583 /* Some timers on omap4 and later */
1584 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff, 0),
1585 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff, 0),
1586 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000040, 0xffffffff, 0),
1587 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000011, 0xffffffff, 0),
1588 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0),
1589 SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0),
1590 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
1591 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
1592 SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0),
1593 SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0),
1594 #endif
1595 };
1596
1597 /*
1598 * Early quirks based on module base and register offsets only that are
1599 * needed before the module revision can be read
1600 */
sysc_init_early_quirks(struct sysc * ddata)1601 static void sysc_init_early_quirks(struct sysc *ddata)
1602 {
1603 const struct sysc_revision_quirk *q;
1604 int i;
1605
1606 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1607 q = &sysc_revision_quirks[i];
1608
1609 if (!q->base)
1610 continue;
1611
1612 if (q->base != ddata->module_pa)
1613 continue;
1614
1615 if (q->rev_offset != ddata->offsets[SYSC_REVISION])
1616 continue;
1617
1618 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1619 continue;
1620
1621 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1622 continue;
1623
1624 ddata->name = q->name;
1625 ddata->cfg.quirks |= q->quirks;
1626 }
1627 }
1628
1629 /* Quirks that also consider the revision register value */
sysc_init_revision_quirks(struct sysc * ddata)1630 static void sysc_init_revision_quirks(struct sysc *ddata)
1631 {
1632 const struct sysc_revision_quirk *q;
1633 int i;
1634
1635 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1636 q = &sysc_revision_quirks[i];
1637
1638 if (q->base && q->base != ddata->module_pa)
1639 continue;
1640
1641 if (q->rev_offset != ddata->offsets[SYSC_REVISION])
1642 continue;
1643
1644 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1645 continue;
1646
1647 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1648 continue;
1649
1650 if (q->revision == ddata->revision ||
1651 (q->revision & q->revision_mask) ==
1652 (ddata->revision & q->revision_mask)) {
1653 ddata->name = q->name;
1654 ddata->cfg.quirks |= q->quirks;
1655 }
1656 }
1657 }
1658
1659 /*
1660 * DSS needs dispc outputs disabled to reset modules. Returns mask of
1661 * enabled DSS interrupts. Eventually we may be able to do this on
1662 * dispc init rather than top-level DSS init.
1663 */
sysc_quirk_dispc(struct sysc * ddata,int dispc_offset,bool disable)1664 static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset,
1665 bool disable)
1666 {
1667 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
1668 const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1);
1669 int manager_count;
1670 bool framedonetv_irq = true;
1671 u32 val, irq_mask = 0;
1672
1673 switch (sysc_soc->soc) {
1674 case SOC_2420 ... SOC_3630:
1675 manager_count = 2;
1676 framedonetv_irq = false;
1677 break;
1678 case SOC_4430 ... SOC_4470:
1679 manager_count = 3;
1680 break;
1681 case SOC_5430:
1682 case SOC_DRA7:
1683 manager_count = 4;
1684 break;
1685 case SOC_AM4:
1686 manager_count = 1;
1687 framedonetv_irq = false;
1688 break;
1689 case SOC_UNKNOWN:
1690 default:
1691 return 0;
1692 };
1693
1694 /* Remap the whole module range to be able to reset dispc outputs */
1695 devm_iounmap(ddata->dev, ddata->module_va);
1696 ddata->module_va = devm_ioremap(ddata->dev,
1697 ddata->module_pa,
1698 ddata->module_size);
1699 if (!ddata->module_va)
1700 return -EIO;
1701
1702 /* DISP_CONTROL */
1703 val = sysc_read(ddata, dispc_offset + 0x40);
1704 lcd_en = val & lcd_en_mask;
1705 digit_en = val & digit_en_mask;
1706 if (lcd_en)
1707 irq_mask |= BIT(0); /* FRAMEDONE */
1708 if (digit_en) {
1709 if (framedonetv_irq)
1710 irq_mask |= BIT(24); /* FRAMEDONETV */
1711 else
1712 irq_mask |= BIT(2) | BIT(3); /* EVSYNC bits */
1713 }
1714 if (disable & (lcd_en | digit_en))
1715 sysc_write(ddata, dispc_offset + 0x40,
1716 val & ~(lcd_en_mask | digit_en_mask));
1717
1718 if (manager_count <= 2)
1719 return irq_mask;
1720
1721 /* DISPC_CONTROL2 */
1722 val = sysc_read(ddata, dispc_offset + 0x238);
1723 lcd2_en = val & lcd_en_mask;
1724 if (lcd2_en)
1725 irq_mask |= BIT(22); /* FRAMEDONE2 */
1726 if (disable && lcd2_en)
1727 sysc_write(ddata, dispc_offset + 0x238,
1728 val & ~lcd_en_mask);
1729
1730 if (manager_count <= 3)
1731 return irq_mask;
1732
1733 /* DISPC_CONTROL3 */
1734 val = sysc_read(ddata, dispc_offset + 0x848);
1735 lcd3_en = val & lcd_en_mask;
1736 if (lcd3_en)
1737 irq_mask |= BIT(30); /* FRAMEDONE3 */
1738 if (disable && lcd3_en)
1739 sysc_write(ddata, dispc_offset + 0x848,
1740 val & ~lcd_en_mask);
1741
1742 return irq_mask;
1743 }
1744
1745 /* DSS needs child outputs disabled and SDI registers cleared for reset */
sysc_pre_reset_quirk_dss(struct sysc * ddata)1746 static void sysc_pre_reset_quirk_dss(struct sysc *ddata)
1747 {
1748 const int dispc_offset = 0x1000;
1749 int error;
1750 u32 irq_mask, val;
1751
1752 /* Get enabled outputs */
1753 irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false);
1754 if (!irq_mask)
1755 return;
1756
1757 /* Clear IRQSTATUS */
1758 sysc_write(ddata, dispc_offset + 0x18, irq_mask);
1759
1760 /* Disable outputs */
1761 val = sysc_quirk_dispc(ddata, dispc_offset, true);
1762
1763 /* Poll IRQSTATUS */
1764 error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18,
1765 val, val != irq_mask, 100, 50);
1766 if (error)
1767 dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n",
1768 __func__, val, irq_mask);
1769
1770 if (sysc_soc->soc == SOC_3430) {
1771 /* Clear DSS_SDI_CONTROL */
1772 sysc_write(ddata, 0x44, 0);
1773
1774 /* Clear DSS_PLL_CONTROL */
1775 sysc_write(ddata, 0x48, 0);
1776 }
1777
1778 /* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */
1779 sysc_write(ddata, 0x40, 0);
1780 }
1781
1782 /* 1-wire needs module's internal clocks enabled for reset */
sysc_pre_reset_quirk_hdq1w(struct sysc * ddata)1783 static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata)
1784 {
1785 int offset = 0x0c; /* HDQ_CTRL_STATUS */
1786 u16 val;
1787
1788 val = sysc_read(ddata, offset);
1789 val |= BIT(5);
1790 sysc_write(ddata, offset, val);
1791 }
1792
1793 /* AESS (Audio Engine SubSystem) needs autogating set after enable */
sysc_module_enable_quirk_aess(struct sysc * ddata)1794 static void sysc_module_enable_quirk_aess(struct sysc *ddata)
1795 {
1796 int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */
1797
1798 sysc_write(ddata, offset, 1);
1799 }
1800
1801 /* I2C needs to be disabled for reset */
sysc_clk_quirk_i2c(struct sysc * ddata,bool enable)1802 static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
1803 {
1804 int offset;
1805 u16 val;
1806
1807 /* I2C_CON, omap2/3 is different from omap4 and later */
1808 if ((ddata->revision & 0xffffff00) == 0x001f0000)
1809 offset = 0x24;
1810 else
1811 offset = 0xa4;
1812
1813 /* I2C_EN */
1814 val = sysc_read(ddata, offset);
1815 if (enable)
1816 val |= BIT(15);
1817 else
1818 val &= ~BIT(15);
1819 sysc_write(ddata, offset, val);
1820 }
1821
sysc_pre_reset_quirk_i2c(struct sysc * ddata)1822 static void sysc_pre_reset_quirk_i2c(struct sysc *ddata)
1823 {
1824 sysc_clk_quirk_i2c(ddata, false);
1825 }
1826
sysc_post_reset_quirk_i2c(struct sysc * ddata)1827 static void sysc_post_reset_quirk_i2c(struct sysc *ddata)
1828 {
1829 sysc_clk_quirk_i2c(ddata, true);
1830 }
1831
1832 /* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */
sysc_quirk_rtc(struct sysc * ddata,bool lock)1833 static void sysc_quirk_rtc(struct sysc *ddata, bool lock)
1834 {
1835 u32 val, kick0_val = 0, kick1_val = 0;
1836 unsigned long flags;
1837 int error;
1838
1839 if (!lock) {
1840 kick0_val = 0x83e70b13;
1841 kick1_val = 0x95a4f1e0;
1842 }
1843
1844 local_irq_save(flags);
1845 /* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */
1846 error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val,
1847 !(val & BIT(0)), 100, 50);
1848 if (error)
1849 dev_warn(ddata->dev, "rtc busy timeout\n");
1850 /* Now we have ~15 microseconds to read/write various registers */
1851 sysc_write(ddata, 0x6c, kick0_val);
1852 sysc_write(ddata, 0x70, kick1_val);
1853 local_irq_restore(flags);
1854 }
1855
sysc_module_unlock_quirk_rtc(struct sysc * ddata)1856 static void sysc_module_unlock_quirk_rtc(struct sysc *ddata)
1857 {
1858 sysc_quirk_rtc(ddata, false);
1859 }
1860
sysc_module_lock_quirk_rtc(struct sysc * ddata)1861 static void sysc_module_lock_quirk_rtc(struct sysc *ddata)
1862 {
1863 sysc_quirk_rtc(ddata, true);
1864 }
1865
1866 /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */
sysc_module_enable_quirk_sgx(struct sysc * ddata)1867 static void sysc_module_enable_quirk_sgx(struct sysc *ddata)
1868 {
1869 int offset = 0xff08; /* OCP_DEBUG_CONFIG */
1870 u32 val = BIT(31); /* THALIA_INT_BYPASS */
1871
1872 sysc_write(ddata, offset, val);
1873 }
1874
1875 /* Watchdog timer needs a disable sequence after reset */
sysc_reset_done_quirk_wdt(struct sysc * ddata)1876 static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
1877 {
1878 int wps, spr, error;
1879 u32 val;
1880
1881 wps = 0x34;
1882 spr = 0x48;
1883
1884 sysc_write(ddata, spr, 0xaaaa);
1885 error = readl_poll_timeout(ddata->module_va + wps, val,
1886 !(val & 0x10), 100,
1887 MAX_MODULE_SOFTRESET_WAIT);
1888 if (error)
1889 dev_warn(ddata->dev, "wdt disable step1 failed\n");
1890
1891 sysc_write(ddata, spr, 0x5555);
1892 error = readl_poll_timeout(ddata->module_va + wps, val,
1893 !(val & 0x10), 100,
1894 MAX_MODULE_SOFTRESET_WAIT);
1895 if (error)
1896 dev_warn(ddata->dev, "wdt disable step2 failed\n");
1897 }
1898
1899 /* PRUSS needs to set MSTANDBY_INIT inorder to idle properly */
sysc_module_disable_quirk_pruss(struct sysc * ddata)1900 static void sysc_module_disable_quirk_pruss(struct sysc *ddata)
1901 {
1902 u32 reg;
1903
1904 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1905 reg |= SYSC_PRUSS_STANDBY_INIT;
1906 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
1907 }
1908
sysc_init_module_quirks(struct sysc * ddata)1909 static void sysc_init_module_quirks(struct sysc *ddata)
1910 {
1911 if (ddata->legacy_mode || !ddata->name)
1912 return;
1913
1914 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
1915 ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w;
1916
1917 return;
1918 }
1919
1920 #ifdef CONFIG_OMAP_GPMC_DEBUG
1921 if (ddata->cfg.quirks & SYSC_QUIRK_GPMC_DEBUG) {
1922 ddata->cfg.quirks |= SYSC_QUIRK_NO_RESET_ON_INIT;
1923
1924 return;
1925 }
1926 #endif
1927
1928 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) {
1929 ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c;
1930 ddata->post_reset_quirk = sysc_post_reset_quirk_i2c;
1931
1932 return;
1933 }
1934
1935 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS)
1936 ddata->module_enable_quirk = sysc_module_enable_quirk_aess;
1937
1938 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET)
1939 ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss;
1940
1941 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) {
1942 ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc;
1943 ddata->module_lock_quirk = sysc_module_lock_quirk_rtc;
1944
1945 return;
1946 }
1947
1948 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
1949 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
1950
1951 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) {
1952 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
1953 ddata->module_disable_quirk = sysc_reset_done_quirk_wdt;
1954 }
1955
1956 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS)
1957 ddata->module_disable_quirk = sysc_module_disable_quirk_pruss;
1958 }
1959
sysc_clockdomain_init(struct sysc * ddata)1960 static int sysc_clockdomain_init(struct sysc *ddata)
1961 {
1962 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1963 struct clk *fck = NULL, *ick = NULL;
1964 int error;
1965
1966 if (!pdata || !pdata->init_clockdomain)
1967 return 0;
1968
1969 switch (ddata->nr_clocks) {
1970 case 2:
1971 ick = ddata->clocks[SYSC_ICK];
1972 fallthrough;
1973 case 1:
1974 fck = ddata->clocks[SYSC_FCK];
1975 break;
1976 case 0:
1977 return 0;
1978 }
1979
1980 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie);
1981 if (!error || error == -ENODEV)
1982 return 0;
1983
1984 return error;
1985 }
1986
1987 /*
1988 * Note that pdata->init_module() typically does a reset first. After
1989 * pdata->init_module() is done, PM runtime can be used for the interconnect
1990 * target module.
1991 */
sysc_legacy_init(struct sysc * ddata)1992 static int sysc_legacy_init(struct sysc *ddata)
1993 {
1994 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1995 int error;
1996
1997 if (!pdata || !pdata->init_module)
1998 return 0;
1999
2000 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
2001 if (error == -EEXIST)
2002 error = 0;
2003
2004 return error;
2005 }
2006
2007 /*
2008 * Note that the caller must ensure the interconnect target module is enabled
2009 * before calling reset. Otherwise reset will not complete.
2010 */
sysc_reset(struct sysc * ddata)2011 static int sysc_reset(struct sysc *ddata)
2012 {
2013 int sysc_offset, sysc_val, error;
2014 u32 sysc_mask;
2015
2016 sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
2017
2018 if (ddata->legacy_mode ||
2019 ddata->cap->regbits->srst_shift < 0 ||
2020 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
2021 return 0;
2022
2023 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
2024
2025 if (ddata->pre_reset_quirk)
2026 ddata->pre_reset_quirk(ddata);
2027
2028 if (sysc_offset >= 0) {
2029 sysc_val = sysc_read_sysconfig(ddata);
2030 sysc_val |= sysc_mask;
2031 sysc_write(ddata, sysc_offset, sysc_val);
2032 }
2033
2034 if (ddata->cfg.srst_udelay)
2035 usleep_range(ddata->cfg.srst_udelay,
2036 ddata->cfg.srst_udelay * 2);
2037
2038 if (ddata->post_reset_quirk)
2039 ddata->post_reset_quirk(ddata);
2040
2041 error = sysc_wait_softreset(ddata);
2042 if (error)
2043 dev_warn(ddata->dev, "OCP softreset timed out\n");
2044
2045 if (ddata->reset_done_quirk)
2046 ddata->reset_done_quirk(ddata);
2047
2048 return error;
2049 }
2050
2051 /*
2052 * At this point the module is configured enough to read the revision but
2053 * module may not be completely configured yet to use PM runtime. Enable
2054 * all clocks directly during init to configure the quirks needed for PM
2055 * runtime based on the revision register.
2056 */
sysc_init_module(struct sysc * ddata)2057 static int sysc_init_module(struct sysc *ddata)
2058 {
2059 int error = 0;
2060
2061 error = sysc_clockdomain_init(ddata);
2062 if (error)
2063 return error;
2064
2065 sysc_clkdm_deny_idle(ddata);
2066
2067 /*
2068 * Always enable clocks. The bootloader may or may not have enabled
2069 * the related clocks.
2070 */
2071 error = sysc_enable_opt_clocks(ddata);
2072 if (error)
2073 return error;
2074
2075 error = sysc_enable_main_clocks(ddata);
2076 if (error)
2077 goto err_opt_clocks;
2078
2079 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
2080 error = reset_control_deassert(ddata->rsts);
2081 if (error)
2082 goto err_main_clocks;
2083 }
2084
2085 ddata->revision = sysc_read_revision(ddata);
2086 sysc_init_revision_quirks(ddata);
2087 sysc_init_module_quirks(ddata);
2088
2089 if (ddata->legacy_mode) {
2090 error = sysc_legacy_init(ddata);
2091 if (error)
2092 goto err_reset;
2093 }
2094
2095 if (!ddata->legacy_mode) {
2096 error = sysc_enable_module(ddata->dev);
2097 if (error)
2098 goto err_reset;
2099 }
2100
2101 error = sysc_reset(ddata);
2102 if (error)
2103 dev_err(ddata->dev, "Reset failed with %d\n", error);
2104
2105 if (error && !ddata->legacy_mode)
2106 sysc_disable_module(ddata->dev);
2107
2108 err_reset:
2109 if (error && !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
2110 reset_control_assert(ddata->rsts);
2111
2112 err_main_clocks:
2113 if (error)
2114 sysc_disable_main_clocks(ddata);
2115 err_opt_clocks:
2116 /* No re-enable of clockdomain autoidle to prevent module autoidle */
2117 if (error) {
2118 sysc_disable_opt_clocks(ddata);
2119 sysc_clkdm_allow_idle(ddata);
2120 }
2121
2122 return error;
2123 }
2124
sysc_init_sysc_mask(struct sysc * ddata)2125 static int sysc_init_sysc_mask(struct sysc *ddata)
2126 {
2127 struct device_node *np = ddata->dev->of_node;
2128 int error;
2129 u32 val;
2130
2131 error = of_property_read_u32(np, "ti,sysc-mask", &val);
2132 if (error)
2133 return 0;
2134
2135 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
2136
2137 return 0;
2138 }
2139
sysc_init_idlemode(struct sysc * ddata,u8 * idlemodes,const char * name)2140 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
2141 const char *name)
2142 {
2143 struct device_node *np = ddata->dev->of_node;
2144 struct property *prop;
2145 const __be32 *p;
2146 u32 val;
2147
2148 of_property_for_each_u32(np, name, prop, p, val) {
2149 if (val >= SYSC_NR_IDLEMODES) {
2150 dev_err(ddata->dev, "invalid idlemode: %i\n", val);
2151 return -EINVAL;
2152 }
2153 *idlemodes |= (1 << val);
2154 }
2155
2156 return 0;
2157 }
2158
sysc_init_idlemodes(struct sysc * ddata)2159 static int sysc_init_idlemodes(struct sysc *ddata)
2160 {
2161 int error;
2162
2163 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
2164 "ti,sysc-midle");
2165 if (error)
2166 return error;
2167
2168 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
2169 "ti,sysc-sidle");
2170 if (error)
2171 return error;
2172
2173 return 0;
2174 }
2175
2176 /*
2177 * Only some devices on omap4 and later have SYSCONFIG reset done
2178 * bit. We can detect this if there is no SYSSTATUS at all, or the
2179 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
2180 * have multiple bits for the child devices like OHCI and EHCI.
2181 * Depends on SYSC being parsed first.
2182 */
sysc_init_syss_mask(struct sysc * ddata)2183 static int sysc_init_syss_mask(struct sysc *ddata)
2184 {
2185 struct device_node *np = ddata->dev->of_node;
2186 int error;
2187 u32 val;
2188
2189 error = of_property_read_u32(np, "ti,syss-mask", &val);
2190 if (error) {
2191 if ((ddata->cap->type == TI_SYSC_OMAP4 ||
2192 ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
2193 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
2194 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
2195
2196 return 0;
2197 }
2198
2199 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
2200 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
2201
2202 ddata->cfg.syss_mask = val;
2203
2204 return 0;
2205 }
2206
2207 /*
2208 * Many child device drivers need to have fck and opt clocks available
2209 * to get the clock rate for device internal configuration etc.
2210 */
sysc_child_add_named_clock(struct sysc * ddata,struct device * child,const char * name)2211 static int sysc_child_add_named_clock(struct sysc *ddata,
2212 struct device *child,
2213 const char *name)
2214 {
2215 struct clk *clk;
2216 struct clk_lookup *l;
2217 int error = 0;
2218
2219 if (!name)
2220 return 0;
2221
2222 clk = clk_get(child, name);
2223 if (!IS_ERR(clk)) {
2224 error = -EEXIST;
2225 goto put_clk;
2226 }
2227
2228 clk = clk_get(ddata->dev, name);
2229 if (IS_ERR(clk))
2230 return -ENODEV;
2231
2232 l = clkdev_create(clk, name, dev_name(child));
2233 if (!l)
2234 error = -ENOMEM;
2235 put_clk:
2236 clk_put(clk);
2237
2238 return error;
2239 }
2240
sysc_child_add_clocks(struct sysc * ddata,struct device * child)2241 static int sysc_child_add_clocks(struct sysc *ddata,
2242 struct device *child)
2243 {
2244 int i, error;
2245
2246 for (i = 0; i < ddata->nr_clocks; i++) {
2247 error = sysc_child_add_named_clock(ddata,
2248 child,
2249 ddata->clock_roles[i]);
2250 if (error && error != -EEXIST) {
2251 dev_err(ddata->dev, "could not add child clock %s: %i\n",
2252 ddata->clock_roles[i], error);
2253
2254 return error;
2255 }
2256 }
2257
2258 return 0;
2259 }
2260
2261 static struct device_type sysc_device_type = {
2262 };
2263
sysc_child_to_parent(struct device * dev)2264 static struct sysc *sysc_child_to_parent(struct device *dev)
2265 {
2266 struct device *parent = dev->parent;
2267
2268 if (!parent || parent->type != &sysc_device_type)
2269 return NULL;
2270
2271 return dev_get_drvdata(parent);
2272 }
2273
sysc_child_runtime_suspend(struct device * dev)2274 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
2275 {
2276 struct sysc *ddata;
2277 int error;
2278
2279 ddata = sysc_child_to_parent(dev);
2280
2281 error = pm_generic_runtime_suspend(dev);
2282 if (error)
2283 return error;
2284
2285 if (!ddata->enabled)
2286 return 0;
2287
2288 return sysc_runtime_suspend(ddata->dev);
2289 }
2290
sysc_child_runtime_resume(struct device * dev)2291 static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
2292 {
2293 struct sysc *ddata;
2294 int error;
2295
2296 ddata = sysc_child_to_parent(dev);
2297
2298 if (!ddata->enabled) {
2299 error = sysc_runtime_resume(ddata->dev);
2300 if (error < 0)
2301 dev_err(ddata->dev,
2302 "%s error: %i\n", __func__, error);
2303 }
2304
2305 return pm_generic_runtime_resume(dev);
2306 }
2307
2308 #ifdef CONFIG_PM_SLEEP
sysc_child_suspend_noirq(struct device * dev)2309 static int sysc_child_suspend_noirq(struct device *dev)
2310 {
2311 struct sysc *ddata;
2312 int error;
2313
2314 ddata = sysc_child_to_parent(dev);
2315
2316 dev_dbg(ddata->dev, "%s %s\n", __func__,
2317 ddata->name ? ddata->name : "");
2318
2319 error = pm_generic_suspend_noirq(dev);
2320 if (error) {
2321 dev_err(dev, "%s error at %i: %i\n",
2322 __func__, __LINE__, error);
2323
2324 return error;
2325 }
2326
2327 if (!pm_runtime_status_suspended(dev)) {
2328 error = pm_generic_runtime_suspend(dev);
2329 if (error) {
2330 dev_dbg(dev, "%s busy at %i: %i\n",
2331 __func__, __LINE__, error);
2332
2333 return 0;
2334 }
2335
2336 error = sysc_runtime_suspend(ddata->dev);
2337 if (error) {
2338 dev_err(dev, "%s error at %i: %i\n",
2339 __func__, __LINE__, error);
2340
2341 return error;
2342 }
2343
2344 ddata->child_needs_resume = true;
2345 }
2346
2347 return 0;
2348 }
2349
sysc_child_resume_noirq(struct device * dev)2350 static int sysc_child_resume_noirq(struct device *dev)
2351 {
2352 struct sysc *ddata;
2353 int error;
2354
2355 ddata = sysc_child_to_parent(dev);
2356
2357 dev_dbg(ddata->dev, "%s %s\n", __func__,
2358 ddata->name ? ddata->name : "");
2359
2360 if (ddata->child_needs_resume) {
2361 ddata->child_needs_resume = false;
2362
2363 error = sysc_runtime_resume(ddata->dev);
2364 if (error)
2365 dev_err(ddata->dev,
2366 "%s runtime resume error: %i\n",
2367 __func__, error);
2368
2369 error = pm_generic_runtime_resume(dev);
2370 if (error)
2371 dev_err(ddata->dev,
2372 "%s generic runtime resume: %i\n",
2373 __func__, error);
2374 }
2375
2376 return pm_generic_resume_noirq(dev);
2377 }
2378 #endif
2379
2380 static struct dev_pm_domain sysc_child_pm_domain = {
2381 .ops = {
2382 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
2383 sysc_child_runtime_resume,
2384 NULL)
2385 USE_PLATFORM_PM_SLEEP_OPS
2386 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
2387 sysc_child_resume_noirq)
2388 }
2389 };
2390
2391 /**
2392 * sysc_legacy_idle_quirk - handle children in omap_device compatible way
2393 * @ddata: device driver data
2394 * @child: child device driver
2395 *
2396 * Allow idle for child devices as done with _od_runtime_suspend().
2397 * Otherwise many child devices will not idle because of the permanent
2398 * parent usecount set in pm_runtime_irq_safe().
2399 *
2400 * Note that the long term solution is to just modify the child device
2401 * drivers to not set pm_runtime_irq_safe() and then this can be just
2402 * dropped.
2403 */
sysc_legacy_idle_quirk(struct sysc * ddata,struct device * child)2404 static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
2405 {
2406 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
2407 dev_pm_domain_set(child, &sysc_child_pm_domain);
2408 }
2409
sysc_notifier_call(struct notifier_block * nb,unsigned long event,void * device)2410 static int sysc_notifier_call(struct notifier_block *nb,
2411 unsigned long event, void *device)
2412 {
2413 struct device *dev = device;
2414 struct sysc *ddata;
2415 int error;
2416
2417 ddata = sysc_child_to_parent(dev);
2418 if (!ddata)
2419 return NOTIFY_DONE;
2420
2421 switch (event) {
2422 case BUS_NOTIFY_ADD_DEVICE:
2423 error = sysc_child_add_clocks(ddata, dev);
2424 if (error)
2425 return error;
2426 sysc_legacy_idle_quirk(ddata, dev);
2427 break;
2428 default:
2429 break;
2430 }
2431
2432 return NOTIFY_DONE;
2433 }
2434
2435 static struct notifier_block sysc_nb = {
2436 .notifier_call = sysc_notifier_call,
2437 };
2438
2439 /* Device tree configured quirks */
2440 struct sysc_dts_quirk {
2441 const char *name;
2442 u32 mask;
2443 };
2444
2445 static const struct sysc_dts_quirk sysc_dts_quirks[] = {
2446 { .name = "ti,no-idle-on-init",
2447 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
2448 { .name = "ti,no-reset-on-init",
2449 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
2450 { .name = "ti,no-idle",
2451 .mask = SYSC_QUIRK_NO_IDLE, },
2452 };
2453
sysc_parse_dts_quirks(struct sysc * ddata,struct device_node * np,bool is_child)2454 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
2455 bool is_child)
2456 {
2457 const struct property *prop;
2458 int i, len;
2459
2460 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
2461 const char *name = sysc_dts_quirks[i].name;
2462
2463 prop = of_get_property(np, name, &len);
2464 if (!prop)
2465 continue;
2466
2467 ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
2468 if (is_child) {
2469 dev_warn(ddata->dev,
2470 "dts flag should be at module level for %s\n",
2471 name);
2472 }
2473 }
2474 }
2475
sysc_init_dts_quirks(struct sysc * ddata)2476 static int sysc_init_dts_quirks(struct sysc *ddata)
2477 {
2478 struct device_node *np = ddata->dev->of_node;
2479 int error;
2480 u32 val;
2481
2482 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
2483
2484 sysc_parse_dts_quirks(ddata, np, false);
2485 error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
2486 if (!error) {
2487 if (val > 255) {
2488 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
2489 val);
2490 }
2491
2492 ddata->cfg.srst_udelay = (u8)val;
2493 }
2494
2495 return 0;
2496 }
2497
sysc_unprepare(struct sysc * ddata)2498 static void sysc_unprepare(struct sysc *ddata)
2499 {
2500 int i;
2501
2502 if (!ddata->clocks)
2503 return;
2504
2505 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
2506 if (!IS_ERR_OR_NULL(ddata->clocks[i]))
2507 clk_unprepare(ddata->clocks[i]);
2508 }
2509 }
2510
2511 /*
2512 * Common sysc register bits found on omap2, also known as type1
2513 */
2514 static const struct sysc_regbits sysc_regbits_omap2 = {
2515 .dmadisable_shift = -ENODEV,
2516 .midle_shift = 12,
2517 .sidle_shift = 3,
2518 .clkact_shift = 8,
2519 .emufree_shift = 5,
2520 .enwkup_shift = 2,
2521 .srst_shift = 1,
2522 .autoidle_shift = 0,
2523 };
2524
2525 static const struct sysc_capabilities sysc_omap2 = {
2526 .type = TI_SYSC_OMAP2,
2527 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2528 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2529 SYSC_OMAP2_AUTOIDLE,
2530 .regbits = &sysc_regbits_omap2,
2531 };
2532
2533 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
2534 static const struct sysc_capabilities sysc_omap2_timer = {
2535 .type = TI_SYSC_OMAP2_TIMER,
2536 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2537 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2538 SYSC_OMAP2_AUTOIDLE,
2539 .regbits = &sysc_regbits_omap2,
2540 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
2541 };
2542
2543 /*
2544 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
2545 * with different sidle position
2546 */
2547 static const struct sysc_regbits sysc_regbits_omap3_sham = {
2548 .dmadisable_shift = -ENODEV,
2549 .midle_shift = -ENODEV,
2550 .sidle_shift = 4,
2551 .clkact_shift = -ENODEV,
2552 .enwkup_shift = -ENODEV,
2553 .srst_shift = 1,
2554 .autoidle_shift = 0,
2555 .emufree_shift = -ENODEV,
2556 };
2557
2558 static const struct sysc_capabilities sysc_omap3_sham = {
2559 .type = TI_SYSC_OMAP3_SHAM,
2560 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2561 .regbits = &sysc_regbits_omap3_sham,
2562 };
2563
2564 /*
2565 * AES register bits found on omap3 and later, a variant of
2566 * sysc_regbits_omap2 with different sidle position
2567 */
2568 static const struct sysc_regbits sysc_regbits_omap3_aes = {
2569 .dmadisable_shift = -ENODEV,
2570 .midle_shift = -ENODEV,
2571 .sidle_shift = 6,
2572 .clkact_shift = -ENODEV,
2573 .enwkup_shift = -ENODEV,
2574 .srst_shift = 1,
2575 .autoidle_shift = 0,
2576 .emufree_shift = -ENODEV,
2577 };
2578
2579 static const struct sysc_capabilities sysc_omap3_aes = {
2580 .type = TI_SYSC_OMAP3_AES,
2581 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2582 .regbits = &sysc_regbits_omap3_aes,
2583 };
2584
2585 /*
2586 * Common sysc register bits found on omap4, also known as type2
2587 */
2588 static const struct sysc_regbits sysc_regbits_omap4 = {
2589 .dmadisable_shift = 16,
2590 .midle_shift = 4,
2591 .sidle_shift = 2,
2592 .clkact_shift = -ENODEV,
2593 .enwkup_shift = -ENODEV,
2594 .emufree_shift = 1,
2595 .srst_shift = 0,
2596 .autoidle_shift = -ENODEV,
2597 };
2598
2599 static const struct sysc_capabilities sysc_omap4 = {
2600 .type = TI_SYSC_OMAP4,
2601 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2602 SYSC_OMAP4_SOFTRESET,
2603 .regbits = &sysc_regbits_omap4,
2604 };
2605
2606 static const struct sysc_capabilities sysc_omap4_timer = {
2607 .type = TI_SYSC_OMAP4_TIMER,
2608 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2609 SYSC_OMAP4_SOFTRESET,
2610 .regbits = &sysc_regbits_omap4,
2611 };
2612
2613 /*
2614 * Common sysc register bits found on omap4, also known as type3
2615 */
2616 static const struct sysc_regbits sysc_regbits_omap4_simple = {
2617 .dmadisable_shift = -ENODEV,
2618 .midle_shift = 2,
2619 .sidle_shift = 0,
2620 .clkact_shift = -ENODEV,
2621 .enwkup_shift = -ENODEV,
2622 .srst_shift = -ENODEV,
2623 .emufree_shift = -ENODEV,
2624 .autoidle_shift = -ENODEV,
2625 };
2626
2627 static const struct sysc_capabilities sysc_omap4_simple = {
2628 .type = TI_SYSC_OMAP4_SIMPLE,
2629 .regbits = &sysc_regbits_omap4_simple,
2630 };
2631
2632 /*
2633 * SmartReflex sysc found on omap34xx
2634 */
2635 static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
2636 .dmadisable_shift = -ENODEV,
2637 .midle_shift = -ENODEV,
2638 .sidle_shift = -ENODEV,
2639 .clkact_shift = 20,
2640 .enwkup_shift = -ENODEV,
2641 .srst_shift = -ENODEV,
2642 .emufree_shift = -ENODEV,
2643 .autoidle_shift = -ENODEV,
2644 };
2645
2646 static const struct sysc_capabilities sysc_34xx_sr = {
2647 .type = TI_SYSC_OMAP34XX_SR,
2648 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
2649 .regbits = &sysc_regbits_omap34xx_sr,
2650 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
2651 SYSC_QUIRK_LEGACY_IDLE,
2652 };
2653
2654 /*
2655 * SmartReflex sysc found on omap36xx and later
2656 */
2657 static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
2658 .dmadisable_shift = -ENODEV,
2659 .midle_shift = -ENODEV,
2660 .sidle_shift = 24,
2661 .clkact_shift = -ENODEV,
2662 .enwkup_shift = 26,
2663 .srst_shift = -ENODEV,
2664 .emufree_shift = -ENODEV,
2665 .autoidle_shift = -ENODEV,
2666 };
2667
2668 static const struct sysc_capabilities sysc_36xx_sr = {
2669 .type = TI_SYSC_OMAP36XX_SR,
2670 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
2671 .regbits = &sysc_regbits_omap36xx_sr,
2672 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
2673 };
2674
2675 static const struct sysc_capabilities sysc_omap4_sr = {
2676 .type = TI_SYSC_OMAP4_SR,
2677 .regbits = &sysc_regbits_omap36xx_sr,
2678 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
2679 };
2680
2681 /*
2682 * McASP register bits found on omap4 and later
2683 */
2684 static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
2685 .dmadisable_shift = -ENODEV,
2686 .midle_shift = -ENODEV,
2687 .sidle_shift = 0,
2688 .clkact_shift = -ENODEV,
2689 .enwkup_shift = -ENODEV,
2690 .srst_shift = -ENODEV,
2691 .emufree_shift = -ENODEV,
2692 .autoidle_shift = -ENODEV,
2693 };
2694
2695 static const struct sysc_capabilities sysc_omap4_mcasp = {
2696 .type = TI_SYSC_OMAP4_MCASP,
2697 .regbits = &sysc_regbits_omap4_mcasp,
2698 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2699 };
2700
2701 /*
2702 * McASP found on dra7 and later
2703 */
2704 static const struct sysc_capabilities sysc_dra7_mcasp = {
2705 .type = TI_SYSC_OMAP4_SIMPLE,
2706 .regbits = &sysc_regbits_omap4_simple,
2707 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2708 };
2709
2710 /*
2711 * FS USB host found on omap4 and later
2712 */
2713 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
2714 .dmadisable_shift = -ENODEV,
2715 .midle_shift = -ENODEV,
2716 .sidle_shift = 24,
2717 .clkact_shift = -ENODEV,
2718 .enwkup_shift = 26,
2719 .srst_shift = -ENODEV,
2720 .emufree_shift = -ENODEV,
2721 .autoidle_shift = -ENODEV,
2722 };
2723
2724 static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
2725 .type = TI_SYSC_OMAP4_USB_HOST_FS,
2726 .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
2727 .regbits = &sysc_regbits_omap4_usb_host_fs,
2728 };
2729
2730 static const struct sysc_regbits sysc_regbits_dra7_mcan = {
2731 .dmadisable_shift = -ENODEV,
2732 .midle_shift = -ENODEV,
2733 .sidle_shift = -ENODEV,
2734 .clkact_shift = -ENODEV,
2735 .enwkup_shift = 4,
2736 .srst_shift = 0,
2737 .emufree_shift = -ENODEV,
2738 .autoidle_shift = -ENODEV,
2739 };
2740
2741 static const struct sysc_capabilities sysc_dra7_mcan = {
2742 .type = TI_SYSC_DRA7_MCAN,
2743 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
2744 .regbits = &sysc_regbits_dra7_mcan,
2745 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
2746 };
2747
2748 /*
2749 * PRUSS found on some AM33xx, AM437x and AM57xx SoCs
2750 */
2751 static const struct sysc_capabilities sysc_pruss = {
2752 .type = TI_SYSC_PRUSS,
2753 .sysc_mask = SYSC_PRUSS_STANDBY_INIT | SYSC_PRUSS_SUB_MWAIT,
2754 .regbits = &sysc_regbits_omap4_simple,
2755 .mod_quirks = SYSC_MODULE_QUIRK_PRUSS,
2756 };
2757
sysc_init_pdata(struct sysc * ddata)2758 static int sysc_init_pdata(struct sysc *ddata)
2759 {
2760 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2761 struct ti_sysc_module_data *mdata;
2762
2763 if (!pdata)
2764 return 0;
2765
2766 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
2767 if (!mdata)
2768 return -ENOMEM;
2769
2770 if (ddata->legacy_mode) {
2771 mdata->name = ddata->legacy_mode;
2772 mdata->module_pa = ddata->module_pa;
2773 mdata->module_size = ddata->module_size;
2774 mdata->offsets = ddata->offsets;
2775 mdata->nr_offsets = SYSC_MAX_REGS;
2776 mdata->cap = ddata->cap;
2777 mdata->cfg = &ddata->cfg;
2778 }
2779
2780 ddata->mdata = mdata;
2781
2782 return 0;
2783 }
2784
sysc_init_match(struct sysc * ddata)2785 static int sysc_init_match(struct sysc *ddata)
2786 {
2787 const struct sysc_capabilities *cap;
2788
2789 cap = of_device_get_match_data(ddata->dev);
2790 if (!cap)
2791 return -EINVAL;
2792
2793 ddata->cap = cap;
2794 if (ddata->cap)
2795 ddata->cfg.quirks |= ddata->cap->mod_quirks;
2796
2797 return 0;
2798 }
2799
ti_sysc_idle(struct work_struct * work)2800 static void ti_sysc_idle(struct work_struct *work)
2801 {
2802 struct sysc *ddata;
2803
2804 ddata = container_of(work, struct sysc, idle_work.work);
2805
2806 /*
2807 * One time decrement of clock usage counts if left on from init.
2808 * Note that we disable opt clocks unconditionally in this case
2809 * as they are enabled unconditionally during init without
2810 * considering sysc_opt_clks_needed() at that point.
2811 */
2812 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
2813 SYSC_QUIRK_NO_IDLE_ON_INIT)) {
2814 sysc_disable_main_clocks(ddata);
2815 sysc_disable_opt_clocks(ddata);
2816 sysc_clkdm_allow_idle(ddata);
2817 }
2818
2819 /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */
2820 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
2821 return;
2822
2823 /*
2824 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT
2825 * and SYSC_QUIRK_NO_RESET_ON_INIT
2826 */
2827 if (pm_runtime_active(ddata->dev))
2828 pm_runtime_put_sync(ddata->dev);
2829 }
2830
2831 /*
2832 * SoC model and features detection. Only needed for SoCs that need
2833 * special handling for quirks, no need to list others.
2834 */
2835 static const struct soc_device_attribute sysc_soc_match[] = {
2836 SOC_FLAG("OMAP242*", SOC_2420),
2837 SOC_FLAG("OMAP243*", SOC_2430),
2838 SOC_FLAG("OMAP3[45]*", SOC_3430),
2839 SOC_FLAG("OMAP3[67]*", SOC_3630),
2840 SOC_FLAG("OMAP443*", SOC_4430),
2841 SOC_FLAG("OMAP446*", SOC_4460),
2842 SOC_FLAG("OMAP447*", SOC_4470),
2843 SOC_FLAG("OMAP54*", SOC_5430),
2844 SOC_FLAG("AM433", SOC_AM3),
2845 SOC_FLAG("AM43*", SOC_AM4),
2846 SOC_FLAG("DRA7*", SOC_DRA7),
2847
2848 { /* sentinel */ },
2849 };
2850
2851 /*
2852 * List of SoCs variants with disabled features. By default we assume all
2853 * devices in the device tree are available so no need to list those SoCs.
2854 */
2855 static const struct soc_device_attribute sysc_soc_feat_match[] = {
2856 /* OMAP3430/3530 and AM3517 variants with some accelerators disabled */
2857 SOC_FLAG("AM3505", DIS_SGX),
2858 SOC_FLAG("OMAP3525", DIS_SGX),
2859 SOC_FLAG("OMAP3515", DIS_IVA | DIS_SGX),
2860 SOC_FLAG("OMAP3503", DIS_ISP | DIS_IVA | DIS_SGX),
2861
2862 /* OMAP3630/DM3730 variants with some accelerators disabled */
2863 SOC_FLAG("AM3703", DIS_IVA | DIS_SGX),
2864 SOC_FLAG("DM3725", DIS_SGX),
2865 SOC_FLAG("OMAP3611", DIS_ISP | DIS_IVA | DIS_SGX),
2866 SOC_FLAG("OMAP3615/AM3715", DIS_IVA),
2867 SOC_FLAG("OMAP3621", DIS_ISP),
2868
2869 { /* sentinel */ },
2870 };
2871
sysc_add_disabled(unsigned long base)2872 static int sysc_add_disabled(unsigned long base)
2873 {
2874 struct sysc_address *disabled_module;
2875
2876 disabled_module = kzalloc(sizeof(*disabled_module), GFP_KERNEL);
2877 if (!disabled_module)
2878 return -ENOMEM;
2879
2880 disabled_module->base = base;
2881
2882 mutex_lock(&sysc_soc->list_lock);
2883 list_add(&disabled_module->node, &sysc_soc->disabled_modules);
2884 mutex_unlock(&sysc_soc->list_lock);
2885
2886 return 0;
2887 }
2888
2889 /*
2890 * One time init to detect the booted SoC and disable unavailable features.
2891 * Note that we initialize static data shared across all ti-sysc instances
2892 * so ddata is only used for SoC type. This can be called from module_init
2893 * once we no longer need to rely on platform data.
2894 */
sysc_init_soc(struct sysc * ddata)2895 static int sysc_init_soc(struct sysc *ddata)
2896 {
2897 const struct soc_device_attribute *match;
2898 struct ti_sysc_platform_data *pdata;
2899 unsigned long features = 0;
2900
2901 if (sysc_soc)
2902 return 0;
2903
2904 sysc_soc = kzalloc(sizeof(*sysc_soc), GFP_KERNEL);
2905 if (!sysc_soc)
2906 return -ENOMEM;
2907
2908 mutex_init(&sysc_soc->list_lock);
2909 INIT_LIST_HEAD(&sysc_soc->disabled_modules);
2910 sysc_soc->general_purpose = true;
2911
2912 pdata = dev_get_platdata(ddata->dev);
2913 if (pdata && pdata->soc_type_gp)
2914 sysc_soc->general_purpose = pdata->soc_type_gp();
2915
2916 match = soc_device_match(sysc_soc_match);
2917 if (match && match->data)
2918 sysc_soc->soc = (int)match->data;
2919
2920 /* Ignore devices that are not available on HS and EMU SoCs */
2921 if (!sysc_soc->general_purpose) {
2922 switch (sysc_soc->soc) {
2923 case SOC_3430 ... SOC_3630:
2924 sysc_add_disabled(0x48304000); /* timer12 */
2925 break;
2926 case SOC_AM3:
2927 sysc_add_disabled(0x48310000); /* rng */
2928 break;
2929 default:
2930 break;
2931 };
2932 }
2933
2934 match = soc_device_match(sysc_soc_feat_match);
2935 if (!match)
2936 return 0;
2937
2938 if (match->data)
2939 features = (unsigned long)match->data;
2940
2941 /*
2942 * Add disabled devices to the list based on the module base.
2943 * Note that this must be done before we attempt to access the
2944 * device and have module revision checks working.
2945 */
2946 if (features & DIS_ISP)
2947 sysc_add_disabled(0x480bd400);
2948 if (features & DIS_IVA)
2949 sysc_add_disabled(0x5d000000);
2950 if (features & DIS_SGX)
2951 sysc_add_disabled(0x50000000);
2952
2953 return 0;
2954 }
2955
sysc_cleanup_soc(void)2956 static void sysc_cleanup_soc(void)
2957 {
2958 struct sysc_address *disabled_module;
2959 struct list_head *pos, *tmp;
2960
2961 if (!sysc_soc)
2962 return;
2963
2964 mutex_lock(&sysc_soc->list_lock);
2965 list_for_each_safe(pos, tmp, &sysc_soc->disabled_modules) {
2966 disabled_module = list_entry(pos, struct sysc_address, node);
2967 list_del(pos);
2968 kfree(disabled_module);
2969 }
2970 mutex_unlock(&sysc_soc->list_lock);
2971 }
2972
sysc_check_disabled_devices(struct sysc * ddata)2973 static int sysc_check_disabled_devices(struct sysc *ddata)
2974 {
2975 struct sysc_address *disabled_module;
2976 struct list_head *pos;
2977 int error = 0;
2978
2979 mutex_lock(&sysc_soc->list_lock);
2980 list_for_each(pos, &sysc_soc->disabled_modules) {
2981 disabled_module = list_entry(pos, struct sysc_address, node);
2982 if (ddata->module_pa == disabled_module->base) {
2983 dev_dbg(ddata->dev, "module disabled for this SoC\n");
2984 error = -ENODEV;
2985 break;
2986 }
2987 }
2988 mutex_unlock(&sysc_soc->list_lock);
2989
2990 return error;
2991 }
2992
2993 /*
2994 * Ignore timers tagged with no-reset and no-idle. These are likely in use,
2995 * for example by drivers/clocksource/timer-ti-dm-systimer.c. If more checks
2996 * are needed, we could also look at the timer register configuration.
2997 */
sysc_check_active_timer(struct sysc * ddata)2998 static int sysc_check_active_timer(struct sysc *ddata)
2999 {
3000 if (ddata->cap->type != TI_SYSC_OMAP2_TIMER &&
3001 ddata->cap->type != TI_SYSC_OMAP4_TIMER)
3002 return 0;
3003
3004 if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) &&
3005 (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE))
3006 return -ENXIO;
3007
3008 return 0;
3009 }
3010
3011 static const struct of_device_id sysc_match_table[] = {
3012 { .compatible = "simple-bus", },
3013 { /* sentinel */ },
3014 };
3015
sysc_probe(struct platform_device * pdev)3016 static int sysc_probe(struct platform_device *pdev)
3017 {
3018 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
3019 struct sysc *ddata;
3020 int error;
3021
3022 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
3023 if (!ddata)
3024 return -ENOMEM;
3025
3026 ddata->dev = &pdev->dev;
3027 platform_set_drvdata(pdev, ddata);
3028
3029 error = sysc_init_soc(ddata);
3030 if (error)
3031 return error;
3032
3033 error = sysc_init_match(ddata);
3034 if (error)
3035 return error;
3036
3037 error = sysc_init_dts_quirks(ddata);
3038 if (error)
3039 return error;
3040
3041 error = sysc_map_and_check_registers(ddata);
3042 if (error)
3043 return error;
3044
3045 error = sysc_init_sysc_mask(ddata);
3046 if (error)
3047 return error;
3048
3049 error = sysc_init_idlemodes(ddata);
3050 if (error)
3051 return error;
3052
3053 error = sysc_init_syss_mask(ddata);
3054 if (error)
3055 return error;
3056
3057 error = sysc_init_pdata(ddata);
3058 if (error)
3059 return error;
3060
3061 sysc_init_early_quirks(ddata);
3062
3063 error = sysc_check_disabled_devices(ddata);
3064 if (error)
3065 return error;
3066
3067 error = sysc_check_active_timer(ddata);
3068 if (error == -ENXIO)
3069 ddata->reserved = true;
3070 else if (error)
3071 return error;
3072
3073 error = sysc_get_clocks(ddata);
3074 if (error)
3075 return error;
3076
3077 error = sysc_init_resets(ddata);
3078 if (error)
3079 goto unprepare;
3080
3081 error = sysc_init_module(ddata);
3082 if (error)
3083 goto unprepare;
3084
3085 pm_runtime_enable(ddata->dev);
3086 error = pm_runtime_get_sync(ddata->dev);
3087 if (error < 0) {
3088 pm_runtime_put_noidle(ddata->dev);
3089 pm_runtime_disable(ddata->dev);
3090 goto unprepare;
3091 }
3092
3093 /* Balance use counts as PM runtime should have enabled these all */
3094 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
3095 reset_control_assert(ddata->rsts);
3096
3097 if (!(ddata->cfg.quirks &
3098 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) {
3099 sysc_disable_main_clocks(ddata);
3100 sysc_disable_opt_clocks(ddata);
3101 sysc_clkdm_allow_idle(ddata);
3102 }
3103
3104 sysc_show_registers(ddata);
3105
3106 ddata->dev->type = &sysc_device_type;
3107
3108 if (!ddata->reserved) {
3109 error = of_platform_populate(ddata->dev->of_node,
3110 sysc_match_table,
3111 pdata ? pdata->auxdata : NULL,
3112 ddata->dev);
3113 if (error)
3114 goto err;
3115 }
3116
3117 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
3118
3119 /* At least earlycon won't survive without deferred idle */
3120 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
3121 SYSC_QUIRK_NO_IDLE_ON_INIT |
3122 SYSC_QUIRK_NO_RESET_ON_INIT)) {
3123 schedule_delayed_work(&ddata->idle_work, 3000);
3124 } else {
3125 pm_runtime_put(&pdev->dev);
3126 }
3127
3128 return 0;
3129
3130 err:
3131 pm_runtime_put_sync(&pdev->dev);
3132 pm_runtime_disable(&pdev->dev);
3133 unprepare:
3134 sysc_unprepare(ddata);
3135
3136 return error;
3137 }
3138
sysc_remove(struct platform_device * pdev)3139 static int sysc_remove(struct platform_device *pdev)
3140 {
3141 struct sysc *ddata = platform_get_drvdata(pdev);
3142 int error;
3143
3144 cancel_delayed_work_sync(&ddata->idle_work);
3145
3146 error = pm_runtime_get_sync(ddata->dev);
3147 if (error < 0) {
3148 pm_runtime_put_noidle(ddata->dev);
3149 pm_runtime_disable(ddata->dev);
3150 goto unprepare;
3151 }
3152
3153 of_platform_depopulate(&pdev->dev);
3154
3155 pm_runtime_put_sync(&pdev->dev);
3156 pm_runtime_disable(&pdev->dev);
3157
3158 if (!reset_control_status(ddata->rsts))
3159 reset_control_assert(ddata->rsts);
3160
3161 unprepare:
3162 sysc_unprepare(ddata);
3163
3164 return 0;
3165 }
3166
3167 static const struct of_device_id sysc_match[] = {
3168 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
3169 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
3170 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
3171 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
3172 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
3173 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
3174 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
3175 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
3176 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
3177 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
3178 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
3179 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
3180 { .compatible = "ti,sysc-usb-host-fs",
3181 .data = &sysc_omap4_usb_host_fs, },
3182 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
3183 { .compatible = "ti,sysc-pruss", .data = &sysc_pruss, },
3184 { },
3185 };
3186 MODULE_DEVICE_TABLE(of, sysc_match);
3187
3188 static struct platform_driver sysc_driver = {
3189 .probe = sysc_probe,
3190 .remove = sysc_remove,
3191 .driver = {
3192 .name = "ti-sysc",
3193 .of_match_table = sysc_match,
3194 .pm = &sysc_pm_ops,
3195 },
3196 };
3197
sysc_init(void)3198 static int __init sysc_init(void)
3199 {
3200 bus_register_notifier(&platform_bus_type, &sysc_nb);
3201
3202 return platform_driver_register(&sysc_driver);
3203 }
3204 module_init(sysc_init);
3205
sysc_exit(void)3206 static void __exit sysc_exit(void)
3207 {
3208 bus_unregister_notifier(&platform_bus_type, &sysc_nb);
3209 platform_driver_unregister(&sysc_driver);
3210 sysc_cleanup_soc();
3211 }
3212 module_exit(sysc_exit);
3213
3214 MODULE_DESCRIPTION("TI sysc interconnect target driver");
3215 MODULE_LICENSE("GPL v2");
3216