1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 Broadcom
4 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
5 * Copyright (C) 2013 Red Hat
6 * Author: Rob Clark <robdclark@gmail.com>
7 */
8
9 /**
10 * DOC: VC4 Falcon HDMI module
11 *
12 * The HDMI core has a state machine and a PHY. On BCM2835, most of
13 * the unit operates off of the HSM clock from CPRMAN. It also
14 * internally uses the PLLH_PIX clock for the PHY.
15 *
16 * HDMI infoframes are kept within a small packet ram, where each
17 * packet can be individually enabled for including in a frame.
18 *
19 * HDMI audio is implemented entirely within the HDMI IP block. A
20 * register in the HDMI encoder takes SPDIF frames from the DMA engine
21 * and transfers them over an internal MAI (multi-channel audio
22 * interconnect) bus to the encoder side for insertion into the video
23 * blank regions.
24 *
25 * The driver's HDMI encoder does not yet support power management.
26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
27 * continuously running, and only the HDMI logic and packet ram are
28 * powered off/on at disable/enable time.
29 *
30 * The driver does not yet support CEC control, though the HDMI
31 * encoder block has CEC support.
32 */
33
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_edid.h>
36 #include <drm/drm_probe_helper.h>
37 #include <drm/drm_simple_kms_helper.h>
38 #include <linux/clk.h>
39 #include <linux/component.h>
40 #include <linux/i2c.h>
41 #include <linux/of_address.h>
42 #include <linux/of_gpio.h>
43 #include <linux/of_platform.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/rational.h>
46 #include <linux/reset.h>
47 #include <sound/dmaengine_pcm.h>
48 #include <sound/pcm_drm_eld.h>
49 #include <sound/pcm_params.h>
50 #include <sound/soc.h>
51 #include "media/cec.h"
52 #include "vc4_drv.h"
53 #include "vc4_hdmi.h"
54 #include "vc4_hdmi_regs.h"
55 #include "vc4_regs.h"
56
57 #define VC5_HDMI_HORZA_HFP_SHIFT 16
58 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16)
59 #define VC5_HDMI_HORZA_VPOS BIT(15)
60 #define VC5_HDMI_HORZA_HPOS BIT(14)
61 #define VC5_HDMI_HORZA_HAP_SHIFT 0
62 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0)
63
64 #define VC5_HDMI_HORZB_HBP_SHIFT 16
65 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16)
66 #define VC5_HDMI_HORZB_HSP_SHIFT 0
67 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0)
68
69 #define VC5_HDMI_VERTA_VSP_SHIFT 24
70 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24)
71 #define VC5_HDMI_VERTA_VFP_SHIFT 16
72 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16)
73 #define VC5_HDMI_VERTA_VAL_SHIFT 0
74 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
75
76 #define VC5_HDMI_VERTB_VSPO_SHIFT 16
77 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
78
79 # define VC4_HD_M_SW_RST BIT(2)
80 # define VC4_HD_M_ENABLE BIT(0)
81
82 #define CEC_CLOCK_FREQ 40000
83 #define VC4_HSM_MID_CLOCK 149985000
84
vc4_hdmi_debugfs_regs(struct seq_file * m,void * unused)85 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
86 {
87 struct drm_info_node *node = (struct drm_info_node *)m->private;
88 struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
89 struct drm_printer p = drm_seq_file_printer(m);
90
91 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
92 drm_print_regset32(&p, &vc4_hdmi->hd_regset);
93
94 return 0;
95 }
96
vc4_hdmi_reset(struct vc4_hdmi * vc4_hdmi)97 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
98 {
99 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
100 udelay(1);
101 HDMI_WRITE(HDMI_M_CTL, 0);
102
103 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
104
105 HDMI_WRITE(HDMI_SW_RESET_CONTROL,
106 VC4_HDMI_SW_RESET_HDMI |
107 VC4_HDMI_SW_RESET_FORMAT_DETECT);
108
109 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
110 }
111
vc5_hdmi_reset(struct vc4_hdmi * vc4_hdmi)112 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
113 {
114 reset_control_reset(vc4_hdmi->reset);
115
116 HDMI_WRITE(HDMI_DVP_CTL, 0);
117
118 HDMI_WRITE(HDMI_CLOCK_STOP,
119 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
120 }
121
122 #ifdef CONFIG_DRM_VC4_HDMI_CEC
vc4_hdmi_cec_update_clk_div(struct vc4_hdmi * vc4_hdmi)123 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
124 {
125 u16 clk_cnt;
126 u32 value;
127
128 value = HDMI_READ(HDMI_CEC_CNTRL_1);
129 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
130
131 /*
132 * Set the clock divider: the hsm_clock rate and this divider
133 * setting will give a 40 kHz CEC clock.
134 */
135 clk_cnt = clk_get_rate(vc4_hdmi->hsm_clock) / CEC_CLOCK_FREQ;
136 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
137 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
138 }
139 #else
vc4_hdmi_cec_update_clk_div(struct vc4_hdmi * vc4_hdmi)140 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
141 #endif
142
143 static enum drm_connector_status
vc4_hdmi_connector_detect(struct drm_connector * connector,bool force)144 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
145 {
146 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
147 bool connected = false;
148
149 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
150
151 if (vc4_hdmi->hpd_gpio) {
152 if (gpio_get_value_cansleep(vc4_hdmi->hpd_gpio) ^
153 vc4_hdmi->hpd_active_low)
154 connected = true;
155 } else if (drm_probe_ddc(vc4_hdmi->ddc)) {
156 connected = true;
157 } else if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) {
158 connected = true;
159 }
160
161 if (connected) {
162 if (connector->status != connector_status_connected) {
163 struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
164
165 if (edid) {
166 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
167 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid);
168 kfree(edid);
169 }
170 }
171
172 pm_runtime_put(&vc4_hdmi->pdev->dev);
173 return connector_status_connected;
174 }
175
176 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
177 pm_runtime_put(&vc4_hdmi->pdev->dev);
178 return connector_status_disconnected;
179 }
180
vc4_hdmi_connector_destroy(struct drm_connector * connector)181 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
182 {
183 drm_connector_unregister(connector);
184 drm_connector_cleanup(connector);
185 }
186
vc4_hdmi_connector_get_modes(struct drm_connector * connector)187 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
188 {
189 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
190 struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
191 int ret = 0;
192 struct edid *edid;
193
194 edid = drm_get_edid(connector, vc4_hdmi->ddc);
195 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
196 if (!edid)
197 return -ENODEV;
198
199 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
200
201 drm_connector_update_edid_property(connector, edid);
202 ret = drm_add_edid_modes(connector, edid);
203 kfree(edid);
204
205 return ret;
206 }
207
vc4_hdmi_connector_reset(struct drm_connector * connector)208 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
209 {
210 drm_atomic_helper_connector_reset(connector);
211 drm_atomic_helper_connector_tv_reset(connector);
212 }
213
214 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
215 .detect = vc4_hdmi_connector_detect,
216 .fill_modes = drm_helper_probe_single_connector_modes,
217 .destroy = vc4_hdmi_connector_destroy,
218 .reset = vc4_hdmi_connector_reset,
219 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
220 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
221 };
222
223 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
224 .get_modes = vc4_hdmi_connector_get_modes,
225 };
226
vc4_hdmi_connector_init(struct drm_device * dev,struct vc4_hdmi * vc4_hdmi)227 static int vc4_hdmi_connector_init(struct drm_device *dev,
228 struct vc4_hdmi *vc4_hdmi)
229 {
230 struct drm_connector *connector = &vc4_hdmi->connector;
231 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
232 int ret;
233
234 drm_connector_init_with_ddc(dev, connector,
235 &vc4_hdmi_connector_funcs,
236 DRM_MODE_CONNECTOR_HDMIA,
237 vc4_hdmi->ddc);
238 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
239
240 /* Create and attach TV margin props to this connector. */
241 ret = drm_mode_create_tv_margin_properties(dev);
242 if (ret)
243 return ret;
244
245 drm_connector_attach_tv_margin_properties(connector);
246
247 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
248 DRM_CONNECTOR_POLL_DISCONNECT);
249
250 connector->interlace_allowed = 1;
251 connector->doublescan_allowed = 0;
252
253 drm_connector_attach_encoder(connector, encoder);
254
255 return 0;
256 }
257
vc4_hdmi_stop_packet(struct drm_encoder * encoder,enum hdmi_infoframe_type type)258 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
259 enum hdmi_infoframe_type type)
260 {
261 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
262 u32 packet_id = type - 0x80;
263
264 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
265 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
266
267 return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
268 BIT(packet_id)), 100);
269 }
270
vc4_hdmi_write_infoframe(struct drm_encoder * encoder,union hdmi_infoframe * frame)271 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
272 union hdmi_infoframe *frame)
273 {
274 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
275 u32 packet_id = frame->any.type - 0x80;
276 const struct vc4_hdmi_register *ram_packet_start =
277 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
278 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
279 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
280 ram_packet_start->reg);
281 uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
282 ssize_t len, i;
283 int ret;
284
285 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
286 VC4_HDMI_RAM_PACKET_ENABLE),
287 "Packet RAM has to be on to store the packet.");
288
289 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
290 if (len < 0)
291 return;
292
293 ret = vc4_hdmi_stop_packet(encoder, frame->any.type);
294 if (ret) {
295 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
296 return;
297 }
298
299 for (i = 0; i < len; i += 7) {
300 writel(buffer[i + 0] << 0 |
301 buffer[i + 1] << 8 |
302 buffer[i + 2] << 16,
303 base + packet_reg);
304 packet_reg += 4;
305
306 writel(buffer[i + 3] << 0 |
307 buffer[i + 4] << 8 |
308 buffer[i + 5] << 16 |
309 buffer[i + 6] << 24,
310 base + packet_reg);
311 packet_reg += 4;
312 }
313
314 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
315 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
316 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
317 BIT(packet_id)), 100);
318 if (ret)
319 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
320 }
321
vc4_hdmi_set_avi_infoframe(struct drm_encoder * encoder)322 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
323 {
324 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
325 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
326 struct drm_connector *connector = &vc4_hdmi->connector;
327 struct drm_connector_state *cstate = connector->state;
328 struct drm_crtc *crtc = encoder->crtc;
329 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
330 union hdmi_infoframe frame;
331 int ret;
332
333 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
334 connector, mode);
335 if (ret < 0) {
336 DRM_ERROR("couldn't fill AVI infoframe\n");
337 return;
338 }
339
340 drm_hdmi_avi_infoframe_quant_range(&frame.avi,
341 connector, mode,
342 vc4_encoder->limited_rgb_range ?
343 HDMI_QUANTIZATION_RANGE_LIMITED :
344 HDMI_QUANTIZATION_RANGE_FULL);
345
346 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
347
348 vc4_hdmi_write_infoframe(encoder, &frame);
349 }
350
vc4_hdmi_set_spd_infoframe(struct drm_encoder * encoder)351 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
352 {
353 union hdmi_infoframe frame;
354 int ret;
355
356 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
357 if (ret < 0) {
358 DRM_ERROR("couldn't fill SPD infoframe\n");
359 return;
360 }
361
362 frame.spd.sdi = HDMI_SPD_SDI_PC;
363
364 vc4_hdmi_write_infoframe(encoder, &frame);
365 }
366
vc4_hdmi_set_audio_infoframe(struct drm_encoder * encoder)367 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
368 {
369 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
370 union hdmi_infoframe frame;
371 int ret;
372
373 ret = hdmi_audio_infoframe_init(&frame.audio);
374
375 frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
376 frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
377 frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
378 frame.audio.channels = vc4_hdmi->audio.channels;
379
380 vc4_hdmi_write_infoframe(encoder, &frame);
381 }
382
vc4_hdmi_set_infoframes(struct drm_encoder * encoder)383 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
384 {
385 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
386
387 vc4_hdmi_set_avi_infoframe(encoder);
388 vc4_hdmi_set_spd_infoframe(encoder);
389 /*
390 * If audio was streaming, then we need to reenabled the audio
391 * infoframe here during encoder_enable.
392 */
393 if (vc4_hdmi->audio.streaming)
394 vc4_hdmi_set_audio_infoframe(encoder);
395 }
396
vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder * encoder)397 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder)
398 {
399 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
400
401 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
402
403 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) |
404 VC4_HD_VID_CTL_CLRRGB | VC4_HD_VID_CTL_CLRSYNC);
405
406 HDMI_WRITE(HDMI_VID_CTL,
407 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
408 }
409
vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder * encoder)410 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder)
411 {
412 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
413 int ret;
414
415 if (vc4_hdmi->variant->phy_disable)
416 vc4_hdmi->variant->phy_disable(vc4_hdmi);
417
418 HDMI_WRITE(HDMI_VID_CTL,
419 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
420
421 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
422 clk_disable_unprepare(vc4_hdmi->pixel_clock);
423
424 ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
425 if (ret < 0)
426 DRM_ERROR("Failed to release power domain: %d\n", ret);
427 }
428
vc4_hdmi_encoder_disable(struct drm_encoder * encoder)429 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
430 {
431 }
432
vc4_hdmi_csc_setup(struct vc4_hdmi * vc4_hdmi,bool enable)433 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
434 {
435 u32 csc_ctl;
436
437 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
438 VC4_HD_CSC_CTL_ORDER);
439
440 if (enable) {
441 /* CEA VICs other than #1 requre limited range RGB
442 * output unless overridden by an AVI infoframe.
443 * Apply a colorspace conversion to squash 0-255 down
444 * to 16-235. The matrix here is:
445 *
446 * [ 0 0 0.8594 16]
447 * [ 0 0.8594 0 16]
448 * [ 0.8594 0 0 16]
449 * [ 0 0 0 1]
450 */
451 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
452 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
453 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
454 VC4_HD_CSC_CTL_MODE);
455
456 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
457 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
458 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
459 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
460 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
461 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
462 }
463
464 /* The RGB order applies even when CSC is disabled. */
465 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
466 }
467
vc5_hdmi_csc_setup(struct vc4_hdmi * vc4_hdmi,bool enable)468 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
469 {
470 u32 csc_ctl;
471
472 csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
473
474 if (enable) {
475 /* CEA VICs other than #1 requre limited range RGB
476 * output unless overridden by an AVI infoframe.
477 * Apply a colorspace conversion to squash 0-255 down
478 * to 16-235. The matrix here is:
479 *
480 * [ 0.8594 0 0 16]
481 * [ 0 0.8594 0 16]
482 * [ 0 0 0.8594 16]
483 * [ 0 0 0 1]
484 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
485 */
486 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80);
487 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000);
488 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000);
489 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000);
490 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
491 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80);
492 } else {
493 /* Still use the matrix for full range, but make it unity.
494 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
495 */
496 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000);
497 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000);
498 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000);
499 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000);
500 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
501 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000);
502 }
503
504 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
505 }
506
vc4_hdmi_set_timings(struct vc4_hdmi * vc4_hdmi,struct drm_display_mode * mode)507 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
508 struct drm_display_mode *mode)
509 {
510 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
511 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
512 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
513 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
514 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
515 VC4_HDMI_VERTA_VSP) |
516 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
517 VC4_HDMI_VERTA_VFP) |
518 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
519 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
520 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
521 VC4_HDMI_VERTB_VBP));
522 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
523 VC4_SET_FIELD(mode->crtc_vtotal -
524 mode->crtc_vsync_end -
525 interlaced,
526 VC4_HDMI_VERTB_VBP));
527
528 HDMI_WRITE(HDMI_HORZA,
529 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
530 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
531 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
532 VC4_HDMI_HORZA_HAP));
533
534 HDMI_WRITE(HDMI_HORZB,
535 VC4_SET_FIELD((mode->htotal -
536 mode->hsync_end) * pixel_rep,
537 VC4_HDMI_HORZB_HBP) |
538 VC4_SET_FIELD((mode->hsync_end -
539 mode->hsync_start) * pixel_rep,
540 VC4_HDMI_HORZB_HSP) |
541 VC4_SET_FIELD((mode->hsync_start -
542 mode->hdisplay) * pixel_rep,
543 VC4_HDMI_HORZB_HFP));
544
545 HDMI_WRITE(HDMI_VERTA0, verta);
546 HDMI_WRITE(HDMI_VERTA1, verta);
547
548 HDMI_WRITE(HDMI_VERTB0, vertb_even);
549 HDMI_WRITE(HDMI_VERTB1, vertb);
550 }
vc5_hdmi_set_timings(struct vc4_hdmi * vc4_hdmi,struct drm_display_mode * mode)551 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
552 struct drm_display_mode *mode)
553 {
554 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
555 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
556 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
557 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
558 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
559 VC5_HDMI_VERTA_VSP) |
560 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
561 VC5_HDMI_VERTA_VFP) |
562 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
563 u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
564 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
565 VC4_HDMI_VERTB_VBP));
566 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
567 VC4_SET_FIELD(mode->crtc_vtotal -
568 mode->crtc_vsync_end -
569 interlaced,
570 VC4_HDMI_VERTB_VBP));
571
572 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
573 HDMI_WRITE(HDMI_HORZA,
574 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
575 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
576 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
577 VC5_HDMI_HORZA_HAP) |
578 VC4_SET_FIELD((mode->hsync_start -
579 mode->hdisplay) * pixel_rep,
580 VC5_HDMI_HORZA_HFP));
581
582 HDMI_WRITE(HDMI_HORZB,
583 VC4_SET_FIELD((mode->htotal -
584 mode->hsync_end) * pixel_rep,
585 VC5_HDMI_HORZB_HBP) |
586 VC4_SET_FIELD((mode->hsync_end -
587 mode->hsync_start) * pixel_rep,
588 VC5_HDMI_HORZB_HSP));
589
590 HDMI_WRITE(HDMI_VERTA0, verta);
591 HDMI_WRITE(HDMI_VERTA1, verta);
592
593 HDMI_WRITE(HDMI_VERTB0, vertb_even);
594 HDMI_WRITE(HDMI_VERTB1, vertb);
595
596 HDMI_WRITE(HDMI_CLOCK_STOP, 0);
597 }
598
vc4_hdmi_recenter_fifo(struct vc4_hdmi * vc4_hdmi)599 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
600 {
601 u32 drift;
602 int ret;
603
604 drift = HDMI_READ(HDMI_FIFO_CTL);
605 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
606
607 HDMI_WRITE(HDMI_FIFO_CTL,
608 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
609 HDMI_WRITE(HDMI_FIFO_CTL,
610 drift | VC4_HDMI_FIFO_CTL_RECENTER);
611 usleep_range(1000, 1100);
612 HDMI_WRITE(HDMI_FIFO_CTL,
613 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
614 HDMI_WRITE(HDMI_FIFO_CTL,
615 drift | VC4_HDMI_FIFO_CTL_RECENTER);
616
617 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
618 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
619 WARN_ONCE(ret, "Timeout waiting for "
620 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
621 }
622
vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder * encoder)623 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder)
624 {
625 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
626 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
627 unsigned long pixel_rate, hsm_rate;
628 int ret;
629
630 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
631 if (ret < 0) {
632 DRM_ERROR("Failed to retain power domain: %d\n", ret);
633 return;
634 }
635
636 pixel_rate = mode->clock * 1000 * ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1);
637 ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
638 if (ret) {
639 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
640 return;
641 }
642
643 ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
644 if (ret) {
645 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
646 return;
647 }
648
649 /*
650 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
651 * be faster than pixel clock, infinitesimally faster, tested in
652 * simulation. Otherwise, exact value is unimportant for HDMI
653 * operation." This conflicts with bcm2835's vc4 documentation, which
654 * states HSM's clock has to be at least 108% of the pixel clock.
655 *
656 * Real life tests reveal that vc4's firmware statement holds up, and
657 * users are able to use pixel clocks closer to HSM's, namely for
658 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
659 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
660 * 162MHz.
661 *
662 * Additionally, the AXI clock needs to be at least 25% of
663 * pixel clock, but HSM ends up being the limiting factor.
664 */
665 hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
666 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
667 if (ret) {
668 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
669 return;
670 }
671
672 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
673
674 /*
675 * FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup
676 * at 300MHz.
677 */
678 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock,
679 (hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000));
680 if (ret) {
681 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
682 clk_disable_unprepare(vc4_hdmi->pixel_clock);
683 return;
684 }
685
686 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
687 if (ret) {
688 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
689 clk_disable_unprepare(vc4_hdmi->pixel_clock);
690 return;
691 }
692
693 if (vc4_hdmi->variant->phy_init)
694 vc4_hdmi->variant->phy_init(vc4_hdmi, mode);
695
696 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
697 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
698 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
699 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
700
701 if (vc4_hdmi->variant->set_timings)
702 vc4_hdmi->variant->set_timings(vc4_hdmi, mode);
703 }
704
vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder * encoder)705 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder)
706 {
707 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
708 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
709 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
710
711 if (vc4_encoder->hdmi_monitor &&
712 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
713 if (vc4_hdmi->variant->csc_setup)
714 vc4_hdmi->variant->csc_setup(vc4_hdmi, true);
715
716 vc4_encoder->limited_rgb_range = true;
717 } else {
718 if (vc4_hdmi->variant->csc_setup)
719 vc4_hdmi->variant->csc_setup(vc4_hdmi, false);
720
721 vc4_encoder->limited_rgb_range = false;
722 }
723
724 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
725 }
726
vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder * encoder)727 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder)
728 {
729 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
730 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
731 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
732 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
733 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
734 int ret;
735
736 HDMI_WRITE(HDMI_VID_CTL,
737 VC4_HD_VID_CTL_ENABLE |
738 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
739 VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
740 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
741 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
742
743 HDMI_WRITE(HDMI_VID_CTL,
744 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
745
746 if (vc4_encoder->hdmi_monitor) {
747 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
748 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
749 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
750
751 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
752 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
753 WARN_ONCE(ret, "Timeout waiting for "
754 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
755 } else {
756 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
757 HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
758 ~(VC4_HDMI_RAM_PACKET_ENABLE));
759 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
760 HDMI_READ(HDMI_SCHEDULER_CONTROL) &
761 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
762
763 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
764 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
765 WARN_ONCE(ret, "Timeout waiting for "
766 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
767 }
768
769 if (vc4_encoder->hdmi_monitor) {
770 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
771 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
772 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
773 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
774 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
775
776 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
777 VC4_HDMI_RAM_PACKET_ENABLE);
778
779 vc4_hdmi_set_infoframes(encoder);
780 }
781
782 vc4_hdmi_recenter_fifo(vc4_hdmi);
783 }
784
vc4_hdmi_encoder_enable(struct drm_encoder * encoder)785 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
786 {
787 }
788
789 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
790 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
791
vc4_hdmi_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)792 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
793 struct drm_crtc_state *crtc_state,
794 struct drm_connector_state *conn_state)
795 {
796 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
797 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
798 unsigned long long pixel_rate = mode->clock * 1000;
799 unsigned long long tmds_rate;
800
801 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
802 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
803 (mode->hsync_end % 2) || (mode->htotal % 2)))
804 return -EINVAL;
805
806 /*
807 * The 1440p@60 pixel rate is in the same range than the first
808 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
809 * bandwidth). Slightly lower the frequency to bring it out of
810 * the WiFi range.
811 */
812 tmds_rate = pixel_rate * 10;
813 if (vc4_hdmi->disable_wifi_frequencies &&
814 (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
815 tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
816 mode->clock = 238560;
817 pixel_rate = mode->clock * 1000;
818 }
819
820 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
821 pixel_rate = pixel_rate * 2;
822
823 if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
824 return -EINVAL;
825
826 return 0;
827 }
828
829 static enum drm_mode_status
vc4_hdmi_encoder_mode_valid(struct drm_encoder * encoder,const struct drm_display_mode * mode)830 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
831 const struct drm_display_mode *mode)
832 {
833 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
834
835 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
836 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
837 (mode->hsync_end % 2) || (mode->htotal % 2)))
838 return MODE_H_ILLEGAL;
839
840 if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
841 return MODE_CLOCK_HIGH;
842
843 return MODE_OK;
844 }
845
846 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
847 .atomic_check = vc4_hdmi_encoder_atomic_check,
848 .mode_valid = vc4_hdmi_encoder_mode_valid,
849 .disable = vc4_hdmi_encoder_disable,
850 .enable = vc4_hdmi_encoder_enable,
851 };
852
vc4_hdmi_channel_map(struct vc4_hdmi * vc4_hdmi,u32 channel_mask)853 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
854 {
855 int i;
856 u32 channel_map = 0;
857
858 for (i = 0; i < 8; i++) {
859 if (channel_mask & BIT(i))
860 channel_map |= i << (3 * i);
861 }
862 return channel_map;
863 }
864
vc5_hdmi_channel_map(struct vc4_hdmi * vc4_hdmi,u32 channel_mask)865 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
866 {
867 int i;
868 u32 channel_map = 0;
869
870 for (i = 0; i < 8; i++) {
871 if (channel_mask & BIT(i))
872 channel_map |= i << (4 * i);
873 }
874 return channel_map;
875 }
876
877 /* HDMI audio codec callbacks */
vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi * vc4_hdmi)878 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi)
879 {
880 u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
881 unsigned long n, m;
882
883 rational_best_approximation(hsm_clock, vc4_hdmi->audio.samplerate,
884 VC4_HD_MAI_SMP_N_MASK >>
885 VC4_HD_MAI_SMP_N_SHIFT,
886 (VC4_HD_MAI_SMP_M_MASK >>
887 VC4_HD_MAI_SMP_M_SHIFT) + 1,
888 &n, &m);
889
890 HDMI_WRITE(HDMI_MAI_SMP,
891 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
892 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
893 }
894
vc4_hdmi_set_n_cts(struct vc4_hdmi * vc4_hdmi)895 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi)
896 {
897 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
898 struct drm_crtc *crtc = encoder->crtc;
899 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
900 u32 samplerate = vc4_hdmi->audio.samplerate;
901 u32 n, cts;
902 u64 tmp;
903
904 n = 128 * samplerate / 1000;
905 tmp = (u64)(mode->clock * 1000) * n;
906 do_div(tmp, 128 * samplerate);
907 cts = tmp;
908
909 HDMI_WRITE(HDMI_CRP_CFG,
910 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
911 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
912
913 /*
914 * We could get slightly more accurate clocks in some cases by
915 * providing a CTS_1 value. The two CTS values are alternated
916 * between based on the period fields
917 */
918 HDMI_WRITE(HDMI_CTS_0, cts);
919 HDMI_WRITE(HDMI_CTS_1, cts);
920 }
921
dai_to_hdmi(struct snd_soc_dai * dai)922 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
923 {
924 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
925
926 return snd_soc_card_get_drvdata(card);
927 }
928
vc4_hdmi_audio_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)929 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream,
930 struct snd_soc_dai *dai)
931 {
932 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
933 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
934 struct drm_connector *connector = &vc4_hdmi->connector;
935 int ret;
936
937 if (vc4_hdmi->audio.substream && vc4_hdmi->audio.substream != substream)
938 return -EINVAL;
939
940 vc4_hdmi->audio.substream = substream;
941
942 /*
943 * If the HDMI encoder hasn't probed, or the encoder is
944 * currently in DVI mode, treat the codec dai as missing.
945 */
946 if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
947 VC4_HDMI_RAM_PACKET_ENABLE))
948 return -ENODEV;
949
950 ret = snd_pcm_hw_constraint_eld(substream->runtime, connector->eld);
951 if (ret)
952 return ret;
953
954 return 0;
955 }
956
vc4_hdmi_audio_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)957 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
958 {
959 return 0;
960 }
961
vc4_hdmi_audio_reset(struct vc4_hdmi * vc4_hdmi)962 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
963 {
964 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
965 struct device *dev = &vc4_hdmi->pdev->dev;
966 int ret;
967
968 vc4_hdmi->audio.streaming = false;
969 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO);
970 if (ret)
971 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
972
973 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
974 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
975 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
976 }
977
vc4_hdmi_audio_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)978 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream,
979 struct snd_soc_dai *dai)
980 {
981 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
982
983 if (substream != vc4_hdmi->audio.substream)
984 return;
985
986 vc4_hdmi_audio_reset(vc4_hdmi);
987
988 vc4_hdmi->audio.substream = NULL;
989 }
990
991 /* HDMI audio codec callbacks */
vc4_hdmi_audio_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)992 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
993 struct snd_pcm_hw_params *params,
994 struct snd_soc_dai *dai)
995 {
996 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
997 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
998 struct device *dev = &vc4_hdmi->pdev->dev;
999 u32 audio_packet_config, channel_mask;
1000 u32 channel_map;
1001
1002 if (substream != vc4_hdmi->audio.substream)
1003 return -EINVAL;
1004
1005 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1006 params_rate(params), params_width(params),
1007 params_channels(params));
1008
1009 vc4_hdmi->audio.channels = params_channels(params);
1010 vc4_hdmi->audio.samplerate = params_rate(params);
1011
1012 HDMI_WRITE(HDMI_MAI_CTL,
1013 VC4_HD_MAI_CTL_RESET |
1014 VC4_HD_MAI_CTL_FLUSH |
1015 VC4_HD_MAI_CTL_DLATE |
1016 VC4_HD_MAI_CTL_ERRORE |
1017 VC4_HD_MAI_CTL_ERRORF);
1018
1019 vc4_hdmi_audio_set_mai_clock(vc4_hdmi);
1020
1021 /* The B frame identifier should match the value used by alsa-lib (8) */
1022 audio_packet_config =
1023 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1024 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1025 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1026
1027 channel_mask = GENMASK(vc4_hdmi->audio.channels - 1, 0);
1028 audio_packet_config |= VC4_SET_FIELD(channel_mask,
1029 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1030
1031 /* Set the MAI threshold. This logic mimics the firmware's. */
1032 if (vc4_hdmi->audio.samplerate > 96000) {
1033 HDMI_WRITE(HDMI_MAI_THR,
1034 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) |
1035 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
1036 } else if (vc4_hdmi->audio.samplerate > 48000) {
1037 HDMI_WRITE(HDMI_MAI_THR,
1038 VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) |
1039 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
1040 } else {
1041 HDMI_WRITE(HDMI_MAI_THR,
1042 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
1043 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
1044 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
1045 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
1046 }
1047
1048 HDMI_WRITE(HDMI_MAI_CONFIG,
1049 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1050 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1051
1052 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1053 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1054 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1055 vc4_hdmi_set_n_cts(vc4_hdmi);
1056
1057 vc4_hdmi_set_audio_infoframe(encoder);
1058
1059 return 0;
1060 }
1061
vc4_hdmi_audio_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)1062 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
1063 struct snd_soc_dai *dai)
1064 {
1065 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1066
1067 switch (cmd) {
1068 case SNDRV_PCM_TRIGGER_START:
1069 vc4_hdmi->audio.streaming = true;
1070
1071 if (vc4_hdmi->variant->phy_rng_enable)
1072 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1073
1074 HDMI_WRITE(HDMI_MAI_CTL,
1075 VC4_SET_FIELD(vc4_hdmi->audio.channels,
1076 VC4_HD_MAI_CTL_CHNUM) |
1077 VC4_HD_MAI_CTL_WHOLSMP |
1078 VC4_HD_MAI_CTL_CHALIGN |
1079 VC4_HD_MAI_CTL_ENABLE);
1080 break;
1081 case SNDRV_PCM_TRIGGER_STOP:
1082 HDMI_WRITE(HDMI_MAI_CTL,
1083 VC4_HD_MAI_CTL_DLATE |
1084 VC4_HD_MAI_CTL_ERRORE |
1085 VC4_HD_MAI_CTL_ERRORF);
1086
1087 if (vc4_hdmi->variant->phy_rng_disable)
1088 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1089
1090 vc4_hdmi->audio.streaming = false;
1091
1092 break;
1093 default:
1094 break;
1095 }
1096
1097 return 0;
1098 }
1099
1100 static inline struct vc4_hdmi *
snd_component_to_hdmi(struct snd_soc_component * component)1101 snd_component_to_hdmi(struct snd_soc_component *component)
1102 {
1103 struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
1104
1105 return snd_soc_card_get_drvdata(card);
1106 }
1107
vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1108 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol,
1109 struct snd_ctl_elem_info *uinfo)
1110 {
1111 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1112 struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);
1113 struct drm_connector *connector = &vc4_hdmi->connector;
1114
1115 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1116 uinfo->count = sizeof(connector->eld);
1117
1118 return 0;
1119 }
1120
vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1121 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol,
1122 struct snd_ctl_elem_value *ucontrol)
1123 {
1124 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1125 struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);
1126 struct drm_connector *connector = &vc4_hdmi->connector;
1127
1128 memcpy(ucontrol->value.bytes.data, connector->eld,
1129 sizeof(connector->eld));
1130
1131 return 0;
1132 }
1133
1134 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = {
1135 {
1136 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1137 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1138 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1139 .name = "ELD",
1140 .info = vc4_hdmi_audio_eld_ctl_info,
1141 .get = vc4_hdmi_audio_eld_ctl_get,
1142 },
1143 };
1144
1145 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = {
1146 SND_SOC_DAPM_OUTPUT("TX"),
1147 };
1148
1149 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = {
1150 { "TX", NULL, "Playback" },
1151 };
1152
1153 static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = {
1154 .name = "vc4-hdmi-codec-dai-component",
1155 .controls = vc4_hdmi_audio_controls,
1156 .num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls),
1157 .dapm_widgets = vc4_hdmi_audio_widgets,
1158 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets),
1159 .dapm_routes = vc4_hdmi_audio_routes,
1160 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes),
1161 .idle_bias_on = 1,
1162 .use_pmdown_time = 1,
1163 .endianness = 1,
1164 .non_legacy_dai_naming = 1,
1165 };
1166
1167 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = {
1168 .startup = vc4_hdmi_audio_startup,
1169 .shutdown = vc4_hdmi_audio_shutdown,
1170 .hw_params = vc4_hdmi_audio_hw_params,
1171 .set_fmt = vc4_hdmi_audio_set_fmt,
1172 .trigger = vc4_hdmi_audio_trigger,
1173 };
1174
1175 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = {
1176 .name = "vc4-hdmi-hifi",
1177 .playback = {
1178 .stream_name = "Playback",
1179 .channels_min = 2,
1180 .channels_max = 8,
1181 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1182 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1183 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1184 SNDRV_PCM_RATE_192000,
1185 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1186 },
1187 };
1188
1189 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1190 .name = "vc4-hdmi-cpu-dai-component",
1191 };
1192
vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai * dai)1193 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1194 {
1195 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1196
1197 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1198
1199 return 0;
1200 }
1201
1202 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1203 .name = "vc4-hdmi-cpu-dai",
1204 .probe = vc4_hdmi_audio_cpu_dai_probe,
1205 .playback = {
1206 .stream_name = "Playback",
1207 .channels_min = 1,
1208 .channels_max = 8,
1209 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1210 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1211 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1212 SNDRV_PCM_RATE_192000,
1213 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1214 },
1215 .ops = &vc4_hdmi_audio_dai_ops,
1216 };
1217
1218 static const struct snd_dmaengine_pcm_config pcm_conf = {
1219 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1220 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1221 };
1222
vc4_hdmi_audio_init(struct vc4_hdmi * vc4_hdmi)1223 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1224 {
1225 const struct vc4_hdmi_register *mai_data =
1226 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1227 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1228 struct snd_soc_card *card = &vc4_hdmi->audio.card;
1229 struct device *dev = &vc4_hdmi->pdev->dev;
1230 const __be32 *addr;
1231 int index;
1232 int ret;
1233
1234 if (!of_find_property(dev->of_node, "dmas", NULL)) {
1235 dev_warn(dev,
1236 "'dmas' DT property is missing, no HDMI audio\n");
1237 return 0;
1238 }
1239
1240 if (mai_data->reg != VC4_HD) {
1241 WARN_ONCE(true, "MAI isn't in the HD block\n");
1242 return -EINVAL;
1243 }
1244
1245 /*
1246 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1247 * the bus address specified in the DT, because the physical address
1248 * (the one returned by platform_get_resource()) is not appropriate
1249 * for DMA transfers.
1250 * This VC/MMU should probably be exposed to avoid this kind of hacks.
1251 */
1252 index = of_property_match_string(dev->of_node, "reg-names", "hd");
1253 /* Before BCM2711, we don't have a named register range */
1254 if (index < 0)
1255 index = 1;
1256
1257 addr = of_get_address(dev->of_node, index, NULL, NULL);
1258
1259 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1260 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1261 vc4_hdmi->audio.dma_data.maxburst = 2;
1262
1263 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1264 if (ret) {
1265 dev_err(dev, "Could not register PCM component: %d\n", ret);
1266 return ret;
1267 }
1268
1269 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1270 &vc4_hdmi_audio_cpu_dai_drv, 1);
1271 if (ret) {
1272 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1273 return ret;
1274 }
1275
1276 /* register component and codec dai */
1277 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv,
1278 &vc4_hdmi_audio_codec_dai_drv, 1);
1279 if (ret) {
1280 dev_err(dev, "Could not register component: %d\n", ret);
1281 return ret;
1282 }
1283
1284 dai_link->cpus = &vc4_hdmi->audio.cpu;
1285 dai_link->codecs = &vc4_hdmi->audio.codec;
1286 dai_link->platforms = &vc4_hdmi->audio.platform;
1287
1288 dai_link->num_cpus = 1;
1289 dai_link->num_codecs = 1;
1290 dai_link->num_platforms = 1;
1291
1292 dai_link->name = "MAI";
1293 dai_link->stream_name = "MAI PCM";
1294 dai_link->codecs->dai_name = vc4_hdmi_audio_codec_dai_drv.name;
1295 dai_link->cpus->dai_name = dev_name(dev);
1296 dai_link->codecs->name = dev_name(dev);
1297 dai_link->platforms->name = dev_name(dev);
1298
1299 card->dai_link = dai_link;
1300 card->num_links = 1;
1301 card->name = vc4_hdmi->variant->card_name;
1302 card->driver_name = "vc4-hdmi";
1303 card->dev = dev;
1304 card->owner = THIS_MODULE;
1305
1306 /*
1307 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1308 * stores a pointer to the snd card object in dev->driver_data. This
1309 * means we cannot use it for something else. The hdmi back-pointer is
1310 * now stored in card->drvdata and should be retrieved with
1311 * snd_soc_card_get_drvdata() if needed.
1312 */
1313 snd_soc_card_set_drvdata(card, vc4_hdmi);
1314 ret = devm_snd_soc_register_card(dev, card);
1315 if (ret)
1316 dev_err(dev, "Could not register sound card: %d\n", ret);
1317
1318 return ret;
1319
1320 }
1321
1322 #ifdef CONFIG_DRM_VC4_HDMI_CEC
vc4_cec_irq_handler_thread(int irq,void * priv)1323 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1324 {
1325 struct vc4_hdmi *vc4_hdmi = priv;
1326
1327 if (vc4_hdmi->cec_irq_was_rx) {
1328 if (vc4_hdmi->cec_rx_msg.len)
1329 cec_received_msg(vc4_hdmi->cec_adap,
1330 &vc4_hdmi->cec_rx_msg);
1331 } else if (vc4_hdmi->cec_tx_ok) {
1332 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1333 0, 0, 0, 0);
1334 } else {
1335 /*
1336 * This CEC implementation makes 1 retry, so if we
1337 * get a NACK, then that means it made 2 attempts.
1338 */
1339 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1340 0, 2, 0, 0);
1341 }
1342 return IRQ_HANDLED;
1343 }
1344
vc4_cec_read_msg(struct vc4_hdmi * vc4_hdmi,u32 cntrl1)1345 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1346 {
1347 struct drm_device *dev = vc4_hdmi->connector.dev;
1348 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1349 unsigned int i;
1350
1351 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1352 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1353
1354 if (msg->len > 16) {
1355 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
1356 return;
1357 }
1358
1359 for (i = 0; i < msg->len; i += 4) {
1360 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
1361
1362 msg->msg[i] = val & 0xff;
1363 msg->msg[i + 1] = (val >> 8) & 0xff;
1364 msg->msg[i + 2] = (val >> 16) & 0xff;
1365 msg->msg[i + 3] = (val >> 24) & 0xff;
1366 }
1367 }
1368
vc4_cec_irq_handler(int irq,void * priv)1369 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1370 {
1371 struct vc4_hdmi *vc4_hdmi = priv;
1372 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
1373 u32 cntrl1, cntrl5;
1374
1375 if (!(stat & VC4_HDMI_CPU_CEC))
1376 return IRQ_NONE;
1377 vc4_hdmi->cec_rx_msg.len = 0;
1378 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1379 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
1380 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1381 if (vc4_hdmi->cec_irq_was_rx) {
1382 vc4_cec_read_msg(vc4_hdmi, cntrl1);
1383 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1384 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1385 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1386 } else {
1387 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1388 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1389 }
1390 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1391 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1392
1393 return IRQ_WAKE_THREAD;
1394 }
1395
vc4_hdmi_cec_adap_enable(struct cec_adapter * adap,bool enable)1396 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1397 {
1398 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1399 /* clock period in microseconds */
1400 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1401 u32 val = HDMI_READ(HDMI_CEC_CNTRL_5);
1402
1403 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1404 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1405 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1406 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1407 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1408
1409 if (enable) {
1410 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1411 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1412 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
1413 HDMI_WRITE(HDMI_CEC_CNTRL_2,
1414 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1415 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1416 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1417 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1418 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1419 HDMI_WRITE(HDMI_CEC_CNTRL_3,
1420 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1421 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1422 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1423 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1424 HDMI_WRITE(HDMI_CEC_CNTRL_4,
1425 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1426 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1427 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1428 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1429
1430 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1431 } else {
1432 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1433 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1434 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1435 }
1436 return 0;
1437 }
1438
vc4_hdmi_cec_adap_log_addr(struct cec_adapter * adap,u8 log_addr)1439 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1440 {
1441 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1442
1443 HDMI_WRITE(HDMI_CEC_CNTRL_1,
1444 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1445 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1446 return 0;
1447 }
1448
vc4_hdmi_cec_adap_transmit(struct cec_adapter * adap,u8 attempts,u32 signal_free_time,struct cec_msg * msg)1449 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1450 u32 signal_free_time, struct cec_msg *msg)
1451 {
1452 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1453 struct drm_device *dev = vc4_hdmi->connector.dev;
1454 u32 val;
1455 unsigned int i;
1456
1457 if (msg->len > 16) {
1458 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
1459 return -ENOMEM;
1460 }
1461
1462 for (i = 0; i < msg->len; i += 4)
1463 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
1464 (msg->msg[i]) |
1465 (msg->msg[i + 1] << 8) |
1466 (msg->msg[i + 2] << 16) |
1467 (msg->msg[i + 3] << 24));
1468
1469 val = HDMI_READ(HDMI_CEC_CNTRL_1);
1470 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1471 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1472 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1473 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1474 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1475
1476 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1477 return 0;
1478 }
1479
1480 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1481 .adap_enable = vc4_hdmi_cec_adap_enable,
1482 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1483 .adap_transmit = vc4_hdmi_cec_adap_transmit,
1484 };
1485
vc4_hdmi_cec_init(struct vc4_hdmi * vc4_hdmi)1486 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1487 {
1488 struct cec_connector_info conn_info;
1489 struct platform_device *pdev = vc4_hdmi->pdev;
1490 u32 value;
1491 int ret;
1492
1493 if (!vc4_hdmi->variant->cec_available)
1494 return 0;
1495
1496 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1497 vc4_hdmi, "vc4",
1498 CEC_CAP_DEFAULTS |
1499 CEC_CAP_CONNECTOR_INFO, 1);
1500 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
1501 if (ret < 0)
1502 return ret;
1503
1504 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
1505 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
1506
1507 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
1508
1509 value = HDMI_READ(HDMI_CEC_CNTRL_1);
1510 /* Set the logical address to Unregistered */
1511 value |= VC4_HDMI_CEC_ADDR_MASK;
1512 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
1513
1514 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1515
1516 ret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0),
1517 vc4_cec_irq_handler,
1518 vc4_cec_irq_handler_thread, 0,
1519 "vc4 hdmi cec", vc4_hdmi);
1520 if (ret)
1521 goto err_delete_cec_adap;
1522
1523 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
1524 if (ret < 0)
1525 goto err_delete_cec_adap;
1526
1527 return 0;
1528
1529 err_delete_cec_adap:
1530 cec_delete_adapter(vc4_hdmi->cec_adap);
1531
1532 return ret;
1533 }
1534
vc4_hdmi_cec_exit(struct vc4_hdmi * vc4_hdmi)1535 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
1536 {
1537 cec_unregister_adapter(vc4_hdmi->cec_adap);
1538 }
1539 #else
vc4_hdmi_cec_init(struct vc4_hdmi * vc4_hdmi)1540 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1541 {
1542 return 0;
1543 }
1544
vc4_hdmi_cec_exit(struct vc4_hdmi * vc4_hdmi)1545 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
1546
1547 #endif
1548
vc4_hdmi_build_regset(struct vc4_hdmi * vc4_hdmi,struct debugfs_regset32 * regset,enum vc4_hdmi_regs reg)1549 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
1550 struct debugfs_regset32 *regset,
1551 enum vc4_hdmi_regs reg)
1552 {
1553 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1554 struct debugfs_reg32 *regs, *new_regs;
1555 unsigned int count = 0;
1556 unsigned int i;
1557
1558 regs = kcalloc(variant->num_registers, sizeof(*regs),
1559 GFP_KERNEL);
1560 if (!regs)
1561 return -ENOMEM;
1562
1563 for (i = 0; i < variant->num_registers; i++) {
1564 const struct vc4_hdmi_register *field = &variant->registers[i];
1565
1566 if (field->reg != reg)
1567 continue;
1568
1569 regs[count].name = field->name;
1570 regs[count].offset = field->offset;
1571 count++;
1572 }
1573
1574 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
1575 if (!new_regs)
1576 return -ENOMEM;
1577
1578 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
1579 regset->regs = new_regs;
1580 regset->nregs = count;
1581
1582 return 0;
1583 }
1584
vc4_hdmi_init_resources(struct vc4_hdmi * vc4_hdmi)1585 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1586 {
1587 struct platform_device *pdev = vc4_hdmi->pdev;
1588 struct device *dev = &pdev->dev;
1589 int ret;
1590
1591 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1592 if (IS_ERR(vc4_hdmi->hdmicore_regs))
1593 return PTR_ERR(vc4_hdmi->hdmicore_regs);
1594
1595 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1596 if (IS_ERR(vc4_hdmi->hd_regs))
1597 return PTR_ERR(vc4_hdmi->hd_regs);
1598
1599 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
1600 if (ret)
1601 return ret;
1602
1603 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
1604 if (ret)
1605 return ret;
1606
1607 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1608 if (IS_ERR(vc4_hdmi->pixel_clock)) {
1609 ret = PTR_ERR(vc4_hdmi->pixel_clock);
1610 if (ret != -EPROBE_DEFER)
1611 DRM_ERROR("Failed to get pixel clock\n");
1612 return ret;
1613 }
1614
1615 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1616 if (IS_ERR(vc4_hdmi->hsm_clock)) {
1617 DRM_ERROR("Failed to get HDMI state machine clock\n");
1618 return PTR_ERR(vc4_hdmi->hsm_clock);
1619 }
1620 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
1621
1622 return 0;
1623 }
1624
vc5_hdmi_init_resources(struct vc4_hdmi * vc4_hdmi)1625 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1626 {
1627 struct platform_device *pdev = vc4_hdmi->pdev;
1628 struct device *dev = &pdev->dev;
1629 struct resource *res;
1630
1631 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
1632 if (!res)
1633 return -ENODEV;
1634
1635 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
1636 resource_size(res));
1637 if (!vc4_hdmi->hdmicore_regs)
1638 return -ENOMEM;
1639
1640 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
1641 if (!res)
1642 return -ENODEV;
1643
1644 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
1645 if (!vc4_hdmi->hd_regs)
1646 return -ENOMEM;
1647
1648 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
1649 if (!res)
1650 return -ENODEV;
1651
1652 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
1653 if (!vc4_hdmi->cec_regs)
1654 return -ENOMEM;
1655
1656 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
1657 if (!res)
1658 return -ENODEV;
1659
1660 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
1661 if (!vc4_hdmi->csc_regs)
1662 return -ENOMEM;
1663
1664 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
1665 if (!res)
1666 return -ENODEV;
1667
1668 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
1669 if (!vc4_hdmi->dvp_regs)
1670 return -ENOMEM;
1671
1672 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
1673 if (!res)
1674 return -ENODEV;
1675
1676 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
1677 if (!vc4_hdmi->phy_regs)
1678 return -ENOMEM;
1679
1680 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
1681 if (!res)
1682 return -ENODEV;
1683
1684 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
1685 if (!vc4_hdmi->ram_regs)
1686 return -ENOMEM;
1687
1688 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
1689 if (!res)
1690 return -ENODEV;
1691
1692 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
1693 if (!vc4_hdmi->rm_regs)
1694 return -ENOMEM;
1695
1696 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1697 if (IS_ERR(vc4_hdmi->hsm_clock)) {
1698 DRM_ERROR("Failed to get HDMI state machine clock\n");
1699 return PTR_ERR(vc4_hdmi->hsm_clock);
1700 }
1701
1702 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
1703 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
1704 DRM_ERROR("Failed to get pixel bvb clock\n");
1705 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
1706 }
1707
1708 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
1709 if (IS_ERR(vc4_hdmi->audio_clock)) {
1710 DRM_ERROR("Failed to get audio clock\n");
1711 return PTR_ERR(vc4_hdmi->audio_clock);
1712 }
1713
1714 vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
1715 if (IS_ERR(vc4_hdmi->reset)) {
1716 DRM_ERROR("Failed to get HDMI reset line\n");
1717 return PTR_ERR(vc4_hdmi->reset);
1718 }
1719
1720 return 0;
1721 }
1722
1723 #ifdef CONFIG_PM
vc4_hdmi_runtime_suspend(struct device * dev)1724 static int vc4_hdmi_runtime_suspend(struct device *dev)
1725 {
1726 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1727
1728 clk_disable_unprepare(vc4_hdmi->hsm_clock);
1729
1730 return 0;
1731 }
1732
vc4_hdmi_runtime_resume(struct device * dev)1733 static int vc4_hdmi_runtime_resume(struct device *dev)
1734 {
1735 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1736 int ret;
1737
1738 ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
1739 if (ret)
1740 return ret;
1741
1742 return 0;
1743 }
1744 #endif
1745
vc4_hdmi_bind(struct device * dev,struct device * master,void * data)1746 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
1747 {
1748 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
1749 struct platform_device *pdev = to_platform_device(dev);
1750 struct drm_device *drm = dev_get_drvdata(master);
1751 struct vc4_hdmi *vc4_hdmi;
1752 struct drm_encoder *encoder;
1753 struct device_node *ddc_node;
1754 u32 value;
1755 int ret;
1756
1757 vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
1758 if (!vc4_hdmi)
1759 return -ENOMEM;
1760
1761 dev_set_drvdata(dev, vc4_hdmi);
1762 encoder = &vc4_hdmi->encoder.base.base;
1763 vc4_hdmi->encoder.base.type = variant->encoder_type;
1764 vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
1765 vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
1766 vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
1767 vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
1768 vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
1769 vc4_hdmi->pdev = pdev;
1770 vc4_hdmi->variant = variant;
1771
1772 ret = variant->init_resources(vc4_hdmi);
1773 if (ret)
1774 return ret;
1775
1776 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
1777 if (!ddc_node) {
1778 DRM_ERROR("Failed to find ddc node in device tree\n");
1779 return -ENODEV;
1780 }
1781
1782 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1783 of_node_put(ddc_node);
1784 if (!vc4_hdmi->ddc) {
1785 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
1786 return -EPROBE_DEFER;
1787 }
1788
1789 /* Only use the GPIO HPD pin if present in the DT, otherwise
1790 * we'll use the HDMI core's register.
1791 */
1792 if (of_find_property(dev->of_node, "hpd-gpios", &value)) {
1793 enum of_gpio_flags hpd_gpio_flags;
1794
1795 vc4_hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
1796 "hpd-gpios", 0,
1797 &hpd_gpio_flags);
1798 if (vc4_hdmi->hpd_gpio < 0) {
1799 ret = vc4_hdmi->hpd_gpio;
1800 goto err_put_ddc;
1801 }
1802
1803 vc4_hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
1804 }
1805
1806 vc4_hdmi->disable_wifi_frequencies =
1807 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
1808
1809 if (vc4_hdmi->variant->reset)
1810 vc4_hdmi->variant->reset(vc4_hdmi);
1811
1812 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
1813 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
1814 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
1815 clk_prepare_enable(vc4_hdmi->pixel_clock);
1816 clk_prepare_enable(vc4_hdmi->hsm_clock);
1817 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1818 }
1819
1820 pm_runtime_enable(dev);
1821
1822 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
1823 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
1824
1825 ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
1826 if (ret)
1827 goto err_destroy_encoder;
1828
1829 ret = vc4_hdmi_cec_init(vc4_hdmi);
1830 if (ret)
1831 goto err_destroy_conn;
1832
1833 ret = vc4_hdmi_audio_init(vc4_hdmi);
1834 if (ret)
1835 goto err_free_cec;
1836
1837 vc4_debugfs_add_file(drm, variant->debugfs_name,
1838 vc4_hdmi_debugfs_regs,
1839 vc4_hdmi);
1840
1841 return 0;
1842
1843 err_free_cec:
1844 vc4_hdmi_cec_exit(vc4_hdmi);
1845 err_destroy_conn:
1846 vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
1847 err_destroy_encoder:
1848 drm_encoder_cleanup(encoder);
1849 pm_runtime_disable(dev);
1850 err_put_ddc:
1851 put_device(&vc4_hdmi->ddc->dev);
1852
1853 return ret;
1854 }
1855
vc4_hdmi_unbind(struct device * dev,struct device * master,void * data)1856 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
1857 void *data)
1858 {
1859 struct vc4_hdmi *vc4_hdmi;
1860
1861 /*
1862 * ASoC makes it a bit hard to retrieve a pointer to the
1863 * vc4_hdmi structure. Registering the card will overwrite our
1864 * device drvdata with a pointer to the snd_soc_card structure,
1865 * which can then be used to retrieve whatever drvdata we want
1866 * to associate.
1867 *
1868 * However, that doesn't fly in the case where we wouldn't
1869 * register an ASoC card (because of an old DT that is missing
1870 * the dmas properties for example), then the card isn't
1871 * registered and the device drvdata wouldn't be set.
1872 *
1873 * We can deal with both cases by making sure a snd_soc_card
1874 * pointer and a vc4_hdmi structure are pointing to the same
1875 * memory address, so we can treat them indistinctly without any
1876 * issue.
1877 */
1878 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
1879 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
1880 vc4_hdmi = dev_get_drvdata(dev);
1881
1882 kfree(vc4_hdmi->hdmi_regset.regs);
1883 kfree(vc4_hdmi->hd_regset.regs);
1884
1885 vc4_hdmi_cec_exit(vc4_hdmi);
1886 vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
1887 drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
1888
1889 pm_runtime_disable(dev);
1890
1891 put_device(&vc4_hdmi->ddc->dev);
1892 }
1893
1894 static const struct component_ops vc4_hdmi_ops = {
1895 .bind = vc4_hdmi_bind,
1896 .unbind = vc4_hdmi_unbind,
1897 };
1898
vc4_hdmi_dev_probe(struct platform_device * pdev)1899 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
1900 {
1901 return component_add(&pdev->dev, &vc4_hdmi_ops);
1902 }
1903
vc4_hdmi_dev_remove(struct platform_device * pdev)1904 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
1905 {
1906 component_del(&pdev->dev, &vc4_hdmi_ops);
1907 return 0;
1908 }
1909
1910 static const struct vc4_hdmi_variant bcm2835_variant = {
1911 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
1912 .debugfs_name = "hdmi_regs",
1913 .card_name = "vc4-hdmi",
1914 .max_pixel_clock = 162000000,
1915 .cec_available = true,
1916 .registers = vc4_hdmi_fields,
1917 .num_registers = ARRAY_SIZE(vc4_hdmi_fields),
1918
1919 .init_resources = vc4_hdmi_init_resources,
1920 .csc_setup = vc4_hdmi_csc_setup,
1921 .reset = vc4_hdmi_reset,
1922 .set_timings = vc4_hdmi_set_timings,
1923 .phy_init = vc4_hdmi_phy_init,
1924 .phy_disable = vc4_hdmi_phy_disable,
1925 .phy_rng_enable = vc4_hdmi_phy_rng_enable,
1926 .phy_rng_disable = vc4_hdmi_phy_rng_disable,
1927 .channel_map = vc4_hdmi_channel_map,
1928 };
1929
1930 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
1931 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
1932 .debugfs_name = "hdmi0_regs",
1933 .card_name = "vc4-hdmi-0",
1934 .max_pixel_clock = 297000000,
1935 .registers = vc5_hdmi_hdmi0_fields,
1936 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
1937 .phy_lane_mapping = {
1938 PHY_LANE_0,
1939 PHY_LANE_1,
1940 PHY_LANE_2,
1941 PHY_LANE_CK,
1942 },
1943 .unsupported_odd_h_timings = true,
1944
1945 .init_resources = vc5_hdmi_init_resources,
1946 .csc_setup = vc5_hdmi_csc_setup,
1947 .reset = vc5_hdmi_reset,
1948 .set_timings = vc5_hdmi_set_timings,
1949 .phy_init = vc5_hdmi_phy_init,
1950 .phy_disable = vc5_hdmi_phy_disable,
1951 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
1952 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
1953 .channel_map = vc5_hdmi_channel_map,
1954 };
1955
1956 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
1957 .encoder_type = VC4_ENCODER_TYPE_HDMI1,
1958 .debugfs_name = "hdmi1_regs",
1959 .card_name = "vc4-hdmi-1",
1960 .max_pixel_clock = 297000000,
1961 .registers = vc5_hdmi_hdmi1_fields,
1962 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
1963 .phy_lane_mapping = {
1964 PHY_LANE_1,
1965 PHY_LANE_0,
1966 PHY_LANE_CK,
1967 PHY_LANE_2,
1968 },
1969 .unsupported_odd_h_timings = true,
1970
1971 .init_resources = vc5_hdmi_init_resources,
1972 .csc_setup = vc5_hdmi_csc_setup,
1973 .reset = vc5_hdmi_reset,
1974 .set_timings = vc5_hdmi_set_timings,
1975 .phy_init = vc5_hdmi_phy_init,
1976 .phy_disable = vc5_hdmi_phy_disable,
1977 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
1978 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
1979 .channel_map = vc5_hdmi_channel_map,
1980 };
1981
1982 static const struct of_device_id vc4_hdmi_dt_match[] = {
1983 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
1984 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
1985 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
1986 {}
1987 };
1988
1989 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
1990 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
1991 vc4_hdmi_runtime_resume,
1992 NULL)
1993 };
1994
1995 struct platform_driver vc4_hdmi_driver = {
1996 .probe = vc4_hdmi_dev_probe,
1997 .remove = vc4_hdmi_dev_remove,
1998 .driver = {
1999 .name = "vc4_hdmi",
2000 .of_match_table = vc4_hdmi_dt_match,
2001 .pm = &vc4_hdmi_pm_ops,
2002 },
2003 };
2004