1 /*
2 * Copyright(c) 2015 - 2020 Intel Corporation.
3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * BSD LICENSE
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 *
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
29 * distribution.
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 */
47
48 #include <linux/pci.h>
49 #include <linux/netdevice.h>
50 #include <linux/vmalloc.h>
51 #include <linux/delay.h>
52 #include <linux/xarray.h>
53 #include <linux/module.h>
54 #include <linux/printk.h>
55 #include <linux/hrtimer.h>
56 #include <linux/bitmap.h>
57 #include <linux/numa.h>
58 #include <rdma/rdma_vt.h>
59
60 #include "hfi.h"
61 #include "device.h"
62 #include "common.h"
63 #include "trace.h"
64 #include "mad.h"
65 #include "sdma.h"
66 #include "debugfs.h"
67 #include "verbs.h"
68 #include "aspm.h"
69 #include "affinity.h"
70 #include "vnic.h"
71 #include "exp_rcv.h"
72 #include "netdev.h"
73
74 #undef pr_fmt
75 #define pr_fmt(fmt) DRIVER_NAME ": " fmt
76
77 /*
78 * min buffers we want to have per context, after driver
79 */
80 #define HFI1_MIN_USER_CTXT_BUFCNT 7
81
82 #define HFI1_MIN_EAGER_BUFFER_SIZE (4 * 1024) /* 4KB */
83 #define HFI1_MAX_EAGER_BUFFER_SIZE (256 * 1024) /* 256KB */
84
85 #define NUM_IB_PORTS 1
86
87 /*
88 * Number of user receive contexts we are configured to use (to allow for more
89 * pio buffers per ctxt, etc.) Zero means use one user context per CPU.
90 */
91 int num_user_contexts = -1;
92 module_param_named(num_user_contexts, num_user_contexts, int, 0444);
93 MODULE_PARM_DESC(
94 num_user_contexts, "Set max number of user contexts to use (default: -1 will use the real (non-HT) CPU count)");
95
96 uint krcvqs[RXE_NUM_DATA_VL];
97 int krcvqsset;
98 module_param_array(krcvqs, uint, &krcvqsset, S_IRUGO);
99 MODULE_PARM_DESC(krcvqs, "Array of the number of non-control kernel receive queues by VL");
100
101 /* computed based on above array */
102 unsigned long n_krcvqs;
103
104 static unsigned hfi1_rcvarr_split = 25;
105 module_param_named(rcvarr_split, hfi1_rcvarr_split, uint, S_IRUGO);
106 MODULE_PARM_DESC(rcvarr_split, "Percent of context's RcvArray entries used for Eager buffers");
107
108 static uint eager_buffer_size = (8 << 20); /* 8MB */
109 module_param(eager_buffer_size, uint, S_IRUGO);
110 MODULE_PARM_DESC(eager_buffer_size, "Size of the eager buffers, default: 8MB");
111
112 static uint rcvhdrcnt = 2048; /* 2x the max eager buffer count */
113 module_param_named(rcvhdrcnt, rcvhdrcnt, uint, S_IRUGO);
114 MODULE_PARM_DESC(rcvhdrcnt, "Receive header queue count (default 2048)");
115
116 static uint hfi1_hdrq_entsize = 32;
117 module_param_named(hdrq_entsize, hfi1_hdrq_entsize, uint, 0444);
118 MODULE_PARM_DESC(hdrq_entsize, "Size of header queue entries: 2 - 8B, 16 - 64B, 32 - 128B (default)");
119
120 unsigned int user_credit_return_threshold = 33; /* default is 33% */
121 module_param(user_credit_return_threshold, uint, S_IRUGO);
122 MODULE_PARM_DESC(user_credit_return_threshold, "Credit return threshold for user send contexts, return when unreturned credits passes this many blocks (in percent of allocated blocks, 0 is off)");
123
124 DEFINE_XARRAY_FLAGS(hfi1_dev_table, XA_FLAGS_ALLOC | XA_FLAGS_LOCK_IRQ);
125
hfi1_create_kctxt(struct hfi1_devdata * dd,struct hfi1_pportdata * ppd)126 static int hfi1_create_kctxt(struct hfi1_devdata *dd,
127 struct hfi1_pportdata *ppd)
128 {
129 struct hfi1_ctxtdata *rcd;
130 int ret;
131
132 /* Control context has to be always 0 */
133 BUILD_BUG_ON(HFI1_CTRL_CTXT != 0);
134
135 ret = hfi1_create_ctxtdata(ppd, dd->node, &rcd);
136 if (ret < 0) {
137 dd_dev_err(dd, "Kernel receive context allocation failed\n");
138 return ret;
139 }
140
141 /*
142 * Set up the kernel context flags here and now because they use
143 * default values for all receive side memories. User contexts will
144 * be handled as they are created.
145 */
146 rcd->flags = HFI1_CAP_KGET(MULTI_PKT_EGR) |
147 HFI1_CAP_KGET(NODROP_RHQ_FULL) |
148 HFI1_CAP_KGET(NODROP_EGR_FULL) |
149 HFI1_CAP_KGET(DMA_RTAIL);
150
151 /* Control context must use DMA_RTAIL */
152 if (rcd->ctxt == HFI1_CTRL_CTXT)
153 rcd->flags |= HFI1_CAP_DMA_RTAIL;
154 rcd->fast_handler = get_dma_rtail_setting(rcd) ?
155 handle_receive_interrupt_dma_rtail :
156 handle_receive_interrupt_nodma_rtail;
157 rcd->slow_handler = handle_receive_interrupt;
158
159 hfi1_set_seq_cnt(rcd, 1);
160
161 rcd->sc = sc_alloc(dd, SC_ACK, rcd->rcvhdrqentsize, dd->node);
162 if (!rcd->sc) {
163 dd_dev_err(dd, "Kernel send context allocation failed\n");
164 return -ENOMEM;
165 }
166 hfi1_init_ctxt(rcd->sc);
167
168 return 0;
169 }
170
171 /*
172 * Create the receive context array and one or more kernel contexts
173 */
hfi1_create_kctxts(struct hfi1_devdata * dd)174 int hfi1_create_kctxts(struct hfi1_devdata *dd)
175 {
176 u16 i;
177 int ret;
178
179 dd->rcd = kcalloc_node(dd->num_rcv_contexts, sizeof(*dd->rcd),
180 GFP_KERNEL, dd->node);
181 if (!dd->rcd)
182 return -ENOMEM;
183
184 for (i = 0; i < dd->first_dyn_alloc_ctxt; ++i) {
185 ret = hfi1_create_kctxt(dd, dd->pport);
186 if (ret)
187 goto bail;
188 }
189
190 return 0;
191 bail:
192 for (i = 0; dd->rcd && i < dd->first_dyn_alloc_ctxt; ++i)
193 hfi1_free_ctxt(dd->rcd[i]);
194
195 /* All the contexts should be freed, free the array */
196 kfree(dd->rcd);
197 dd->rcd = NULL;
198 return ret;
199 }
200
201 /*
202 * Helper routines for the receive context reference count (rcd and uctxt).
203 */
hfi1_rcd_init(struct hfi1_ctxtdata * rcd)204 static void hfi1_rcd_init(struct hfi1_ctxtdata *rcd)
205 {
206 kref_init(&rcd->kref);
207 }
208
209 /**
210 * hfi1_rcd_free - When reference is zero clean up.
211 * @kref: pointer to an initialized rcd data structure
212 *
213 */
hfi1_rcd_free(struct kref * kref)214 static void hfi1_rcd_free(struct kref *kref)
215 {
216 unsigned long flags;
217 struct hfi1_ctxtdata *rcd =
218 container_of(kref, struct hfi1_ctxtdata, kref);
219
220 spin_lock_irqsave(&rcd->dd->uctxt_lock, flags);
221 rcd->dd->rcd[rcd->ctxt] = NULL;
222 spin_unlock_irqrestore(&rcd->dd->uctxt_lock, flags);
223
224 hfi1_free_ctxtdata(rcd->dd, rcd);
225
226 kfree(rcd);
227 }
228
229 /**
230 * hfi1_rcd_put - decrement reference for rcd
231 * @rcd: pointer to an initialized rcd data structure
232 *
233 * Use this to put a reference after the init.
234 */
hfi1_rcd_put(struct hfi1_ctxtdata * rcd)235 int hfi1_rcd_put(struct hfi1_ctxtdata *rcd)
236 {
237 if (rcd)
238 return kref_put(&rcd->kref, hfi1_rcd_free);
239
240 return 0;
241 }
242
243 /**
244 * hfi1_rcd_get - increment reference for rcd
245 * @rcd: pointer to an initialized rcd data structure
246 *
247 * Use this to get a reference after the init.
248 *
249 * Return : reflect kref_get_unless_zero(), which returns non-zero on
250 * increment, otherwise 0.
251 */
hfi1_rcd_get(struct hfi1_ctxtdata * rcd)252 int hfi1_rcd_get(struct hfi1_ctxtdata *rcd)
253 {
254 return kref_get_unless_zero(&rcd->kref);
255 }
256
257 /**
258 * allocate_rcd_index - allocate an rcd index from the rcd array
259 * @dd: pointer to a valid devdata structure
260 * @rcd: rcd data structure to assign
261 * @index: pointer to index that is allocated
262 *
263 * Find an empty index in the rcd array, and assign the given rcd to it.
264 * If the array is full, we are EBUSY.
265 *
266 */
allocate_rcd_index(struct hfi1_devdata * dd,struct hfi1_ctxtdata * rcd,u16 * index)267 static int allocate_rcd_index(struct hfi1_devdata *dd,
268 struct hfi1_ctxtdata *rcd, u16 *index)
269 {
270 unsigned long flags;
271 u16 ctxt;
272
273 spin_lock_irqsave(&dd->uctxt_lock, flags);
274 for (ctxt = 0; ctxt < dd->num_rcv_contexts; ctxt++)
275 if (!dd->rcd[ctxt])
276 break;
277
278 if (ctxt < dd->num_rcv_contexts) {
279 rcd->ctxt = ctxt;
280 dd->rcd[ctxt] = rcd;
281 hfi1_rcd_init(rcd);
282 }
283 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
284
285 if (ctxt >= dd->num_rcv_contexts)
286 return -EBUSY;
287
288 *index = ctxt;
289
290 return 0;
291 }
292
293 /**
294 * hfi1_rcd_get_by_index_safe - validate the ctxt index before accessing the
295 * array
296 * @dd: pointer to a valid devdata structure
297 * @ctxt: the index of an possilbe rcd
298 *
299 * This is a wrapper for hfi1_rcd_get_by_index() to validate that the given
300 * ctxt index is valid.
301 *
302 * The caller is responsible for making the _put().
303 *
304 */
hfi1_rcd_get_by_index_safe(struct hfi1_devdata * dd,u16 ctxt)305 struct hfi1_ctxtdata *hfi1_rcd_get_by_index_safe(struct hfi1_devdata *dd,
306 u16 ctxt)
307 {
308 if (ctxt < dd->num_rcv_contexts)
309 return hfi1_rcd_get_by_index(dd, ctxt);
310
311 return NULL;
312 }
313
314 /**
315 * hfi1_rcd_get_by_index
316 * @dd: pointer to a valid devdata structure
317 * @ctxt: the index of an possilbe rcd
318 *
319 * We need to protect access to the rcd array. If access is needed to
320 * one or more index, get the protecting spinlock and then increment the
321 * kref.
322 *
323 * The caller is responsible for making the _put().
324 *
325 */
hfi1_rcd_get_by_index(struct hfi1_devdata * dd,u16 ctxt)326 struct hfi1_ctxtdata *hfi1_rcd_get_by_index(struct hfi1_devdata *dd, u16 ctxt)
327 {
328 unsigned long flags;
329 struct hfi1_ctxtdata *rcd = NULL;
330
331 spin_lock_irqsave(&dd->uctxt_lock, flags);
332 if (dd->rcd[ctxt]) {
333 rcd = dd->rcd[ctxt];
334 if (!hfi1_rcd_get(rcd))
335 rcd = NULL;
336 }
337 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
338
339 return rcd;
340 }
341
342 /*
343 * Common code for user and kernel context create and setup.
344 * NOTE: the initial kref is done here (hf1_rcd_init()).
345 */
hfi1_create_ctxtdata(struct hfi1_pportdata * ppd,int numa,struct hfi1_ctxtdata ** context)346 int hfi1_create_ctxtdata(struct hfi1_pportdata *ppd, int numa,
347 struct hfi1_ctxtdata **context)
348 {
349 struct hfi1_devdata *dd = ppd->dd;
350 struct hfi1_ctxtdata *rcd;
351 unsigned kctxt_ngroups = 0;
352 u32 base;
353
354 if (dd->rcv_entries.nctxt_extra >
355 dd->num_rcv_contexts - dd->first_dyn_alloc_ctxt)
356 kctxt_ngroups = (dd->rcv_entries.nctxt_extra -
357 (dd->num_rcv_contexts - dd->first_dyn_alloc_ctxt));
358 rcd = kzalloc_node(sizeof(*rcd), GFP_KERNEL, numa);
359 if (rcd) {
360 u32 rcvtids, max_entries;
361 u16 ctxt;
362 int ret;
363
364 ret = allocate_rcd_index(dd, rcd, &ctxt);
365 if (ret) {
366 *context = NULL;
367 kfree(rcd);
368 return ret;
369 }
370
371 INIT_LIST_HEAD(&rcd->qp_wait_list);
372 hfi1_exp_tid_group_init(rcd);
373 rcd->ppd = ppd;
374 rcd->dd = dd;
375 rcd->numa_id = numa;
376 rcd->rcv_array_groups = dd->rcv_entries.ngroups;
377 rcd->rhf_rcv_function_map = normal_rhf_rcv_functions;
378 rcd->msix_intr = CCE_NUM_MSIX_VECTORS;
379
380 mutex_init(&rcd->exp_mutex);
381 spin_lock_init(&rcd->exp_lock);
382 INIT_LIST_HEAD(&rcd->flow_queue.queue_head);
383 INIT_LIST_HEAD(&rcd->rarr_queue.queue_head);
384
385 hfi1_cdbg(PROC, "setting up context %u\n", rcd->ctxt);
386
387 /*
388 * Calculate the context's RcvArray entry starting point.
389 * We do this here because we have to take into account all
390 * the RcvArray entries that previous context would have
391 * taken and we have to account for any extra groups assigned
392 * to the static (kernel) or dynamic (vnic/user) contexts.
393 */
394 if (ctxt < dd->first_dyn_alloc_ctxt) {
395 if (ctxt < kctxt_ngroups) {
396 base = ctxt * (dd->rcv_entries.ngroups + 1);
397 rcd->rcv_array_groups++;
398 } else {
399 base = kctxt_ngroups +
400 (ctxt * dd->rcv_entries.ngroups);
401 }
402 } else {
403 u16 ct = ctxt - dd->first_dyn_alloc_ctxt;
404
405 base = ((dd->n_krcv_queues * dd->rcv_entries.ngroups) +
406 kctxt_ngroups);
407 if (ct < dd->rcv_entries.nctxt_extra) {
408 base += ct * (dd->rcv_entries.ngroups + 1);
409 rcd->rcv_array_groups++;
410 } else {
411 base += dd->rcv_entries.nctxt_extra +
412 (ct * dd->rcv_entries.ngroups);
413 }
414 }
415 rcd->eager_base = base * dd->rcv_entries.group_size;
416
417 rcd->rcvhdrq_cnt = rcvhdrcnt;
418 rcd->rcvhdrqentsize = hfi1_hdrq_entsize;
419 rcd->rhf_offset =
420 rcd->rcvhdrqentsize - sizeof(u64) / sizeof(u32);
421 /*
422 * Simple Eager buffer allocation: we have already pre-allocated
423 * the number of RcvArray entry groups. Each ctxtdata structure
424 * holds the number of groups for that context.
425 *
426 * To follow CSR requirements and maintain cacheline alignment,
427 * make sure all sizes and bases are multiples of group_size.
428 *
429 * The expected entry count is what is left after assigning
430 * eager.
431 */
432 max_entries = rcd->rcv_array_groups *
433 dd->rcv_entries.group_size;
434 rcvtids = ((max_entries * hfi1_rcvarr_split) / 100);
435 rcd->egrbufs.count = round_down(rcvtids,
436 dd->rcv_entries.group_size);
437 if (rcd->egrbufs.count > MAX_EAGER_ENTRIES) {
438 dd_dev_err(dd, "ctxt%u: requested too many RcvArray entries.\n",
439 rcd->ctxt);
440 rcd->egrbufs.count = MAX_EAGER_ENTRIES;
441 }
442 hfi1_cdbg(PROC,
443 "ctxt%u: max Eager buffer RcvArray entries: %u\n",
444 rcd->ctxt, rcd->egrbufs.count);
445
446 /*
447 * Allocate array that will hold the eager buffer accounting
448 * data.
449 * This will allocate the maximum possible buffer count based
450 * on the value of the RcvArray split parameter.
451 * The resulting value will be rounded down to the closest
452 * multiple of dd->rcv_entries.group_size.
453 */
454 rcd->egrbufs.buffers =
455 kcalloc_node(rcd->egrbufs.count,
456 sizeof(*rcd->egrbufs.buffers),
457 GFP_KERNEL, numa);
458 if (!rcd->egrbufs.buffers)
459 goto bail;
460 rcd->egrbufs.rcvtids =
461 kcalloc_node(rcd->egrbufs.count,
462 sizeof(*rcd->egrbufs.rcvtids),
463 GFP_KERNEL, numa);
464 if (!rcd->egrbufs.rcvtids)
465 goto bail;
466 rcd->egrbufs.size = eager_buffer_size;
467 /*
468 * The size of the buffers programmed into the RcvArray
469 * entries needs to be big enough to handle the highest
470 * MTU supported.
471 */
472 if (rcd->egrbufs.size < hfi1_max_mtu) {
473 rcd->egrbufs.size = __roundup_pow_of_two(hfi1_max_mtu);
474 hfi1_cdbg(PROC,
475 "ctxt%u: eager bufs size too small. Adjusting to %u\n",
476 rcd->ctxt, rcd->egrbufs.size);
477 }
478 rcd->egrbufs.rcvtid_size = HFI1_MAX_EAGER_BUFFER_SIZE;
479
480 /* Applicable only for statically created kernel contexts */
481 if (ctxt < dd->first_dyn_alloc_ctxt) {
482 rcd->opstats = kzalloc_node(sizeof(*rcd->opstats),
483 GFP_KERNEL, numa);
484 if (!rcd->opstats)
485 goto bail;
486
487 /* Initialize TID flow generations for the context */
488 hfi1_kern_init_ctxt_generations(rcd);
489 }
490
491 *context = rcd;
492 return 0;
493 }
494
495 bail:
496 *context = NULL;
497 hfi1_free_ctxt(rcd);
498 return -ENOMEM;
499 }
500
501 /**
502 * hfi1_free_ctxt
503 * @rcd: pointer to an initialized rcd data structure
504 *
505 * This wrapper is the free function that matches hfi1_create_ctxtdata().
506 * When a context is done being used (kernel or user), this function is called
507 * for the "final" put to match the kref init from hf1i_create_ctxtdata().
508 * Other users of the context do a get/put sequence to make sure that the
509 * structure isn't removed while in use.
510 */
hfi1_free_ctxt(struct hfi1_ctxtdata * rcd)511 void hfi1_free_ctxt(struct hfi1_ctxtdata *rcd)
512 {
513 hfi1_rcd_put(rcd);
514 }
515
516 /*
517 * Select the largest ccti value over all SLs to determine the intra-
518 * packet gap for the link.
519 *
520 * called with cca_timer_lock held (to protect access to cca_timer
521 * array), and rcu_read_lock() (to protect access to cc_state).
522 */
set_link_ipg(struct hfi1_pportdata * ppd)523 void set_link_ipg(struct hfi1_pportdata *ppd)
524 {
525 struct hfi1_devdata *dd = ppd->dd;
526 struct cc_state *cc_state;
527 int i;
528 u16 cce, ccti_limit, max_ccti = 0;
529 u16 shift, mult;
530 u64 src;
531 u32 current_egress_rate; /* Mbits /sec */
532 u32 max_pkt_time;
533 /*
534 * max_pkt_time is the maximum packet egress time in units
535 * of the fabric clock period 1/(805 MHz).
536 */
537
538 cc_state = get_cc_state(ppd);
539
540 if (!cc_state)
541 /*
542 * This should _never_ happen - rcu_read_lock() is held,
543 * and set_link_ipg() should not be called if cc_state
544 * is NULL.
545 */
546 return;
547
548 for (i = 0; i < OPA_MAX_SLS; i++) {
549 u16 ccti = ppd->cca_timer[i].ccti;
550
551 if (ccti > max_ccti)
552 max_ccti = ccti;
553 }
554
555 ccti_limit = cc_state->cct.ccti_limit;
556 if (max_ccti > ccti_limit)
557 max_ccti = ccti_limit;
558
559 cce = cc_state->cct.entries[max_ccti].entry;
560 shift = (cce & 0xc000) >> 14;
561 mult = (cce & 0x3fff);
562
563 current_egress_rate = active_egress_rate(ppd);
564
565 max_pkt_time = egress_cycles(ppd->ibmaxlen, current_egress_rate);
566
567 src = (max_pkt_time >> shift) * mult;
568
569 src &= SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SMASK;
570 src <<= SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SHIFT;
571
572 write_csr(dd, SEND_STATIC_RATE_CONTROL, src);
573 }
574
cca_timer_fn(struct hrtimer * t)575 static enum hrtimer_restart cca_timer_fn(struct hrtimer *t)
576 {
577 struct cca_timer *cca_timer;
578 struct hfi1_pportdata *ppd;
579 int sl;
580 u16 ccti_timer, ccti_min;
581 struct cc_state *cc_state;
582 unsigned long flags;
583 enum hrtimer_restart ret = HRTIMER_NORESTART;
584
585 cca_timer = container_of(t, struct cca_timer, hrtimer);
586 ppd = cca_timer->ppd;
587 sl = cca_timer->sl;
588
589 rcu_read_lock();
590
591 cc_state = get_cc_state(ppd);
592
593 if (!cc_state) {
594 rcu_read_unlock();
595 return HRTIMER_NORESTART;
596 }
597
598 /*
599 * 1) decrement ccti for SL
600 * 2) calculate IPG for link (set_link_ipg())
601 * 3) restart timer, unless ccti is at min value
602 */
603
604 ccti_min = cc_state->cong_setting.entries[sl].ccti_min;
605 ccti_timer = cc_state->cong_setting.entries[sl].ccti_timer;
606
607 spin_lock_irqsave(&ppd->cca_timer_lock, flags);
608
609 if (cca_timer->ccti > ccti_min) {
610 cca_timer->ccti--;
611 set_link_ipg(ppd);
612 }
613
614 if (cca_timer->ccti > ccti_min) {
615 unsigned long nsec = 1024 * ccti_timer;
616 /* ccti_timer is in units of 1.024 usec */
617 hrtimer_forward_now(t, ns_to_ktime(nsec));
618 ret = HRTIMER_RESTART;
619 }
620
621 spin_unlock_irqrestore(&ppd->cca_timer_lock, flags);
622 rcu_read_unlock();
623 return ret;
624 }
625
626 /*
627 * Common code for initializing the physical port structure.
628 */
hfi1_init_pportdata(struct pci_dev * pdev,struct hfi1_pportdata * ppd,struct hfi1_devdata * dd,u8 hw_pidx,u8 port)629 void hfi1_init_pportdata(struct pci_dev *pdev, struct hfi1_pportdata *ppd,
630 struct hfi1_devdata *dd, u8 hw_pidx, u8 port)
631 {
632 int i;
633 uint default_pkey_idx;
634 struct cc_state *cc_state;
635
636 ppd->dd = dd;
637 ppd->hw_pidx = hw_pidx;
638 ppd->port = port; /* IB port number, not index */
639 ppd->prev_link_width = LINK_WIDTH_DEFAULT;
640 /*
641 * There are C_VL_COUNT number of PortVLXmitWait counters.
642 * Adding 1 to C_VL_COUNT to include the PortXmitWait counter.
643 */
644 for (i = 0; i < C_VL_COUNT + 1; i++) {
645 ppd->port_vl_xmit_wait_last[i] = 0;
646 ppd->vl_xmit_flit_cnt[i] = 0;
647 }
648
649 default_pkey_idx = 1;
650
651 ppd->pkeys[default_pkey_idx] = DEFAULT_P_KEY;
652 ppd->part_enforce |= HFI1_PART_ENFORCE_IN;
653 ppd->pkeys[0] = 0x8001;
654
655 INIT_WORK(&ppd->link_vc_work, handle_verify_cap);
656 INIT_WORK(&ppd->link_up_work, handle_link_up);
657 INIT_WORK(&ppd->link_down_work, handle_link_down);
658 INIT_WORK(&ppd->freeze_work, handle_freeze);
659 INIT_WORK(&ppd->link_downgrade_work, handle_link_downgrade);
660 INIT_WORK(&ppd->sma_message_work, handle_sma_message);
661 INIT_WORK(&ppd->link_bounce_work, handle_link_bounce);
662 INIT_DELAYED_WORK(&ppd->start_link_work, handle_start_link);
663 INIT_WORK(&ppd->linkstate_active_work, receive_interrupt_work);
664 INIT_WORK(&ppd->qsfp_info.qsfp_work, qsfp_event);
665
666 mutex_init(&ppd->hls_lock);
667 spin_lock_init(&ppd->qsfp_info.qsfp_lock);
668
669 ppd->qsfp_info.ppd = ppd;
670 ppd->sm_trap_qp = 0x0;
671 ppd->sa_qp = 0x1;
672
673 ppd->hfi1_wq = NULL;
674
675 spin_lock_init(&ppd->cca_timer_lock);
676
677 for (i = 0; i < OPA_MAX_SLS; i++) {
678 hrtimer_init(&ppd->cca_timer[i].hrtimer, CLOCK_MONOTONIC,
679 HRTIMER_MODE_REL);
680 ppd->cca_timer[i].ppd = ppd;
681 ppd->cca_timer[i].sl = i;
682 ppd->cca_timer[i].ccti = 0;
683 ppd->cca_timer[i].hrtimer.function = cca_timer_fn;
684 }
685
686 ppd->cc_max_table_entries = IB_CC_TABLE_CAP_DEFAULT;
687
688 spin_lock_init(&ppd->cc_state_lock);
689 spin_lock_init(&ppd->cc_log_lock);
690 cc_state = kzalloc(sizeof(*cc_state), GFP_KERNEL);
691 RCU_INIT_POINTER(ppd->cc_state, cc_state);
692 if (!cc_state)
693 goto bail;
694 return;
695
696 bail:
697 dd_dev_err(dd, "Congestion Control Agent disabled for port %d\n", port);
698 }
699
700 /*
701 * Do initialization for device that is only needed on
702 * first detect, not on resets.
703 */
loadtime_init(struct hfi1_devdata * dd)704 static int loadtime_init(struct hfi1_devdata *dd)
705 {
706 return 0;
707 }
708
709 /**
710 * init_after_reset - re-initialize after a reset
711 * @dd: the hfi1_ib device
712 *
713 * sanity check at least some of the values after reset, and
714 * ensure no receive or transmit (explicitly, in case reset
715 * failed
716 */
init_after_reset(struct hfi1_devdata * dd)717 static int init_after_reset(struct hfi1_devdata *dd)
718 {
719 int i;
720 struct hfi1_ctxtdata *rcd;
721 /*
722 * Ensure chip does no sends or receives, tail updates, or
723 * pioavail updates while we re-initialize. This is mostly
724 * for the driver data structures, not chip registers.
725 */
726 for (i = 0; i < dd->num_rcv_contexts; i++) {
727 rcd = hfi1_rcd_get_by_index(dd, i);
728 hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_DIS |
729 HFI1_RCVCTRL_INTRAVAIL_DIS |
730 HFI1_RCVCTRL_TAILUPD_DIS, rcd);
731 hfi1_rcd_put(rcd);
732 }
733 pio_send_control(dd, PSC_GLOBAL_DISABLE);
734 for (i = 0; i < dd->num_send_contexts; i++)
735 sc_disable(dd->send_contexts[i].sc);
736
737 return 0;
738 }
739
enable_chip(struct hfi1_devdata * dd)740 static void enable_chip(struct hfi1_devdata *dd)
741 {
742 struct hfi1_ctxtdata *rcd;
743 u32 rcvmask;
744 u16 i;
745
746 /* enable PIO send */
747 pio_send_control(dd, PSC_GLOBAL_ENABLE);
748
749 /*
750 * Enable kernel ctxts' receive and receive interrupt.
751 * Other ctxts done as user opens and initializes them.
752 */
753 for (i = 0; i < dd->first_dyn_alloc_ctxt; ++i) {
754 rcd = hfi1_rcd_get_by_index(dd, i);
755 if (!rcd)
756 continue;
757 rcvmask = HFI1_RCVCTRL_CTXT_ENB | HFI1_RCVCTRL_INTRAVAIL_ENB;
758 rcvmask |= HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL) ?
759 HFI1_RCVCTRL_TAILUPD_ENB : HFI1_RCVCTRL_TAILUPD_DIS;
760 if (!HFI1_CAP_KGET_MASK(rcd->flags, MULTI_PKT_EGR))
761 rcvmask |= HFI1_RCVCTRL_ONE_PKT_EGR_ENB;
762 if (HFI1_CAP_KGET_MASK(rcd->flags, NODROP_RHQ_FULL))
763 rcvmask |= HFI1_RCVCTRL_NO_RHQ_DROP_ENB;
764 if (HFI1_CAP_KGET_MASK(rcd->flags, NODROP_EGR_FULL))
765 rcvmask |= HFI1_RCVCTRL_NO_EGR_DROP_ENB;
766 if (HFI1_CAP_IS_KSET(TID_RDMA))
767 rcvmask |= HFI1_RCVCTRL_TIDFLOW_ENB;
768 hfi1_rcvctrl(dd, rcvmask, rcd);
769 sc_enable(rcd->sc);
770 hfi1_rcd_put(rcd);
771 }
772 }
773
774 /**
775 * create_workqueues - create per port workqueues
776 * @dd: the hfi1_ib device
777 */
create_workqueues(struct hfi1_devdata * dd)778 static int create_workqueues(struct hfi1_devdata *dd)
779 {
780 int pidx;
781 struct hfi1_pportdata *ppd;
782
783 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
784 ppd = dd->pport + pidx;
785 if (!ppd->hfi1_wq) {
786 ppd->hfi1_wq =
787 alloc_workqueue(
788 "hfi%d_%d",
789 WQ_SYSFS | WQ_HIGHPRI | WQ_CPU_INTENSIVE |
790 WQ_MEM_RECLAIM,
791 HFI1_MAX_ACTIVE_WORKQUEUE_ENTRIES,
792 dd->unit, pidx);
793 if (!ppd->hfi1_wq)
794 goto wq_error;
795 }
796 if (!ppd->link_wq) {
797 /*
798 * Make the link workqueue single-threaded to enforce
799 * serialization.
800 */
801 ppd->link_wq =
802 alloc_workqueue(
803 "hfi_link_%d_%d",
804 WQ_SYSFS | WQ_MEM_RECLAIM | WQ_UNBOUND,
805 1, /* max_active */
806 dd->unit, pidx);
807 if (!ppd->link_wq)
808 goto wq_error;
809 }
810 }
811 return 0;
812 wq_error:
813 pr_err("alloc_workqueue failed for port %d\n", pidx + 1);
814 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
815 ppd = dd->pport + pidx;
816 if (ppd->hfi1_wq) {
817 destroy_workqueue(ppd->hfi1_wq);
818 ppd->hfi1_wq = NULL;
819 }
820 if (ppd->link_wq) {
821 destroy_workqueue(ppd->link_wq);
822 ppd->link_wq = NULL;
823 }
824 }
825 return -ENOMEM;
826 }
827
828 /**
829 * destroy_workqueues - destroy per port workqueues
830 * @dd: the hfi1_ib device
831 */
destroy_workqueues(struct hfi1_devdata * dd)832 static void destroy_workqueues(struct hfi1_devdata *dd)
833 {
834 int pidx;
835 struct hfi1_pportdata *ppd;
836
837 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
838 ppd = dd->pport + pidx;
839
840 if (ppd->hfi1_wq) {
841 destroy_workqueue(ppd->hfi1_wq);
842 ppd->hfi1_wq = NULL;
843 }
844 if (ppd->link_wq) {
845 destroy_workqueue(ppd->link_wq);
846 ppd->link_wq = NULL;
847 }
848 }
849 }
850
851 /**
852 * enable_general_intr() - Enable the IRQs that will be handled by the
853 * general interrupt handler.
854 * @dd: valid devdata
855 *
856 */
enable_general_intr(struct hfi1_devdata * dd)857 static void enable_general_intr(struct hfi1_devdata *dd)
858 {
859 set_intr_bits(dd, CCE_ERR_INT, MISC_ERR_INT, true);
860 set_intr_bits(dd, PIO_ERR_INT, TXE_ERR_INT, true);
861 set_intr_bits(dd, IS_SENDCTXT_ERR_START, IS_SENDCTXT_ERR_END, true);
862 set_intr_bits(dd, PBC_INT, GPIO_ASSERT_INT, true);
863 set_intr_bits(dd, TCRIT_INT, TCRIT_INT, true);
864 set_intr_bits(dd, IS_DC_START, IS_DC_END, true);
865 set_intr_bits(dd, IS_SENDCREDIT_START, IS_SENDCREDIT_END, true);
866 }
867
868 /**
869 * hfi1_init - do the actual initialization sequence on the chip
870 * @dd: the hfi1_ib device
871 * @reinit: re-initializing, so don't allocate new memory
872 *
873 * Do the actual initialization sequence on the chip. This is done
874 * both from the init routine called from the PCI infrastructure, and
875 * when we reset the chip, or detect that it was reset internally,
876 * or it's administratively re-enabled.
877 *
878 * Memory allocation here and in called routines is only done in
879 * the first case (reinit == 0). We have to be careful, because even
880 * without memory allocation, we need to re-write all the chip registers
881 * TIDs, etc. after the reset or enable has completed.
882 */
hfi1_init(struct hfi1_devdata * dd,int reinit)883 int hfi1_init(struct hfi1_devdata *dd, int reinit)
884 {
885 int ret = 0, pidx, lastfail = 0;
886 unsigned long len;
887 u16 i;
888 struct hfi1_ctxtdata *rcd;
889 struct hfi1_pportdata *ppd;
890
891 /* Set up send low level handlers */
892 dd->process_pio_send = hfi1_verbs_send_pio;
893 dd->process_dma_send = hfi1_verbs_send_dma;
894 dd->pio_inline_send = pio_copy;
895 dd->process_vnic_dma_send = hfi1_vnic_send_dma;
896
897 if (is_ax(dd)) {
898 atomic_set(&dd->drop_packet, DROP_PACKET_ON);
899 dd->do_drop = true;
900 } else {
901 atomic_set(&dd->drop_packet, DROP_PACKET_OFF);
902 dd->do_drop = false;
903 }
904
905 /* make sure the link is not "up" */
906 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
907 ppd = dd->pport + pidx;
908 ppd->linkup = 0;
909 }
910
911 if (reinit)
912 ret = init_after_reset(dd);
913 else
914 ret = loadtime_init(dd);
915 if (ret)
916 goto done;
917
918 /* allocate dummy tail memory for all receive contexts */
919 dd->rcvhdrtail_dummy_kvaddr = dma_alloc_coherent(&dd->pcidev->dev,
920 sizeof(u64),
921 &dd->rcvhdrtail_dummy_dma,
922 GFP_KERNEL);
923
924 if (!dd->rcvhdrtail_dummy_kvaddr) {
925 dd_dev_err(dd, "cannot allocate dummy tail memory\n");
926 ret = -ENOMEM;
927 goto done;
928 }
929
930 /* dd->rcd can be NULL if early initialization failed */
931 for (i = 0; dd->rcd && i < dd->first_dyn_alloc_ctxt; ++i) {
932 /*
933 * Set up the (kernel) rcvhdr queue and egr TIDs. If doing
934 * re-init, the simplest way to handle this is to free
935 * existing, and re-allocate.
936 * Need to re-create rest of ctxt 0 ctxtdata as well.
937 */
938 rcd = hfi1_rcd_get_by_index(dd, i);
939 if (!rcd)
940 continue;
941
942 rcd->do_interrupt = &handle_receive_interrupt;
943
944 lastfail = hfi1_create_rcvhdrq(dd, rcd);
945 if (!lastfail)
946 lastfail = hfi1_setup_eagerbufs(rcd);
947 if (!lastfail)
948 lastfail = hfi1_kern_exp_rcv_init(rcd, reinit);
949 if (lastfail) {
950 dd_dev_err(dd,
951 "failed to allocate kernel ctxt's rcvhdrq and/or egr bufs\n");
952 ret = lastfail;
953 }
954 /* enable IRQ */
955 hfi1_rcd_put(rcd);
956 }
957
958 /* Allocate enough memory for user event notification. */
959 len = PAGE_ALIGN(chip_rcv_contexts(dd) * HFI1_MAX_SHARED_CTXTS *
960 sizeof(*dd->events));
961 dd->events = vmalloc_user(len);
962 if (!dd->events)
963 dd_dev_err(dd, "Failed to allocate user events page\n");
964 /*
965 * Allocate a page for device and port status.
966 * Page will be shared amongst all user processes.
967 */
968 dd->status = vmalloc_user(PAGE_SIZE);
969 if (!dd->status)
970 dd_dev_err(dd, "Failed to allocate dev status page\n");
971 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
972 ppd = dd->pport + pidx;
973 if (dd->status)
974 /* Currently, we only have one port */
975 ppd->statusp = &dd->status->port;
976
977 set_mtu(ppd);
978 }
979
980 /* enable chip even if we have an error, so we can debug cause */
981 enable_chip(dd);
982
983 done:
984 /*
985 * Set status even if port serdes is not initialized
986 * so that diags will work.
987 */
988 if (dd->status)
989 dd->status->dev |= HFI1_STATUS_CHIP_PRESENT |
990 HFI1_STATUS_INITTED;
991 if (!ret) {
992 /* enable all interrupts from the chip */
993 enable_general_intr(dd);
994 init_qsfp_int(dd);
995
996 /* chip is OK for user apps; mark it as initialized */
997 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
998 ppd = dd->pport + pidx;
999
1000 /*
1001 * start the serdes - must be after interrupts are
1002 * enabled so we are notified when the link goes up
1003 */
1004 lastfail = bringup_serdes(ppd);
1005 if (lastfail)
1006 dd_dev_info(dd,
1007 "Failed to bring up port %u\n",
1008 ppd->port);
1009
1010 /*
1011 * Set status even if port serdes is not initialized
1012 * so that diags will work.
1013 */
1014 if (ppd->statusp)
1015 *ppd->statusp |= HFI1_STATUS_CHIP_PRESENT |
1016 HFI1_STATUS_INITTED;
1017 if (!ppd->link_speed_enabled)
1018 continue;
1019 }
1020 }
1021
1022 /* if ret is non-zero, we probably should do some cleanup here... */
1023 return ret;
1024 }
1025
hfi1_lookup(int unit)1026 struct hfi1_devdata *hfi1_lookup(int unit)
1027 {
1028 return xa_load(&hfi1_dev_table, unit);
1029 }
1030
1031 /*
1032 * Stop the timers during unit shutdown, or after an error late
1033 * in initialization.
1034 */
stop_timers(struct hfi1_devdata * dd)1035 static void stop_timers(struct hfi1_devdata *dd)
1036 {
1037 struct hfi1_pportdata *ppd;
1038 int pidx;
1039
1040 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1041 ppd = dd->pport + pidx;
1042 if (ppd->led_override_timer.function) {
1043 del_timer_sync(&ppd->led_override_timer);
1044 atomic_set(&ppd->led_override_timer_active, 0);
1045 }
1046 }
1047 }
1048
1049 /**
1050 * shutdown_device - shut down a device
1051 * @dd: the hfi1_ib device
1052 *
1053 * This is called to make the device quiet when we are about to
1054 * unload the driver, and also when the device is administratively
1055 * disabled. It does not free any data structures.
1056 * Everything it does has to be setup again by hfi1_init(dd, 1)
1057 */
shutdown_device(struct hfi1_devdata * dd)1058 static void shutdown_device(struct hfi1_devdata *dd)
1059 {
1060 struct hfi1_pportdata *ppd;
1061 struct hfi1_ctxtdata *rcd;
1062 unsigned pidx;
1063 int i;
1064
1065 if (dd->flags & HFI1_SHUTDOWN)
1066 return;
1067 dd->flags |= HFI1_SHUTDOWN;
1068
1069 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1070 ppd = dd->pport + pidx;
1071
1072 ppd->linkup = 0;
1073 if (ppd->statusp)
1074 *ppd->statusp &= ~(HFI1_STATUS_IB_CONF |
1075 HFI1_STATUS_IB_READY);
1076 }
1077 dd->flags &= ~HFI1_INITTED;
1078
1079 /* mask and clean up interrupts */
1080 set_intr_bits(dd, IS_FIRST_SOURCE, IS_LAST_SOURCE, false);
1081 msix_clean_up_interrupts(dd);
1082
1083 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1084 ppd = dd->pport + pidx;
1085 for (i = 0; i < dd->num_rcv_contexts; i++) {
1086 rcd = hfi1_rcd_get_by_index(dd, i);
1087 hfi1_rcvctrl(dd, HFI1_RCVCTRL_TAILUPD_DIS |
1088 HFI1_RCVCTRL_CTXT_DIS |
1089 HFI1_RCVCTRL_INTRAVAIL_DIS |
1090 HFI1_RCVCTRL_PKEY_DIS |
1091 HFI1_RCVCTRL_ONE_PKT_EGR_DIS, rcd);
1092 hfi1_rcd_put(rcd);
1093 }
1094 /*
1095 * Gracefully stop all sends allowing any in progress to
1096 * trickle out first.
1097 */
1098 for (i = 0; i < dd->num_send_contexts; i++)
1099 sc_flush(dd->send_contexts[i].sc);
1100 }
1101
1102 /*
1103 * Enough for anything that's going to trickle out to have actually
1104 * done so.
1105 */
1106 udelay(20);
1107
1108 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1109 ppd = dd->pport + pidx;
1110
1111 /* disable all contexts */
1112 for (i = 0; i < dd->num_send_contexts; i++)
1113 sc_disable(dd->send_contexts[i].sc);
1114 /* disable the send device */
1115 pio_send_control(dd, PSC_GLOBAL_DISABLE);
1116
1117 shutdown_led_override(ppd);
1118
1119 /*
1120 * Clear SerdesEnable.
1121 * We can't count on interrupts since we are stopping.
1122 */
1123 hfi1_quiet_serdes(ppd);
1124 if (ppd->hfi1_wq)
1125 flush_workqueue(ppd->hfi1_wq);
1126 if (ppd->link_wq)
1127 flush_workqueue(ppd->link_wq);
1128 }
1129 sdma_exit(dd);
1130 }
1131
1132 /**
1133 * hfi1_free_ctxtdata - free a context's allocated data
1134 * @dd: the hfi1_ib device
1135 * @rcd: the ctxtdata structure
1136 *
1137 * free up any allocated data for a context
1138 * It should never change any chip state, or global driver state.
1139 */
hfi1_free_ctxtdata(struct hfi1_devdata * dd,struct hfi1_ctxtdata * rcd)1140 void hfi1_free_ctxtdata(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd)
1141 {
1142 u32 e;
1143
1144 if (!rcd)
1145 return;
1146
1147 if (rcd->rcvhdrq) {
1148 dma_free_coherent(&dd->pcidev->dev, rcvhdrq_size(rcd),
1149 rcd->rcvhdrq, rcd->rcvhdrq_dma);
1150 rcd->rcvhdrq = NULL;
1151 if (hfi1_rcvhdrtail_kvaddr(rcd)) {
1152 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
1153 (void *)hfi1_rcvhdrtail_kvaddr(rcd),
1154 rcd->rcvhdrqtailaddr_dma);
1155 rcd->rcvhdrtail_kvaddr = NULL;
1156 }
1157 }
1158
1159 /* all the RcvArray entries should have been cleared by now */
1160 kfree(rcd->egrbufs.rcvtids);
1161 rcd->egrbufs.rcvtids = NULL;
1162
1163 for (e = 0; e < rcd->egrbufs.alloced; e++) {
1164 if (rcd->egrbufs.buffers[e].dma)
1165 dma_free_coherent(&dd->pcidev->dev,
1166 rcd->egrbufs.buffers[e].len,
1167 rcd->egrbufs.buffers[e].addr,
1168 rcd->egrbufs.buffers[e].dma);
1169 }
1170 kfree(rcd->egrbufs.buffers);
1171 rcd->egrbufs.alloced = 0;
1172 rcd->egrbufs.buffers = NULL;
1173
1174 sc_free(rcd->sc);
1175 rcd->sc = NULL;
1176
1177 vfree(rcd->subctxt_uregbase);
1178 vfree(rcd->subctxt_rcvegrbuf);
1179 vfree(rcd->subctxt_rcvhdr_base);
1180 kfree(rcd->opstats);
1181
1182 rcd->subctxt_uregbase = NULL;
1183 rcd->subctxt_rcvegrbuf = NULL;
1184 rcd->subctxt_rcvhdr_base = NULL;
1185 rcd->opstats = NULL;
1186 }
1187
1188 /*
1189 * Release our hold on the shared asic data. If we are the last one,
1190 * return the structure to be finalized outside the lock. Must be
1191 * holding hfi1_dev_table lock.
1192 */
release_asic_data(struct hfi1_devdata * dd)1193 static struct hfi1_asic_data *release_asic_data(struct hfi1_devdata *dd)
1194 {
1195 struct hfi1_asic_data *ad;
1196 int other;
1197
1198 if (!dd->asic_data)
1199 return NULL;
1200 dd->asic_data->dds[dd->hfi1_id] = NULL;
1201 other = dd->hfi1_id ? 0 : 1;
1202 ad = dd->asic_data;
1203 dd->asic_data = NULL;
1204 /* return NULL if the other dd still has a link */
1205 return ad->dds[other] ? NULL : ad;
1206 }
1207
finalize_asic_data(struct hfi1_devdata * dd,struct hfi1_asic_data * ad)1208 static void finalize_asic_data(struct hfi1_devdata *dd,
1209 struct hfi1_asic_data *ad)
1210 {
1211 clean_up_i2c(dd, ad);
1212 kfree(ad);
1213 }
1214
1215 /**
1216 * hfi1_free_devdata - cleans up and frees per-unit data structure
1217 * @dd: pointer to a valid devdata structure
1218 *
1219 * It cleans up and frees all data structures set up by
1220 * by hfi1_alloc_devdata().
1221 */
hfi1_free_devdata(struct hfi1_devdata * dd)1222 void hfi1_free_devdata(struct hfi1_devdata *dd)
1223 {
1224 struct hfi1_asic_data *ad;
1225 unsigned long flags;
1226
1227 xa_lock_irqsave(&hfi1_dev_table, flags);
1228 __xa_erase(&hfi1_dev_table, dd->unit);
1229 ad = release_asic_data(dd);
1230 xa_unlock_irqrestore(&hfi1_dev_table, flags);
1231
1232 finalize_asic_data(dd, ad);
1233 free_platform_config(dd);
1234 rcu_barrier(); /* wait for rcu callbacks to complete */
1235 free_percpu(dd->int_counter);
1236 free_percpu(dd->rcv_limit);
1237 free_percpu(dd->send_schedule);
1238 free_percpu(dd->tx_opstats);
1239 dd->int_counter = NULL;
1240 dd->rcv_limit = NULL;
1241 dd->send_schedule = NULL;
1242 dd->tx_opstats = NULL;
1243 kfree(dd->comp_vect);
1244 dd->comp_vect = NULL;
1245 sdma_clean(dd, dd->num_sdma);
1246 rvt_dealloc_device(&dd->verbs_dev.rdi);
1247 }
1248
1249 /**
1250 * hfi1_alloc_devdata - Allocate our primary per-unit data structure.
1251 * @pdev: Valid PCI device
1252 * @extra: How many bytes to alloc past the default
1253 *
1254 * Must be done via verbs allocator, because the verbs cleanup process
1255 * both does cleanup and free of the data structure.
1256 * "extra" is for chip-specific data.
1257 */
hfi1_alloc_devdata(struct pci_dev * pdev,size_t extra)1258 static struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev,
1259 size_t extra)
1260 {
1261 struct hfi1_devdata *dd;
1262 int ret, nports;
1263
1264 /* extra is * number of ports */
1265 nports = extra / sizeof(struct hfi1_pportdata);
1266
1267 dd = (struct hfi1_devdata *)rvt_alloc_device(sizeof(*dd) + extra,
1268 nports);
1269 if (!dd)
1270 return ERR_PTR(-ENOMEM);
1271 dd->num_pports = nports;
1272 dd->pport = (struct hfi1_pportdata *)(dd + 1);
1273 dd->pcidev = pdev;
1274 pci_set_drvdata(pdev, dd);
1275
1276 ret = xa_alloc_irq(&hfi1_dev_table, &dd->unit, dd, xa_limit_32b,
1277 GFP_KERNEL);
1278 if (ret < 0) {
1279 dev_err(&pdev->dev,
1280 "Could not allocate unit ID: error %d\n", -ret);
1281 goto bail;
1282 }
1283 rvt_set_ibdev_name(&dd->verbs_dev.rdi, "%s_%d", class_name(), dd->unit);
1284 /*
1285 * If the BIOS does not have the NUMA node information set, select
1286 * NUMA 0 so we get consistent performance.
1287 */
1288 dd->node = pcibus_to_node(pdev->bus);
1289 if (dd->node == NUMA_NO_NODE) {
1290 dd_dev_err(dd, "Invalid PCI NUMA node. Performance may be affected\n");
1291 dd->node = 0;
1292 }
1293
1294 /*
1295 * Initialize all locks for the device. This needs to be as early as
1296 * possible so locks are usable.
1297 */
1298 spin_lock_init(&dd->sc_lock);
1299 spin_lock_init(&dd->sendctrl_lock);
1300 spin_lock_init(&dd->rcvctrl_lock);
1301 spin_lock_init(&dd->uctxt_lock);
1302 spin_lock_init(&dd->hfi1_diag_trans_lock);
1303 spin_lock_init(&dd->sc_init_lock);
1304 spin_lock_init(&dd->dc8051_memlock);
1305 seqlock_init(&dd->sc2vl_lock);
1306 spin_lock_init(&dd->sde_map_lock);
1307 spin_lock_init(&dd->pio_map_lock);
1308 mutex_init(&dd->dc8051_lock);
1309 init_waitqueue_head(&dd->event_queue);
1310 spin_lock_init(&dd->irq_src_lock);
1311
1312 dd->int_counter = alloc_percpu(u64);
1313 if (!dd->int_counter) {
1314 ret = -ENOMEM;
1315 goto bail;
1316 }
1317
1318 dd->rcv_limit = alloc_percpu(u64);
1319 if (!dd->rcv_limit) {
1320 ret = -ENOMEM;
1321 goto bail;
1322 }
1323
1324 dd->send_schedule = alloc_percpu(u64);
1325 if (!dd->send_schedule) {
1326 ret = -ENOMEM;
1327 goto bail;
1328 }
1329
1330 dd->tx_opstats = alloc_percpu(struct hfi1_opcode_stats_perctx);
1331 if (!dd->tx_opstats) {
1332 ret = -ENOMEM;
1333 goto bail;
1334 }
1335
1336 dd->comp_vect = kzalloc(sizeof(*dd->comp_vect), GFP_KERNEL);
1337 if (!dd->comp_vect) {
1338 ret = -ENOMEM;
1339 goto bail;
1340 }
1341
1342 atomic_set(&dd->ipoib_rsm_usr_num, 0);
1343 return dd;
1344
1345 bail:
1346 hfi1_free_devdata(dd);
1347 return ERR_PTR(ret);
1348 }
1349
1350 /*
1351 * Called from freeze mode handlers, and from PCI error
1352 * reporting code. Should be paranoid about state of
1353 * system and data structures.
1354 */
hfi1_disable_after_error(struct hfi1_devdata * dd)1355 void hfi1_disable_after_error(struct hfi1_devdata *dd)
1356 {
1357 if (dd->flags & HFI1_INITTED) {
1358 u32 pidx;
1359
1360 dd->flags &= ~HFI1_INITTED;
1361 if (dd->pport)
1362 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1363 struct hfi1_pportdata *ppd;
1364
1365 ppd = dd->pport + pidx;
1366 if (dd->flags & HFI1_PRESENT)
1367 set_link_state(ppd, HLS_DN_DISABLE);
1368
1369 if (ppd->statusp)
1370 *ppd->statusp &= ~HFI1_STATUS_IB_READY;
1371 }
1372 }
1373
1374 /*
1375 * Mark as having had an error for driver, and also
1376 * for /sys and status word mapped to user programs.
1377 * This marks unit as not usable, until reset.
1378 */
1379 if (dd->status)
1380 dd->status->dev |= HFI1_STATUS_HWERROR;
1381 }
1382
1383 static void remove_one(struct pci_dev *);
1384 static int init_one(struct pci_dev *, const struct pci_device_id *);
1385 static void shutdown_one(struct pci_dev *);
1386
1387 #define DRIVER_LOAD_MSG "Intel " DRIVER_NAME " loaded: "
1388 #define PFX DRIVER_NAME ": "
1389
1390 const struct pci_device_id hfi1_pci_tbl[] = {
1391 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL0) },
1392 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL1) },
1393 { 0, }
1394 };
1395
1396 MODULE_DEVICE_TABLE(pci, hfi1_pci_tbl);
1397
1398 static struct pci_driver hfi1_pci_driver = {
1399 .name = DRIVER_NAME,
1400 .probe = init_one,
1401 .remove = remove_one,
1402 .shutdown = shutdown_one,
1403 .id_table = hfi1_pci_tbl,
1404 .err_handler = &hfi1_pci_err_handler,
1405 };
1406
compute_krcvqs(void)1407 static void __init compute_krcvqs(void)
1408 {
1409 int i;
1410
1411 for (i = 0; i < krcvqsset; i++)
1412 n_krcvqs += krcvqs[i];
1413 }
1414
1415 /*
1416 * Do all the generic driver unit- and chip-independent memory
1417 * allocation and initialization.
1418 */
hfi1_mod_init(void)1419 static int __init hfi1_mod_init(void)
1420 {
1421 int ret;
1422
1423 ret = dev_init();
1424 if (ret)
1425 goto bail;
1426
1427 ret = node_affinity_init();
1428 if (ret)
1429 goto bail;
1430
1431 /* validate max MTU before any devices start */
1432 if (!valid_opa_max_mtu(hfi1_max_mtu)) {
1433 pr_err("Invalid max_mtu 0x%x, using 0x%x instead\n",
1434 hfi1_max_mtu, HFI1_DEFAULT_MAX_MTU);
1435 hfi1_max_mtu = HFI1_DEFAULT_MAX_MTU;
1436 }
1437 /* valid CUs run from 1-128 in powers of 2 */
1438 if (hfi1_cu > 128 || !is_power_of_2(hfi1_cu))
1439 hfi1_cu = 1;
1440 /* valid credit return threshold is 0-100, variable is unsigned */
1441 if (user_credit_return_threshold > 100)
1442 user_credit_return_threshold = 100;
1443
1444 compute_krcvqs();
1445 /*
1446 * sanitize receive interrupt count, time must wait until after
1447 * the hardware type is known
1448 */
1449 if (rcv_intr_count > RCV_HDR_HEAD_COUNTER_MASK)
1450 rcv_intr_count = RCV_HDR_HEAD_COUNTER_MASK;
1451 /* reject invalid combinations */
1452 if (rcv_intr_count == 0 && rcv_intr_timeout == 0) {
1453 pr_err("Invalid mode: both receive interrupt count and available timeout are zero - setting interrupt count to 1\n");
1454 rcv_intr_count = 1;
1455 }
1456 if (rcv_intr_count > 1 && rcv_intr_timeout == 0) {
1457 /*
1458 * Avoid indefinite packet delivery by requiring a timeout
1459 * if count is > 1.
1460 */
1461 pr_err("Invalid mode: receive interrupt count greater than 1 and available timeout is zero - setting available timeout to 1\n");
1462 rcv_intr_timeout = 1;
1463 }
1464 if (rcv_intr_dynamic && !(rcv_intr_count > 1 && rcv_intr_timeout > 0)) {
1465 /*
1466 * The dynamic algorithm expects a non-zero timeout
1467 * and a count > 1.
1468 */
1469 pr_err("Invalid mode: dynamic receive interrupt mitigation with invalid count and timeout - turning dynamic off\n");
1470 rcv_intr_dynamic = 0;
1471 }
1472
1473 /* sanitize link CRC options */
1474 link_crc_mask &= SUPPORTED_CRCS;
1475
1476 ret = opfn_init();
1477 if (ret < 0) {
1478 pr_err("Failed to allocate opfn_wq");
1479 goto bail_dev;
1480 }
1481
1482 /*
1483 * These must be called before the driver is registered with
1484 * the PCI subsystem.
1485 */
1486 hfi1_dbg_init();
1487 ret = pci_register_driver(&hfi1_pci_driver);
1488 if (ret < 0) {
1489 pr_err("Unable to register driver: error %d\n", -ret);
1490 goto bail_dev;
1491 }
1492 goto bail; /* all OK */
1493
1494 bail_dev:
1495 hfi1_dbg_exit();
1496 dev_cleanup();
1497 bail:
1498 return ret;
1499 }
1500
1501 module_init(hfi1_mod_init);
1502
1503 /*
1504 * Do the non-unit driver cleanup, memory free, etc. at unload.
1505 */
hfi1_mod_cleanup(void)1506 static void __exit hfi1_mod_cleanup(void)
1507 {
1508 pci_unregister_driver(&hfi1_pci_driver);
1509 opfn_exit();
1510 node_affinity_destroy_all();
1511 hfi1_dbg_exit();
1512
1513 WARN_ON(!xa_empty(&hfi1_dev_table));
1514 dispose_firmware(); /* asymmetric with obtain_firmware() */
1515 dev_cleanup();
1516 }
1517
1518 module_exit(hfi1_mod_cleanup);
1519
1520 /* this can only be called after a successful initialization */
cleanup_device_data(struct hfi1_devdata * dd)1521 static void cleanup_device_data(struct hfi1_devdata *dd)
1522 {
1523 int ctxt;
1524 int pidx;
1525
1526 /* users can't do anything more with chip */
1527 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1528 struct hfi1_pportdata *ppd = &dd->pport[pidx];
1529 struct cc_state *cc_state;
1530 int i;
1531
1532 if (ppd->statusp)
1533 *ppd->statusp &= ~HFI1_STATUS_CHIP_PRESENT;
1534
1535 for (i = 0; i < OPA_MAX_SLS; i++)
1536 hrtimer_cancel(&ppd->cca_timer[i].hrtimer);
1537
1538 spin_lock(&ppd->cc_state_lock);
1539 cc_state = get_cc_state_protected(ppd);
1540 RCU_INIT_POINTER(ppd->cc_state, NULL);
1541 spin_unlock(&ppd->cc_state_lock);
1542
1543 if (cc_state)
1544 kfree_rcu(cc_state, rcu);
1545 }
1546
1547 free_credit_return(dd);
1548
1549 if (dd->rcvhdrtail_dummy_kvaddr) {
1550 dma_free_coherent(&dd->pcidev->dev, sizeof(u64),
1551 (void *)dd->rcvhdrtail_dummy_kvaddr,
1552 dd->rcvhdrtail_dummy_dma);
1553 dd->rcvhdrtail_dummy_kvaddr = NULL;
1554 }
1555
1556 /*
1557 * Free any resources still in use (usually just kernel contexts)
1558 * at unload; we do for ctxtcnt, because that's what we allocate.
1559 */
1560 for (ctxt = 0; dd->rcd && ctxt < dd->num_rcv_contexts; ctxt++) {
1561 struct hfi1_ctxtdata *rcd = dd->rcd[ctxt];
1562
1563 if (rcd) {
1564 hfi1_free_ctxt_rcv_groups(rcd);
1565 hfi1_free_ctxt(rcd);
1566 }
1567 }
1568
1569 kfree(dd->rcd);
1570 dd->rcd = NULL;
1571
1572 free_pio_map(dd);
1573 /* must follow rcv context free - need to remove rcv's hooks */
1574 for (ctxt = 0; ctxt < dd->num_send_contexts; ctxt++)
1575 sc_free(dd->send_contexts[ctxt].sc);
1576 dd->num_send_contexts = 0;
1577 kfree(dd->send_contexts);
1578 dd->send_contexts = NULL;
1579 kfree(dd->hw_to_sw);
1580 dd->hw_to_sw = NULL;
1581 kfree(dd->boardname);
1582 vfree(dd->events);
1583 vfree(dd->status);
1584 }
1585
1586 /*
1587 * Clean up on unit shutdown, or error during unit load after
1588 * successful initialization.
1589 */
postinit_cleanup(struct hfi1_devdata * dd)1590 static void postinit_cleanup(struct hfi1_devdata *dd)
1591 {
1592 hfi1_start_cleanup(dd);
1593 hfi1_comp_vectors_clean_up(dd);
1594 hfi1_dev_affinity_clean_up(dd);
1595
1596 hfi1_pcie_ddcleanup(dd);
1597 hfi1_pcie_cleanup(dd->pcidev);
1598
1599 cleanup_device_data(dd);
1600
1601 hfi1_free_devdata(dd);
1602 }
1603
init_one(struct pci_dev * pdev,const struct pci_device_id * ent)1604 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1605 {
1606 int ret = 0, j, pidx, initfail;
1607 struct hfi1_devdata *dd;
1608 struct hfi1_pportdata *ppd;
1609
1610 /* First, lock the non-writable module parameters */
1611 HFI1_CAP_LOCK();
1612
1613 /* Validate dev ids */
1614 if (!(ent->device == PCI_DEVICE_ID_INTEL0 ||
1615 ent->device == PCI_DEVICE_ID_INTEL1)) {
1616 dev_err(&pdev->dev, "Failing on unknown Intel deviceid 0x%x\n",
1617 ent->device);
1618 ret = -ENODEV;
1619 goto bail;
1620 }
1621
1622 /* Allocate the dd so we can get to work */
1623 dd = hfi1_alloc_devdata(pdev, NUM_IB_PORTS *
1624 sizeof(struct hfi1_pportdata));
1625 if (IS_ERR(dd)) {
1626 ret = PTR_ERR(dd);
1627 goto bail;
1628 }
1629
1630 /* Validate some global module parameters */
1631 ret = hfi1_validate_rcvhdrcnt(dd, rcvhdrcnt);
1632 if (ret)
1633 goto bail;
1634
1635 /* use the encoding function as a sanitization check */
1636 if (!encode_rcv_header_entry_size(hfi1_hdrq_entsize)) {
1637 dd_dev_err(dd, "Invalid HdrQ Entry size %u\n",
1638 hfi1_hdrq_entsize);
1639 ret = -EINVAL;
1640 goto bail;
1641 }
1642
1643 /* The receive eager buffer size must be set before the receive
1644 * contexts are created.
1645 *
1646 * Set the eager buffer size. Validate that it falls in a range
1647 * allowed by the hardware - all powers of 2 between the min and
1648 * max. The maximum valid MTU is within the eager buffer range
1649 * so we do not need to cap the max_mtu by an eager buffer size
1650 * setting.
1651 */
1652 if (eager_buffer_size) {
1653 if (!is_power_of_2(eager_buffer_size))
1654 eager_buffer_size =
1655 roundup_pow_of_two(eager_buffer_size);
1656 eager_buffer_size =
1657 clamp_val(eager_buffer_size,
1658 MIN_EAGER_BUFFER * 8,
1659 MAX_EAGER_BUFFER_TOTAL);
1660 dd_dev_info(dd, "Eager buffer size %u\n",
1661 eager_buffer_size);
1662 } else {
1663 dd_dev_err(dd, "Invalid Eager buffer size of 0\n");
1664 ret = -EINVAL;
1665 goto bail;
1666 }
1667
1668 /* restrict value of hfi1_rcvarr_split */
1669 hfi1_rcvarr_split = clamp_val(hfi1_rcvarr_split, 0, 100);
1670
1671 ret = hfi1_pcie_init(dd);
1672 if (ret)
1673 goto bail;
1674
1675 /*
1676 * Do device-specific initialization, function table setup, dd
1677 * allocation, etc.
1678 */
1679 ret = hfi1_init_dd(dd);
1680 if (ret)
1681 goto clean_bail; /* error already printed */
1682
1683 ret = create_workqueues(dd);
1684 if (ret)
1685 goto clean_bail;
1686
1687 /* do the generic initialization */
1688 initfail = hfi1_init(dd, 0);
1689
1690 ret = hfi1_register_ib_device(dd);
1691
1692 /*
1693 * Now ready for use. this should be cleared whenever we
1694 * detect a reset, or initiate one. If earlier failure,
1695 * we still create devices, so diags, etc. can be used
1696 * to determine cause of problem.
1697 */
1698 if (!initfail && !ret) {
1699 dd->flags |= HFI1_INITTED;
1700 /* create debufs files after init and ib register */
1701 hfi1_dbg_ibdev_init(&dd->verbs_dev);
1702 }
1703
1704 j = hfi1_device_create(dd);
1705 if (j)
1706 dd_dev_err(dd, "Failed to create /dev devices: %d\n", -j);
1707
1708 if (initfail || ret) {
1709 msix_clean_up_interrupts(dd);
1710 stop_timers(dd);
1711 flush_workqueue(ib_wq);
1712 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1713 hfi1_quiet_serdes(dd->pport + pidx);
1714 ppd = dd->pport + pidx;
1715 if (ppd->hfi1_wq) {
1716 destroy_workqueue(ppd->hfi1_wq);
1717 ppd->hfi1_wq = NULL;
1718 }
1719 if (ppd->link_wq) {
1720 destroy_workqueue(ppd->link_wq);
1721 ppd->link_wq = NULL;
1722 }
1723 }
1724 if (!j)
1725 hfi1_device_remove(dd);
1726 if (!ret)
1727 hfi1_unregister_ib_device(dd);
1728 postinit_cleanup(dd);
1729 if (initfail)
1730 ret = initfail;
1731 goto bail; /* everything already cleaned */
1732 }
1733
1734 sdma_start(dd);
1735
1736 return 0;
1737
1738 clean_bail:
1739 hfi1_pcie_cleanup(pdev);
1740 bail:
1741 return ret;
1742 }
1743
wait_for_clients(struct hfi1_devdata * dd)1744 static void wait_for_clients(struct hfi1_devdata *dd)
1745 {
1746 /*
1747 * Remove the device init value and complete the device if there is
1748 * no clients or wait for active clients to finish.
1749 */
1750 if (atomic_dec_and_test(&dd->user_refcount))
1751 complete(&dd->user_comp);
1752
1753 wait_for_completion(&dd->user_comp);
1754 }
1755
remove_one(struct pci_dev * pdev)1756 static void remove_one(struct pci_dev *pdev)
1757 {
1758 struct hfi1_devdata *dd = pci_get_drvdata(pdev);
1759
1760 /* close debugfs files before ib unregister */
1761 hfi1_dbg_ibdev_exit(&dd->verbs_dev);
1762
1763 /* remove the /dev hfi1 interface */
1764 hfi1_device_remove(dd);
1765
1766 /* wait for existing user space clients to finish */
1767 wait_for_clients(dd);
1768
1769 /* unregister from IB core */
1770 hfi1_unregister_ib_device(dd);
1771
1772 /* free netdev data */
1773 hfi1_netdev_free(dd);
1774
1775 /*
1776 * Disable the IB link, disable interrupts on the device,
1777 * clear dma engines, etc.
1778 */
1779 shutdown_device(dd);
1780 destroy_workqueues(dd);
1781
1782 stop_timers(dd);
1783
1784 /* wait until all of our (qsfp) queue_work() calls complete */
1785 flush_workqueue(ib_wq);
1786
1787 postinit_cleanup(dd);
1788 }
1789
shutdown_one(struct pci_dev * pdev)1790 static void shutdown_one(struct pci_dev *pdev)
1791 {
1792 struct hfi1_devdata *dd = pci_get_drvdata(pdev);
1793
1794 shutdown_device(dd);
1795 }
1796
1797 /**
1798 * hfi1_create_rcvhdrq - create a receive header queue
1799 * @dd: the hfi1_ib device
1800 * @rcd: the context data
1801 *
1802 * This must be contiguous memory (from an i/o perspective), and must be
1803 * DMA'able (which means for some systems, it will go through an IOMMU,
1804 * or be forced into a low address range).
1805 */
hfi1_create_rcvhdrq(struct hfi1_devdata * dd,struct hfi1_ctxtdata * rcd)1806 int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd)
1807 {
1808 unsigned amt;
1809
1810 if (!rcd->rcvhdrq) {
1811 gfp_t gfp_flags;
1812
1813 amt = rcvhdrq_size(rcd);
1814
1815 if (rcd->ctxt < dd->first_dyn_alloc_ctxt || rcd->is_vnic)
1816 gfp_flags = GFP_KERNEL;
1817 else
1818 gfp_flags = GFP_USER;
1819 rcd->rcvhdrq = dma_alloc_coherent(&dd->pcidev->dev, amt,
1820 &rcd->rcvhdrq_dma,
1821 gfp_flags | __GFP_COMP);
1822
1823 if (!rcd->rcvhdrq) {
1824 dd_dev_err(dd,
1825 "attempt to allocate %d bytes for ctxt %u rcvhdrq failed\n",
1826 amt, rcd->ctxt);
1827 goto bail;
1828 }
1829
1830 if (HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL) ||
1831 HFI1_CAP_UGET_MASK(rcd->flags, DMA_RTAIL)) {
1832 rcd->rcvhdrtail_kvaddr = dma_alloc_coherent(&dd->pcidev->dev,
1833 PAGE_SIZE,
1834 &rcd->rcvhdrqtailaddr_dma,
1835 gfp_flags);
1836 if (!rcd->rcvhdrtail_kvaddr)
1837 goto bail_free;
1838 }
1839 }
1840
1841 set_hdrq_regs(rcd->dd, rcd->ctxt, rcd->rcvhdrqentsize,
1842 rcd->rcvhdrq_cnt);
1843
1844 return 0;
1845
1846 bail_free:
1847 dd_dev_err(dd,
1848 "attempt to allocate 1 page for ctxt %u rcvhdrqtailaddr failed\n",
1849 rcd->ctxt);
1850 dma_free_coherent(&dd->pcidev->dev, amt, rcd->rcvhdrq,
1851 rcd->rcvhdrq_dma);
1852 rcd->rcvhdrq = NULL;
1853 bail:
1854 return -ENOMEM;
1855 }
1856
1857 /**
1858 * allocate eager buffers, both kernel and user contexts.
1859 * @rcd: the context we are setting up.
1860 *
1861 * Allocate the eager TID buffers and program them into hip.
1862 * They are no longer completely contiguous, we do multiple allocation
1863 * calls. Otherwise we get the OOM code involved, by asking for too
1864 * much per call, with disastrous results on some kernels.
1865 */
hfi1_setup_eagerbufs(struct hfi1_ctxtdata * rcd)1866 int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *rcd)
1867 {
1868 struct hfi1_devdata *dd = rcd->dd;
1869 u32 max_entries, egrtop, alloced_bytes = 0;
1870 gfp_t gfp_flags;
1871 u16 order, idx = 0;
1872 int ret = 0;
1873 u16 round_mtu = roundup_pow_of_two(hfi1_max_mtu);
1874
1875 /*
1876 * GFP_USER, but without GFP_FS, so buffer cache can be
1877 * coalesced (we hope); otherwise, even at order 4,
1878 * heavy filesystem activity makes these fail, and we can
1879 * use compound pages.
1880 */
1881 gfp_flags = __GFP_RECLAIM | __GFP_IO | __GFP_COMP;
1882
1883 /*
1884 * The minimum size of the eager buffers is a groups of MTU-sized
1885 * buffers.
1886 * The global eager_buffer_size parameter is checked against the
1887 * theoretical lower limit of the value. Here, we check against the
1888 * MTU.
1889 */
1890 if (rcd->egrbufs.size < (round_mtu * dd->rcv_entries.group_size))
1891 rcd->egrbufs.size = round_mtu * dd->rcv_entries.group_size;
1892 /*
1893 * If using one-pkt-per-egr-buffer, lower the eager buffer
1894 * size to the max MTU (page-aligned).
1895 */
1896 if (!HFI1_CAP_KGET_MASK(rcd->flags, MULTI_PKT_EGR))
1897 rcd->egrbufs.rcvtid_size = round_mtu;
1898
1899 /*
1900 * Eager buffers sizes of 1MB or less require smaller TID sizes
1901 * to satisfy the "multiple of 8 RcvArray entries" requirement.
1902 */
1903 if (rcd->egrbufs.size <= (1 << 20))
1904 rcd->egrbufs.rcvtid_size = max((unsigned long)round_mtu,
1905 rounddown_pow_of_two(rcd->egrbufs.size / 8));
1906
1907 while (alloced_bytes < rcd->egrbufs.size &&
1908 rcd->egrbufs.alloced < rcd->egrbufs.count) {
1909 rcd->egrbufs.buffers[idx].addr =
1910 dma_alloc_coherent(&dd->pcidev->dev,
1911 rcd->egrbufs.rcvtid_size,
1912 &rcd->egrbufs.buffers[idx].dma,
1913 gfp_flags);
1914 if (rcd->egrbufs.buffers[idx].addr) {
1915 rcd->egrbufs.buffers[idx].len =
1916 rcd->egrbufs.rcvtid_size;
1917 rcd->egrbufs.rcvtids[rcd->egrbufs.alloced].addr =
1918 rcd->egrbufs.buffers[idx].addr;
1919 rcd->egrbufs.rcvtids[rcd->egrbufs.alloced].dma =
1920 rcd->egrbufs.buffers[idx].dma;
1921 rcd->egrbufs.alloced++;
1922 alloced_bytes += rcd->egrbufs.rcvtid_size;
1923 idx++;
1924 } else {
1925 u32 new_size, i, j;
1926 u64 offset = 0;
1927
1928 /*
1929 * Fail the eager buffer allocation if:
1930 * - we are already using the lowest acceptable size
1931 * - we are using one-pkt-per-egr-buffer (this implies
1932 * that we are accepting only one size)
1933 */
1934 if (rcd->egrbufs.rcvtid_size == round_mtu ||
1935 !HFI1_CAP_KGET_MASK(rcd->flags, MULTI_PKT_EGR)) {
1936 dd_dev_err(dd, "ctxt%u: Failed to allocate eager buffers\n",
1937 rcd->ctxt);
1938 ret = -ENOMEM;
1939 goto bail_rcvegrbuf_phys;
1940 }
1941
1942 new_size = rcd->egrbufs.rcvtid_size / 2;
1943
1944 /*
1945 * If the first attempt to allocate memory failed, don't
1946 * fail everything but continue with the next lower
1947 * size.
1948 */
1949 if (idx == 0) {
1950 rcd->egrbufs.rcvtid_size = new_size;
1951 continue;
1952 }
1953
1954 /*
1955 * Re-partition already allocated buffers to a smaller
1956 * size.
1957 */
1958 rcd->egrbufs.alloced = 0;
1959 for (i = 0, j = 0, offset = 0; j < idx; i++) {
1960 if (i >= rcd->egrbufs.count)
1961 break;
1962 rcd->egrbufs.rcvtids[i].dma =
1963 rcd->egrbufs.buffers[j].dma + offset;
1964 rcd->egrbufs.rcvtids[i].addr =
1965 rcd->egrbufs.buffers[j].addr + offset;
1966 rcd->egrbufs.alloced++;
1967 if ((rcd->egrbufs.buffers[j].dma + offset +
1968 new_size) ==
1969 (rcd->egrbufs.buffers[j].dma +
1970 rcd->egrbufs.buffers[j].len)) {
1971 j++;
1972 offset = 0;
1973 } else {
1974 offset += new_size;
1975 }
1976 }
1977 rcd->egrbufs.rcvtid_size = new_size;
1978 }
1979 }
1980 rcd->egrbufs.numbufs = idx;
1981 rcd->egrbufs.size = alloced_bytes;
1982
1983 hfi1_cdbg(PROC,
1984 "ctxt%u: Alloced %u rcv tid entries @ %uKB, total %uKB\n",
1985 rcd->ctxt, rcd->egrbufs.alloced,
1986 rcd->egrbufs.rcvtid_size / 1024, rcd->egrbufs.size / 1024);
1987
1988 /*
1989 * Set the contexts rcv array head update threshold to the closest
1990 * power of 2 (so we can use a mask instead of modulo) below half
1991 * the allocated entries.
1992 */
1993 rcd->egrbufs.threshold =
1994 rounddown_pow_of_two(rcd->egrbufs.alloced / 2);
1995 /*
1996 * Compute the expected RcvArray entry base. This is done after
1997 * allocating the eager buffers in order to maximize the
1998 * expected RcvArray entries for the context.
1999 */
2000 max_entries = rcd->rcv_array_groups * dd->rcv_entries.group_size;
2001 egrtop = roundup(rcd->egrbufs.alloced, dd->rcv_entries.group_size);
2002 rcd->expected_count = max_entries - egrtop;
2003 if (rcd->expected_count > MAX_TID_PAIR_ENTRIES * 2)
2004 rcd->expected_count = MAX_TID_PAIR_ENTRIES * 2;
2005
2006 rcd->expected_base = rcd->eager_base + egrtop;
2007 hfi1_cdbg(PROC, "ctxt%u: eager:%u, exp:%u, egrbase:%u, expbase:%u\n",
2008 rcd->ctxt, rcd->egrbufs.alloced, rcd->expected_count,
2009 rcd->eager_base, rcd->expected_base);
2010
2011 if (!hfi1_rcvbuf_validate(rcd->egrbufs.rcvtid_size, PT_EAGER, &order)) {
2012 hfi1_cdbg(PROC,
2013 "ctxt%u: current Eager buffer size is invalid %u\n",
2014 rcd->ctxt, rcd->egrbufs.rcvtid_size);
2015 ret = -EINVAL;
2016 goto bail_rcvegrbuf_phys;
2017 }
2018
2019 for (idx = 0; idx < rcd->egrbufs.alloced; idx++) {
2020 hfi1_put_tid(dd, rcd->eager_base + idx, PT_EAGER,
2021 rcd->egrbufs.rcvtids[idx].dma, order);
2022 cond_resched();
2023 }
2024
2025 return 0;
2026
2027 bail_rcvegrbuf_phys:
2028 for (idx = 0; idx < rcd->egrbufs.alloced &&
2029 rcd->egrbufs.buffers[idx].addr;
2030 idx++) {
2031 dma_free_coherent(&dd->pcidev->dev,
2032 rcd->egrbufs.buffers[idx].len,
2033 rcd->egrbufs.buffers[idx].addr,
2034 rcd->egrbufs.buffers[idx].dma);
2035 rcd->egrbufs.buffers[idx].addr = NULL;
2036 rcd->egrbufs.buffers[idx].dma = 0;
2037 rcd->egrbufs.buffers[idx].len = 0;
2038 }
2039
2040 return ret;
2041 }
2042