1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/ieee80211.h>
7 #include <linux/kernel.h>
8 #include <linux/skbuff.h>
9 #include <crypto/hash.h>
10 #include "core.h"
11 #include "debug.h"
12 #include "debugfs_htt_stats.h"
13 #include "debugfs_sta.h"
14 #include "hal_desc.h"
15 #include "hw.h"
16 #include "dp_rx.h"
17 #include "hal_rx.h"
18 #include "dp_tx.h"
19 #include "peer.h"
20
21 #define ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ)
22
ath11k_dp_rx_h_80211_hdr(struct hal_rx_desc * desc)23 static u8 *ath11k_dp_rx_h_80211_hdr(struct hal_rx_desc *desc)
24 {
25 return desc->hdr_status;
26 }
27
ath11k_dp_rx_h_mpdu_start_enctype(struct hal_rx_desc * desc)28 static enum hal_encrypt_type ath11k_dp_rx_h_mpdu_start_enctype(struct hal_rx_desc *desc)
29 {
30 if (!(__le32_to_cpu(desc->mpdu_start.info1) &
31 RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID))
32 return HAL_ENCRYPT_TYPE_OPEN;
33
34 return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE,
35 __le32_to_cpu(desc->mpdu_start.info2));
36 }
37
ath11k_dp_rx_h_msdu_start_decap_type(struct hal_rx_desc * desc)38 static u8 ath11k_dp_rx_h_msdu_start_decap_type(struct hal_rx_desc *desc)
39 {
40 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT,
41 __le32_to_cpu(desc->msdu_start.info2));
42 }
43
ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct hal_rx_desc * desc)44 static u8 ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct hal_rx_desc *desc)
45 {
46 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT,
47 __le32_to_cpu(desc->msdu_start.info2));
48 }
49
ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct hal_rx_desc * desc)50 static bool ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct hal_rx_desc *desc)
51 {
52 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID,
53 __le32_to_cpu(desc->mpdu_start.info1));
54 }
55
ath11k_dp_rx_h_mpdu_start_fc_valid(struct hal_rx_desc * desc)56 static bool ath11k_dp_rx_h_mpdu_start_fc_valid(struct hal_rx_desc *desc)
57 {
58 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID,
59 __le32_to_cpu(desc->mpdu_start.info1));
60 }
61
ath11k_dp_rx_h_mpdu_start_more_frags(struct sk_buff * skb)62 static bool ath11k_dp_rx_h_mpdu_start_more_frags(struct sk_buff *skb)
63 {
64 struct ieee80211_hdr *hdr;
65
66 hdr = (struct ieee80211_hdr *)(skb->data + HAL_RX_DESC_SIZE);
67 return ieee80211_has_morefrags(hdr->frame_control);
68 }
69
ath11k_dp_rx_h_mpdu_start_frag_no(struct sk_buff * skb)70 static u16 ath11k_dp_rx_h_mpdu_start_frag_no(struct sk_buff *skb)
71 {
72 struct ieee80211_hdr *hdr;
73
74 hdr = (struct ieee80211_hdr *)(skb->data + HAL_RX_DESC_SIZE);
75 return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
76 }
77
ath11k_dp_rx_h_mpdu_start_seq_no(struct hal_rx_desc * desc)78 static u16 ath11k_dp_rx_h_mpdu_start_seq_no(struct hal_rx_desc *desc)
79 {
80 return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM,
81 __le32_to_cpu(desc->mpdu_start.info1));
82 }
83
ath11k_dp_rx_h_attn_msdu_done(struct hal_rx_desc * desc)84 static bool ath11k_dp_rx_h_attn_msdu_done(struct hal_rx_desc *desc)
85 {
86 return !!FIELD_GET(RX_ATTENTION_INFO2_MSDU_DONE,
87 __le32_to_cpu(desc->attention.info2));
88 }
89
ath11k_dp_rx_h_attn_l4_cksum_fail(struct hal_rx_desc * desc)90 static bool ath11k_dp_rx_h_attn_l4_cksum_fail(struct hal_rx_desc *desc)
91 {
92 return !!FIELD_GET(RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL,
93 __le32_to_cpu(desc->attention.info1));
94 }
95
ath11k_dp_rx_h_attn_ip_cksum_fail(struct hal_rx_desc * desc)96 static bool ath11k_dp_rx_h_attn_ip_cksum_fail(struct hal_rx_desc *desc)
97 {
98 return !!FIELD_GET(RX_ATTENTION_INFO1_IP_CKSUM_FAIL,
99 __le32_to_cpu(desc->attention.info1));
100 }
101
ath11k_dp_rx_h_attn_is_decrypted(struct hal_rx_desc * desc)102 static bool ath11k_dp_rx_h_attn_is_decrypted(struct hal_rx_desc *desc)
103 {
104 return (FIELD_GET(RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE,
105 __le32_to_cpu(desc->attention.info2)) ==
106 RX_DESC_DECRYPT_STATUS_CODE_OK);
107 }
108
ath11k_dp_rx_h_attn_mpdu_err(struct hal_rx_desc * desc)109 static u32 ath11k_dp_rx_h_attn_mpdu_err(struct hal_rx_desc *desc)
110 {
111 u32 info = __le32_to_cpu(desc->attention.info1);
112 u32 errmap = 0;
113
114 if (info & RX_ATTENTION_INFO1_FCS_ERR)
115 errmap |= DP_RX_MPDU_ERR_FCS;
116
117 if (info & RX_ATTENTION_INFO1_DECRYPT_ERR)
118 errmap |= DP_RX_MPDU_ERR_DECRYPT;
119
120 if (info & RX_ATTENTION_INFO1_TKIP_MIC_ERR)
121 errmap |= DP_RX_MPDU_ERR_TKIP_MIC;
122
123 if (info & RX_ATTENTION_INFO1_A_MSDU_ERROR)
124 errmap |= DP_RX_MPDU_ERR_AMSDU_ERR;
125
126 if (info & RX_ATTENTION_INFO1_OVERFLOW_ERR)
127 errmap |= DP_RX_MPDU_ERR_OVERFLOW;
128
129 if (info & RX_ATTENTION_INFO1_MSDU_LEN_ERR)
130 errmap |= DP_RX_MPDU_ERR_MSDU_LEN;
131
132 if (info & RX_ATTENTION_INFO1_MPDU_LEN_ERR)
133 errmap |= DP_RX_MPDU_ERR_MPDU_LEN;
134
135 return errmap;
136 }
137
ath11k_dp_rx_h_msdu_start_msdu_len(struct hal_rx_desc * desc)138 static u16 ath11k_dp_rx_h_msdu_start_msdu_len(struct hal_rx_desc *desc)
139 {
140 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH,
141 __le32_to_cpu(desc->msdu_start.info1));
142 }
143
ath11k_dp_rx_h_msdu_start_sgi(struct hal_rx_desc * desc)144 static u8 ath11k_dp_rx_h_msdu_start_sgi(struct hal_rx_desc *desc)
145 {
146 return FIELD_GET(RX_MSDU_START_INFO3_SGI,
147 __le32_to_cpu(desc->msdu_start.info3));
148 }
149
ath11k_dp_rx_h_msdu_start_rate_mcs(struct hal_rx_desc * desc)150 static u8 ath11k_dp_rx_h_msdu_start_rate_mcs(struct hal_rx_desc *desc)
151 {
152 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS,
153 __le32_to_cpu(desc->msdu_start.info3));
154 }
155
ath11k_dp_rx_h_msdu_start_rx_bw(struct hal_rx_desc * desc)156 static u8 ath11k_dp_rx_h_msdu_start_rx_bw(struct hal_rx_desc *desc)
157 {
158 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW,
159 __le32_to_cpu(desc->msdu_start.info3));
160 }
161
ath11k_dp_rx_h_msdu_start_freq(struct hal_rx_desc * desc)162 static u32 ath11k_dp_rx_h_msdu_start_freq(struct hal_rx_desc *desc)
163 {
164 return __le32_to_cpu(desc->msdu_start.phy_meta_data);
165 }
166
ath11k_dp_rx_h_msdu_start_pkt_type(struct hal_rx_desc * desc)167 static u8 ath11k_dp_rx_h_msdu_start_pkt_type(struct hal_rx_desc *desc)
168 {
169 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE,
170 __le32_to_cpu(desc->msdu_start.info3));
171 }
172
ath11k_dp_rx_h_msdu_start_nss(struct hal_rx_desc * desc)173 static u8 ath11k_dp_rx_h_msdu_start_nss(struct hal_rx_desc *desc)
174 {
175 u8 mimo_ss_bitmap = FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP,
176 __le32_to_cpu(desc->msdu_start.info3));
177
178 return hweight8(mimo_ss_bitmap);
179 }
180
ath11k_dp_rx_h_mpdu_start_tid(struct hal_rx_desc * desc)181 static u8 ath11k_dp_rx_h_mpdu_start_tid(struct hal_rx_desc *desc)
182 {
183 return FIELD_GET(RX_MPDU_START_INFO2_TID,
184 __le32_to_cpu(desc->mpdu_start.info2));
185 }
186
ath11k_dp_rx_h_mpdu_start_peer_id(struct hal_rx_desc * desc)187 static u16 ath11k_dp_rx_h_mpdu_start_peer_id(struct hal_rx_desc *desc)
188 {
189 return __le16_to_cpu(desc->mpdu_start.sw_peer_id);
190 }
191
ath11k_dp_rx_h_msdu_end_l3pad(struct hal_rx_desc * desc)192 static u8 ath11k_dp_rx_h_msdu_end_l3pad(struct hal_rx_desc *desc)
193 {
194 return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING,
195 __le32_to_cpu(desc->msdu_end.info2));
196 }
197
ath11k_dp_rx_h_msdu_end_first_msdu(struct hal_rx_desc * desc)198 static bool ath11k_dp_rx_h_msdu_end_first_msdu(struct hal_rx_desc *desc)
199 {
200 return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU,
201 __le32_to_cpu(desc->msdu_end.info2));
202 }
203
ath11k_dp_rx_h_msdu_end_last_msdu(struct hal_rx_desc * desc)204 static bool ath11k_dp_rx_h_msdu_end_last_msdu(struct hal_rx_desc *desc)
205 {
206 return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU,
207 __le32_to_cpu(desc->msdu_end.info2));
208 }
209
ath11k_dp_rx_desc_end_tlv_copy(struct hal_rx_desc * fdesc,struct hal_rx_desc * ldesc)210 static void ath11k_dp_rx_desc_end_tlv_copy(struct hal_rx_desc *fdesc,
211 struct hal_rx_desc *ldesc)
212 {
213 memcpy((u8 *)&fdesc->msdu_end, (u8 *)&ldesc->msdu_end,
214 sizeof(struct rx_msdu_end));
215 memcpy((u8 *)&fdesc->attention, (u8 *)&ldesc->attention,
216 sizeof(struct rx_attention));
217 memcpy((u8 *)&fdesc->mpdu_end, (u8 *)&ldesc->mpdu_end,
218 sizeof(struct rx_mpdu_end));
219 }
220
ath11k_dp_rxdesc_get_mpdulen_err(struct hal_rx_desc * rx_desc)221 static u32 ath11k_dp_rxdesc_get_mpdulen_err(struct hal_rx_desc *rx_desc)
222 {
223 struct rx_attention *rx_attn;
224
225 rx_attn = &rx_desc->attention;
226
227 return FIELD_GET(RX_ATTENTION_INFO1_MPDU_LEN_ERR,
228 __le32_to_cpu(rx_attn->info1));
229 }
230
ath11k_dp_rxdesc_get_decap_format(struct hal_rx_desc * rx_desc)231 static u32 ath11k_dp_rxdesc_get_decap_format(struct hal_rx_desc *rx_desc)
232 {
233 struct rx_msdu_start *rx_msdu_start;
234
235 rx_msdu_start = &rx_desc->msdu_start;
236
237 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT,
238 __le32_to_cpu(rx_msdu_start->info2));
239 }
240
ath11k_dp_rxdesc_get_80211hdr(struct hal_rx_desc * rx_desc)241 static u8 *ath11k_dp_rxdesc_get_80211hdr(struct hal_rx_desc *rx_desc)
242 {
243 u8 *rx_pkt_hdr;
244
245 rx_pkt_hdr = &rx_desc->msdu_payload[0];
246
247 return rx_pkt_hdr;
248 }
249
ath11k_dp_rxdesc_mpdu_valid(struct hal_rx_desc * rx_desc)250 static bool ath11k_dp_rxdesc_mpdu_valid(struct hal_rx_desc *rx_desc)
251 {
252 u32 tlv_tag;
253
254 tlv_tag = FIELD_GET(HAL_TLV_HDR_TAG,
255 __le32_to_cpu(rx_desc->mpdu_start_tag));
256
257 return tlv_tag == HAL_RX_MPDU_START;
258 }
259
ath11k_dp_rxdesc_get_ppduid(struct hal_rx_desc * rx_desc)260 static u32 ath11k_dp_rxdesc_get_ppduid(struct hal_rx_desc *rx_desc)
261 {
262 return __le16_to_cpu(rx_desc->mpdu_start.phy_ppdu_id);
263 }
264
ath11k_dp_service_mon_ring(struct timer_list * t)265 static void ath11k_dp_service_mon_ring(struct timer_list *t)
266 {
267 struct ath11k_base *ab = from_timer(ab, t, mon_reap_timer);
268 int i;
269
270 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++)
271 ath11k_dp_rx_process_mon_rings(ab, i, NULL, DP_MON_SERVICE_BUDGET);
272
273 mod_timer(&ab->mon_reap_timer, jiffies +
274 msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
275 }
276
277 /* Returns number of Rx buffers replenished */
ath11k_dp_rxbufs_replenish(struct ath11k_base * ab,int mac_id,struct dp_rxdma_ring * rx_ring,int req_entries,enum hal_rx_buf_return_buf_manager mgr)278 int ath11k_dp_rxbufs_replenish(struct ath11k_base *ab, int mac_id,
279 struct dp_rxdma_ring *rx_ring,
280 int req_entries,
281 enum hal_rx_buf_return_buf_manager mgr)
282 {
283 struct hal_srng *srng;
284 u32 *desc;
285 struct sk_buff *skb;
286 int num_free;
287 int num_remain;
288 int buf_id;
289 u32 cookie;
290 dma_addr_t paddr;
291
292 req_entries = min(req_entries, rx_ring->bufs_max);
293
294 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
295
296 spin_lock_bh(&srng->lock);
297
298 ath11k_hal_srng_access_begin(ab, srng);
299
300 num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
301 if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4))
302 req_entries = num_free;
303
304 req_entries = min(num_free, req_entries);
305 num_remain = req_entries;
306
307 while (num_remain > 0) {
308 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
309 DP_RX_BUFFER_ALIGN_SIZE);
310 if (!skb)
311 break;
312
313 if (!IS_ALIGNED((unsigned long)skb->data,
314 DP_RX_BUFFER_ALIGN_SIZE)) {
315 skb_pull(skb,
316 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
317 skb->data);
318 }
319
320 paddr = dma_map_single(ab->dev, skb->data,
321 skb->len + skb_tailroom(skb),
322 DMA_FROM_DEVICE);
323 if (dma_mapping_error(ab->dev, paddr))
324 goto fail_free_skb;
325
326 spin_lock_bh(&rx_ring->idr_lock);
327 buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0,
328 rx_ring->bufs_max * 3, GFP_ATOMIC);
329 spin_unlock_bh(&rx_ring->idr_lock);
330 if (buf_id < 0)
331 goto fail_dma_unmap;
332
333 desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
334 if (!desc)
335 goto fail_idr_remove;
336
337 ATH11K_SKB_RXCB(skb)->paddr = paddr;
338
339 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
340 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
341
342 num_remain--;
343
344 ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
345 }
346
347 ath11k_hal_srng_access_end(ab, srng);
348
349 spin_unlock_bh(&srng->lock);
350
351 return req_entries - num_remain;
352
353 fail_idr_remove:
354 spin_lock_bh(&rx_ring->idr_lock);
355 idr_remove(&rx_ring->bufs_idr, buf_id);
356 spin_unlock_bh(&rx_ring->idr_lock);
357 fail_dma_unmap:
358 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
359 DMA_FROM_DEVICE);
360 fail_free_skb:
361 dev_kfree_skb_any(skb);
362
363 ath11k_hal_srng_access_end(ab, srng);
364
365 spin_unlock_bh(&srng->lock);
366
367 return req_entries - num_remain;
368 }
369
ath11k_dp_rxdma_buf_ring_free(struct ath11k * ar,struct dp_rxdma_ring * rx_ring)370 static int ath11k_dp_rxdma_buf_ring_free(struct ath11k *ar,
371 struct dp_rxdma_ring *rx_ring)
372 {
373 struct ath11k_pdev_dp *dp = &ar->dp;
374 struct sk_buff *skb;
375 int buf_id;
376
377 spin_lock_bh(&rx_ring->idr_lock);
378 idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
379 idr_remove(&rx_ring->bufs_idr, buf_id);
380 /* TODO: Understand where internal driver does this dma_unmap of
381 * of rxdma_buffer.
382 */
383 dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr,
384 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
385 dev_kfree_skb_any(skb);
386 }
387
388 idr_destroy(&rx_ring->bufs_idr);
389 spin_unlock_bh(&rx_ring->idr_lock);
390
391 /* if rxdma1_enable is false, mon_status_refill_ring
392 * isn't setup, so don't clean.
393 */
394 if (!ar->ab->hw_params.rxdma1_enable)
395 return 0;
396
397 rx_ring = &dp->rx_mon_status_refill_ring[0];
398
399 spin_lock_bh(&rx_ring->idr_lock);
400 idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
401 idr_remove(&rx_ring->bufs_idr, buf_id);
402 /* XXX: Understand where internal driver does this dma_unmap of
403 * of rxdma_buffer.
404 */
405 dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr,
406 skb->len + skb_tailroom(skb), DMA_BIDIRECTIONAL);
407 dev_kfree_skb_any(skb);
408 }
409
410 idr_destroy(&rx_ring->bufs_idr);
411 spin_unlock_bh(&rx_ring->idr_lock);
412
413 return 0;
414 }
415
ath11k_dp_rxdma_pdev_buf_free(struct ath11k * ar)416 static int ath11k_dp_rxdma_pdev_buf_free(struct ath11k *ar)
417 {
418 struct ath11k_pdev_dp *dp = &ar->dp;
419 struct ath11k_base *ab = ar->ab;
420 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
421 int i;
422
423 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
424
425 rx_ring = &dp->rxdma_mon_buf_ring;
426 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
427
428 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
429 rx_ring = &dp->rx_mon_status_refill_ring[i];
430 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
431 }
432
433 return 0;
434 }
435
ath11k_dp_rxdma_ring_buf_setup(struct ath11k * ar,struct dp_rxdma_ring * rx_ring,u32 ringtype)436 static int ath11k_dp_rxdma_ring_buf_setup(struct ath11k *ar,
437 struct dp_rxdma_ring *rx_ring,
438 u32 ringtype)
439 {
440 struct ath11k_pdev_dp *dp = &ar->dp;
441 int num_entries;
442
443 num_entries = rx_ring->refill_buf_ring.size /
444 ath11k_hal_srng_get_entrysize(ar->ab, ringtype);
445
446 rx_ring->bufs_max = num_entries;
447 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, rx_ring, num_entries,
448 HAL_RX_BUF_RBM_SW3_BM);
449 return 0;
450 }
451
ath11k_dp_rxdma_pdev_buf_setup(struct ath11k * ar)452 static int ath11k_dp_rxdma_pdev_buf_setup(struct ath11k *ar)
453 {
454 struct ath11k_pdev_dp *dp = &ar->dp;
455 struct ath11k_base *ab = ar->ab;
456 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
457 int i;
458
459 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_BUF);
460
461 if (ar->ab->hw_params.rxdma1_enable) {
462 rx_ring = &dp->rxdma_mon_buf_ring;
463 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_BUF);
464 }
465
466 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
467 rx_ring = &dp->rx_mon_status_refill_ring[i];
468 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_STATUS);
469 }
470
471 return 0;
472 }
473
ath11k_dp_rx_pdev_srng_free(struct ath11k * ar)474 static void ath11k_dp_rx_pdev_srng_free(struct ath11k *ar)
475 {
476 struct ath11k_pdev_dp *dp = &ar->dp;
477 struct ath11k_base *ab = ar->ab;
478 int i;
479
480 ath11k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring);
481
482 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
483 if (ab->hw_params.rx_mac_buf_ring)
484 ath11k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]);
485
486 ath11k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]);
487 ath11k_dp_srng_cleanup(ab,
488 &dp->rx_mon_status_refill_ring[i].refill_buf_ring);
489 }
490
491 ath11k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring);
492 }
493
ath11k_dp_pdev_reo_cleanup(struct ath11k_base * ab)494 void ath11k_dp_pdev_reo_cleanup(struct ath11k_base *ab)
495 {
496 struct ath11k_dp *dp = &ab->dp;
497 int i;
498
499 for (i = 0; i < DP_REO_DST_RING_MAX; i++)
500 ath11k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]);
501 }
502
ath11k_dp_pdev_reo_setup(struct ath11k_base * ab)503 int ath11k_dp_pdev_reo_setup(struct ath11k_base *ab)
504 {
505 struct ath11k_dp *dp = &ab->dp;
506 int ret;
507 int i;
508
509 for (i = 0; i < DP_REO_DST_RING_MAX; i++) {
510 ret = ath11k_dp_srng_setup(ab, &dp->reo_dst_ring[i],
511 HAL_REO_DST, i, 0,
512 DP_REO_DST_RING_SIZE);
513 if (ret) {
514 ath11k_warn(ab, "failed to setup reo_dst_ring\n");
515 goto err_reo_cleanup;
516 }
517 }
518
519 return 0;
520
521 err_reo_cleanup:
522 ath11k_dp_pdev_reo_cleanup(ab);
523
524 return ret;
525 }
526
ath11k_dp_rx_pdev_srng_alloc(struct ath11k * ar)527 static int ath11k_dp_rx_pdev_srng_alloc(struct ath11k *ar)
528 {
529 struct ath11k_pdev_dp *dp = &ar->dp;
530 struct ath11k_base *ab = ar->ab;
531 struct dp_srng *srng = NULL;
532 int i;
533 int ret;
534
535 ret = ath11k_dp_srng_setup(ar->ab,
536 &dp->rx_refill_buf_ring.refill_buf_ring,
537 HAL_RXDMA_BUF, 0,
538 dp->mac_id, DP_RXDMA_BUF_RING_SIZE);
539 if (ret) {
540 ath11k_warn(ar->ab, "failed to setup rx_refill_buf_ring\n");
541 return ret;
542 }
543
544 if (ar->ab->hw_params.rx_mac_buf_ring) {
545 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
546 ret = ath11k_dp_srng_setup(ar->ab,
547 &dp->rx_mac_buf_ring[i],
548 HAL_RXDMA_BUF, 1,
549 dp->mac_id + i, 1024);
550 if (ret) {
551 ath11k_warn(ar->ab, "failed to setup rx_mac_buf_ring %d\n",
552 i);
553 return ret;
554 }
555 }
556 }
557
558 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
559 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_err_dst_ring[i],
560 HAL_RXDMA_DST, 0, dp->mac_id + i,
561 DP_RXDMA_ERR_DST_RING_SIZE);
562 if (ret) {
563 ath11k_warn(ar->ab, "failed to setup rxdma_err_dst_ring %d\n", i);
564 return ret;
565 }
566 }
567
568 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
569 srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring;
570 ret = ath11k_dp_srng_setup(ar->ab,
571 srng,
572 HAL_RXDMA_MONITOR_STATUS, 0, dp->mac_id + i,
573 DP_RXDMA_MON_STATUS_RING_SIZE);
574 if (ret) {
575 ath11k_warn(ar->ab,
576 "failed to setup rx_mon_status_refill_ring %d\n", i);
577 return ret;
578 }
579 }
580
581 /* if rxdma1_enable is false, then it doesn't need
582 * to setup rxdam_mon_buf_ring, rxdma_mon_dst_ring
583 * and rxdma_mon_desc_ring.
584 * init reap timer for QCA6390.
585 */
586 if (!ar->ab->hw_params.rxdma1_enable) {
587 //init mon status buffer reap timer
588 timer_setup(&ar->ab->mon_reap_timer,
589 ath11k_dp_service_mon_ring, 0);
590 return 0;
591 }
592
593 ret = ath11k_dp_srng_setup(ar->ab,
594 &dp->rxdma_mon_buf_ring.refill_buf_ring,
595 HAL_RXDMA_MONITOR_BUF, 0, dp->mac_id,
596 DP_RXDMA_MONITOR_BUF_RING_SIZE);
597 if (ret) {
598 ath11k_warn(ar->ab,
599 "failed to setup HAL_RXDMA_MONITOR_BUF\n");
600 return ret;
601 }
602
603 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_dst_ring,
604 HAL_RXDMA_MONITOR_DST, 0, dp->mac_id,
605 DP_RXDMA_MONITOR_DST_RING_SIZE);
606 if (ret) {
607 ath11k_warn(ar->ab,
608 "failed to setup HAL_RXDMA_MONITOR_DST\n");
609 return ret;
610 }
611
612 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_desc_ring,
613 HAL_RXDMA_MONITOR_DESC, 0, dp->mac_id,
614 DP_RXDMA_MONITOR_DESC_RING_SIZE);
615 if (ret) {
616 ath11k_warn(ar->ab,
617 "failed to setup HAL_RXDMA_MONITOR_DESC\n");
618 return ret;
619 }
620
621 return 0;
622 }
623
ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base * ab)624 void ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base *ab)
625 {
626 struct ath11k_dp *dp = &ab->dp;
627 struct dp_reo_cmd *cmd, *tmp;
628 struct dp_reo_cache_flush_elem *cmd_cache, *tmp_cache;
629
630 spin_lock_bh(&dp->reo_cmd_lock);
631 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
632 list_del(&cmd->list);
633 dma_unmap_single(ab->dev, cmd->data.paddr,
634 cmd->data.size, DMA_BIDIRECTIONAL);
635 kfree(cmd->data.vaddr);
636 kfree(cmd);
637 }
638
639 list_for_each_entry_safe(cmd_cache, tmp_cache,
640 &dp->reo_cmd_cache_flush_list, list) {
641 list_del(&cmd_cache->list);
642 dp->reo_cmd_cache_flush_count--;
643 dma_unmap_single(ab->dev, cmd_cache->data.paddr,
644 cmd_cache->data.size, DMA_BIDIRECTIONAL);
645 kfree(cmd_cache->data.vaddr);
646 kfree(cmd_cache);
647 }
648 spin_unlock_bh(&dp->reo_cmd_lock);
649 }
650
ath11k_dp_reo_cmd_free(struct ath11k_dp * dp,void * ctx,enum hal_reo_cmd_status status)651 static void ath11k_dp_reo_cmd_free(struct ath11k_dp *dp, void *ctx,
652 enum hal_reo_cmd_status status)
653 {
654 struct dp_rx_tid *rx_tid = ctx;
655
656 if (status != HAL_REO_CMD_SUCCESS)
657 ath11k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n",
658 rx_tid->tid, status);
659
660 dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size,
661 DMA_BIDIRECTIONAL);
662 kfree(rx_tid->vaddr);
663 }
664
ath11k_dp_reo_cache_flush(struct ath11k_base * ab,struct dp_rx_tid * rx_tid)665 static void ath11k_dp_reo_cache_flush(struct ath11k_base *ab,
666 struct dp_rx_tid *rx_tid)
667 {
668 struct ath11k_hal_reo_cmd cmd = {0};
669 unsigned long tot_desc_sz, desc_sz;
670 int ret;
671
672 tot_desc_sz = rx_tid->size;
673 desc_sz = ath11k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID);
674
675 while (tot_desc_sz > desc_sz) {
676 tot_desc_sz -= desc_sz;
677 cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz);
678 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
679 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
680 HAL_REO_CMD_FLUSH_CACHE, &cmd,
681 NULL);
682 if (ret)
683 ath11k_warn(ab,
684 "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n",
685 rx_tid->tid, ret);
686 }
687
688 memset(&cmd, 0, sizeof(cmd));
689 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
690 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
691 cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
692 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
693 HAL_REO_CMD_FLUSH_CACHE,
694 &cmd, ath11k_dp_reo_cmd_free);
695 if (ret) {
696 ath11k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n",
697 rx_tid->tid, ret);
698 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
699 DMA_BIDIRECTIONAL);
700 kfree(rx_tid->vaddr);
701 }
702 }
703
ath11k_dp_rx_tid_del_func(struct ath11k_dp * dp,void * ctx,enum hal_reo_cmd_status status)704 static void ath11k_dp_rx_tid_del_func(struct ath11k_dp *dp, void *ctx,
705 enum hal_reo_cmd_status status)
706 {
707 struct ath11k_base *ab = dp->ab;
708 struct dp_rx_tid *rx_tid = ctx;
709 struct dp_reo_cache_flush_elem *elem, *tmp;
710
711 if (status == HAL_REO_CMD_DRAIN) {
712 goto free_desc;
713 } else if (status != HAL_REO_CMD_SUCCESS) {
714 /* Shouldn't happen! Cleanup in case of other failure? */
715 ath11k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n",
716 rx_tid->tid, status);
717 return;
718 }
719
720 elem = kzalloc(sizeof(*elem), GFP_ATOMIC);
721 if (!elem)
722 goto free_desc;
723
724 elem->ts = jiffies;
725 memcpy(&elem->data, rx_tid, sizeof(*rx_tid));
726
727 spin_lock_bh(&dp->reo_cmd_lock);
728 list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list);
729 dp->reo_cmd_cache_flush_count++;
730
731 /* Flush and invalidate aged REO desc from HW cache */
732 list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list,
733 list) {
734 if (dp->reo_cmd_cache_flush_count > DP_REO_DESC_FREE_THRESHOLD ||
735 time_after(jiffies, elem->ts +
736 msecs_to_jiffies(DP_REO_DESC_FREE_TIMEOUT_MS))) {
737 list_del(&elem->list);
738 dp->reo_cmd_cache_flush_count--;
739 spin_unlock_bh(&dp->reo_cmd_lock);
740
741 ath11k_dp_reo_cache_flush(ab, &elem->data);
742 kfree(elem);
743 spin_lock_bh(&dp->reo_cmd_lock);
744 }
745 }
746 spin_unlock_bh(&dp->reo_cmd_lock);
747
748 return;
749 free_desc:
750 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
751 DMA_BIDIRECTIONAL);
752 kfree(rx_tid->vaddr);
753 }
754
ath11k_peer_rx_tid_delete(struct ath11k * ar,struct ath11k_peer * peer,u8 tid)755 void ath11k_peer_rx_tid_delete(struct ath11k *ar,
756 struct ath11k_peer *peer, u8 tid)
757 {
758 struct ath11k_hal_reo_cmd cmd = {0};
759 struct dp_rx_tid *rx_tid = &peer->rx_tid[tid];
760 int ret;
761
762 if (!rx_tid->active)
763 return;
764
765 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
766 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
767 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
768 cmd.upd0 |= HAL_REO_CMD_UPD0_VLD;
769 ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
770 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
771 ath11k_dp_rx_tid_del_func);
772 if (ret) {
773 ath11k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n",
774 tid, ret);
775 dma_unmap_single(ar->ab->dev, rx_tid->paddr, rx_tid->size,
776 DMA_BIDIRECTIONAL);
777 kfree(rx_tid->vaddr);
778 }
779
780 rx_tid->active = false;
781 }
782
ath11k_dp_rx_link_desc_return(struct ath11k_base * ab,u32 * link_desc,enum hal_wbm_rel_bm_act action)783 static int ath11k_dp_rx_link_desc_return(struct ath11k_base *ab,
784 u32 *link_desc,
785 enum hal_wbm_rel_bm_act action)
786 {
787 struct ath11k_dp *dp = &ab->dp;
788 struct hal_srng *srng;
789 u32 *desc;
790 int ret = 0;
791
792 srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id];
793
794 spin_lock_bh(&srng->lock);
795
796 ath11k_hal_srng_access_begin(ab, srng);
797
798 desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
799 if (!desc) {
800 ret = -ENOBUFS;
801 goto exit;
802 }
803
804 ath11k_hal_rx_msdu_link_desc_set(ab, (void *)desc, (void *)link_desc,
805 action);
806
807 exit:
808 ath11k_hal_srng_access_end(ab, srng);
809
810 spin_unlock_bh(&srng->lock);
811
812 return ret;
813 }
814
ath11k_dp_rx_frags_cleanup(struct dp_rx_tid * rx_tid,bool rel_link_desc)815 static void ath11k_dp_rx_frags_cleanup(struct dp_rx_tid *rx_tid, bool rel_link_desc)
816 {
817 struct ath11k_base *ab = rx_tid->ab;
818
819 lockdep_assert_held(&ab->base_lock);
820
821 if (rx_tid->dst_ring_desc) {
822 if (rel_link_desc)
823 ath11k_dp_rx_link_desc_return(ab, (u32 *)rx_tid->dst_ring_desc,
824 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
825 kfree(rx_tid->dst_ring_desc);
826 rx_tid->dst_ring_desc = NULL;
827 }
828
829 rx_tid->cur_sn = 0;
830 rx_tid->last_frag_no = 0;
831 rx_tid->rx_frag_bitmap = 0;
832 __skb_queue_purge(&rx_tid->rx_frags);
833 }
834
ath11k_peer_frags_flush(struct ath11k * ar,struct ath11k_peer * peer)835 void ath11k_peer_frags_flush(struct ath11k *ar, struct ath11k_peer *peer)
836 {
837 struct dp_rx_tid *rx_tid;
838 int i;
839
840 lockdep_assert_held(&ar->ab->base_lock);
841
842 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
843 rx_tid = &peer->rx_tid[i];
844
845 spin_unlock_bh(&ar->ab->base_lock);
846 del_timer_sync(&rx_tid->frag_timer);
847 spin_lock_bh(&ar->ab->base_lock);
848
849 ath11k_dp_rx_frags_cleanup(rx_tid, true);
850 }
851 }
852
ath11k_peer_rx_tid_cleanup(struct ath11k * ar,struct ath11k_peer * peer)853 void ath11k_peer_rx_tid_cleanup(struct ath11k *ar, struct ath11k_peer *peer)
854 {
855 struct dp_rx_tid *rx_tid;
856 int i;
857
858 lockdep_assert_held(&ar->ab->base_lock);
859
860 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
861 rx_tid = &peer->rx_tid[i];
862
863 ath11k_peer_rx_tid_delete(ar, peer, i);
864 ath11k_dp_rx_frags_cleanup(rx_tid, true);
865
866 spin_unlock_bh(&ar->ab->base_lock);
867 del_timer_sync(&rx_tid->frag_timer);
868 spin_lock_bh(&ar->ab->base_lock);
869 }
870 }
871
ath11k_peer_rx_tid_reo_update(struct ath11k * ar,struct ath11k_peer * peer,struct dp_rx_tid * rx_tid,u32 ba_win_sz,u16 ssn,bool update_ssn)872 static int ath11k_peer_rx_tid_reo_update(struct ath11k *ar,
873 struct ath11k_peer *peer,
874 struct dp_rx_tid *rx_tid,
875 u32 ba_win_sz, u16 ssn,
876 bool update_ssn)
877 {
878 struct ath11k_hal_reo_cmd cmd = {0};
879 int ret;
880
881 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
882 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
883 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
884 cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE;
885 cmd.ba_window_size = ba_win_sz;
886
887 if (update_ssn) {
888 cmd.upd0 |= HAL_REO_CMD_UPD0_SSN;
889 cmd.upd2 = FIELD_PREP(HAL_REO_CMD_UPD2_SSN, ssn);
890 }
891
892 ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
893 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
894 NULL);
895 if (ret) {
896 ath11k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n",
897 rx_tid->tid, ret);
898 return ret;
899 }
900
901 rx_tid->ba_win_sz = ba_win_sz;
902
903 return 0;
904 }
905
ath11k_dp_rx_tid_mem_free(struct ath11k_base * ab,const u8 * peer_mac,int vdev_id,u8 tid)906 static void ath11k_dp_rx_tid_mem_free(struct ath11k_base *ab,
907 const u8 *peer_mac, int vdev_id, u8 tid)
908 {
909 struct ath11k_peer *peer;
910 struct dp_rx_tid *rx_tid;
911
912 spin_lock_bh(&ab->base_lock);
913
914 peer = ath11k_peer_find(ab, vdev_id, peer_mac);
915 if (!peer) {
916 ath11k_warn(ab, "failed to find the peer to free up rx tid mem\n");
917 goto unlock_exit;
918 }
919
920 rx_tid = &peer->rx_tid[tid];
921 if (!rx_tid->active)
922 goto unlock_exit;
923
924 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
925 DMA_BIDIRECTIONAL);
926 kfree(rx_tid->vaddr);
927
928 rx_tid->active = false;
929
930 unlock_exit:
931 spin_unlock_bh(&ab->base_lock);
932 }
933
ath11k_peer_rx_tid_setup(struct ath11k * ar,const u8 * peer_mac,int vdev_id,u8 tid,u32 ba_win_sz,u16 ssn,enum hal_pn_type pn_type)934 int ath11k_peer_rx_tid_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id,
935 u8 tid, u32 ba_win_sz, u16 ssn,
936 enum hal_pn_type pn_type)
937 {
938 struct ath11k_base *ab = ar->ab;
939 struct ath11k_peer *peer;
940 struct dp_rx_tid *rx_tid;
941 u32 hw_desc_sz;
942 u32 *addr_aligned;
943 void *vaddr;
944 dma_addr_t paddr;
945 int ret;
946
947 spin_lock_bh(&ab->base_lock);
948
949 peer = ath11k_peer_find(ab, vdev_id, peer_mac);
950 if (!peer) {
951 ath11k_warn(ab, "failed to find the peer to set up rx tid\n");
952 spin_unlock_bh(&ab->base_lock);
953 return -ENOENT;
954 }
955
956 rx_tid = &peer->rx_tid[tid];
957 /* Update the tid queue if it is already setup */
958 if (rx_tid->active) {
959 paddr = rx_tid->paddr;
960 ret = ath11k_peer_rx_tid_reo_update(ar, peer, rx_tid,
961 ba_win_sz, ssn, true);
962 spin_unlock_bh(&ab->base_lock);
963 if (ret) {
964 ath11k_warn(ab, "failed to update reo for rx tid %d\n", tid);
965 return ret;
966 }
967
968 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
969 peer_mac, paddr,
970 tid, 1, ba_win_sz);
971 if (ret)
972 ath11k_warn(ab, "failed to send wmi command to update rx reorder queue, tid :%d (%d)\n",
973 tid, ret);
974 return ret;
975 }
976
977 rx_tid->tid = tid;
978
979 rx_tid->ba_win_sz = ba_win_sz;
980
981 /* TODO: Optimize the memory allocation for qos tid based on the
982 * the actual BA window size in REO tid update path.
983 */
984 if (tid == HAL_DESC_REO_NON_QOS_TID)
985 hw_desc_sz = ath11k_hal_reo_qdesc_size(ba_win_sz, tid);
986 else
987 hw_desc_sz = ath11k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid);
988
989 vaddr = kzalloc(hw_desc_sz + HAL_LINK_DESC_ALIGN - 1, GFP_ATOMIC);
990 if (!vaddr) {
991 spin_unlock_bh(&ab->base_lock);
992 return -ENOMEM;
993 }
994
995 addr_aligned = PTR_ALIGN(vaddr, HAL_LINK_DESC_ALIGN);
996
997 ath11k_hal_reo_qdesc_setup(addr_aligned, tid, ba_win_sz,
998 ssn, pn_type);
999
1000 paddr = dma_map_single(ab->dev, addr_aligned, hw_desc_sz,
1001 DMA_BIDIRECTIONAL);
1002
1003 ret = dma_mapping_error(ab->dev, paddr);
1004 if (ret) {
1005 spin_unlock_bh(&ab->base_lock);
1006 goto err_mem_free;
1007 }
1008
1009 rx_tid->vaddr = vaddr;
1010 rx_tid->paddr = paddr;
1011 rx_tid->size = hw_desc_sz;
1012 rx_tid->active = true;
1013
1014 spin_unlock_bh(&ab->base_lock);
1015
1016 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac,
1017 paddr, tid, 1, ba_win_sz);
1018 if (ret) {
1019 ath11k_warn(ar->ab, "failed to setup rx reorder queue, tid :%d (%d)\n",
1020 tid, ret);
1021 ath11k_dp_rx_tid_mem_free(ab, peer_mac, vdev_id, tid);
1022 }
1023
1024 return ret;
1025
1026 err_mem_free:
1027 kfree(vaddr);
1028
1029 return ret;
1030 }
1031
ath11k_dp_rx_ampdu_start(struct ath11k * ar,struct ieee80211_ampdu_params * params)1032 int ath11k_dp_rx_ampdu_start(struct ath11k *ar,
1033 struct ieee80211_ampdu_params *params)
1034 {
1035 struct ath11k_base *ab = ar->ab;
1036 struct ath11k_sta *arsta = (void *)params->sta->drv_priv;
1037 int vdev_id = arsta->arvif->vdev_id;
1038 int ret;
1039
1040 ret = ath11k_peer_rx_tid_setup(ar, params->sta->addr, vdev_id,
1041 params->tid, params->buf_size,
1042 params->ssn, arsta->pn_type);
1043 if (ret)
1044 ath11k_warn(ab, "failed to setup rx tid %d\n", ret);
1045
1046 return ret;
1047 }
1048
ath11k_dp_rx_ampdu_stop(struct ath11k * ar,struct ieee80211_ampdu_params * params)1049 int ath11k_dp_rx_ampdu_stop(struct ath11k *ar,
1050 struct ieee80211_ampdu_params *params)
1051 {
1052 struct ath11k_base *ab = ar->ab;
1053 struct ath11k_peer *peer;
1054 struct ath11k_sta *arsta = (void *)params->sta->drv_priv;
1055 int vdev_id = arsta->arvif->vdev_id;
1056 dma_addr_t paddr;
1057 bool active;
1058 int ret;
1059
1060 spin_lock_bh(&ab->base_lock);
1061
1062 peer = ath11k_peer_find(ab, vdev_id, params->sta->addr);
1063 if (!peer) {
1064 ath11k_warn(ab, "failed to find the peer to stop rx aggregation\n");
1065 spin_unlock_bh(&ab->base_lock);
1066 return -ENOENT;
1067 }
1068
1069 paddr = peer->rx_tid[params->tid].paddr;
1070 active = peer->rx_tid[params->tid].active;
1071
1072 if (!active) {
1073 spin_unlock_bh(&ab->base_lock);
1074 return 0;
1075 }
1076
1077 ret = ath11k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false);
1078 spin_unlock_bh(&ab->base_lock);
1079 if (ret) {
1080 ath11k_warn(ab, "failed to update reo for rx tid %d: %d\n",
1081 params->tid, ret);
1082 return ret;
1083 }
1084
1085 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
1086 params->sta->addr, paddr,
1087 params->tid, 1, 1);
1088 if (ret)
1089 ath11k_warn(ab, "failed to send wmi to delete rx tid %d\n",
1090 ret);
1091
1092 return ret;
1093 }
1094
ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif * arvif,const u8 * peer_addr,enum set_key_cmd key_cmd,struct ieee80211_key_conf * key)1095 int ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif *arvif,
1096 const u8 *peer_addr,
1097 enum set_key_cmd key_cmd,
1098 struct ieee80211_key_conf *key)
1099 {
1100 struct ath11k *ar = arvif->ar;
1101 struct ath11k_base *ab = ar->ab;
1102 struct ath11k_hal_reo_cmd cmd = {0};
1103 struct ath11k_peer *peer;
1104 struct dp_rx_tid *rx_tid;
1105 u8 tid;
1106 int ret = 0;
1107
1108 /* NOTE: Enable PN/TSC replay check offload only for unicast frames.
1109 * We use mac80211 PN/TSC replay check functionality for bcast/mcast
1110 * for now.
1111 */
1112 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
1113 return 0;
1114
1115 cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
1116 cmd.upd0 |= HAL_REO_CMD_UPD0_PN |
1117 HAL_REO_CMD_UPD0_PN_SIZE |
1118 HAL_REO_CMD_UPD0_PN_VALID |
1119 HAL_REO_CMD_UPD0_PN_CHECK |
1120 HAL_REO_CMD_UPD0_SVLD;
1121
1122 switch (key->cipher) {
1123 case WLAN_CIPHER_SUITE_TKIP:
1124 case WLAN_CIPHER_SUITE_CCMP:
1125 case WLAN_CIPHER_SUITE_CCMP_256:
1126 case WLAN_CIPHER_SUITE_GCMP:
1127 case WLAN_CIPHER_SUITE_GCMP_256:
1128 if (key_cmd == SET_KEY) {
1129 cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK;
1130 cmd.pn_size = 48;
1131 }
1132 break;
1133 default:
1134 break;
1135 }
1136
1137 spin_lock_bh(&ab->base_lock);
1138
1139 peer = ath11k_peer_find(ab, arvif->vdev_id, peer_addr);
1140 if (!peer) {
1141 ath11k_warn(ab, "failed to find the peer to configure pn replay detection\n");
1142 spin_unlock_bh(&ab->base_lock);
1143 return -ENOENT;
1144 }
1145
1146 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) {
1147 rx_tid = &peer->rx_tid[tid];
1148 if (!rx_tid->active)
1149 continue;
1150 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
1151 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
1152 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
1153 HAL_REO_CMD_UPDATE_RX_QUEUE,
1154 &cmd, NULL);
1155 if (ret) {
1156 ath11k_warn(ab, "failed to configure rx tid %d queue for pn replay detection %d\n",
1157 tid, ret);
1158 break;
1159 }
1160 }
1161
1162 spin_unlock_bh(&ar->ab->base_lock);
1163
1164 return ret;
1165 }
1166
ath11k_get_ppdu_user_index(struct htt_ppdu_stats * ppdu_stats,u16 peer_id)1167 static inline int ath11k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats,
1168 u16 peer_id)
1169 {
1170 int i;
1171
1172 for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) {
1173 if (ppdu_stats->user_stats[i].is_valid_peer_id) {
1174 if (peer_id == ppdu_stats->user_stats[i].peer_id)
1175 return i;
1176 } else {
1177 return i;
1178 }
1179 }
1180
1181 return -EINVAL;
1182 }
1183
ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base * ab,u16 tag,u16 len,const void * ptr,void * data)1184 static int ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base *ab,
1185 u16 tag, u16 len, const void *ptr,
1186 void *data)
1187 {
1188 struct htt_ppdu_stats_info *ppdu_info;
1189 struct htt_ppdu_user_stats *user_stats;
1190 int cur_user;
1191 u16 peer_id;
1192
1193 ppdu_info = (struct htt_ppdu_stats_info *)data;
1194
1195 switch (tag) {
1196 case HTT_PPDU_STATS_TAG_COMMON:
1197 if (len < sizeof(struct htt_ppdu_stats_common)) {
1198 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1199 len, tag);
1200 return -EINVAL;
1201 }
1202 memcpy((void *)&ppdu_info->ppdu_stats.common, ptr,
1203 sizeof(struct htt_ppdu_stats_common));
1204 break;
1205 case HTT_PPDU_STATS_TAG_USR_RATE:
1206 if (len < sizeof(struct htt_ppdu_stats_user_rate)) {
1207 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1208 len, tag);
1209 return -EINVAL;
1210 }
1211
1212 peer_id = ((struct htt_ppdu_stats_user_rate *)ptr)->sw_peer_id;
1213 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1214 peer_id);
1215 if (cur_user < 0)
1216 return -EINVAL;
1217 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1218 user_stats->peer_id = peer_id;
1219 user_stats->is_valid_peer_id = true;
1220 memcpy((void *)&user_stats->rate, ptr,
1221 sizeof(struct htt_ppdu_stats_user_rate));
1222 user_stats->tlv_flags |= BIT(tag);
1223 break;
1224 case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON:
1225 if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) {
1226 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1227 len, tag);
1228 return -EINVAL;
1229 }
1230
1231 peer_id = ((struct htt_ppdu_stats_usr_cmpltn_cmn *)ptr)->sw_peer_id;
1232 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1233 peer_id);
1234 if (cur_user < 0)
1235 return -EINVAL;
1236 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1237 user_stats->peer_id = peer_id;
1238 user_stats->is_valid_peer_id = true;
1239 memcpy((void *)&user_stats->cmpltn_cmn, ptr,
1240 sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn));
1241 user_stats->tlv_flags |= BIT(tag);
1242 break;
1243 case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS:
1244 if (len <
1245 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) {
1246 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1247 len, tag);
1248 return -EINVAL;
1249 }
1250
1251 peer_id =
1252 ((struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *)ptr)->sw_peer_id;
1253 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1254 peer_id);
1255 if (cur_user < 0)
1256 return -EINVAL;
1257 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1258 user_stats->peer_id = peer_id;
1259 user_stats->is_valid_peer_id = true;
1260 memcpy((void *)&user_stats->ack_ba, ptr,
1261 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status));
1262 user_stats->tlv_flags |= BIT(tag);
1263 break;
1264 }
1265 return 0;
1266 }
1267
ath11k_dp_htt_tlv_iter(struct ath11k_base * ab,const void * ptr,size_t len,int (* iter)(struct ath11k_base * ar,u16 tag,u16 len,const void * ptr,void * data),void * data)1268 int ath11k_dp_htt_tlv_iter(struct ath11k_base *ab, const void *ptr, size_t len,
1269 int (*iter)(struct ath11k_base *ar, u16 tag, u16 len,
1270 const void *ptr, void *data),
1271 void *data)
1272 {
1273 const struct htt_tlv *tlv;
1274 const void *begin = ptr;
1275 u16 tlv_tag, tlv_len;
1276 int ret = -EINVAL;
1277
1278 while (len > 0) {
1279 if (len < sizeof(*tlv)) {
1280 ath11k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n",
1281 ptr - begin, len, sizeof(*tlv));
1282 return -EINVAL;
1283 }
1284 tlv = (struct htt_tlv *)ptr;
1285 tlv_tag = FIELD_GET(HTT_TLV_TAG, tlv->header);
1286 tlv_len = FIELD_GET(HTT_TLV_LEN, tlv->header);
1287 ptr += sizeof(*tlv);
1288 len -= sizeof(*tlv);
1289
1290 if (tlv_len > len) {
1291 ath11k_err(ab, "htt tlv parse failure of tag %hhu at byte %zd (%zu bytes left, %hhu expected)\n",
1292 tlv_tag, ptr - begin, len, tlv_len);
1293 return -EINVAL;
1294 }
1295 ret = iter(ab, tlv_tag, tlv_len, ptr, data);
1296 if (ret == -ENOMEM)
1297 return ret;
1298
1299 ptr += tlv_len;
1300 len -= tlv_len;
1301 }
1302 return 0;
1303 }
1304
ath11k_he_gi_to_nl80211_he_gi(u8 sgi)1305 static inline u32 ath11k_he_gi_to_nl80211_he_gi(u8 sgi)
1306 {
1307 u32 ret = 0;
1308
1309 switch (sgi) {
1310 case RX_MSDU_START_SGI_0_8_US:
1311 ret = NL80211_RATE_INFO_HE_GI_0_8;
1312 break;
1313 case RX_MSDU_START_SGI_1_6_US:
1314 ret = NL80211_RATE_INFO_HE_GI_1_6;
1315 break;
1316 case RX_MSDU_START_SGI_3_2_US:
1317 ret = NL80211_RATE_INFO_HE_GI_3_2;
1318 break;
1319 }
1320
1321 return ret;
1322 }
1323
1324 static void
ath11k_update_per_peer_tx_stats(struct ath11k * ar,struct htt_ppdu_stats * ppdu_stats,u8 user)1325 ath11k_update_per_peer_tx_stats(struct ath11k *ar,
1326 struct htt_ppdu_stats *ppdu_stats, u8 user)
1327 {
1328 struct ath11k_base *ab = ar->ab;
1329 struct ath11k_peer *peer;
1330 struct ieee80211_sta *sta;
1331 struct ath11k_sta *arsta;
1332 struct htt_ppdu_stats_user_rate *user_rate;
1333 struct ath11k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats;
1334 struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user];
1335 struct htt_ppdu_stats_common *common = &ppdu_stats->common;
1336 int ret;
1337 u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0;
1338 u32 succ_bytes = 0;
1339 u16 rate = 0, succ_pkts = 0;
1340 u32 tx_duration = 0;
1341 u8 tid = HTT_PPDU_STATS_NON_QOS_TID;
1342 bool is_ampdu = false;
1343
1344 if (!usr_stats)
1345 return;
1346
1347 if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE)))
1348 return;
1349
1350 if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON))
1351 is_ampdu =
1352 HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags);
1353
1354 if (usr_stats->tlv_flags &
1355 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) {
1356 succ_bytes = usr_stats->ack_ba.success_bytes;
1357 succ_pkts = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M,
1358 usr_stats->ack_ba.info);
1359 tid = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM,
1360 usr_stats->ack_ba.info);
1361 }
1362
1363 if (common->fes_duration_us)
1364 tx_duration = common->fes_duration_us;
1365
1366 user_rate = &usr_stats->rate;
1367 flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags);
1368 bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2;
1369 nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1;
1370 mcs = HTT_USR_RATE_MCS(user_rate->rate_flags);
1371 sgi = HTT_USR_RATE_GI(user_rate->rate_flags);
1372 dcm = HTT_USR_RATE_DCM(user_rate->rate_flags);
1373
1374 /* Note: If host configured fixed rates and in some other special
1375 * cases, the broadcast/management frames are sent in different rates.
1376 * Firmware rate's control to be skipped for this?
1377 */
1378
1379 if (flags == WMI_RATE_PREAMBLE_HE && mcs > 11) {
1380 ath11k_warn(ab, "Invalid HE mcs %hhd peer stats", mcs);
1381 return;
1382 }
1383
1384 if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH11K_HE_MCS_MAX) {
1385 ath11k_warn(ab, "Invalid HE mcs %hhd peer stats", mcs);
1386 return;
1387 }
1388
1389 if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH11K_VHT_MCS_MAX) {
1390 ath11k_warn(ab, "Invalid VHT mcs %hhd peer stats", mcs);
1391 return;
1392 }
1393
1394 if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH11K_HT_MCS_MAX || nss < 1)) {
1395 ath11k_warn(ab, "Invalid HT mcs %hhd nss %hhd peer stats",
1396 mcs, nss);
1397 return;
1398 }
1399
1400 if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) {
1401 ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs,
1402 flags,
1403 &rate_idx,
1404 &rate);
1405 if (ret < 0)
1406 return;
1407 }
1408
1409 rcu_read_lock();
1410 spin_lock_bh(&ab->base_lock);
1411 peer = ath11k_peer_find_by_id(ab, usr_stats->peer_id);
1412
1413 if (!peer || !peer->sta) {
1414 spin_unlock_bh(&ab->base_lock);
1415 rcu_read_unlock();
1416 return;
1417 }
1418
1419 sta = peer->sta;
1420 arsta = (struct ath11k_sta *)sta->drv_priv;
1421
1422 memset(&arsta->txrate, 0, sizeof(arsta->txrate));
1423
1424 switch (flags) {
1425 case WMI_RATE_PREAMBLE_OFDM:
1426 arsta->txrate.legacy = rate;
1427 break;
1428 case WMI_RATE_PREAMBLE_CCK:
1429 arsta->txrate.legacy = rate;
1430 break;
1431 case WMI_RATE_PREAMBLE_HT:
1432 arsta->txrate.mcs = mcs + 8 * (nss - 1);
1433 arsta->txrate.flags = RATE_INFO_FLAGS_MCS;
1434 if (sgi)
1435 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1436 break;
1437 case WMI_RATE_PREAMBLE_VHT:
1438 arsta->txrate.mcs = mcs;
1439 arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS;
1440 if (sgi)
1441 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1442 break;
1443 case WMI_RATE_PREAMBLE_HE:
1444 arsta->txrate.mcs = mcs;
1445 arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS;
1446 arsta->txrate.he_dcm = dcm;
1447 arsta->txrate.he_gi = ath11k_he_gi_to_nl80211_he_gi(sgi);
1448 arsta->txrate.he_ru_alloc = ath11k_he_ru_tones_to_nl80211_he_ru_alloc(
1449 (user_rate->ru_end -
1450 user_rate->ru_start) + 1);
1451 break;
1452 }
1453
1454 arsta->txrate.nss = nss;
1455 arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw);
1456 arsta->tx_duration += tx_duration;
1457 memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info));
1458
1459 /* PPDU stats reported for mgmt packet doesn't have valid tx bytes.
1460 * So skip peer stats update for mgmt packets.
1461 */
1462 if (tid < HTT_PPDU_STATS_NON_QOS_TID) {
1463 memset(peer_stats, 0, sizeof(*peer_stats));
1464 peer_stats->succ_pkts = succ_pkts;
1465 peer_stats->succ_bytes = succ_bytes;
1466 peer_stats->is_ampdu = is_ampdu;
1467 peer_stats->duration = tx_duration;
1468 peer_stats->ba_fails =
1469 HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) +
1470 HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags);
1471
1472 if (ath11k_debugfs_is_extd_tx_stats_enabled(ar))
1473 ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx);
1474 }
1475
1476 spin_unlock_bh(&ab->base_lock);
1477 rcu_read_unlock();
1478 }
1479
ath11k_htt_update_ppdu_stats(struct ath11k * ar,struct htt_ppdu_stats * ppdu_stats)1480 static void ath11k_htt_update_ppdu_stats(struct ath11k *ar,
1481 struct htt_ppdu_stats *ppdu_stats)
1482 {
1483 u8 user;
1484
1485 for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++)
1486 ath11k_update_per_peer_tx_stats(ar, ppdu_stats, user);
1487 }
1488
1489 static
ath11k_dp_htt_get_ppdu_desc(struct ath11k * ar,u32 ppdu_id)1490 struct htt_ppdu_stats_info *ath11k_dp_htt_get_ppdu_desc(struct ath11k *ar,
1491 u32 ppdu_id)
1492 {
1493 struct htt_ppdu_stats_info *ppdu_info;
1494
1495 spin_lock_bh(&ar->data_lock);
1496 if (!list_empty(&ar->ppdu_stats_info)) {
1497 list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) {
1498 if (ppdu_info->ppdu_id == ppdu_id) {
1499 spin_unlock_bh(&ar->data_lock);
1500 return ppdu_info;
1501 }
1502 }
1503
1504 if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) {
1505 ppdu_info = list_first_entry(&ar->ppdu_stats_info,
1506 typeof(*ppdu_info), list);
1507 list_del(&ppdu_info->list);
1508 ar->ppdu_stat_list_depth--;
1509 ath11k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats);
1510 kfree(ppdu_info);
1511 }
1512 }
1513 spin_unlock_bh(&ar->data_lock);
1514
1515 ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC);
1516 if (!ppdu_info)
1517 return NULL;
1518
1519 spin_lock_bh(&ar->data_lock);
1520 list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info);
1521 ar->ppdu_stat_list_depth++;
1522 spin_unlock_bh(&ar->data_lock);
1523
1524 return ppdu_info;
1525 }
1526
ath11k_htt_pull_ppdu_stats(struct ath11k_base * ab,struct sk_buff * skb)1527 static int ath11k_htt_pull_ppdu_stats(struct ath11k_base *ab,
1528 struct sk_buff *skb)
1529 {
1530 struct ath11k_htt_ppdu_stats_msg *msg;
1531 struct htt_ppdu_stats_info *ppdu_info;
1532 struct ath11k *ar;
1533 int ret;
1534 u8 pdev_id;
1535 u32 ppdu_id, len;
1536
1537 msg = (struct ath11k_htt_ppdu_stats_msg *)skb->data;
1538 len = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE, msg->info);
1539 pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, msg->info);
1540 ppdu_id = msg->ppdu_id;
1541
1542 rcu_read_lock();
1543 ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1544 if (!ar) {
1545 ret = -EINVAL;
1546 goto exit;
1547 }
1548
1549 if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar))
1550 trace_ath11k_htt_ppdu_stats(ar, skb->data, len);
1551
1552 ppdu_info = ath11k_dp_htt_get_ppdu_desc(ar, ppdu_id);
1553 if (!ppdu_info) {
1554 ret = -EINVAL;
1555 goto exit;
1556 }
1557
1558 ppdu_info->ppdu_id = ppdu_id;
1559 ret = ath11k_dp_htt_tlv_iter(ab, msg->data, len,
1560 ath11k_htt_tlv_ppdu_stats_parse,
1561 (void *)ppdu_info);
1562 if (ret) {
1563 ath11k_warn(ab, "Failed to parse tlv %d\n", ret);
1564 goto exit;
1565 }
1566
1567 exit:
1568 rcu_read_unlock();
1569
1570 return ret;
1571 }
1572
ath11k_htt_pktlog(struct ath11k_base * ab,struct sk_buff * skb)1573 static void ath11k_htt_pktlog(struct ath11k_base *ab, struct sk_buff *skb)
1574 {
1575 struct htt_pktlog_msg *data = (struct htt_pktlog_msg *)skb->data;
1576 struct ath_pktlog_hdr *hdr = (struct ath_pktlog_hdr *)data;
1577 struct ath11k *ar;
1578 u8 pdev_id;
1579
1580 pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, data->hdr);
1581 ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1582 if (!ar) {
1583 ath11k_warn(ab, "invalid pdev id %d on htt pktlog\n", pdev_id);
1584 return;
1585 }
1586
1587 trace_ath11k_htt_pktlog(ar, data->payload, hdr->size,
1588 ar->ab->pktlog_defs_checksum);
1589 }
1590
ath11k_htt_backpressure_event_handler(struct ath11k_base * ab,struct sk_buff * skb)1591 static void ath11k_htt_backpressure_event_handler(struct ath11k_base *ab,
1592 struct sk_buff *skb)
1593 {
1594 u32 *data = (u32 *)skb->data;
1595 u8 pdev_id, ring_type, ring_id, pdev_idx;
1596 u16 hp, tp;
1597 u32 backpressure_time;
1598 struct ath11k_bp_stats *bp_stats;
1599
1600 pdev_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_PDEV_ID_M, *data);
1601 ring_type = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_TYPE_M, *data);
1602 ring_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_ID_M, *data);
1603 ++data;
1604
1605 hp = FIELD_GET(HTT_BACKPRESSURE_EVENT_HP_M, *data);
1606 tp = FIELD_GET(HTT_BACKPRESSURE_EVENT_TP_M, *data);
1607 ++data;
1608
1609 backpressure_time = *data;
1610
1611 ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "htt backpressure event, pdev %d, ring type %d,ring id %d, hp %d tp %d, backpressure time %d\n",
1612 pdev_id, ring_type, ring_id, hp, tp, backpressure_time);
1613
1614 if (ring_type == HTT_BACKPRESSURE_UMAC_RING_TYPE) {
1615 if (ring_id >= HTT_SW_UMAC_RING_IDX_MAX)
1616 return;
1617
1618 bp_stats = &ab->soc_stats.bp_stats.umac_ring_bp_stats[ring_id];
1619 } else if (ring_type == HTT_BACKPRESSURE_LMAC_RING_TYPE) {
1620 pdev_idx = DP_HW2SW_MACID(pdev_id);
1621
1622 if (ring_id >= HTT_SW_LMAC_RING_IDX_MAX || pdev_idx >= MAX_RADIOS)
1623 return;
1624
1625 bp_stats = &ab->soc_stats.bp_stats.lmac_ring_bp_stats[ring_id][pdev_idx];
1626 } else {
1627 ath11k_warn(ab, "unknown ring type received in htt bp event %d\n",
1628 ring_type);
1629 return;
1630 }
1631
1632 spin_lock_bh(&ab->base_lock);
1633 bp_stats->hp = hp;
1634 bp_stats->tp = tp;
1635 bp_stats->count++;
1636 bp_stats->jiffies = jiffies;
1637 spin_unlock_bh(&ab->base_lock);
1638 }
1639
ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base * ab,struct sk_buff * skb)1640 void ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base *ab,
1641 struct sk_buff *skb)
1642 {
1643 struct ath11k_dp *dp = &ab->dp;
1644 struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data;
1645 enum htt_t2h_msg_type type = FIELD_GET(HTT_T2H_MSG_TYPE, *(u32 *)resp);
1646 u16 peer_id;
1647 u8 vdev_id;
1648 u8 mac_addr[ETH_ALEN];
1649 u16 peer_mac_h16;
1650 u16 ast_hash;
1651
1652 ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type);
1653
1654 switch (type) {
1655 case HTT_T2H_MSG_TYPE_VERSION_CONF:
1656 dp->htt_tgt_ver_major = FIELD_GET(HTT_T2H_VERSION_CONF_MAJOR,
1657 resp->version_msg.version);
1658 dp->htt_tgt_ver_minor = FIELD_GET(HTT_T2H_VERSION_CONF_MINOR,
1659 resp->version_msg.version);
1660 complete(&dp->htt_tgt_version_received);
1661 break;
1662 case HTT_T2H_MSG_TYPE_PEER_MAP:
1663 vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1664 resp->peer_map_ev.info);
1665 peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1666 resp->peer_map_ev.info);
1667 peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1668 resp->peer_map_ev.info1);
1669 ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1670 peer_mac_h16, mac_addr);
1671 ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0);
1672 break;
1673 case HTT_T2H_MSG_TYPE_PEER_MAP2:
1674 vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1675 resp->peer_map_ev.info);
1676 peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1677 resp->peer_map_ev.info);
1678 peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1679 resp->peer_map_ev.info1);
1680 ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1681 peer_mac_h16, mac_addr);
1682 ast_hash = FIELD_GET(HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL,
1683 resp->peer_map_ev.info2);
1684 ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash);
1685 break;
1686 case HTT_T2H_MSG_TYPE_PEER_UNMAP:
1687 case HTT_T2H_MSG_TYPE_PEER_UNMAP2:
1688 peer_id = FIELD_GET(HTT_T2H_PEER_UNMAP_INFO_PEER_ID,
1689 resp->peer_unmap_ev.info);
1690 ath11k_peer_unmap_event(ab, peer_id);
1691 break;
1692 case HTT_T2H_MSG_TYPE_PPDU_STATS_IND:
1693 ath11k_htt_pull_ppdu_stats(ab, skb);
1694 break;
1695 case HTT_T2H_MSG_TYPE_EXT_STATS_CONF:
1696 ath11k_debugfs_htt_ext_stats_handler(ab, skb);
1697 break;
1698 case HTT_T2H_MSG_TYPE_PKTLOG:
1699 ath11k_htt_pktlog(ab, skb);
1700 break;
1701 case HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND:
1702 ath11k_htt_backpressure_event_handler(ab, skb);
1703 break;
1704 default:
1705 ath11k_warn(ab, "htt event %d not handled\n", type);
1706 break;
1707 }
1708
1709 dev_kfree_skb_any(skb);
1710 }
1711
ath11k_dp_rx_msdu_coalesce(struct ath11k * ar,struct sk_buff_head * msdu_list,struct sk_buff * first,struct sk_buff * last,u8 l3pad_bytes,int msdu_len)1712 static int ath11k_dp_rx_msdu_coalesce(struct ath11k *ar,
1713 struct sk_buff_head *msdu_list,
1714 struct sk_buff *first, struct sk_buff *last,
1715 u8 l3pad_bytes, int msdu_len)
1716 {
1717 struct sk_buff *skb;
1718 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1719 int buf_first_hdr_len, buf_first_len;
1720 struct hal_rx_desc *ldesc;
1721 int space_extra;
1722 int rem_len;
1723 int buf_len;
1724
1725 /* As the msdu is spread across multiple rx buffers,
1726 * find the offset to the start of msdu for computing
1727 * the length of the msdu in the first buffer.
1728 */
1729 buf_first_hdr_len = HAL_RX_DESC_SIZE + l3pad_bytes;
1730 buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len;
1731
1732 if (WARN_ON_ONCE(msdu_len <= buf_first_len)) {
1733 skb_put(first, buf_first_hdr_len + msdu_len);
1734 skb_pull(first, buf_first_hdr_len);
1735 return 0;
1736 }
1737
1738 ldesc = (struct hal_rx_desc *)last->data;
1739 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ldesc);
1740 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ldesc);
1741
1742 /* MSDU spans over multiple buffers because the length of the MSDU
1743 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data
1744 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE.
1745 */
1746 skb_put(first, DP_RX_BUFFER_SIZE);
1747 skb_pull(first, buf_first_hdr_len);
1748
1749 /* When an MSDU spread over multiple buffers attention, MSDU_END and
1750 * MPDU_END tlvs are valid only in the last buffer. Copy those tlvs.
1751 */
1752 ath11k_dp_rx_desc_end_tlv_copy(rxcb->rx_desc, ldesc);
1753
1754 space_extra = msdu_len - (buf_first_len + skb_tailroom(first));
1755 if (space_extra > 0 &&
1756 (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) {
1757 /* Free up all buffers of the MSDU */
1758 while ((skb = __skb_dequeue(msdu_list)) != NULL) {
1759 rxcb = ATH11K_SKB_RXCB(skb);
1760 if (!rxcb->is_continuation) {
1761 dev_kfree_skb_any(skb);
1762 break;
1763 }
1764 dev_kfree_skb_any(skb);
1765 }
1766 return -ENOMEM;
1767 }
1768
1769 rem_len = msdu_len - buf_first_len;
1770 while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) {
1771 rxcb = ATH11K_SKB_RXCB(skb);
1772 if (rxcb->is_continuation)
1773 buf_len = DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE;
1774 else
1775 buf_len = rem_len;
1776
1777 if (buf_len > (DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE)) {
1778 WARN_ON_ONCE(1);
1779 dev_kfree_skb_any(skb);
1780 return -EINVAL;
1781 }
1782
1783 skb_put(skb, buf_len + HAL_RX_DESC_SIZE);
1784 skb_pull(skb, HAL_RX_DESC_SIZE);
1785 skb_copy_from_linear_data(skb, skb_put(first, buf_len),
1786 buf_len);
1787 dev_kfree_skb_any(skb);
1788
1789 rem_len -= buf_len;
1790 if (!rxcb->is_continuation)
1791 break;
1792 }
1793
1794 return 0;
1795 }
1796
ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head * msdu_list,struct sk_buff * first)1797 static struct sk_buff *ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list,
1798 struct sk_buff *first)
1799 {
1800 struct sk_buff *skb;
1801 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1802
1803 if (!rxcb->is_continuation)
1804 return first;
1805
1806 skb_queue_walk(msdu_list, skb) {
1807 rxcb = ATH11K_SKB_RXCB(skb);
1808 if (!rxcb->is_continuation)
1809 return skb;
1810 }
1811
1812 return NULL;
1813 }
1814
ath11k_dp_rx_h_csum_offload(struct sk_buff * msdu)1815 static void ath11k_dp_rx_h_csum_offload(struct sk_buff *msdu)
1816 {
1817 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1818 bool ip_csum_fail, l4_csum_fail;
1819
1820 ip_csum_fail = ath11k_dp_rx_h_attn_ip_cksum_fail(rxcb->rx_desc);
1821 l4_csum_fail = ath11k_dp_rx_h_attn_l4_cksum_fail(rxcb->rx_desc);
1822
1823 msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ?
1824 CHECKSUM_NONE : CHECKSUM_UNNECESSARY;
1825 }
1826
ath11k_dp_rx_crypto_mic_len(struct ath11k * ar,enum hal_encrypt_type enctype)1827 static int ath11k_dp_rx_crypto_mic_len(struct ath11k *ar,
1828 enum hal_encrypt_type enctype)
1829 {
1830 switch (enctype) {
1831 case HAL_ENCRYPT_TYPE_OPEN:
1832 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1833 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1834 return 0;
1835 case HAL_ENCRYPT_TYPE_CCMP_128:
1836 return IEEE80211_CCMP_MIC_LEN;
1837 case HAL_ENCRYPT_TYPE_CCMP_256:
1838 return IEEE80211_CCMP_256_MIC_LEN;
1839 case HAL_ENCRYPT_TYPE_GCMP_128:
1840 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1841 return IEEE80211_GCMP_MIC_LEN;
1842 case HAL_ENCRYPT_TYPE_WEP_40:
1843 case HAL_ENCRYPT_TYPE_WEP_104:
1844 case HAL_ENCRYPT_TYPE_WEP_128:
1845 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1846 case HAL_ENCRYPT_TYPE_WAPI:
1847 break;
1848 }
1849
1850 ath11k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype);
1851 return 0;
1852 }
1853
ath11k_dp_rx_crypto_param_len(struct ath11k * ar,enum hal_encrypt_type enctype)1854 static int ath11k_dp_rx_crypto_param_len(struct ath11k *ar,
1855 enum hal_encrypt_type enctype)
1856 {
1857 switch (enctype) {
1858 case HAL_ENCRYPT_TYPE_OPEN:
1859 return 0;
1860 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1861 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1862 return IEEE80211_TKIP_IV_LEN;
1863 case HAL_ENCRYPT_TYPE_CCMP_128:
1864 return IEEE80211_CCMP_HDR_LEN;
1865 case HAL_ENCRYPT_TYPE_CCMP_256:
1866 return IEEE80211_CCMP_256_HDR_LEN;
1867 case HAL_ENCRYPT_TYPE_GCMP_128:
1868 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1869 return IEEE80211_GCMP_HDR_LEN;
1870 case HAL_ENCRYPT_TYPE_WEP_40:
1871 case HAL_ENCRYPT_TYPE_WEP_104:
1872 case HAL_ENCRYPT_TYPE_WEP_128:
1873 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1874 case HAL_ENCRYPT_TYPE_WAPI:
1875 break;
1876 }
1877
1878 ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1879 return 0;
1880 }
1881
ath11k_dp_rx_crypto_icv_len(struct ath11k * ar,enum hal_encrypt_type enctype)1882 static int ath11k_dp_rx_crypto_icv_len(struct ath11k *ar,
1883 enum hal_encrypt_type enctype)
1884 {
1885 switch (enctype) {
1886 case HAL_ENCRYPT_TYPE_OPEN:
1887 case HAL_ENCRYPT_TYPE_CCMP_128:
1888 case HAL_ENCRYPT_TYPE_CCMP_256:
1889 case HAL_ENCRYPT_TYPE_GCMP_128:
1890 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1891 return 0;
1892 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1893 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1894 return IEEE80211_TKIP_ICV_LEN;
1895 case HAL_ENCRYPT_TYPE_WEP_40:
1896 case HAL_ENCRYPT_TYPE_WEP_104:
1897 case HAL_ENCRYPT_TYPE_WEP_128:
1898 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1899 case HAL_ENCRYPT_TYPE_WAPI:
1900 break;
1901 }
1902
1903 ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1904 return 0;
1905 }
1906
ath11k_dp_rx_h_undecap_nwifi(struct ath11k * ar,struct sk_buff * msdu,u8 * first_hdr,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)1907 static void ath11k_dp_rx_h_undecap_nwifi(struct ath11k *ar,
1908 struct sk_buff *msdu,
1909 u8 *first_hdr,
1910 enum hal_encrypt_type enctype,
1911 struct ieee80211_rx_status *status)
1912 {
1913 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1914 u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN];
1915 struct ieee80211_hdr *hdr;
1916 size_t hdr_len;
1917 u8 da[ETH_ALEN];
1918 u8 sa[ETH_ALEN];
1919 u16 qos_ctl = 0;
1920 u8 *qos;
1921
1922 /* copy SA & DA and pull decapped header */
1923 hdr = (struct ieee80211_hdr *)msdu->data;
1924 hdr_len = ieee80211_hdrlen(hdr->frame_control);
1925 ether_addr_copy(da, ieee80211_get_DA(hdr));
1926 ether_addr_copy(sa, ieee80211_get_SA(hdr));
1927 skb_pull(msdu, ieee80211_hdrlen(hdr->frame_control));
1928
1929 if (rxcb->is_first_msdu) {
1930 /* original 802.11 header is valid for the first msdu
1931 * hence we can reuse the same header
1932 */
1933 hdr = (struct ieee80211_hdr *)first_hdr;
1934 hdr_len = ieee80211_hdrlen(hdr->frame_control);
1935
1936 /* Each A-MSDU subframe will be reported as a separate MSDU,
1937 * so strip the A-MSDU bit from QoS Ctl.
1938 */
1939 if (ieee80211_is_data_qos(hdr->frame_control)) {
1940 qos = ieee80211_get_qos_ctl(hdr);
1941 qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT;
1942 }
1943 } else {
1944 /* Rebuild qos header if this is a middle/last msdu */
1945 hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
1946
1947 /* Reset the order bit as the HT_Control header is stripped */
1948 hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER));
1949
1950 qos_ctl = rxcb->tid;
1951
1952 if (ath11k_dp_rx_h_msdu_start_mesh_ctl_present(rxcb->rx_desc))
1953 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT;
1954
1955 /* TODO Add other QoS ctl fields when required */
1956
1957 /* copy decap header before overwriting for reuse below */
1958 memcpy(decap_hdr, (uint8_t *)hdr, hdr_len);
1959 }
1960
1961 if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
1962 memcpy(skb_push(msdu,
1963 ath11k_dp_rx_crypto_param_len(ar, enctype)),
1964 (void *)hdr + hdr_len,
1965 ath11k_dp_rx_crypto_param_len(ar, enctype));
1966 }
1967
1968 if (!rxcb->is_first_msdu) {
1969 memcpy(skb_push(msdu,
1970 IEEE80211_QOS_CTL_LEN), &qos_ctl,
1971 IEEE80211_QOS_CTL_LEN);
1972 memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len);
1973 return;
1974 }
1975
1976 memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
1977
1978 /* original 802.11 header has a different DA and in
1979 * case of 4addr it may also have different SA
1980 */
1981 hdr = (struct ieee80211_hdr *)msdu->data;
1982 ether_addr_copy(ieee80211_get_DA(hdr), da);
1983 ether_addr_copy(ieee80211_get_SA(hdr), sa);
1984 }
1985
ath11k_dp_rx_h_undecap_raw(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)1986 static void ath11k_dp_rx_h_undecap_raw(struct ath11k *ar, struct sk_buff *msdu,
1987 enum hal_encrypt_type enctype,
1988 struct ieee80211_rx_status *status,
1989 bool decrypted)
1990 {
1991 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1992 struct ieee80211_hdr *hdr;
1993 size_t hdr_len;
1994 size_t crypto_len;
1995
1996 if (!rxcb->is_first_msdu ||
1997 !(rxcb->is_first_msdu && rxcb->is_last_msdu)) {
1998 WARN_ON_ONCE(1);
1999 return;
2000 }
2001
2002 skb_trim(msdu, msdu->len - FCS_LEN);
2003
2004 if (!decrypted)
2005 return;
2006
2007 hdr = (void *)msdu->data;
2008
2009 /* Tail */
2010 if (status->flag & RX_FLAG_IV_STRIPPED) {
2011 skb_trim(msdu, msdu->len -
2012 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2013
2014 skb_trim(msdu, msdu->len -
2015 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2016 } else {
2017 /* MIC */
2018 if (status->flag & RX_FLAG_MIC_STRIPPED)
2019 skb_trim(msdu, msdu->len -
2020 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2021
2022 /* ICV */
2023 if (status->flag & RX_FLAG_ICV_STRIPPED)
2024 skb_trim(msdu, msdu->len -
2025 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2026 }
2027
2028 /* MMIC */
2029 if ((status->flag & RX_FLAG_MMIC_STRIPPED) &&
2030 !ieee80211_has_morefrags(hdr->frame_control) &&
2031 enctype == HAL_ENCRYPT_TYPE_TKIP_MIC)
2032 skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN);
2033
2034 /* Head */
2035 if (status->flag & RX_FLAG_IV_STRIPPED) {
2036 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2037 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2038
2039 memmove((void *)msdu->data + crypto_len,
2040 (void *)msdu->data, hdr_len);
2041 skb_pull(msdu, crypto_len);
2042 }
2043 }
2044
ath11k_dp_rx_h_find_rfc1042(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype)2045 static void *ath11k_dp_rx_h_find_rfc1042(struct ath11k *ar,
2046 struct sk_buff *msdu,
2047 enum hal_encrypt_type enctype)
2048 {
2049 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2050 struct ieee80211_hdr *hdr;
2051 size_t hdr_len, crypto_len;
2052 void *rfc1042;
2053 bool is_amsdu;
2054
2055 is_amsdu = !(rxcb->is_first_msdu && rxcb->is_last_msdu);
2056 hdr = (struct ieee80211_hdr *)ath11k_dp_rx_h_80211_hdr(rxcb->rx_desc);
2057 rfc1042 = hdr;
2058
2059 if (rxcb->is_first_msdu) {
2060 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2061 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2062
2063 rfc1042 += hdr_len + crypto_len;
2064 }
2065
2066 if (is_amsdu)
2067 rfc1042 += sizeof(struct ath11k_dp_amsdu_subframe_hdr);
2068
2069 return rfc1042;
2070 }
2071
ath11k_dp_rx_h_undecap_eth(struct ath11k * ar,struct sk_buff * msdu,u8 * first_hdr,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)2072 static void ath11k_dp_rx_h_undecap_eth(struct ath11k *ar,
2073 struct sk_buff *msdu,
2074 u8 *first_hdr,
2075 enum hal_encrypt_type enctype,
2076 struct ieee80211_rx_status *status)
2077 {
2078 struct ieee80211_hdr *hdr;
2079 struct ethhdr *eth;
2080 size_t hdr_len;
2081 u8 da[ETH_ALEN];
2082 u8 sa[ETH_ALEN];
2083 void *rfc1042;
2084
2085 rfc1042 = ath11k_dp_rx_h_find_rfc1042(ar, msdu, enctype);
2086 if (WARN_ON_ONCE(!rfc1042))
2087 return;
2088
2089 /* pull decapped header and copy SA & DA */
2090 eth = (struct ethhdr *)msdu->data;
2091 ether_addr_copy(da, eth->h_dest);
2092 ether_addr_copy(sa, eth->h_source);
2093 skb_pull(msdu, sizeof(struct ethhdr));
2094
2095 /* push rfc1042/llc/snap */
2096 memcpy(skb_push(msdu, sizeof(struct ath11k_dp_rfc1042_hdr)), rfc1042,
2097 sizeof(struct ath11k_dp_rfc1042_hdr));
2098
2099 /* push original 802.11 header */
2100 hdr = (struct ieee80211_hdr *)first_hdr;
2101 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2102
2103 if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2104 memcpy(skb_push(msdu,
2105 ath11k_dp_rx_crypto_param_len(ar, enctype)),
2106 (void *)hdr + hdr_len,
2107 ath11k_dp_rx_crypto_param_len(ar, enctype));
2108 }
2109
2110 memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2111
2112 /* original 802.11 header has a different DA and in
2113 * case of 4addr it may also have different SA
2114 */
2115 hdr = (struct ieee80211_hdr *)msdu->data;
2116 ether_addr_copy(ieee80211_get_DA(hdr), da);
2117 ether_addr_copy(ieee80211_get_SA(hdr), sa);
2118 }
2119
ath11k_dp_rx_h_undecap(struct ath11k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2120 static void ath11k_dp_rx_h_undecap(struct ath11k *ar, struct sk_buff *msdu,
2121 struct hal_rx_desc *rx_desc,
2122 enum hal_encrypt_type enctype,
2123 struct ieee80211_rx_status *status,
2124 bool decrypted)
2125 {
2126 u8 *first_hdr;
2127 u8 decap;
2128
2129 first_hdr = ath11k_dp_rx_h_80211_hdr(rx_desc);
2130 decap = ath11k_dp_rx_h_msdu_start_decap_type(rx_desc);
2131
2132 switch (decap) {
2133 case DP_RX_DECAP_TYPE_NATIVE_WIFI:
2134 ath11k_dp_rx_h_undecap_nwifi(ar, msdu, first_hdr,
2135 enctype, status);
2136 break;
2137 case DP_RX_DECAP_TYPE_RAW:
2138 ath11k_dp_rx_h_undecap_raw(ar, msdu, enctype, status,
2139 decrypted);
2140 break;
2141 case DP_RX_DECAP_TYPE_ETHERNET2_DIX:
2142 /* TODO undecap support for middle/last msdu's of amsdu */
2143 ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
2144 enctype, status);
2145 break;
2146 case DP_RX_DECAP_TYPE_8023:
2147 /* TODO: Handle undecap for these formats */
2148 break;
2149 }
2150 }
2151
ath11k_dp_rx_h_mpdu(struct ath11k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2152 static void ath11k_dp_rx_h_mpdu(struct ath11k *ar,
2153 struct sk_buff *msdu,
2154 struct hal_rx_desc *rx_desc,
2155 struct ieee80211_rx_status *rx_status)
2156 {
2157 bool fill_crypto_hdr, mcast;
2158 enum hal_encrypt_type enctype;
2159 bool is_decrypted = false;
2160 struct ieee80211_hdr *hdr;
2161 struct ath11k_peer *peer;
2162 u32 err_bitmap;
2163
2164 hdr = (struct ieee80211_hdr *)msdu->data;
2165
2166 /* PN for multicast packets will be checked in mac80211 */
2167
2168 mcast = is_multicast_ether_addr(hdr->addr1);
2169 fill_crypto_hdr = mcast;
2170
2171 spin_lock_bh(&ar->ab->base_lock);
2172 peer = ath11k_peer_find_by_addr(ar->ab, hdr->addr2);
2173 if (peer) {
2174 if (mcast)
2175 enctype = peer->sec_type_grp;
2176 else
2177 enctype = peer->sec_type;
2178 } else {
2179 enctype = HAL_ENCRYPT_TYPE_OPEN;
2180 }
2181 spin_unlock_bh(&ar->ab->base_lock);
2182
2183 err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_desc);
2184 if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap)
2185 is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_desc);
2186
2187 /* Clear per-MPDU flags while leaving per-PPDU flags intact */
2188 rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC |
2189 RX_FLAG_MMIC_ERROR |
2190 RX_FLAG_DECRYPTED |
2191 RX_FLAG_IV_STRIPPED |
2192 RX_FLAG_MMIC_STRIPPED);
2193
2194 if (err_bitmap & DP_RX_MPDU_ERR_FCS)
2195 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
2196 if (err_bitmap & DP_RX_MPDU_ERR_TKIP_MIC)
2197 rx_status->flag |= RX_FLAG_MMIC_ERROR;
2198
2199 if (is_decrypted) {
2200 rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED;
2201
2202 if (fill_crypto_hdr)
2203 rx_status->flag |= RX_FLAG_MIC_STRIPPED |
2204 RX_FLAG_ICV_STRIPPED;
2205 else
2206 rx_status->flag |= RX_FLAG_IV_STRIPPED |
2207 RX_FLAG_PN_VALIDATED;
2208 }
2209
2210 ath11k_dp_rx_h_csum_offload(msdu);
2211 ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
2212 enctype, rx_status, is_decrypted);
2213
2214 if (!is_decrypted || fill_crypto_hdr)
2215 return;
2216
2217 hdr = (void *)msdu->data;
2218 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED);
2219 }
2220
ath11k_dp_rx_h_rate(struct ath11k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2221 static void ath11k_dp_rx_h_rate(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2222 struct ieee80211_rx_status *rx_status)
2223 {
2224 struct ieee80211_supported_band *sband;
2225 enum rx_msdu_start_pkt_type pkt_type;
2226 u8 bw;
2227 u8 rate_mcs, nss;
2228 u8 sgi;
2229 bool is_cck;
2230
2231 pkt_type = ath11k_dp_rx_h_msdu_start_pkt_type(rx_desc);
2232 bw = ath11k_dp_rx_h_msdu_start_rx_bw(rx_desc);
2233 rate_mcs = ath11k_dp_rx_h_msdu_start_rate_mcs(rx_desc);
2234 nss = ath11k_dp_rx_h_msdu_start_nss(rx_desc);
2235 sgi = ath11k_dp_rx_h_msdu_start_sgi(rx_desc);
2236
2237 switch (pkt_type) {
2238 case RX_MSDU_START_PKT_TYPE_11A:
2239 case RX_MSDU_START_PKT_TYPE_11B:
2240 is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B);
2241 sband = &ar->mac.sbands[rx_status->band];
2242 rx_status->rate_idx = ath11k_mac_hw_rate_to_idx(sband, rate_mcs,
2243 is_cck);
2244 break;
2245 case RX_MSDU_START_PKT_TYPE_11N:
2246 rx_status->encoding = RX_ENC_HT;
2247 if (rate_mcs > ATH11K_HT_MCS_MAX) {
2248 ath11k_warn(ar->ab,
2249 "Received with invalid mcs in HT mode %d\n",
2250 rate_mcs);
2251 break;
2252 }
2253 rx_status->rate_idx = rate_mcs + (8 * (nss - 1));
2254 if (sgi)
2255 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2256 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2257 break;
2258 case RX_MSDU_START_PKT_TYPE_11AC:
2259 rx_status->encoding = RX_ENC_VHT;
2260 rx_status->rate_idx = rate_mcs;
2261 if (rate_mcs > ATH11K_VHT_MCS_MAX) {
2262 ath11k_warn(ar->ab,
2263 "Received with invalid mcs in VHT mode %d\n",
2264 rate_mcs);
2265 break;
2266 }
2267 rx_status->nss = nss;
2268 if (sgi)
2269 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2270 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2271 break;
2272 case RX_MSDU_START_PKT_TYPE_11AX:
2273 rx_status->rate_idx = rate_mcs;
2274 if (rate_mcs > ATH11K_HE_MCS_MAX) {
2275 ath11k_warn(ar->ab,
2276 "Received with invalid mcs in HE mode %d\n",
2277 rate_mcs);
2278 break;
2279 }
2280 rx_status->encoding = RX_ENC_HE;
2281 rx_status->nss = nss;
2282 rx_status->he_gi = ath11k_he_gi_to_nl80211_he_gi(sgi);
2283 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2284 break;
2285 }
2286 }
2287
ath11k_dp_rx_h_ppdu(struct ath11k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2288 static void ath11k_dp_rx_h_ppdu(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2289 struct ieee80211_rx_status *rx_status)
2290 {
2291 u8 channel_num;
2292 u32 center_freq;
2293 struct ieee80211_channel *channel;
2294
2295 rx_status->freq = 0;
2296 rx_status->rate_idx = 0;
2297 rx_status->nss = 0;
2298 rx_status->encoding = RX_ENC_LEGACY;
2299 rx_status->bw = RATE_INFO_BW_20;
2300
2301 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
2302
2303 channel_num = ath11k_dp_rx_h_msdu_start_freq(rx_desc);
2304 center_freq = ath11k_dp_rx_h_msdu_start_freq(rx_desc) >> 16;
2305
2306 if (center_freq >= 5935 && center_freq <= 7105) {
2307 rx_status->band = NL80211_BAND_6GHZ;
2308 } else if (channel_num >= 1 && channel_num <= 14) {
2309 rx_status->band = NL80211_BAND_2GHZ;
2310 } else if (channel_num >= 36 && channel_num <= 173) {
2311 rx_status->band = NL80211_BAND_5GHZ;
2312 } else {
2313 spin_lock_bh(&ar->data_lock);
2314 channel = ar->rx_channel;
2315 if (channel) {
2316 rx_status->band = channel->band;
2317 channel_num =
2318 ieee80211_frequency_to_channel(channel->center_freq);
2319 }
2320 spin_unlock_bh(&ar->data_lock);
2321 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "rx_desc: ",
2322 rx_desc, sizeof(struct hal_rx_desc));
2323 }
2324
2325 rx_status->freq = ieee80211_channel_to_frequency(channel_num,
2326 rx_status->band);
2327
2328 ath11k_dp_rx_h_rate(ar, rx_desc, rx_status);
2329 }
2330
ath11k_print_get_tid(struct ieee80211_hdr * hdr,char * out,size_t size)2331 static char *ath11k_print_get_tid(struct ieee80211_hdr *hdr, char *out,
2332 size_t size)
2333 {
2334 u8 *qc;
2335 int tid;
2336
2337 if (!ieee80211_is_data_qos(hdr->frame_control))
2338 return "";
2339
2340 qc = ieee80211_get_qos_ctl(hdr);
2341 tid = *qc & IEEE80211_QOS_CTL_TID_MASK;
2342 snprintf(out, size, "tid %d", tid);
2343
2344 return out;
2345 }
2346
ath11k_dp_rx_deliver_msdu(struct ath11k * ar,struct napi_struct * napi,struct sk_buff * msdu)2347 static void ath11k_dp_rx_deliver_msdu(struct ath11k *ar, struct napi_struct *napi,
2348 struct sk_buff *msdu)
2349 {
2350 static const struct ieee80211_radiotap_he known = {
2351 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
2352 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
2353 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
2354 };
2355 struct ieee80211_rx_status *status;
2356 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data;
2357 struct ieee80211_radiotap_he *he = NULL;
2358 char tid[32];
2359
2360 status = IEEE80211_SKB_RXCB(msdu);
2361 if (status->encoding == RX_ENC_HE) {
2362 he = skb_push(msdu, sizeof(known));
2363 memcpy(he, &known, sizeof(known));
2364 status->flag |= RX_FLAG_RADIOTAP_HE;
2365 }
2366
2367 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
2368 "rx skb %pK len %u peer %pM %s %s sn %u %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
2369 msdu,
2370 msdu->len,
2371 ieee80211_get_SA(hdr),
2372 ath11k_print_get_tid(hdr, tid, sizeof(tid)),
2373 is_multicast_ether_addr(ieee80211_get_DA(hdr)) ?
2374 "mcast" : "ucast",
2375 (__le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4,
2376 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "",
2377 (status->encoding == RX_ENC_HT) ? "ht" : "",
2378 (status->encoding == RX_ENC_VHT) ? "vht" : "",
2379 (status->encoding == RX_ENC_HE) ? "he" : "",
2380 (status->bw == RATE_INFO_BW_40) ? "40" : "",
2381 (status->bw == RATE_INFO_BW_80) ? "80" : "",
2382 (status->bw == RATE_INFO_BW_160) ? "160" : "",
2383 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "",
2384 status->rate_idx,
2385 status->nss,
2386 status->freq,
2387 status->band, status->flag,
2388 !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
2389 !!(status->flag & RX_FLAG_MMIC_ERROR),
2390 !!(status->flag & RX_FLAG_AMSDU_MORE));
2391
2392 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DP_RX, NULL, "dp rx msdu: ",
2393 msdu->data, msdu->len);
2394
2395 /* TODO: trace rx packet */
2396
2397 ieee80211_rx_napi(ar->hw, NULL, msdu, napi);
2398 }
2399
ath11k_dp_rx_process_msdu(struct ath11k * ar,struct sk_buff * msdu,struct sk_buff_head * msdu_list)2400 static int ath11k_dp_rx_process_msdu(struct ath11k *ar,
2401 struct sk_buff *msdu,
2402 struct sk_buff_head *msdu_list)
2403 {
2404 struct hal_rx_desc *rx_desc, *lrx_desc;
2405 struct ieee80211_rx_status rx_status = {0};
2406 struct ieee80211_rx_status *status;
2407 struct ath11k_skb_rxcb *rxcb;
2408 struct ieee80211_hdr *hdr;
2409 struct sk_buff *last_buf;
2410 u8 l3_pad_bytes;
2411 u8 *hdr_status;
2412 u16 msdu_len;
2413 int ret;
2414
2415 last_buf = ath11k_dp_rx_get_msdu_last_buf(msdu_list, msdu);
2416 if (!last_buf) {
2417 ath11k_warn(ar->ab,
2418 "No valid Rx buffer to access Atten/MSDU_END/MPDU_END tlvs\n");
2419 ret = -EIO;
2420 goto free_out;
2421 }
2422
2423 rx_desc = (struct hal_rx_desc *)msdu->data;
2424 lrx_desc = (struct hal_rx_desc *)last_buf->data;
2425 if (!ath11k_dp_rx_h_attn_msdu_done(lrx_desc)) {
2426 ath11k_warn(ar->ab, "msdu_done bit in attention is not set\n");
2427 ret = -EIO;
2428 goto free_out;
2429 }
2430
2431 rxcb = ATH11K_SKB_RXCB(msdu);
2432 rxcb->rx_desc = rx_desc;
2433 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(rx_desc);
2434 l3_pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(lrx_desc);
2435
2436 if (rxcb->is_frag) {
2437 skb_pull(msdu, HAL_RX_DESC_SIZE);
2438 } else if (!rxcb->is_continuation) {
2439 if ((msdu_len + HAL_RX_DESC_SIZE) > DP_RX_BUFFER_SIZE) {
2440 hdr_status = ath11k_dp_rx_h_80211_hdr(rx_desc);
2441 ret = -EINVAL;
2442 ath11k_warn(ar->ab, "invalid msdu len %u\n", msdu_len);
2443 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
2444 sizeof(struct ieee80211_hdr));
2445 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
2446 sizeof(struct hal_rx_desc));
2447 goto free_out;
2448 }
2449 skb_put(msdu, HAL_RX_DESC_SIZE + l3_pad_bytes + msdu_len);
2450 skb_pull(msdu, HAL_RX_DESC_SIZE + l3_pad_bytes);
2451 } else {
2452 ret = ath11k_dp_rx_msdu_coalesce(ar, msdu_list,
2453 msdu, last_buf,
2454 l3_pad_bytes, msdu_len);
2455 if (ret) {
2456 ath11k_warn(ar->ab,
2457 "failed to coalesce msdu rx buffer%d\n", ret);
2458 goto free_out;
2459 }
2460 }
2461
2462 hdr = (struct ieee80211_hdr *)msdu->data;
2463
2464 /* Process only data frames */
2465 if (!ieee80211_is_data(hdr->frame_control))
2466 return -EINVAL;
2467
2468 ath11k_dp_rx_h_ppdu(ar, rx_desc, &rx_status);
2469 ath11k_dp_rx_h_mpdu(ar, msdu, rx_desc, &rx_status);
2470
2471 rx_status.flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED;
2472
2473 status = IEEE80211_SKB_RXCB(msdu);
2474 *status = rx_status;
2475 return 0;
2476
2477 free_out:
2478 return ret;
2479 }
2480
ath11k_dp_rx_process_received_packets(struct ath11k_base * ab,struct napi_struct * napi,struct sk_buff_head * msdu_list,int * quota,int ring_id)2481 static void ath11k_dp_rx_process_received_packets(struct ath11k_base *ab,
2482 struct napi_struct *napi,
2483 struct sk_buff_head *msdu_list,
2484 int *quota, int ring_id)
2485 {
2486 struct ath11k_skb_rxcb *rxcb;
2487 struct sk_buff *msdu;
2488 struct ath11k *ar;
2489 u8 mac_id;
2490 int ret;
2491
2492 if (skb_queue_empty(msdu_list))
2493 return;
2494
2495 rcu_read_lock();
2496
2497 while (*quota && (msdu = __skb_dequeue(msdu_list))) {
2498 rxcb = ATH11K_SKB_RXCB(msdu);
2499 mac_id = rxcb->mac_id;
2500 ar = ab->pdevs[mac_id].ar;
2501 if (!rcu_dereference(ab->pdevs_active[mac_id])) {
2502 dev_kfree_skb_any(msdu);
2503 continue;
2504 }
2505
2506 if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
2507 dev_kfree_skb_any(msdu);
2508 continue;
2509 }
2510
2511 ret = ath11k_dp_rx_process_msdu(ar, msdu, msdu_list);
2512 if (ret) {
2513 ath11k_dbg(ab, ATH11K_DBG_DATA,
2514 "Unable to process msdu %d", ret);
2515 dev_kfree_skb_any(msdu);
2516 continue;
2517 }
2518
2519 ath11k_dp_rx_deliver_msdu(ar, napi, msdu);
2520 (*quota)--;
2521 }
2522
2523 rcu_read_unlock();
2524 }
2525
ath11k_dp_process_rx(struct ath11k_base * ab,int ring_id,struct napi_struct * napi,int budget)2526 int ath11k_dp_process_rx(struct ath11k_base *ab, int ring_id,
2527 struct napi_struct *napi, int budget)
2528 {
2529 struct ath11k_dp *dp = &ab->dp;
2530 struct dp_rxdma_ring *rx_ring;
2531 int num_buffs_reaped[MAX_RADIOS] = {0};
2532 struct sk_buff_head msdu_list;
2533 struct ath11k_skb_rxcb *rxcb;
2534 int total_msdu_reaped = 0;
2535 struct hal_srng *srng;
2536 struct sk_buff *msdu;
2537 int quota = budget;
2538 bool done = false;
2539 int buf_id, mac_id;
2540 struct ath11k *ar;
2541 u32 *rx_desc;
2542 int i;
2543
2544 __skb_queue_head_init(&msdu_list);
2545
2546 srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id];
2547
2548 spin_lock_bh(&srng->lock);
2549
2550 ath11k_hal_srng_access_begin(ab, srng);
2551
2552 try_again:
2553 while ((rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
2554 struct hal_reo_dest_ring desc = *(struct hal_reo_dest_ring *)rx_desc;
2555 enum hal_reo_dest_ring_push_reason push_reason;
2556 u32 cookie;
2557
2558 cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
2559 desc.buf_addr_info.info1);
2560 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
2561 cookie);
2562 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, cookie);
2563
2564 ar = ab->pdevs[mac_id].ar;
2565 rx_ring = &ar->dp.rx_refill_buf_ring;
2566 spin_lock_bh(&rx_ring->idr_lock);
2567 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
2568 if (!msdu) {
2569 ath11k_warn(ab, "frame rx with invalid buf_id %d\n",
2570 buf_id);
2571 spin_unlock_bh(&rx_ring->idr_lock);
2572 continue;
2573 }
2574
2575 idr_remove(&rx_ring->bufs_idr, buf_id);
2576 spin_unlock_bh(&rx_ring->idr_lock);
2577
2578 rxcb = ATH11K_SKB_RXCB(msdu);
2579 dma_unmap_single(ab->dev, rxcb->paddr,
2580 msdu->len + skb_tailroom(msdu),
2581 DMA_FROM_DEVICE);
2582
2583 num_buffs_reaped[mac_id]++;
2584 total_msdu_reaped++;
2585
2586 push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON,
2587 desc.info0);
2588 if (push_reason !=
2589 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) {
2590 dev_kfree_skb_any(msdu);
2591 ab->soc_stats.hal_reo_error[dp->reo_dst_ring[ring_id].ring_id]++;
2592 continue;
2593 }
2594
2595 rxcb->is_first_msdu = !!(desc.rx_msdu_info.info0 &
2596 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU);
2597 rxcb->is_last_msdu = !!(desc.rx_msdu_info.info0 &
2598 RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU);
2599 rxcb->is_continuation = !!(desc.rx_msdu_info.info0 &
2600 RX_MSDU_DESC_INFO0_MSDU_CONTINUATION);
2601 rxcb->mac_id = mac_id;
2602 rxcb->tid = FIELD_GET(HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM,
2603 desc.info0);
2604
2605 __skb_queue_tail(&msdu_list, msdu);
2606
2607 if (total_msdu_reaped >= quota && !rxcb->is_continuation) {
2608 done = true;
2609 break;
2610 }
2611 }
2612
2613 /* Hw might have updated the head pointer after we cached it.
2614 * In this case, even though there are entries in the ring we'll
2615 * get rx_desc NULL. Give the read another try with updated cached
2616 * head pointer so that we can reap complete MPDU in the current
2617 * rx processing.
2618 */
2619 if (!done && ath11k_hal_srng_dst_num_free(ab, srng, true)) {
2620 ath11k_hal_srng_access_end(ab, srng);
2621 goto try_again;
2622 }
2623
2624 ath11k_hal_srng_access_end(ab, srng);
2625
2626 spin_unlock_bh(&srng->lock);
2627
2628 if (!total_msdu_reaped)
2629 goto exit;
2630
2631 for (i = 0; i < ab->num_radios; i++) {
2632 if (!num_buffs_reaped[i])
2633 continue;
2634
2635 ar = ab->pdevs[i].ar;
2636 rx_ring = &ar->dp.rx_refill_buf_ring;
2637
2638 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
2639 HAL_RX_BUF_RBM_SW3_BM);
2640 }
2641
2642 ath11k_dp_rx_process_received_packets(ab, napi, &msdu_list,
2643 "a, ring_id);
2644
2645 exit:
2646 return budget - quota;
2647 }
2648
ath11k_dp_rx_update_peer_stats(struct ath11k_sta * arsta,struct hal_rx_mon_ppdu_info * ppdu_info)2649 static void ath11k_dp_rx_update_peer_stats(struct ath11k_sta *arsta,
2650 struct hal_rx_mon_ppdu_info *ppdu_info)
2651 {
2652 struct ath11k_rx_peer_stats *rx_stats = arsta->rx_stats;
2653 u32 num_msdu;
2654
2655 if (!rx_stats)
2656 return;
2657
2658 num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count +
2659 ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count;
2660
2661 rx_stats->num_msdu += num_msdu;
2662 rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count +
2663 ppdu_info->tcp_ack_msdu_count;
2664 rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count;
2665 rx_stats->other_msdu_count += ppdu_info->other_msdu_count;
2666
2667 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A ||
2668 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) {
2669 ppdu_info->nss = 1;
2670 ppdu_info->mcs = HAL_RX_MAX_MCS;
2671 ppdu_info->tid = IEEE80211_NUM_TIDS;
2672 }
2673
2674 if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS)
2675 rx_stats->nss_count[ppdu_info->nss - 1] += num_msdu;
2676
2677 if (ppdu_info->mcs <= HAL_RX_MAX_MCS)
2678 rx_stats->mcs_count[ppdu_info->mcs] += num_msdu;
2679
2680 if (ppdu_info->gi < HAL_RX_GI_MAX)
2681 rx_stats->gi_count[ppdu_info->gi] += num_msdu;
2682
2683 if (ppdu_info->bw < HAL_RX_BW_MAX)
2684 rx_stats->bw_count[ppdu_info->bw] += num_msdu;
2685
2686 if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX)
2687 rx_stats->coding_count[ppdu_info->ldpc] += num_msdu;
2688
2689 if (ppdu_info->tid <= IEEE80211_NUM_TIDS)
2690 rx_stats->tid_count[ppdu_info->tid] += num_msdu;
2691
2692 if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX)
2693 rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu;
2694
2695 if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX)
2696 rx_stats->reception_type[ppdu_info->reception_type] += num_msdu;
2697
2698 if (ppdu_info->is_stbc)
2699 rx_stats->stbc_count += num_msdu;
2700
2701 if (ppdu_info->beamformed)
2702 rx_stats->beamformed_count += num_msdu;
2703
2704 if (ppdu_info->num_mpdu_fcs_ok > 1)
2705 rx_stats->ampdu_msdu_count += num_msdu;
2706 else
2707 rx_stats->non_ampdu_msdu_count += num_msdu;
2708
2709 rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok;
2710 rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err;
2711 rx_stats->dcm_count += ppdu_info->dcm;
2712 rx_stats->ru_alloc_cnt[ppdu_info->ru_alloc] += num_msdu;
2713
2714 arsta->rssi_comb = ppdu_info->rssi_comb;
2715 rx_stats->rx_duration += ppdu_info->rx_duration;
2716 arsta->rx_duration = rx_stats->rx_duration;
2717 }
2718
ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base * ab,struct dp_rxdma_ring * rx_ring,int * buf_id)2719 static struct sk_buff *ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base *ab,
2720 struct dp_rxdma_ring *rx_ring,
2721 int *buf_id)
2722 {
2723 struct sk_buff *skb;
2724 dma_addr_t paddr;
2725
2726 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
2727 DP_RX_BUFFER_ALIGN_SIZE);
2728
2729 if (!skb)
2730 goto fail_alloc_skb;
2731
2732 if (!IS_ALIGNED((unsigned long)skb->data,
2733 DP_RX_BUFFER_ALIGN_SIZE)) {
2734 skb_pull(skb, PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
2735 skb->data);
2736 }
2737
2738 paddr = dma_map_single(ab->dev, skb->data,
2739 skb->len + skb_tailroom(skb),
2740 DMA_BIDIRECTIONAL);
2741 if (unlikely(dma_mapping_error(ab->dev, paddr)))
2742 goto fail_free_skb;
2743
2744 spin_lock_bh(&rx_ring->idr_lock);
2745 *buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0,
2746 rx_ring->bufs_max, GFP_ATOMIC);
2747 spin_unlock_bh(&rx_ring->idr_lock);
2748 if (*buf_id < 0)
2749 goto fail_dma_unmap;
2750
2751 ATH11K_SKB_RXCB(skb)->paddr = paddr;
2752 return skb;
2753
2754 fail_dma_unmap:
2755 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2756 DMA_BIDIRECTIONAL);
2757 fail_free_skb:
2758 dev_kfree_skb_any(skb);
2759 fail_alloc_skb:
2760 return NULL;
2761 }
2762
ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base * ab,int mac_id,struct dp_rxdma_ring * rx_ring,int req_entries,enum hal_rx_buf_return_buf_manager mgr)2763 int ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base *ab, int mac_id,
2764 struct dp_rxdma_ring *rx_ring,
2765 int req_entries,
2766 enum hal_rx_buf_return_buf_manager mgr)
2767 {
2768 struct hal_srng *srng;
2769 u32 *desc;
2770 struct sk_buff *skb;
2771 int num_free;
2772 int num_remain;
2773 int buf_id;
2774 u32 cookie;
2775 dma_addr_t paddr;
2776
2777 req_entries = min(req_entries, rx_ring->bufs_max);
2778
2779 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
2780
2781 spin_lock_bh(&srng->lock);
2782
2783 ath11k_hal_srng_access_begin(ab, srng);
2784
2785 num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
2786
2787 req_entries = min(num_free, req_entries);
2788 num_remain = req_entries;
2789
2790 while (num_remain > 0) {
2791 skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
2792 &buf_id);
2793 if (!skb)
2794 break;
2795 paddr = ATH11K_SKB_RXCB(skb)->paddr;
2796
2797 desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
2798 if (!desc)
2799 goto fail_desc_get;
2800
2801 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
2802 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
2803
2804 num_remain--;
2805
2806 ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
2807 }
2808
2809 ath11k_hal_srng_access_end(ab, srng);
2810
2811 spin_unlock_bh(&srng->lock);
2812
2813 return req_entries - num_remain;
2814
2815 fail_desc_get:
2816 spin_lock_bh(&rx_ring->idr_lock);
2817 idr_remove(&rx_ring->bufs_idr, buf_id);
2818 spin_unlock_bh(&rx_ring->idr_lock);
2819 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2820 DMA_BIDIRECTIONAL);
2821 dev_kfree_skb_any(skb);
2822 ath11k_hal_srng_access_end(ab, srng);
2823 spin_unlock_bh(&srng->lock);
2824
2825 return req_entries - num_remain;
2826 }
2827
ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base * ab,int mac_id,int * budget,struct sk_buff_head * skb_list)2828 static int ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base *ab, int mac_id,
2829 int *budget, struct sk_buff_head *skb_list)
2830 {
2831 struct ath11k *ar;
2832 struct ath11k_pdev_dp *dp;
2833 struct dp_rxdma_ring *rx_ring;
2834 struct hal_srng *srng;
2835 void *rx_mon_status_desc;
2836 struct sk_buff *skb;
2837 struct ath11k_skb_rxcb *rxcb;
2838 struct hal_tlv_hdr *tlv;
2839 u32 cookie;
2840 int buf_id, srng_id;
2841 dma_addr_t paddr;
2842 u8 rbm;
2843 int num_buffs_reaped = 0;
2844
2845 ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
2846 dp = &ar->dp;
2847 srng_id = ath11k_hw_mac_id_to_srng_id(&ab->hw_params, mac_id);
2848 rx_ring = &dp->rx_mon_status_refill_ring[srng_id];
2849
2850 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
2851
2852 spin_lock_bh(&srng->lock);
2853
2854 ath11k_hal_srng_access_begin(ab, srng);
2855 while (*budget) {
2856 *budget -= 1;
2857 rx_mon_status_desc =
2858 ath11k_hal_srng_src_peek(ab, srng);
2859 if (!rx_mon_status_desc)
2860 break;
2861
2862 ath11k_hal_rx_buf_addr_info_get(rx_mon_status_desc, &paddr,
2863 &cookie, &rbm);
2864 if (paddr) {
2865 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie);
2866
2867 spin_lock_bh(&rx_ring->idr_lock);
2868 skb = idr_find(&rx_ring->bufs_idr, buf_id);
2869 if (!skb) {
2870 ath11k_warn(ab, "rx monitor status with invalid buf_id %d\n",
2871 buf_id);
2872 spin_unlock_bh(&rx_ring->idr_lock);
2873 goto move_next;
2874 }
2875
2876 idr_remove(&rx_ring->bufs_idr, buf_id);
2877 spin_unlock_bh(&rx_ring->idr_lock);
2878
2879 rxcb = ATH11K_SKB_RXCB(skb);
2880
2881 dma_sync_single_for_cpu(ab->dev, rxcb->paddr,
2882 skb->len + skb_tailroom(skb),
2883 DMA_FROM_DEVICE);
2884
2885 dma_unmap_single(ab->dev, rxcb->paddr,
2886 skb->len + skb_tailroom(skb),
2887 DMA_BIDIRECTIONAL);
2888
2889 tlv = (struct hal_tlv_hdr *)skb->data;
2890 if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) !=
2891 HAL_RX_STATUS_BUFFER_DONE) {
2892 ath11k_warn(ab, "mon status DONE not set %lx\n",
2893 FIELD_GET(HAL_TLV_HDR_TAG,
2894 tlv->tl));
2895 dev_kfree_skb_any(skb);
2896 goto move_next;
2897 }
2898
2899 __skb_queue_tail(skb_list, skb);
2900 }
2901 move_next:
2902 skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
2903 &buf_id);
2904
2905 if (!skb) {
2906 ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, 0, 0,
2907 HAL_RX_BUF_RBM_SW3_BM);
2908 num_buffs_reaped++;
2909 break;
2910 }
2911 rxcb = ATH11K_SKB_RXCB(skb);
2912
2913 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
2914 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
2915
2916 ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, rxcb->paddr,
2917 cookie, HAL_RX_BUF_RBM_SW3_BM);
2918 ath11k_hal_srng_src_get_next_entry(ab, srng);
2919 num_buffs_reaped++;
2920 }
2921 ath11k_hal_srng_access_end(ab, srng);
2922 spin_unlock_bh(&srng->lock);
2923
2924 return num_buffs_reaped;
2925 }
2926
ath11k_dp_rx_process_mon_status(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)2927 int ath11k_dp_rx_process_mon_status(struct ath11k_base *ab, int mac_id,
2928 struct napi_struct *napi, int budget)
2929 {
2930 struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
2931 enum hal_rx_mon_status hal_status;
2932 struct sk_buff *skb;
2933 struct sk_buff_head skb_list;
2934 struct hal_rx_mon_ppdu_info ppdu_info;
2935 struct ath11k_peer *peer;
2936 struct ath11k_sta *arsta;
2937 int num_buffs_reaped = 0;
2938
2939 __skb_queue_head_init(&skb_list);
2940
2941 num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ab, mac_id, &budget,
2942 &skb_list);
2943 if (!num_buffs_reaped)
2944 goto exit;
2945
2946 while ((skb = __skb_dequeue(&skb_list))) {
2947 memset(&ppdu_info, 0, sizeof(ppdu_info));
2948 ppdu_info.peer_id = HAL_INVALID_PEERID;
2949
2950 if (ath11k_debugfs_is_pktlog_rx_stats_enabled(ar))
2951 trace_ath11k_htt_rxdesc(ar, skb->data, DP_RX_BUFFER_SIZE);
2952
2953 hal_status = ath11k_hal_rx_parse_mon_status(ab, &ppdu_info, skb);
2954
2955 if (ppdu_info.peer_id == HAL_INVALID_PEERID ||
2956 hal_status != HAL_RX_MON_STATUS_PPDU_DONE) {
2957 dev_kfree_skb_any(skb);
2958 continue;
2959 }
2960
2961 rcu_read_lock();
2962 spin_lock_bh(&ab->base_lock);
2963 peer = ath11k_peer_find_by_id(ab, ppdu_info.peer_id);
2964
2965 if (!peer || !peer->sta) {
2966 ath11k_dbg(ab, ATH11K_DBG_DATA,
2967 "failed to find the peer with peer_id %d\n",
2968 ppdu_info.peer_id);
2969 spin_unlock_bh(&ab->base_lock);
2970 rcu_read_unlock();
2971 dev_kfree_skb_any(skb);
2972 continue;
2973 }
2974
2975 arsta = (struct ath11k_sta *)peer->sta->drv_priv;
2976 ath11k_dp_rx_update_peer_stats(arsta, &ppdu_info);
2977
2978 if (ath11k_debugfs_is_pktlog_peer_valid(ar, peer->addr))
2979 trace_ath11k_htt_rxdesc(ar, skb->data, DP_RX_BUFFER_SIZE);
2980
2981 spin_unlock_bh(&ab->base_lock);
2982 rcu_read_unlock();
2983
2984 dev_kfree_skb_any(skb);
2985 }
2986 exit:
2987 return num_buffs_reaped;
2988 }
2989
ath11k_dp_rx_frag_timer(struct timer_list * timer)2990 static void ath11k_dp_rx_frag_timer(struct timer_list *timer)
2991 {
2992 struct dp_rx_tid *rx_tid = from_timer(rx_tid, timer, frag_timer);
2993
2994 spin_lock_bh(&rx_tid->ab->base_lock);
2995 if (rx_tid->last_frag_no &&
2996 rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) {
2997 spin_unlock_bh(&rx_tid->ab->base_lock);
2998 return;
2999 }
3000 ath11k_dp_rx_frags_cleanup(rx_tid, true);
3001 spin_unlock_bh(&rx_tid->ab->base_lock);
3002 }
3003
ath11k_peer_rx_frag_setup(struct ath11k * ar,const u8 * peer_mac,int vdev_id)3004 int ath11k_peer_rx_frag_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id)
3005 {
3006 struct ath11k_base *ab = ar->ab;
3007 struct crypto_shash *tfm;
3008 struct ath11k_peer *peer;
3009 struct dp_rx_tid *rx_tid;
3010 int i;
3011
3012 tfm = crypto_alloc_shash("michael_mic", 0, 0);
3013 if (IS_ERR(tfm))
3014 return PTR_ERR(tfm);
3015
3016 spin_lock_bh(&ab->base_lock);
3017
3018 peer = ath11k_peer_find(ab, vdev_id, peer_mac);
3019 if (!peer) {
3020 ath11k_warn(ab, "failed to find the peer to set up fragment info\n");
3021 spin_unlock_bh(&ab->base_lock);
3022 return -ENOENT;
3023 }
3024
3025 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
3026 rx_tid = &peer->rx_tid[i];
3027 rx_tid->ab = ab;
3028 timer_setup(&rx_tid->frag_timer, ath11k_dp_rx_frag_timer, 0);
3029 skb_queue_head_init(&rx_tid->rx_frags);
3030 }
3031
3032 peer->tfm_mmic = tfm;
3033 spin_unlock_bh(&ab->base_lock);
3034
3035 return 0;
3036 }
3037
ath11k_dp_rx_h_michael_mic(struct crypto_shash * tfm,u8 * key,struct ieee80211_hdr * hdr,u8 * data,size_t data_len,u8 * mic)3038 static int ath11k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key,
3039 struct ieee80211_hdr *hdr, u8 *data,
3040 size_t data_len, u8 *mic)
3041 {
3042 SHASH_DESC_ON_STACK(desc, tfm);
3043 u8 mic_hdr[16] = {0};
3044 u8 tid = 0;
3045 int ret;
3046
3047 if (!tfm)
3048 return -EINVAL;
3049
3050 desc->tfm = tfm;
3051
3052 ret = crypto_shash_setkey(tfm, key, 8);
3053 if (ret)
3054 goto out;
3055
3056 ret = crypto_shash_init(desc);
3057 if (ret)
3058 goto out;
3059
3060 /* TKIP MIC header */
3061 memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN);
3062 memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN);
3063 if (ieee80211_is_data_qos(hdr->frame_control))
3064 tid = ieee80211_get_tid(hdr);
3065 mic_hdr[12] = tid;
3066
3067 ret = crypto_shash_update(desc, mic_hdr, 16);
3068 if (ret)
3069 goto out;
3070 ret = crypto_shash_update(desc, data, data_len);
3071 if (ret)
3072 goto out;
3073 ret = crypto_shash_final(desc, mic);
3074 out:
3075 shash_desc_zero(desc);
3076 return ret;
3077 }
3078
ath11k_dp_rx_h_verify_tkip_mic(struct ath11k * ar,struct ath11k_peer * peer,struct sk_buff * msdu)3079 static int ath11k_dp_rx_h_verify_tkip_mic(struct ath11k *ar, struct ath11k_peer *peer,
3080 struct sk_buff *msdu)
3081 {
3082 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data;
3083 struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu);
3084 struct ieee80211_key_conf *key_conf;
3085 struct ieee80211_hdr *hdr;
3086 u8 mic[IEEE80211_CCMP_MIC_LEN];
3087 int head_len, tail_len, ret;
3088 size_t data_len;
3089 u32 hdr_len;
3090 u8 *key, *data;
3091 u8 key_idx;
3092
3093 if (ath11k_dp_rx_h_mpdu_start_enctype(rx_desc) != HAL_ENCRYPT_TYPE_TKIP_MIC)
3094 return 0;
3095
3096 hdr = (struct ieee80211_hdr *)(msdu->data + HAL_RX_DESC_SIZE);
3097 hdr_len = ieee80211_hdrlen(hdr->frame_control);
3098 head_len = hdr_len + HAL_RX_DESC_SIZE + IEEE80211_TKIP_IV_LEN;
3099 tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN;
3100
3101 if (!is_multicast_ether_addr(hdr->addr1))
3102 key_idx = peer->ucast_keyidx;
3103 else
3104 key_idx = peer->mcast_keyidx;
3105
3106 key_conf = peer->keys[key_idx];
3107
3108 data = msdu->data + head_len;
3109 data_len = msdu->len - head_len - tail_len;
3110 key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY];
3111
3112 ret = ath11k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic);
3113 if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN))
3114 goto mic_fail;
3115
3116 return 0;
3117
3118 mic_fail:
3119 (ATH11K_SKB_RXCB(msdu))->is_first_msdu = true;
3120 (ATH11K_SKB_RXCB(msdu))->is_last_msdu = true;
3121
3122 rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED |
3123 RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED;
3124 skb_pull(msdu, HAL_RX_DESC_SIZE);
3125
3126 ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
3127 ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
3128 HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true);
3129 ieee80211_rx(ar->hw, msdu);
3130 return -EINVAL;
3131 }
3132
ath11k_dp_rx_h_undecap_frag(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,u32 flags)3133 static void ath11k_dp_rx_h_undecap_frag(struct ath11k *ar, struct sk_buff *msdu,
3134 enum hal_encrypt_type enctype, u32 flags)
3135 {
3136 struct ieee80211_hdr *hdr;
3137 size_t hdr_len;
3138 size_t crypto_len;
3139
3140 if (!flags)
3141 return;
3142
3143 hdr = (struct ieee80211_hdr *)(msdu->data + HAL_RX_DESC_SIZE);
3144
3145 if (flags & RX_FLAG_MIC_STRIPPED)
3146 skb_trim(msdu, msdu->len -
3147 ath11k_dp_rx_crypto_mic_len(ar, enctype));
3148
3149 if (flags & RX_FLAG_ICV_STRIPPED)
3150 skb_trim(msdu, msdu->len -
3151 ath11k_dp_rx_crypto_icv_len(ar, enctype));
3152
3153 if (flags & RX_FLAG_IV_STRIPPED) {
3154 hdr_len = ieee80211_hdrlen(hdr->frame_control);
3155 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
3156
3157 memmove((void *)msdu->data + HAL_RX_DESC_SIZE + crypto_len,
3158 (void *)msdu->data + HAL_RX_DESC_SIZE, hdr_len);
3159 skb_pull(msdu, crypto_len);
3160 }
3161 }
3162
ath11k_dp_rx_h_defrag(struct ath11k * ar,struct ath11k_peer * peer,struct dp_rx_tid * rx_tid,struct sk_buff ** defrag_skb)3163 static int ath11k_dp_rx_h_defrag(struct ath11k *ar,
3164 struct ath11k_peer *peer,
3165 struct dp_rx_tid *rx_tid,
3166 struct sk_buff **defrag_skb)
3167 {
3168 struct hal_rx_desc *rx_desc;
3169 struct sk_buff *skb, *first_frag, *last_frag;
3170 struct ieee80211_hdr *hdr;
3171 enum hal_encrypt_type enctype;
3172 bool is_decrypted = false;
3173 int msdu_len = 0;
3174 int extra_space;
3175 u32 flags;
3176
3177 first_frag = skb_peek(&rx_tid->rx_frags);
3178 last_frag = skb_peek_tail(&rx_tid->rx_frags);
3179
3180 skb_queue_walk(&rx_tid->rx_frags, skb) {
3181 flags = 0;
3182 rx_desc = (struct hal_rx_desc *)skb->data;
3183 hdr = (struct ieee80211_hdr *)(skb->data + HAL_RX_DESC_SIZE);
3184
3185 enctype = ath11k_dp_rx_h_mpdu_start_enctype(rx_desc);
3186 if (enctype != HAL_ENCRYPT_TYPE_OPEN)
3187 is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_desc);
3188
3189 if (is_decrypted) {
3190 if (skb != first_frag)
3191 flags |= RX_FLAG_IV_STRIPPED;
3192 if (skb != last_frag)
3193 flags |= RX_FLAG_ICV_STRIPPED |
3194 RX_FLAG_MIC_STRIPPED;
3195 }
3196
3197 /* RX fragments are always raw packets */
3198 if (skb != last_frag)
3199 skb_trim(skb, skb->len - FCS_LEN);
3200 ath11k_dp_rx_h_undecap_frag(ar, skb, enctype, flags);
3201
3202 if (skb != first_frag)
3203 skb_pull(skb, HAL_RX_DESC_SIZE +
3204 ieee80211_hdrlen(hdr->frame_control));
3205 msdu_len += skb->len;
3206 }
3207
3208 extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag));
3209 if (extra_space > 0 &&
3210 (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0))
3211 return -ENOMEM;
3212
3213 __skb_unlink(first_frag, &rx_tid->rx_frags);
3214 while ((skb = __skb_dequeue(&rx_tid->rx_frags))) {
3215 skb_put_data(first_frag, skb->data, skb->len);
3216 dev_kfree_skb_any(skb);
3217 }
3218
3219 hdr = (struct ieee80211_hdr *)(first_frag->data + HAL_RX_DESC_SIZE);
3220 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS);
3221 ATH11K_SKB_RXCB(first_frag)->is_frag = 1;
3222
3223 if (ath11k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag))
3224 first_frag = NULL;
3225
3226 *defrag_skb = first_frag;
3227 return 0;
3228 }
3229
ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k * ar,struct dp_rx_tid * rx_tid,struct sk_buff * defrag_skb)3230 static int ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k *ar, struct dp_rx_tid *rx_tid,
3231 struct sk_buff *defrag_skb)
3232 {
3233 struct ath11k_base *ab = ar->ab;
3234 struct ath11k_pdev_dp *dp = &ar->dp;
3235 struct dp_rxdma_ring *rx_refill_ring = &dp->rx_refill_buf_ring;
3236 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data;
3237 struct hal_reo_entrance_ring *reo_ent_ring;
3238 struct hal_reo_dest_ring *reo_dest_ring;
3239 struct dp_link_desc_bank *link_desc_banks;
3240 struct hal_rx_msdu_link *msdu_link;
3241 struct hal_rx_msdu_details *msdu0;
3242 struct hal_srng *srng;
3243 dma_addr_t paddr;
3244 u32 desc_bank, msdu_info, mpdu_info;
3245 u32 dst_idx, cookie;
3246 u32 *msdu_len_offset;
3247 int ret, buf_id;
3248
3249 link_desc_banks = ab->dp.link_desc_banks;
3250 reo_dest_ring = rx_tid->dst_ring_desc;
3251
3252 ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3253 msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr +
3254 (paddr - link_desc_banks[desc_bank].paddr));
3255 msdu0 = &msdu_link->msdu_link[0];
3256 dst_idx = FIELD_GET(RX_MSDU_DESC_INFO0_REO_DEST_IND, msdu0->rx_msdu_info.info0);
3257 memset(msdu0, 0, sizeof(*msdu0));
3258
3259 msdu_info = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1) |
3260 FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1) |
3261 FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_CONTINUATION, 0) |
3262 FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_LENGTH,
3263 defrag_skb->len - HAL_RX_DESC_SIZE) |
3264 FIELD_PREP(RX_MSDU_DESC_INFO0_REO_DEST_IND, dst_idx) |
3265 FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_SA, 1) |
3266 FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_DA, 1);
3267 msdu0->rx_msdu_info.info0 = msdu_info;
3268
3269 /* change msdu len in hal rx desc */
3270 msdu_len_offset = (u32 *)&rx_desc->msdu_start;
3271 *msdu_len_offset &= ~(RX_MSDU_START_INFO1_MSDU_LENGTH);
3272 *msdu_len_offset |= defrag_skb->len - HAL_RX_DESC_SIZE;
3273
3274 paddr = dma_map_single(ab->dev, defrag_skb->data,
3275 defrag_skb->len + skb_tailroom(defrag_skb),
3276 DMA_FROM_DEVICE);
3277 if (dma_mapping_error(ab->dev, paddr))
3278 return -ENOMEM;
3279
3280 spin_lock_bh(&rx_refill_ring->idr_lock);
3281 buf_id = idr_alloc(&rx_refill_ring->bufs_idr, defrag_skb, 0,
3282 rx_refill_ring->bufs_max * 3, GFP_ATOMIC);
3283 spin_unlock_bh(&rx_refill_ring->idr_lock);
3284 if (buf_id < 0) {
3285 ret = -ENOMEM;
3286 goto err_unmap_dma;
3287 }
3288
3289 ATH11K_SKB_RXCB(defrag_skb)->paddr = paddr;
3290 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, dp->mac_id) |
3291 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
3292
3293 ath11k_hal_rx_buf_addr_info_set(msdu0, paddr, cookie, HAL_RX_BUF_RBM_SW3_BM);
3294
3295 /* Fill mpdu details into reo entrace ring */
3296 srng = &ab->hal.srng_list[ab->dp.reo_reinject_ring.ring_id];
3297
3298 spin_lock_bh(&srng->lock);
3299 ath11k_hal_srng_access_begin(ab, srng);
3300
3301 reo_ent_ring = (struct hal_reo_entrance_ring *)
3302 ath11k_hal_srng_src_get_next_entry(ab, srng);
3303 if (!reo_ent_ring) {
3304 ath11k_hal_srng_access_end(ab, srng);
3305 spin_unlock_bh(&srng->lock);
3306 ret = -ENOSPC;
3307 goto err_free_idr;
3308 }
3309 memset(reo_ent_ring, 0, sizeof(*reo_ent_ring));
3310
3311 ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3312 ath11k_hal_rx_buf_addr_info_set(reo_ent_ring, paddr, desc_bank,
3313 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST);
3314
3315 mpdu_info = FIELD_PREP(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1) |
3316 FIELD_PREP(RX_MPDU_DESC_INFO0_SEQ_NUM, rx_tid->cur_sn) |
3317 FIELD_PREP(RX_MPDU_DESC_INFO0_FRAG_FLAG, 0) |
3318 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_SA, 1) |
3319 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_DA, 1) |
3320 FIELD_PREP(RX_MPDU_DESC_INFO0_RAW_MPDU, 1) |
3321 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_PN, 1);
3322
3323 reo_ent_ring->rx_mpdu_info.info0 = mpdu_info;
3324 reo_ent_ring->rx_mpdu_info.meta_data = reo_dest_ring->rx_mpdu_info.meta_data;
3325 reo_ent_ring->queue_addr_lo = reo_dest_ring->queue_addr_lo;
3326 reo_ent_ring->info0 = FIELD_PREP(HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI,
3327 FIELD_GET(HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI,
3328 reo_dest_ring->info0)) |
3329 FIELD_PREP(HAL_REO_ENTR_RING_INFO0_DEST_IND, dst_idx);
3330 ath11k_hal_srng_access_end(ab, srng);
3331 spin_unlock_bh(&srng->lock);
3332
3333 return 0;
3334
3335 err_free_idr:
3336 spin_lock_bh(&rx_refill_ring->idr_lock);
3337 idr_remove(&rx_refill_ring->bufs_idr, buf_id);
3338 spin_unlock_bh(&rx_refill_ring->idr_lock);
3339 err_unmap_dma:
3340 dma_unmap_single(ab->dev, paddr, defrag_skb->len + skb_tailroom(defrag_skb),
3341 DMA_FROM_DEVICE);
3342 return ret;
3343 }
3344
ath11k_dp_rx_h_cmp_frags(struct sk_buff * a,struct sk_buff * b)3345 static int ath11k_dp_rx_h_cmp_frags(struct sk_buff *a, struct sk_buff *b)
3346 {
3347 int frag1, frag2;
3348
3349 frag1 = ath11k_dp_rx_h_mpdu_start_frag_no(a);
3350 frag2 = ath11k_dp_rx_h_mpdu_start_frag_no(b);
3351
3352 return frag1 - frag2;
3353 }
3354
ath11k_dp_rx_h_sort_frags(struct sk_buff_head * frag_list,struct sk_buff * cur_frag)3355 static void ath11k_dp_rx_h_sort_frags(struct sk_buff_head *frag_list,
3356 struct sk_buff *cur_frag)
3357 {
3358 struct sk_buff *skb;
3359 int cmp;
3360
3361 skb_queue_walk(frag_list, skb) {
3362 cmp = ath11k_dp_rx_h_cmp_frags(skb, cur_frag);
3363 if (cmp < 0)
3364 continue;
3365 __skb_queue_before(frag_list, skb, cur_frag);
3366 return;
3367 }
3368 __skb_queue_tail(frag_list, cur_frag);
3369 }
3370
ath11k_dp_rx_h_get_pn(struct sk_buff * skb)3371 static u64 ath11k_dp_rx_h_get_pn(struct sk_buff *skb)
3372 {
3373 struct ieee80211_hdr *hdr;
3374 u64 pn = 0;
3375 u8 *ehdr;
3376
3377 hdr = (struct ieee80211_hdr *)(skb->data + HAL_RX_DESC_SIZE);
3378 ehdr = skb->data + HAL_RX_DESC_SIZE + ieee80211_hdrlen(hdr->frame_control);
3379
3380 pn = ehdr[0];
3381 pn |= (u64)ehdr[1] << 8;
3382 pn |= (u64)ehdr[4] << 16;
3383 pn |= (u64)ehdr[5] << 24;
3384 pn |= (u64)ehdr[6] << 32;
3385 pn |= (u64)ehdr[7] << 40;
3386
3387 return pn;
3388 }
3389
3390 static bool
ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k * ar,struct dp_rx_tid * rx_tid)3391 ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k *ar, struct dp_rx_tid *rx_tid)
3392 {
3393 enum hal_encrypt_type encrypt_type;
3394 struct sk_buff *first_frag, *skb;
3395 struct hal_rx_desc *desc;
3396 u64 last_pn;
3397 u64 cur_pn;
3398
3399 first_frag = skb_peek(&rx_tid->rx_frags);
3400 desc = (struct hal_rx_desc *)first_frag->data;
3401
3402 encrypt_type = ath11k_dp_rx_h_mpdu_start_enctype(desc);
3403 if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 &&
3404 encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 &&
3405 encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 &&
3406 encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256)
3407 return true;
3408
3409 last_pn = ath11k_dp_rx_h_get_pn(first_frag);
3410 skb_queue_walk(&rx_tid->rx_frags, skb) {
3411 if (skb == first_frag)
3412 continue;
3413
3414 cur_pn = ath11k_dp_rx_h_get_pn(skb);
3415 if (cur_pn != last_pn + 1)
3416 return false;
3417 last_pn = cur_pn;
3418 }
3419 return true;
3420 }
3421
ath11k_dp_rx_frag_h_mpdu(struct ath11k * ar,struct sk_buff * msdu,u32 * ring_desc)3422 static int ath11k_dp_rx_frag_h_mpdu(struct ath11k *ar,
3423 struct sk_buff *msdu,
3424 u32 *ring_desc)
3425 {
3426 struct ath11k_base *ab = ar->ab;
3427 struct hal_rx_desc *rx_desc;
3428 struct ath11k_peer *peer;
3429 struct dp_rx_tid *rx_tid;
3430 struct sk_buff *defrag_skb = NULL;
3431 u32 peer_id;
3432 u16 seqno, frag_no;
3433 u8 tid;
3434 int ret = 0;
3435 bool more_frags;
3436
3437 rx_desc = (struct hal_rx_desc *)msdu->data;
3438 peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(rx_desc);
3439 tid = ath11k_dp_rx_h_mpdu_start_tid(rx_desc);
3440 seqno = ath11k_dp_rx_h_mpdu_start_seq_no(rx_desc);
3441 frag_no = ath11k_dp_rx_h_mpdu_start_frag_no(msdu);
3442 more_frags = ath11k_dp_rx_h_mpdu_start_more_frags(msdu);
3443
3444 if (!ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(rx_desc) ||
3445 !ath11k_dp_rx_h_mpdu_start_fc_valid(rx_desc) ||
3446 tid > IEEE80211_NUM_TIDS)
3447 return -EINVAL;
3448
3449 /* received unfragmented packet in reo
3450 * exception ring, this shouldn't happen
3451 * as these packets typically come from
3452 * reo2sw srngs.
3453 */
3454 if (WARN_ON_ONCE(!frag_no && !more_frags))
3455 return -EINVAL;
3456
3457 spin_lock_bh(&ab->base_lock);
3458 peer = ath11k_peer_find_by_id(ab, peer_id);
3459 if (!peer) {
3460 ath11k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n",
3461 peer_id);
3462 ret = -ENOENT;
3463 goto out_unlock;
3464 }
3465 rx_tid = &peer->rx_tid[tid];
3466
3467 if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) ||
3468 skb_queue_empty(&rx_tid->rx_frags)) {
3469 /* Flush stored fragments and start a new sequence */
3470 ath11k_dp_rx_frags_cleanup(rx_tid, true);
3471 rx_tid->cur_sn = seqno;
3472 }
3473
3474 if (rx_tid->rx_frag_bitmap & BIT(frag_no)) {
3475 /* Fragment already present */
3476 ret = -EINVAL;
3477 goto out_unlock;
3478 }
3479
3480 if (frag_no > __fls(rx_tid->rx_frag_bitmap))
3481 __skb_queue_tail(&rx_tid->rx_frags, msdu);
3482 else
3483 ath11k_dp_rx_h_sort_frags(&rx_tid->rx_frags, msdu);
3484
3485 rx_tid->rx_frag_bitmap |= BIT(frag_no);
3486 if (!more_frags)
3487 rx_tid->last_frag_no = frag_no;
3488
3489 if (frag_no == 0) {
3490 rx_tid->dst_ring_desc = kmemdup(ring_desc,
3491 sizeof(*rx_tid->dst_ring_desc),
3492 GFP_ATOMIC);
3493 if (!rx_tid->dst_ring_desc) {
3494 ret = -ENOMEM;
3495 goto out_unlock;
3496 }
3497 } else {
3498 ath11k_dp_rx_link_desc_return(ab, ring_desc,
3499 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3500 }
3501
3502 if (!rx_tid->last_frag_no ||
3503 rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) {
3504 mod_timer(&rx_tid->frag_timer, jiffies +
3505 ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS);
3506 goto out_unlock;
3507 }
3508
3509 spin_unlock_bh(&ab->base_lock);
3510 del_timer_sync(&rx_tid->frag_timer);
3511 spin_lock_bh(&ab->base_lock);
3512
3513 peer = ath11k_peer_find_by_id(ab, peer_id);
3514 if (!peer)
3515 goto err_frags_cleanup;
3516
3517 if (!ath11k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid))
3518 goto err_frags_cleanup;
3519
3520 if (ath11k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb))
3521 goto err_frags_cleanup;
3522
3523 if (!defrag_skb)
3524 goto err_frags_cleanup;
3525
3526 if (ath11k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb))
3527 goto err_frags_cleanup;
3528
3529 ath11k_dp_rx_frags_cleanup(rx_tid, false);
3530 goto out_unlock;
3531
3532 err_frags_cleanup:
3533 dev_kfree_skb_any(defrag_skb);
3534 ath11k_dp_rx_frags_cleanup(rx_tid, true);
3535 out_unlock:
3536 spin_unlock_bh(&ab->base_lock);
3537 return ret;
3538 }
3539
3540 static int
ath11k_dp_process_rx_err_buf(struct ath11k * ar,u32 * ring_desc,int buf_id,bool drop)3541 ath11k_dp_process_rx_err_buf(struct ath11k *ar, u32 *ring_desc, int buf_id, bool drop)
3542 {
3543 struct ath11k_pdev_dp *dp = &ar->dp;
3544 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
3545 struct sk_buff *msdu;
3546 struct ath11k_skb_rxcb *rxcb;
3547 struct hal_rx_desc *rx_desc;
3548 u8 *hdr_status;
3549 u16 msdu_len;
3550
3551 spin_lock_bh(&rx_ring->idr_lock);
3552 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
3553 if (!msdu) {
3554 ath11k_warn(ar->ab, "rx err buf with invalid buf_id %d\n",
3555 buf_id);
3556 spin_unlock_bh(&rx_ring->idr_lock);
3557 return -EINVAL;
3558 }
3559
3560 idr_remove(&rx_ring->bufs_idr, buf_id);
3561 spin_unlock_bh(&rx_ring->idr_lock);
3562
3563 rxcb = ATH11K_SKB_RXCB(msdu);
3564 dma_unmap_single(ar->ab->dev, rxcb->paddr,
3565 msdu->len + skb_tailroom(msdu),
3566 DMA_FROM_DEVICE);
3567
3568 if (drop) {
3569 dev_kfree_skb_any(msdu);
3570 return 0;
3571 }
3572
3573 rcu_read_lock();
3574 if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) {
3575 dev_kfree_skb_any(msdu);
3576 goto exit;
3577 }
3578
3579 if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
3580 dev_kfree_skb_any(msdu);
3581 goto exit;
3582 }
3583
3584 rx_desc = (struct hal_rx_desc *)msdu->data;
3585 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(rx_desc);
3586 if ((msdu_len + HAL_RX_DESC_SIZE) > DP_RX_BUFFER_SIZE) {
3587 hdr_status = ath11k_dp_rx_h_80211_hdr(rx_desc);
3588 ath11k_warn(ar->ab, "invalid msdu leng %u", msdu_len);
3589 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
3590 sizeof(struct ieee80211_hdr));
3591 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
3592 sizeof(struct hal_rx_desc));
3593 dev_kfree_skb_any(msdu);
3594 goto exit;
3595 }
3596
3597 skb_put(msdu, HAL_RX_DESC_SIZE + msdu_len);
3598
3599 if (ath11k_dp_rx_frag_h_mpdu(ar, msdu, ring_desc)) {
3600 dev_kfree_skb_any(msdu);
3601 ath11k_dp_rx_link_desc_return(ar->ab, ring_desc,
3602 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3603 }
3604 exit:
3605 rcu_read_unlock();
3606 return 0;
3607 }
3608
ath11k_dp_process_rx_err(struct ath11k_base * ab,struct napi_struct * napi,int budget)3609 int ath11k_dp_process_rx_err(struct ath11k_base *ab, struct napi_struct *napi,
3610 int budget)
3611 {
3612 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
3613 struct dp_link_desc_bank *link_desc_banks;
3614 enum hal_rx_buf_return_buf_manager rbm;
3615 int tot_n_bufs_reaped, quota, ret, i;
3616 int n_bufs_reaped[MAX_RADIOS] = {0};
3617 struct dp_rxdma_ring *rx_ring;
3618 struct dp_srng *reo_except;
3619 u32 desc_bank, num_msdus;
3620 struct hal_srng *srng;
3621 struct ath11k_dp *dp;
3622 void *link_desc_va;
3623 int buf_id, mac_id;
3624 struct ath11k *ar;
3625 dma_addr_t paddr;
3626 u32 *desc;
3627 bool is_frag;
3628 u8 drop = 0;
3629
3630 tot_n_bufs_reaped = 0;
3631 quota = budget;
3632
3633 dp = &ab->dp;
3634 reo_except = &dp->reo_except_ring;
3635 link_desc_banks = dp->link_desc_banks;
3636
3637 srng = &ab->hal.srng_list[reo_except->ring_id];
3638
3639 spin_lock_bh(&srng->lock);
3640
3641 ath11k_hal_srng_access_begin(ab, srng);
3642
3643 while (budget &&
3644 (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
3645 struct hal_reo_dest_ring *reo_desc = (struct hal_reo_dest_ring *)desc;
3646
3647 ab->soc_stats.err_ring_pkts++;
3648 ret = ath11k_hal_desc_reo_parse_err(ab, desc, &paddr,
3649 &desc_bank);
3650 if (ret) {
3651 ath11k_warn(ab, "failed to parse error reo desc %d\n",
3652 ret);
3653 continue;
3654 }
3655 link_desc_va = link_desc_banks[desc_bank].vaddr +
3656 (paddr - link_desc_banks[desc_bank].paddr);
3657 ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies,
3658 &rbm);
3659 if (rbm != HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST &&
3660 rbm != HAL_RX_BUF_RBM_SW3_BM) {
3661 ab->soc_stats.invalid_rbm++;
3662 ath11k_warn(ab, "invalid return buffer manager %d\n", rbm);
3663 ath11k_dp_rx_link_desc_return(ab, desc,
3664 HAL_WBM_REL_BM_ACT_REL_MSDU);
3665 continue;
3666 }
3667
3668 is_frag = !!(reo_desc->rx_mpdu_info.info0 & RX_MPDU_DESC_INFO0_FRAG_FLAG);
3669
3670 /* Process only rx fragments with one msdu per link desc below, and drop
3671 * msdu's indicated due to error reasons.
3672 */
3673 if (!is_frag || num_msdus > 1) {
3674 drop = 1;
3675 /* Return the link desc back to wbm idle list */
3676 ath11k_dp_rx_link_desc_return(ab, desc,
3677 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3678 }
3679
3680 for (i = 0; i < num_msdus; i++) {
3681 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
3682 msdu_cookies[i]);
3683
3684 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID,
3685 msdu_cookies[i]);
3686
3687 ar = ab->pdevs[mac_id].ar;
3688
3689 if (!ath11k_dp_process_rx_err_buf(ar, desc, buf_id, drop)) {
3690 n_bufs_reaped[mac_id]++;
3691 tot_n_bufs_reaped++;
3692 }
3693 }
3694
3695 if (tot_n_bufs_reaped >= quota) {
3696 tot_n_bufs_reaped = quota;
3697 goto exit;
3698 }
3699
3700 budget = quota - tot_n_bufs_reaped;
3701 }
3702
3703 exit:
3704 ath11k_hal_srng_access_end(ab, srng);
3705
3706 spin_unlock_bh(&srng->lock);
3707
3708 for (i = 0; i < ab->num_radios; i++) {
3709 if (!n_bufs_reaped[i])
3710 continue;
3711
3712 ar = ab->pdevs[i].ar;
3713 rx_ring = &ar->dp.rx_refill_buf_ring;
3714
3715 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, n_bufs_reaped[i],
3716 HAL_RX_BUF_RBM_SW3_BM);
3717 }
3718
3719 return tot_n_bufs_reaped;
3720 }
3721
ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k * ar,int msdu_len,struct sk_buff_head * msdu_list)3722 static void ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k *ar,
3723 int msdu_len,
3724 struct sk_buff_head *msdu_list)
3725 {
3726 struct sk_buff *skb, *tmp;
3727 struct ath11k_skb_rxcb *rxcb;
3728 int n_buffs;
3729
3730 n_buffs = DIV_ROUND_UP(msdu_len,
3731 (DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE));
3732
3733 skb_queue_walk_safe(msdu_list, skb, tmp) {
3734 rxcb = ATH11K_SKB_RXCB(skb);
3735 if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO &&
3736 rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) {
3737 if (!n_buffs)
3738 break;
3739 __skb_unlink(skb, msdu_list);
3740 dev_kfree_skb_any(skb);
3741 n_buffs--;
3742 }
3743 }
3744 }
3745
ath11k_dp_rx_h_null_q_desc(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)3746 static int ath11k_dp_rx_h_null_q_desc(struct ath11k *ar, struct sk_buff *msdu,
3747 struct ieee80211_rx_status *status,
3748 struct sk_buff_head *msdu_list)
3749 {
3750 u16 msdu_len;
3751 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
3752 u8 l3pad_bytes;
3753 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3754
3755 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(desc);
3756
3757 if (!rxcb->is_frag && ((msdu_len + HAL_RX_DESC_SIZE) > DP_RX_BUFFER_SIZE)) {
3758 /* First buffer will be freed by the caller, so deduct it's length */
3759 msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE);
3760 ath11k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list);
3761 return -EINVAL;
3762 }
3763
3764 if (!ath11k_dp_rx_h_attn_msdu_done(desc)) {
3765 ath11k_warn(ar->ab,
3766 "msdu_done bit not set in null_q_des processing\n");
3767 __skb_queue_purge(msdu_list);
3768 return -EIO;
3769 }
3770
3771 /* Handle NULL queue descriptor violations arising out a missing
3772 * REO queue for a given peer or a given TID. This typically
3773 * may happen if a packet is received on a QOS enabled TID before the
3774 * ADDBA negotiation for that TID, when the TID queue is setup. Or
3775 * it may also happen for MC/BC frames if they are not routed to the
3776 * non-QOS TID queue, in the absence of any other default TID queue.
3777 * This error can show up both in a REO destination or WBM release ring.
3778 */
3779
3780 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(desc);
3781 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(desc);
3782
3783 if (rxcb->is_frag) {
3784 skb_pull(msdu, HAL_RX_DESC_SIZE);
3785 } else {
3786 l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(desc);
3787
3788 if ((HAL_RX_DESC_SIZE + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE)
3789 return -EINVAL;
3790
3791 skb_put(msdu, HAL_RX_DESC_SIZE + l3pad_bytes + msdu_len);
3792 skb_pull(msdu, HAL_RX_DESC_SIZE + l3pad_bytes);
3793 }
3794 ath11k_dp_rx_h_ppdu(ar, desc, status);
3795
3796 ath11k_dp_rx_h_mpdu(ar, msdu, desc, status);
3797
3798 rxcb->tid = ath11k_dp_rx_h_mpdu_start_tid(desc);
3799
3800 /* Please note that caller will having the access to msdu and completing
3801 * rx with mac80211. Need not worry about cleaning up amsdu_list.
3802 */
3803
3804 return 0;
3805 }
3806
ath11k_dp_rx_h_reo_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)3807 static bool ath11k_dp_rx_h_reo_err(struct ath11k *ar, struct sk_buff *msdu,
3808 struct ieee80211_rx_status *status,
3809 struct sk_buff_head *msdu_list)
3810 {
3811 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3812 bool drop = false;
3813
3814 ar->ab->soc_stats.reo_error[rxcb->err_code]++;
3815
3816 switch (rxcb->err_code) {
3817 case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO:
3818 if (ath11k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list))
3819 drop = true;
3820 break;
3821 case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED:
3822 /* TODO: Do not drop PN failed packets in the driver;
3823 * instead, it is good to drop such packets in mac80211
3824 * after incrementing the replay counters.
3825 */
3826 fallthrough;
3827 default:
3828 /* TODO: Review other errors and process them to mac80211
3829 * as appropriate.
3830 */
3831 drop = true;
3832 break;
3833 }
3834
3835 return drop;
3836 }
3837
ath11k_dp_rx_h_tkip_mic_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)3838 static void ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu,
3839 struct ieee80211_rx_status *status)
3840 {
3841 u16 msdu_len;
3842 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
3843 u8 l3pad_bytes;
3844 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3845
3846 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(desc);
3847 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(desc);
3848
3849 l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(desc);
3850 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(desc);
3851 skb_put(msdu, HAL_RX_DESC_SIZE + l3pad_bytes + msdu_len);
3852 skb_pull(msdu, HAL_RX_DESC_SIZE + l3pad_bytes);
3853
3854 ath11k_dp_rx_h_ppdu(ar, desc, status);
3855
3856 status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR |
3857 RX_FLAG_DECRYPTED);
3858
3859 ath11k_dp_rx_h_undecap(ar, msdu, desc,
3860 HAL_ENCRYPT_TYPE_TKIP_MIC, status, false);
3861 }
3862
ath11k_dp_rx_h_rxdma_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)3863 static bool ath11k_dp_rx_h_rxdma_err(struct ath11k *ar, struct sk_buff *msdu,
3864 struct ieee80211_rx_status *status)
3865 {
3866 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3867 bool drop = false;
3868
3869 ar->ab->soc_stats.rxdma_error[rxcb->err_code]++;
3870
3871 switch (rxcb->err_code) {
3872 case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR:
3873 ath11k_dp_rx_h_tkip_mic_err(ar, msdu, status);
3874 break;
3875 default:
3876 /* TODO: Review other rxdma error code to check if anything is
3877 * worth reporting to mac80211
3878 */
3879 drop = true;
3880 break;
3881 }
3882
3883 return drop;
3884 }
3885
ath11k_dp_rx_wbm_err(struct ath11k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct sk_buff_head * msdu_list)3886 static void ath11k_dp_rx_wbm_err(struct ath11k *ar,
3887 struct napi_struct *napi,
3888 struct sk_buff *msdu,
3889 struct sk_buff_head *msdu_list)
3890 {
3891 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3892 struct ieee80211_rx_status rxs = {0};
3893 struct ieee80211_rx_status *status;
3894 bool drop = true;
3895
3896 switch (rxcb->err_rel_src) {
3897 case HAL_WBM_REL_SRC_MODULE_REO:
3898 drop = ath11k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list);
3899 break;
3900 case HAL_WBM_REL_SRC_MODULE_RXDMA:
3901 drop = ath11k_dp_rx_h_rxdma_err(ar, msdu, &rxs);
3902 break;
3903 default:
3904 /* msdu will get freed */
3905 break;
3906 }
3907
3908 if (drop) {
3909 dev_kfree_skb_any(msdu);
3910 return;
3911 }
3912
3913 status = IEEE80211_SKB_RXCB(msdu);
3914 *status = rxs;
3915
3916 ath11k_dp_rx_deliver_msdu(ar, napi, msdu);
3917 }
3918
ath11k_dp_rx_process_wbm_err(struct ath11k_base * ab,struct napi_struct * napi,int budget)3919 int ath11k_dp_rx_process_wbm_err(struct ath11k_base *ab,
3920 struct napi_struct *napi, int budget)
3921 {
3922 struct ath11k *ar;
3923 struct ath11k_dp *dp = &ab->dp;
3924 struct dp_rxdma_ring *rx_ring;
3925 struct hal_rx_wbm_rel_info err_info;
3926 struct hal_srng *srng;
3927 struct sk_buff *msdu;
3928 struct sk_buff_head msdu_list[MAX_RADIOS];
3929 struct ath11k_skb_rxcb *rxcb;
3930 u32 *rx_desc;
3931 int buf_id, mac_id;
3932 int num_buffs_reaped[MAX_RADIOS] = {0};
3933 int total_num_buffs_reaped = 0;
3934 int ret, i;
3935
3936 for (i = 0; i < ab->num_radios; i++)
3937 __skb_queue_head_init(&msdu_list[i]);
3938
3939 srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id];
3940
3941 spin_lock_bh(&srng->lock);
3942
3943 ath11k_hal_srng_access_begin(ab, srng);
3944
3945 while (budget) {
3946 rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng);
3947 if (!rx_desc)
3948 break;
3949
3950 ret = ath11k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info);
3951 if (ret) {
3952 ath11k_warn(ab,
3953 "failed to parse rx error in wbm_rel ring desc %d\n",
3954 ret);
3955 continue;
3956 }
3957
3958 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, err_info.cookie);
3959 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, err_info.cookie);
3960
3961 ar = ab->pdevs[mac_id].ar;
3962 rx_ring = &ar->dp.rx_refill_buf_ring;
3963
3964 spin_lock_bh(&rx_ring->idr_lock);
3965 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
3966 if (!msdu) {
3967 ath11k_warn(ab, "frame rx with invalid buf_id %d pdev %d\n",
3968 buf_id, mac_id);
3969 spin_unlock_bh(&rx_ring->idr_lock);
3970 continue;
3971 }
3972
3973 idr_remove(&rx_ring->bufs_idr, buf_id);
3974 spin_unlock_bh(&rx_ring->idr_lock);
3975
3976 rxcb = ATH11K_SKB_RXCB(msdu);
3977 dma_unmap_single(ab->dev, rxcb->paddr,
3978 msdu->len + skb_tailroom(msdu),
3979 DMA_FROM_DEVICE);
3980
3981 num_buffs_reaped[mac_id]++;
3982 total_num_buffs_reaped++;
3983 budget--;
3984
3985 if (err_info.push_reason !=
3986 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
3987 dev_kfree_skb_any(msdu);
3988 continue;
3989 }
3990
3991 rxcb->err_rel_src = err_info.err_rel_src;
3992 rxcb->err_code = err_info.err_code;
3993 rxcb->rx_desc = (struct hal_rx_desc *)msdu->data;
3994 __skb_queue_tail(&msdu_list[mac_id], msdu);
3995 }
3996
3997 ath11k_hal_srng_access_end(ab, srng);
3998
3999 spin_unlock_bh(&srng->lock);
4000
4001 if (!total_num_buffs_reaped)
4002 goto done;
4003
4004 for (i = 0; i < ab->num_radios; i++) {
4005 if (!num_buffs_reaped[i])
4006 continue;
4007
4008 ar = ab->pdevs[i].ar;
4009 rx_ring = &ar->dp.rx_refill_buf_ring;
4010
4011 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
4012 HAL_RX_BUF_RBM_SW3_BM);
4013 }
4014
4015 rcu_read_lock();
4016 for (i = 0; i < ab->num_radios; i++) {
4017 if (!rcu_dereference(ab->pdevs_active[i])) {
4018 __skb_queue_purge(&msdu_list[i]);
4019 continue;
4020 }
4021
4022 ar = ab->pdevs[i].ar;
4023
4024 if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
4025 __skb_queue_purge(&msdu_list[i]);
4026 continue;
4027 }
4028
4029 while ((msdu = __skb_dequeue(&msdu_list[i])) != NULL)
4030 ath11k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list[i]);
4031 }
4032 rcu_read_unlock();
4033 done:
4034 return total_num_buffs_reaped;
4035 }
4036
ath11k_dp_process_rxdma_err(struct ath11k_base * ab,int mac_id,int budget)4037 int ath11k_dp_process_rxdma_err(struct ath11k_base *ab, int mac_id, int budget)
4038 {
4039 struct ath11k *ar;
4040 struct dp_srng *err_ring;
4041 struct dp_rxdma_ring *rx_ring;
4042 struct dp_link_desc_bank *link_desc_banks = ab->dp.link_desc_banks;
4043 struct hal_srng *srng;
4044 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
4045 enum hal_rx_buf_return_buf_manager rbm;
4046 enum hal_reo_entr_rxdma_ecode rxdma_err_code;
4047 struct ath11k_skb_rxcb *rxcb;
4048 struct sk_buff *skb;
4049 struct hal_reo_entrance_ring *entr_ring;
4050 void *desc;
4051 int num_buf_freed = 0;
4052 int quota = budget;
4053 dma_addr_t paddr;
4054 u32 desc_bank;
4055 void *link_desc_va;
4056 int num_msdus;
4057 int i;
4058 int buf_id;
4059
4060 ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
4061 err_ring = &ar->dp.rxdma_err_dst_ring[ath11k_hw_mac_id_to_srng_id(&ab->hw_params,
4062 mac_id)];
4063 rx_ring = &ar->dp.rx_refill_buf_ring;
4064
4065 srng = &ab->hal.srng_list[err_ring->ring_id];
4066
4067 spin_lock_bh(&srng->lock);
4068
4069 ath11k_hal_srng_access_begin(ab, srng);
4070
4071 while (quota-- &&
4072 (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4073 ath11k_hal_rx_reo_ent_paddr_get(ab, desc, &paddr, &desc_bank);
4074
4075 entr_ring = (struct hal_reo_entrance_ring *)desc;
4076 rxdma_err_code =
4077 FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4078 entr_ring->info1);
4079 ab->soc_stats.rxdma_error[rxdma_err_code]++;
4080
4081 link_desc_va = link_desc_banks[desc_bank].vaddr +
4082 (paddr - link_desc_banks[desc_bank].paddr);
4083 ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus,
4084 msdu_cookies, &rbm);
4085
4086 for (i = 0; i < num_msdus; i++) {
4087 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4088 msdu_cookies[i]);
4089
4090 spin_lock_bh(&rx_ring->idr_lock);
4091 skb = idr_find(&rx_ring->bufs_idr, buf_id);
4092 if (!skb) {
4093 ath11k_warn(ab, "rxdma error with invalid buf_id %d\n",
4094 buf_id);
4095 spin_unlock_bh(&rx_ring->idr_lock);
4096 continue;
4097 }
4098
4099 idr_remove(&rx_ring->bufs_idr, buf_id);
4100 spin_unlock_bh(&rx_ring->idr_lock);
4101
4102 rxcb = ATH11K_SKB_RXCB(skb);
4103 dma_unmap_single(ab->dev, rxcb->paddr,
4104 skb->len + skb_tailroom(skb),
4105 DMA_FROM_DEVICE);
4106 dev_kfree_skb_any(skb);
4107
4108 num_buf_freed++;
4109 }
4110
4111 ath11k_dp_rx_link_desc_return(ab, desc,
4112 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4113 }
4114
4115 ath11k_hal_srng_access_end(ab, srng);
4116
4117 spin_unlock_bh(&srng->lock);
4118
4119 if (num_buf_freed)
4120 ath11k_dp_rxbufs_replenish(ab, mac_id, rx_ring, num_buf_freed,
4121 HAL_RX_BUF_RBM_SW3_BM);
4122
4123 return budget - quota;
4124 }
4125
ath11k_dp_process_reo_status(struct ath11k_base * ab)4126 void ath11k_dp_process_reo_status(struct ath11k_base *ab)
4127 {
4128 struct ath11k_dp *dp = &ab->dp;
4129 struct hal_srng *srng;
4130 struct dp_reo_cmd *cmd, *tmp;
4131 bool found = false;
4132 u32 *reo_desc;
4133 u16 tag;
4134 struct hal_reo_status reo_status;
4135
4136 srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id];
4137
4138 memset(&reo_status, 0, sizeof(reo_status));
4139
4140 spin_lock_bh(&srng->lock);
4141
4142 ath11k_hal_srng_access_begin(ab, srng);
4143
4144 while ((reo_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4145 tag = FIELD_GET(HAL_SRNG_TLV_HDR_TAG, *reo_desc);
4146
4147 switch (tag) {
4148 case HAL_REO_GET_QUEUE_STATS_STATUS:
4149 ath11k_hal_reo_status_queue_stats(ab, reo_desc,
4150 &reo_status);
4151 break;
4152 case HAL_REO_FLUSH_QUEUE_STATUS:
4153 ath11k_hal_reo_flush_queue_status(ab, reo_desc,
4154 &reo_status);
4155 break;
4156 case HAL_REO_FLUSH_CACHE_STATUS:
4157 ath11k_hal_reo_flush_cache_status(ab, reo_desc,
4158 &reo_status);
4159 break;
4160 case HAL_REO_UNBLOCK_CACHE_STATUS:
4161 ath11k_hal_reo_unblk_cache_status(ab, reo_desc,
4162 &reo_status);
4163 break;
4164 case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS:
4165 ath11k_hal_reo_flush_timeout_list_status(ab, reo_desc,
4166 &reo_status);
4167 break;
4168 case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS:
4169 ath11k_hal_reo_desc_thresh_reached_status(ab, reo_desc,
4170 &reo_status);
4171 break;
4172 case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS:
4173 ath11k_hal_reo_update_rx_reo_queue_status(ab, reo_desc,
4174 &reo_status);
4175 break;
4176 default:
4177 ath11k_warn(ab, "Unknown reo status type %d\n", tag);
4178 continue;
4179 }
4180
4181 spin_lock_bh(&dp->reo_cmd_lock);
4182 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
4183 if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) {
4184 found = true;
4185 list_del(&cmd->list);
4186 break;
4187 }
4188 }
4189 spin_unlock_bh(&dp->reo_cmd_lock);
4190
4191 if (found) {
4192 cmd->handler(dp, (void *)&cmd->data,
4193 reo_status.uniform_hdr.cmd_status);
4194 kfree(cmd);
4195 }
4196
4197 found = false;
4198 }
4199
4200 ath11k_hal_srng_access_end(ab, srng);
4201
4202 spin_unlock_bh(&srng->lock);
4203 }
4204
ath11k_dp_rx_pdev_free(struct ath11k_base * ab,int mac_id)4205 void ath11k_dp_rx_pdev_free(struct ath11k_base *ab, int mac_id)
4206 {
4207 struct ath11k *ar = ab->pdevs[mac_id].ar;
4208
4209 ath11k_dp_rx_pdev_srng_free(ar);
4210 ath11k_dp_rxdma_pdev_buf_free(ar);
4211 }
4212
ath11k_dp_rx_pdev_alloc(struct ath11k_base * ab,int mac_id)4213 int ath11k_dp_rx_pdev_alloc(struct ath11k_base *ab, int mac_id)
4214 {
4215 struct ath11k *ar = ab->pdevs[mac_id].ar;
4216 struct ath11k_pdev_dp *dp = &ar->dp;
4217 u32 ring_id;
4218 int i;
4219 int ret;
4220
4221 ret = ath11k_dp_rx_pdev_srng_alloc(ar);
4222 if (ret) {
4223 ath11k_warn(ab, "failed to setup rx srngs\n");
4224 return ret;
4225 }
4226
4227 ret = ath11k_dp_rxdma_pdev_buf_setup(ar);
4228 if (ret) {
4229 ath11k_warn(ab, "failed to setup rxdma ring\n");
4230 return ret;
4231 }
4232
4233 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
4234 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id, HAL_RXDMA_BUF);
4235 if (ret) {
4236 ath11k_warn(ab, "failed to configure rx_refill_buf_ring %d\n",
4237 ret);
4238 return ret;
4239 }
4240
4241 if (ab->hw_params.rx_mac_buf_ring) {
4242 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
4243 ring_id = dp->rx_mac_buf_ring[i].ring_id;
4244 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4245 mac_id + i, HAL_RXDMA_BUF);
4246 if (ret) {
4247 ath11k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n",
4248 i, ret);
4249 return ret;
4250 }
4251 }
4252 }
4253
4254 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
4255 ring_id = dp->rxdma_err_dst_ring[i].ring_id;
4256 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4257 mac_id + i, HAL_RXDMA_DST);
4258 if (ret) {
4259 ath11k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n",
4260 i, ret);
4261 return ret;
4262 }
4263 }
4264
4265 if (!ab->hw_params.rxdma1_enable)
4266 goto config_refill_ring;
4267
4268 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
4269 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4270 mac_id, HAL_RXDMA_MONITOR_BUF);
4271 if (ret) {
4272 ath11k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n",
4273 ret);
4274 return ret;
4275 }
4276 ret = ath11k_dp_tx_htt_srng_setup(ab,
4277 dp->rxdma_mon_dst_ring.ring_id,
4278 mac_id, HAL_RXDMA_MONITOR_DST);
4279 if (ret) {
4280 ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4281 ret);
4282 return ret;
4283 }
4284 ret = ath11k_dp_tx_htt_srng_setup(ab,
4285 dp->rxdma_mon_desc_ring.ring_id,
4286 mac_id, HAL_RXDMA_MONITOR_DESC);
4287 if (ret) {
4288 ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4289 ret);
4290 return ret;
4291 }
4292
4293 config_refill_ring:
4294 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
4295 ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id;
4296 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id + i,
4297 HAL_RXDMA_MONITOR_STATUS);
4298 if (ret) {
4299 ath11k_warn(ab,
4300 "failed to configure mon_status_refill_ring%d %d\n",
4301 i, ret);
4302 return ret;
4303 }
4304 }
4305
4306 return 0;
4307 }
4308
ath11k_dp_mon_set_frag_len(u32 * total_len,u32 * frag_len)4309 static void ath11k_dp_mon_set_frag_len(u32 *total_len, u32 *frag_len)
4310 {
4311 if (*total_len >= (DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc))) {
4312 *frag_len = DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc);
4313 *total_len -= *frag_len;
4314 } else {
4315 *frag_len = *total_len;
4316 *total_len = 0;
4317 }
4318 }
4319
4320 static
ath11k_dp_rx_monitor_link_desc_return(struct ath11k * ar,void * p_last_buf_addr_info,u8 mac_id)4321 int ath11k_dp_rx_monitor_link_desc_return(struct ath11k *ar,
4322 void *p_last_buf_addr_info,
4323 u8 mac_id)
4324 {
4325 struct ath11k_pdev_dp *dp = &ar->dp;
4326 struct dp_srng *dp_srng;
4327 void *hal_srng;
4328 void *src_srng_desc;
4329 int ret = 0;
4330
4331 if (ar->ab->hw_params.rxdma1_enable) {
4332 dp_srng = &dp->rxdma_mon_desc_ring;
4333 hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4334 } else {
4335 dp_srng = &ar->ab->dp.wbm_desc_rel_ring;
4336 hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4337 }
4338
4339 ath11k_hal_srng_access_begin(ar->ab, hal_srng);
4340
4341 src_srng_desc = ath11k_hal_srng_src_get_next_entry(ar->ab, hal_srng);
4342
4343 if (src_srng_desc) {
4344 struct ath11k_buffer_addr *src_desc =
4345 (struct ath11k_buffer_addr *)src_srng_desc;
4346
4347 *src_desc = *((struct ath11k_buffer_addr *)p_last_buf_addr_info);
4348 } else {
4349 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4350 "Monitor Link Desc Ring %d Full", mac_id);
4351 ret = -ENOMEM;
4352 }
4353
4354 ath11k_hal_srng_access_end(ar->ab, hal_srng);
4355 return ret;
4356 }
4357
4358 static
ath11k_dp_rx_mon_next_link_desc_get(void * rx_msdu_link_desc,dma_addr_t * paddr,u32 * sw_cookie,u8 * rbm,void ** pp_buf_addr_info)4359 void ath11k_dp_rx_mon_next_link_desc_get(void *rx_msdu_link_desc,
4360 dma_addr_t *paddr, u32 *sw_cookie,
4361 u8 *rbm,
4362 void **pp_buf_addr_info)
4363 {
4364 struct hal_rx_msdu_link *msdu_link =
4365 (struct hal_rx_msdu_link *)rx_msdu_link_desc;
4366 struct ath11k_buffer_addr *buf_addr_info;
4367
4368 buf_addr_info = (struct ath11k_buffer_addr *)&msdu_link->buf_addr_info;
4369
4370 ath11k_hal_rx_buf_addr_info_get(buf_addr_info, paddr, sw_cookie, rbm);
4371
4372 *pp_buf_addr_info = (void *)buf_addr_info;
4373 }
4374
ath11k_dp_pkt_set_pktlen(struct sk_buff * skb,u32 len)4375 static int ath11k_dp_pkt_set_pktlen(struct sk_buff *skb, u32 len)
4376 {
4377 if (skb->len > len) {
4378 skb_trim(skb, len);
4379 } else {
4380 if (skb_tailroom(skb) < len - skb->len) {
4381 if ((pskb_expand_head(skb, 0,
4382 len - skb->len - skb_tailroom(skb),
4383 GFP_ATOMIC))) {
4384 dev_kfree_skb_any(skb);
4385 return -ENOMEM;
4386 }
4387 }
4388 skb_put(skb, (len - skb->len));
4389 }
4390 return 0;
4391 }
4392
ath11k_hal_rx_msdu_list_get(struct ath11k * ar,void * msdu_link_desc,struct hal_rx_msdu_list * msdu_list,u16 * num_msdus)4393 static void ath11k_hal_rx_msdu_list_get(struct ath11k *ar,
4394 void *msdu_link_desc,
4395 struct hal_rx_msdu_list *msdu_list,
4396 u16 *num_msdus)
4397 {
4398 struct hal_rx_msdu_details *msdu_details = NULL;
4399 struct rx_msdu_desc *msdu_desc_info = NULL;
4400 struct hal_rx_msdu_link *msdu_link = NULL;
4401 int i;
4402 u32 last = FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1);
4403 u32 first = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1);
4404 u8 tmp = 0;
4405
4406 msdu_link = (struct hal_rx_msdu_link *)msdu_link_desc;
4407 msdu_details = &msdu_link->msdu_link[0];
4408
4409 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
4410 if (FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
4411 msdu_details[i].buf_addr_info.info0) == 0) {
4412 msdu_desc_info = &msdu_details[i - 1].rx_msdu_info;
4413 msdu_desc_info->info0 |= last;
4414 ;
4415 break;
4416 }
4417 msdu_desc_info = &msdu_details[i].rx_msdu_info;
4418
4419 if (!i)
4420 msdu_desc_info->info0 |= first;
4421 else if (i == (HAL_RX_NUM_MSDU_DESC - 1))
4422 msdu_desc_info->info0 |= last;
4423 msdu_list->msdu_info[i].msdu_flags = msdu_desc_info->info0;
4424 msdu_list->msdu_info[i].msdu_len =
4425 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info->info0);
4426 msdu_list->sw_cookie[i] =
4427 FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
4428 msdu_details[i].buf_addr_info.info1);
4429 tmp = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
4430 msdu_details[i].buf_addr_info.info1);
4431 msdu_list->rbm[i] = tmp;
4432 }
4433 *num_msdus = i;
4434 }
4435
ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id,u32 * ppdu_id,u32 * rx_bufs_used)4436 static u32 ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id, u32 *ppdu_id,
4437 u32 *rx_bufs_used)
4438 {
4439 u32 ret = 0;
4440
4441 if ((*ppdu_id < msdu_ppdu_id) &&
4442 ((msdu_ppdu_id - *ppdu_id) < DP_NOT_PPDU_ID_WRAP_AROUND)) {
4443 *ppdu_id = msdu_ppdu_id;
4444 ret = msdu_ppdu_id;
4445 } else if ((*ppdu_id > msdu_ppdu_id) &&
4446 ((*ppdu_id - msdu_ppdu_id) > DP_NOT_PPDU_ID_WRAP_AROUND)) {
4447 /* mon_dst is behind than mon_status
4448 * skip dst_ring and free it
4449 */
4450 *rx_bufs_used += 1;
4451 *ppdu_id = msdu_ppdu_id;
4452 ret = msdu_ppdu_id;
4453 }
4454 return ret;
4455 }
4456
ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info * info,bool * is_frag,u32 * total_len,u32 * frag_len,u32 * msdu_cnt)4457 static void ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info *info,
4458 bool *is_frag, u32 *total_len,
4459 u32 *frag_len, u32 *msdu_cnt)
4460 {
4461 if (info->msdu_flags & RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) {
4462 if (!*is_frag) {
4463 *total_len = info->msdu_len;
4464 *is_frag = true;
4465 }
4466 ath11k_dp_mon_set_frag_len(total_len,
4467 frag_len);
4468 } else {
4469 if (*is_frag) {
4470 ath11k_dp_mon_set_frag_len(total_len,
4471 frag_len);
4472 } else {
4473 *frag_len = info->msdu_len;
4474 }
4475 *is_frag = false;
4476 *msdu_cnt -= 1;
4477 }
4478 }
4479
4480 static u32
ath11k_dp_rx_mon_mpdu_pop(struct ath11k * ar,int mac_id,void * ring_entry,struct sk_buff ** head_msdu,struct sk_buff ** tail_msdu,u32 * npackets,u32 * ppdu_id)4481 ath11k_dp_rx_mon_mpdu_pop(struct ath11k *ar, int mac_id,
4482 void *ring_entry, struct sk_buff **head_msdu,
4483 struct sk_buff **tail_msdu, u32 *npackets,
4484 u32 *ppdu_id)
4485 {
4486 struct ath11k_pdev_dp *dp = &ar->dp;
4487 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4488 struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
4489 struct sk_buff *msdu = NULL, *last = NULL;
4490 struct hal_rx_msdu_list msdu_list;
4491 void *p_buf_addr_info, *p_last_buf_addr_info;
4492 struct hal_rx_desc *rx_desc;
4493 void *rx_msdu_link_desc;
4494 dma_addr_t paddr;
4495 u16 num_msdus = 0;
4496 u32 rx_buf_size, rx_pkt_offset, sw_cookie;
4497 u32 rx_bufs_used = 0, i = 0;
4498 u32 msdu_ppdu_id = 0, msdu_cnt = 0;
4499 u32 total_len = 0, frag_len = 0;
4500 bool is_frag, is_first_msdu;
4501 bool drop_mpdu = false;
4502 struct ath11k_skb_rxcb *rxcb;
4503 struct hal_reo_entrance_ring *ent_desc =
4504 (struct hal_reo_entrance_ring *)ring_entry;
4505 int buf_id;
4506 u32 rx_link_buf_info[2];
4507 u8 rbm;
4508
4509 if (!ar->ab->hw_params.rxdma1_enable)
4510 rx_ring = &dp->rx_refill_buf_ring;
4511
4512 ath11k_hal_rx_reo_ent_buf_paddr_get(ring_entry, &paddr,
4513 &sw_cookie,
4514 &p_last_buf_addr_info, &rbm,
4515 &msdu_cnt);
4516
4517 if (FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON,
4518 ent_desc->info1) ==
4519 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4520 u8 rxdma_err =
4521 FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4522 ent_desc->info1);
4523 if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
4524 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
4525 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
4526 drop_mpdu = true;
4527 pmon->rx_mon_stats.dest_mpdu_drop++;
4528 }
4529 }
4530
4531 is_frag = false;
4532 is_first_msdu = true;
4533
4534 do {
4535 if (pmon->mon_last_linkdesc_paddr == paddr) {
4536 pmon->rx_mon_stats.dup_mon_linkdesc_cnt++;
4537 return rx_bufs_used;
4538 }
4539
4540 if (ar->ab->hw_params.rxdma1_enable)
4541 rx_msdu_link_desc =
4542 (void *)pmon->link_desc_banks[sw_cookie].vaddr +
4543 (paddr - pmon->link_desc_banks[sw_cookie].paddr);
4544 else
4545 rx_msdu_link_desc =
4546 (void *)ar->ab->dp.link_desc_banks[sw_cookie].vaddr +
4547 (paddr - ar->ab->dp.link_desc_banks[sw_cookie].paddr);
4548
4549 ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
4550 &num_msdus);
4551
4552 for (i = 0; i < num_msdus; i++) {
4553 u32 l2_hdr_offset;
4554
4555 if (pmon->mon_last_buf_cookie == msdu_list.sw_cookie[i]) {
4556 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4557 "i %d last_cookie %d is same\n",
4558 i, pmon->mon_last_buf_cookie);
4559 drop_mpdu = true;
4560 pmon->rx_mon_stats.dup_mon_buf_cnt++;
4561 continue;
4562 }
4563 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4564 msdu_list.sw_cookie[i]);
4565
4566 spin_lock_bh(&rx_ring->idr_lock);
4567 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4568 spin_unlock_bh(&rx_ring->idr_lock);
4569 if (!msdu) {
4570 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4571 "msdu_pop: invalid buf_id %d\n", buf_id);
4572 break;
4573 }
4574 rxcb = ATH11K_SKB_RXCB(msdu);
4575 if (!rxcb->unmapped) {
4576 dma_unmap_single(ar->ab->dev, rxcb->paddr,
4577 msdu->len +
4578 skb_tailroom(msdu),
4579 DMA_FROM_DEVICE);
4580 rxcb->unmapped = 1;
4581 }
4582 if (drop_mpdu) {
4583 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4584 "i %d drop msdu %p *ppdu_id %x\n",
4585 i, msdu, *ppdu_id);
4586 dev_kfree_skb_any(msdu);
4587 msdu = NULL;
4588 goto next_msdu;
4589 }
4590
4591 rx_desc = (struct hal_rx_desc *)msdu->data;
4592
4593 rx_pkt_offset = sizeof(struct hal_rx_desc);
4594 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(rx_desc);
4595
4596 if (is_first_msdu) {
4597 if (!ath11k_dp_rxdesc_mpdu_valid(rx_desc)) {
4598 drop_mpdu = true;
4599 dev_kfree_skb_any(msdu);
4600 msdu = NULL;
4601 pmon->mon_last_linkdesc_paddr = paddr;
4602 goto next_msdu;
4603 }
4604
4605 msdu_ppdu_id =
4606 ath11k_dp_rxdesc_get_ppduid(rx_desc);
4607
4608 if (ath11k_dp_rx_mon_comp_ppduid(msdu_ppdu_id,
4609 ppdu_id,
4610 &rx_bufs_used)) {
4611 if (rx_bufs_used) {
4612 drop_mpdu = true;
4613 dev_kfree_skb_any(msdu);
4614 msdu = NULL;
4615 goto next_msdu;
4616 }
4617 return rx_bufs_used;
4618 }
4619 pmon->mon_last_linkdesc_paddr = paddr;
4620 is_first_msdu = false;
4621 }
4622 ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
4623 &is_frag, &total_len,
4624 &frag_len, &msdu_cnt);
4625 rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
4626
4627 ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
4628
4629 if (!(*head_msdu))
4630 *head_msdu = msdu;
4631 else if (last)
4632 last->next = msdu;
4633
4634 last = msdu;
4635 next_msdu:
4636 pmon->mon_last_buf_cookie = msdu_list.sw_cookie[i];
4637 rx_bufs_used++;
4638 spin_lock_bh(&rx_ring->idr_lock);
4639 idr_remove(&rx_ring->bufs_idr, buf_id);
4640 spin_unlock_bh(&rx_ring->idr_lock);
4641 }
4642
4643 ath11k_hal_rx_buf_addr_info_set(rx_link_buf_info, paddr, sw_cookie, rbm);
4644
4645 ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc, &paddr,
4646 &sw_cookie, &rbm,
4647 &p_buf_addr_info);
4648
4649 if (ar->ab->hw_params.rxdma1_enable) {
4650 if (ath11k_dp_rx_monitor_link_desc_return(ar,
4651 p_last_buf_addr_info,
4652 dp->mac_id))
4653 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4654 "dp_rx_monitor_link_desc_return failed");
4655 } else {
4656 ath11k_dp_rx_link_desc_return(ar->ab, rx_link_buf_info,
4657 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4658 }
4659
4660 p_last_buf_addr_info = p_buf_addr_info;
4661
4662 } while (paddr && msdu_cnt);
4663
4664 if (last)
4665 last->next = NULL;
4666
4667 *tail_msdu = msdu;
4668
4669 if (msdu_cnt == 0)
4670 *npackets = 1;
4671
4672 return rx_bufs_used;
4673 }
4674
ath11k_dp_rx_msdus_set_payload(struct sk_buff * msdu)4675 static void ath11k_dp_rx_msdus_set_payload(struct sk_buff *msdu)
4676 {
4677 u32 rx_pkt_offset, l2_hdr_offset;
4678
4679 rx_pkt_offset = sizeof(struct hal_rx_desc);
4680 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad((struct hal_rx_desc *)msdu->data);
4681 skb_pull(msdu, rx_pkt_offset + l2_hdr_offset);
4682 }
4683
4684 static struct sk_buff *
ath11k_dp_rx_mon_merg_msdus(struct ath11k * ar,u32 mac_id,struct sk_buff * head_msdu,struct sk_buff * last_msdu,struct ieee80211_rx_status * rxs)4685 ath11k_dp_rx_mon_merg_msdus(struct ath11k *ar,
4686 u32 mac_id, struct sk_buff *head_msdu,
4687 struct sk_buff *last_msdu,
4688 struct ieee80211_rx_status *rxs)
4689 {
4690 struct sk_buff *msdu, *mpdu_buf, *prev_buf;
4691 u32 decap_format, wifi_hdr_len;
4692 struct hal_rx_desc *rx_desc;
4693 char *hdr_desc;
4694 u8 *dest;
4695 struct ieee80211_hdr_3addr *wh;
4696
4697 mpdu_buf = NULL;
4698
4699 if (!head_msdu)
4700 goto err_merge_fail;
4701
4702 rx_desc = (struct hal_rx_desc *)head_msdu->data;
4703
4704 if (ath11k_dp_rxdesc_get_mpdulen_err(rx_desc))
4705 return NULL;
4706
4707 decap_format = ath11k_dp_rxdesc_get_decap_format(rx_desc);
4708
4709 ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
4710
4711 if (decap_format == DP_RX_DECAP_TYPE_RAW) {
4712 ath11k_dp_rx_msdus_set_payload(head_msdu);
4713
4714 prev_buf = head_msdu;
4715 msdu = head_msdu->next;
4716
4717 while (msdu) {
4718 ath11k_dp_rx_msdus_set_payload(msdu);
4719
4720 prev_buf = msdu;
4721 msdu = msdu->next;
4722 }
4723
4724 prev_buf->next = NULL;
4725
4726 skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN);
4727 } else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) {
4728 __le16 qos_field;
4729 u8 qos_pkt = 0;
4730
4731 rx_desc = (struct hal_rx_desc *)head_msdu->data;
4732 hdr_desc = ath11k_dp_rxdesc_get_80211hdr(rx_desc);
4733
4734 /* Base size */
4735 wifi_hdr_len = sizeof(struct ieee80211_hdr_3addr);
4736 wh = (struct ieee80211_hdr_3addr *)hdr_desc;
4737
4738 if (ieee80211_is_data_qos(wh->frame_control)) {
4739 struct ieee80211_qos_hdr *qwh =
4740 (struct ieee80211_qos_hdr *)hdr_desc;
4741
4742 qos_field = qwh->qos_ctrl;
4743 qos_pkt = 1;
4744 }
4745 msdu = head_msdu;
4746
4747 while (msdu) {
4748 rx_desc = (struct hal_rx_desc *)msdu->data;
4749 hdr_desc = ath11k_dp_rxdesc_get_80211hdr(rx_desc);
4750
4751 if (qos_pkt) {
4752 dest = skb_push(msdu, sizeof(__le16));
4753 if (!dest)
4754 goto err_merge_fail;
4755 memcpy(dest, hdr_desc, wifi_hdr_len);
4756 memcpy(dest + wifi_hdr_len,
4757 (u8 *)&qos_field, sizeof(__le16));
4758 }
4759 ath11k_dp_rx_msdus_set_payload(msdu);
4760 prev_buf = msdu;
4761 msdu = msdu->next;
4762 }
4763 dest = skb_put(prev_buf, HAL_RX_FCS_LEN);
4764 if (!dest)
4765 goto err_merge_fail;
4766
4767 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4768 "mpdu_buf %pK mpdu_buf->len %u",
4769 prev_buf, prev_buf->len);
4770 } else {
4771 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4772 "decap format %d is not supported!\n",
4773 decap_format);
4774 goto err_merge_fail;
4775 }
4776
4777 return head_msdu;
4778
4779 err_merge_fail:
4780 if (mpdu_buf && decap_format != DP_RX_DECAP_TYPE_RAW) {
4781 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4782 "err_merge_fail mpdu_buf %pK", mpdu_buf);
4783 /* Free the head buffer */
4784 dev_kfree_skb_any(mpdu_buf);
4785 }
4786 return NULL;
4787 }
4788
ath11k_dp_rx_mon_deliver(struct ath11k * ar,u32 mac_id,struct sk_buff * head_msdu,struct sk_buff * tail_msdu,struct napi_struct * napi)4789 static int ath11k_dp_rx_mon_deliver(struct ath11k *ar, u32 mac_id,
4790 struct sk_buff *head_msdu,
4791 struct sk_buff *tail_msdu,
4792 struct napi_struct *napi)
4793 {
4794 struct ath11k_pdev_dp *dp = &ar->dp;
4795 struct sk_buff *mon_skb, *skb_next, *header;
4796 struct ieee80211_rx_status *rxs = &dp->rx_status, *status;
4797
4798 mon_skb = ath11k_dp_rx_mon_merg_msdus(ar, mac_id, head_msdu,
4799 tail_msdu, rxs);
4800
4801 if (!mon_skb)
4802 goto mon_deliver_fail;
4803
4804 header = mon_skb;
4805
4806 rxs->flag = 0;
4807 do {
4808 skb_next = mon_skb->next;
4809 if (!skb_next)
4810 rxs->flag &= ~RX_FLAG_AMSDU_MORE;
4811 else
4812 rxs->flag |= RX_FLAG_AMSDU_MORE;
4813
4814 if (mon_skb == header) {
4815 header = NULL;
4816 rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN;
4817 } else {
4818 rxs->flag |= RX_FLAG_ALLOW_SAME_PN;
4819 }
4820 rxs->flag |= RX_FLAG_ONLY_MONITOR;
4821
4822 status = IEEE80211_SKB_RXCB(mon_skb);
4823 *status = *rxs;
4824
4825 ath11k_dp_rx_deliver_msdu(ar, napi, mon_skb);
4826 mon_skb = skb_next;
4827 } while (mon_skb);
4828 rxs->flag = 0;
4829
4830 return 0;
4831
4832 mon_deliver_fail:
4833 mon_skb = head_msdu;
4834 while (mon_skb) {
4835 skb_next = mon_skb->next;
4836 dev_kfree_skb_any(mon_skb);
4837 mon_skb = skb_next;
4838 }
4839 return -EINVAL;
4840 }
4841
ath11k_dp_rx_mon_dest_process(struct ath11k * ar,int mac_id,u32 quota,struct napi_struct * napi)4842 static void ath11k_dp_rx_mon_dest_process(struct ath11k *ar, int mac_id,
4843 u32 quota, struct napi_struct *napi)
4844 {
4845 struct ath11k_pdev_dp *dp = &ar->dp;
4846 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4847 void *ring_entry;
4848 void *mon_dst_srng;
4849 u32 ppdu_id;
4850 u32 rx_bufs_used;
4851 u32 ring_id;
4852 struct ath11k_pdev_mon_stats *rx_mon_stats;
4853 u32 npackets = 0;
4854
4855 if (ar->ab->hw_params.rxdma1_enable)
4856 ring_id = dp->rxdma_mon_dst_ring.ring_id;
4857 else
4858 ring_id = dp->rxdma_err_dst_ring[mac_id].ring_id;
4859
4860 mon_dst_srng = &ar->ab->hal.srng_list[ring_id];
4861
4862 if (!mon_dst_srng) {
4863 ath11k_warn(ar->ab,
4864 "HAL Monitor Destination Ring Init Failed -- %pK",
4865 mon_dst_srng);
4866 return;
4867 }
4868
4869 spin_lock_bh(&pmon->mon_lock);
4870
4871 ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
4872
4873 ppdu_id = pmon->mon_ppdu_info.ppdu_id;
4874 rx_bufs_used = 0;
4875 rx_mon_stats = &pmon->rx_mon_stats;
4876
4877 while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
4878 struct sk_buff *head_msdu, *tail_msdu;
4879
4880 head_msdu = NULL;
4881 tail_msdu = NULL;
4882
4883 rx_bufs_used += ath11k_dp_rx_mon_mpdu_pop(ar, mac_id, ring_entry,
4884 &head_msdu,
4885 &tail_msdu,
4886 &npackets, &ppdu_id);
4887
4888 if (ppdu_id != pmon->mon_ppdu_info.ppdu_id) {
4889 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
4890 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4891 "dest_rx: new ppdu_id %x != status ppdu_id %x",
4892 ppdu_id, pmon->mon_ppdu_info.ppdu_id);
4893 break;
4894 }
4895 if (head_msdu && tail_msdu) {
4896 ath11k_dp_rx_mon_deliver(ar, dp->mac_id, head_msdu,
4897 tail_msdu, napi);
4898 rx_mon_stats->dest_mpdu_done++;
4899 }
4900
4901 ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
4902 mon_dst_srng);
4903 }
4904 ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
4905
4906 spin_unlock_bh(&pmon->mon_lock);
4907
4908 if (rx_bufs_used) {
4909 rx_mon_stats->dest_ppdu_done++;
4910 if (ar->ab->hw_params.rxdma1_enable)
4911 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
4912 &dp->rxdma_mon_buf_ring,
4913 rx_bufs_used,
4914 HAL_RX_BUF_RBM_SW3_BM);
4915 else
4916 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
4917 &dp->rx_refill_buf_ring,
4918 rx_bufs_used,
4919 HAL_RX_BUF_RBM_SW3_BM);
4920 }
4921 }
4922
ath11k_dp_rx_mon_status_process_tlv(struct ath11k * ar,int mac_id,u32 quota,struct napi_struct * napi)4923 static void ath11k_dp_rx_mon_status_process_tlv(struct ath11k *ar,
4924 int mac_id, u32 quota,
4925 struct napi_struct *napi)
4926 {
4927 struct ath11k_pdev_dp *dp = &ar->dp;
4928 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4929 struct hal_rx_mon_ppdu_info *ppdu_info;
4930 struct sk_buff *status_skb;
4931 u32 tlv_status = HAL_TLV_STATUS_BUF_DONE;
4932 struct ath11k_pdev_mon_stats *rx_mon_stats;
4933
4934 ppdu_info = &pmon->mon_ppdu_info;
4935 rx_mon_stats = &pmon->rx_mon_stats;
4936
4937 if (pmon->mon_ppdu_status != DP_PPDU_STATUS_START)
4938 return;
4939
4940 while (!skb_queue_empty(&pmon->rx_status_q)) {
4941 status_skb = skb_dequeue(&pmon->rx_status_q);
4942
4943 tlv_status = ath11k_hal_rx_parse_mon_status(ar->ab, ppdu_info,
4944 status_skb);
4945 if (tlv_status == HAL_TLV_STATUS_PPDU_DONE) {
4946 rx_mon_stats->status_ppdu_done++;
4947 pmon->mon_ppdu_status = DP_PPDU_STATUS_DONE;
4948 ath11k_dp_rx_mon_dest_process(ar, mac_id, quota, napi);
4949 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
4950 }
4951 dev_kfree_skb_any(status_skb);
4952 }
4953 }
4954
ath11k_dp_mon_process_rx(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)4955 static int ath11k_dp_mon_process_rx(struct ath11k_base *ab, int mac_id,
4956 struct napi_struct *napi, int budget)
4957 {
4958 struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
4959 struct ath11k_pdev_dp *dp = &ar->dp;
4960 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4961 int num_buffs_reaped = 0;
4962
4963 num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ar->ab, mac_id, &budget,
4964 &pmon->rx_status_q);
4965 if (num_buffs_reaped)
4966 ath11k_dp_rx_mon_status_process_tlv(ar, mac_id, budget, napi);
4967
4968 return num_buffs_reaped;
4969 }
4970
ath11k_dp_rx_process_mon_rings(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)4971 int ath11k_dp_rx_process_mon_rings(struct ath11k_base *ab, int mac_id,
4972 struct napi_struct *napi, int budget)
4973 {
4974 struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
4975 int ret = 0;
4976
4977 if (test_bit(ATH11K_FLAG_MONITOR_ENABLED, &ar->monitor_flags))
4978 ret = ath11k_dp_mon_process_rx(ab, mac_id, napi, budget);
4979 else
4980 ret = ath11k_dp_rx_process_mon_status(ab, mac_id, napi, budget);
4981 return ret;
4982 }
4983
ath11k_dp_rx_pdev_mon_status_attach(struct ath11k * ar)4984 static int ath11k_dp_rx_pdev_mon_status_attach(struct ath11k *ar)
4985 {
4986 struct ath11k_pdev_dp *dp = &ar->dp;
4987 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4988
4989 skb_queue_head_init(&pmon->rx_status_q);
4990
4991 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
4992
4993 memset(&pmon->rx_mon_stats, 0,
4994 sizeof(pmon->rx_mon_stats));
4995 return 0;
4996 }
4997
ath11k_dp_rx_pdev_mon_attach(struct ath11k * ar)4998 int ath11k_dp_rx_pdev_mon_attach(struct ath11k *ar)
4999 {
5000 struct ath11k_pdev_dp *dp = &ar->dp;
5001 struct ath11k_mon_data *pmon = &dp->mon_data;
5002 struct hal_srng *mon_desc_srng = NULL;
5003 struct dp_srng *dp_srng;
5004 int ret = 0;
5005 u32 n_link_desc = 0;
5006
5007 ret = ath11k_dp_rx_pdev_mon_status_attach(ar);
5008 if (ret) {
5009 ath11k_warn(ar->ab, "pdev_mon_status_attach() failed");
5010 return ret;
5011 }
5012
5013 /* if rxdma1_enable is false, no need to setup
5014 * rxdma_mon_desc_ring.
5015 */
5016 if (!ar->ab->hw_params.rxdma1_enable)
5017 return 0;
5018
5019 dp_srng = &dp->rxdma_mon_desc_ring;
5020 n_link_desc = dp_srng->size /
5021 ath11k_hal_srng_get_entrysize(ar->ab, HAL_RXDMA_MONITOR_DESC);
5022 mon_desc_srng =
5023 &ar->ab->hal.srng_list[dp->rxdma_mon_desc_ring.ring_id];
5024
5025 ret = ath11k_dp_link_desc_setup(ar->ab, pmon->link_desc_banks,
5026 HAL_RXDMA_MONITOR_DESC, mon_desc_srng,
5027 n_link_desc);
5028 if (ret) {
5029 ath11k_warn(ar->ab, "mon_link_desc_pool_setup() failed");
5030 return ret;
5031 }
5032 pmon->mon_last_linkdesc_paddr = 0;
5033 pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1;
5034 spin_lock_init(&pmon->mon_lock);
5035
5036 return 0;
5037 }
5038
ath11k_dp_mon_link_free(struct ath11k * ar)5039 static int ath11k_dp_mon_link_free(struct ath11k *ar)
5040 {
5041 struct ath11k_pdev_dp *dp = &ar->dp;
5042 struct ath11k_mon_data *pmon = &dp->mon_data;
5043
5044 ath11k_dp_link_desc_cleanup(ar->ab, pmon->link_desc_banks,
5045 HAL_RXDMA_MONITOR_DESC,
5046 &dp->rxdma_mon_desc_ring);
5047 return 0;
5048 }
5049
ath11k_dp_rx_pdev_mon_detach(struct ath11k * ar)5050 int ath11k_dp_rx_pdev_mon_detach(struct ath11k *ar)
5051 {
5052 ath11k_dp_mon_link_free(ar);
5053 return 0;
5054 }
5055