1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include <linux/delay.h>
19 #include "ath9k.h"
20 #include "btcoex.h"
21
22 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
23 u32 queues, bool drop);
24
ath9k_parse_mpdudensity(u8 mpdudensity)25 u8 ath9k_parse_mpdudensity(u8 mpdudensity)
26 {
27 /*
28 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
29 * 0 for no restriction
30 * 1 for 1/4 us
31 * 2 for 1/2 us
32 * 3 for 1 us
33 * 4 for 2 us
34 * 5 for 4 us
35 * 6 for 8 us
36 * 7 for 16 us
37 */
38 switch (mpdudensity) {
39 case 0:
40 return 0;
41 case 1:
42 case 2:
43 case 3:
44 /* Our lower layer calculations limit our precision to
45 1 microsecond */
46 return 1;
47 case 4:
48 return 2;
49 case 5:
50 return 4;
51 case 6:
52 return 8;
53 case 7:
54 return 16;
55 default:
56 return 0;
57 }
58 }
59
ath9k_has_pending_frames(struct ath_softc * sc,struct ath_txq * txq,bool sw_pending)60 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq,
61 bool sw_pending)
62 {
63 bool pending = false;
64
65 spin_lock_bh(&txq->axq_lock);
66
67 if (txq->axq_depth) {
68 pending = true;
69 goto out;
70 }
71
72 if (!sw_pending)
73 goto out;
74
75 if (txq->mac80211_qnum >= 0) {
76 struct ath_acq *acq;
77
78 acq = &sc->cur_chan->acq[txq->mac80211_qnum];
79 if (!list_empty(&acq->acq_new) || !list_empty(&acq->acq_old))
80 pending = true;
81 }
82 out:
83 spin_unlock_bh(&txq->axq_lock);
84 return pending;
85 }
86
ath9k_setpower(struct ath_softc * sc,enum ath9k_power_mode mode)87 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
88 {
89 unsigned long flags;
90 bool ret;
91
92 spin_lock_irqsave(&sc->sc_pm_lock, flags);
93 ret = ath9k_hw_setpower(sc->sc_ah, mode);
94 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
95
96 return ret;
97 }
98
ath_ps_full_sleep(struct timer_list * t)99 void ath_ps_full_sleep(struct timer_list *t)
100 {
101 struct ath_softc *sc = from_timer(sc, t, sleep_timer);
102 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
103 unsigned long flags;
104 bool reset;
105
106 spin_lock_irqsave(&common->cc_lock, flags);
107 ath_hw_cycle_counters_update(common);
108 spin_unlock_irqrestore(&common->cc_lock, flags);
109
110 ath9k_hw_setrxabort(sc->sc_ah, 1);
111 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
112
113 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
114 }
115
ath9k_ps_wakeup(struct ath_softc * sc)116 void ath9k_ps_wakeup(struct ath_softc *sc)
117 {
118 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
119 unsigned long flags;
120 enum ath9k_power_mode power_mode;
121
122 spin_lock_irqsave(&sc->sc_pm_lock, flags);
123 if (++sc->ps_usecount != 1)
124 goto unlock;
125
126 del_timer_sync(&sc->sleep_timer);
127 power_mode = sc->sc_ah->power_mode;
128 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
129
130 /*
131 * While the hardware is asleep, the cycle counters contain no
132 * useful data. Better clear them now so that they don't mess up
133 * survey data results.
134 */
135 if (power_mode != ATH9K_PM_AWAKE) {
136 spin_lock(&common->cc_lock);
137 ath_hw_cycle_counters_update(common);
138 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
139 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
140 spin_unlock(&common->cc_lock);
141 }
142
143 unlock:
144 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
145 }
146
ath9k_ps_restore(struct ath_softc * sc)147 void ath9k_ps_restore(struct ath_softc *sc)
148 {
149 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
150 enum ath9k_power_mode mode;
151 unsigned long flags;
152
153 spin_lock_irqsave(&sc->sc_pm_lock, flags);
154 if (--sc->ps_usecount != 0)
155 goto unlock;
156
157 if (sc->ps_idle) {
158 mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
159 goto unlock;
160 }
161
162 if (sc->ps_enabled &&
163 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
164 PS_WAIT_FOR_CAB |
165 PS_WAIT_FOR_PSPOLL_DATA |
166 PS_WAIT_FOR_TX_ACK |
167 PS_WAIT_FOR_ANI))) {
168 mode = ATH9K_PM_NETWORK_SLEEP;
169 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
170 ath9k_btcoex_stop_gen_timer(sc);
171 } else {
172 goto unlock;
173 }
174
175 spin_lock(&common->cc_lock);
176 ath_hw_cycle_counters_update(common);
177 spin_unlock(&common->cc_lock);
178
179 ath9k_hw_setpower(sc->sc_ah, mode);
180
181 unlock:
182 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
183 }
184
__ath_cancel_work(struct ath_softc * sc)185 static void __ath_cancel_work(struct ath_softc *sc)
186 {
187 cancel_work_sync(&sc->paprd_work);
188 cancel_delayed_work_sync(&sc->hw_check_work);
189 cancel_delayed_work_sync(&sc->hw_pll_work);
190
191 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
192 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
193 cancel_work_sync(&sc->mci_work);
194 #endif
195 }
196
ath_cancel_work(struct ath_softc * sc)197 void ath_cancel_work(struct ath_softc *sc)
198 {
199 __ath_cancel_work(sc);
200 cancel_work_sync(&sc->hw_reset_work);
201 }
202
ath_restart_work(struct ath_softc * sc)203 void ath_restart_work(struct ath_softc *sc)
204 {
205 ieee80211_queue_delayed_work(sc->hw, &sc->hw_check_work,
206 ATH_HW_CHECK_POLL_INT);
207
208 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
209 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
210 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
211
212 ath_start_ani(sc);
213 }
214
ath_prepare_reset(struct ath_softc * sc)215 static bool ath_prepare_reset(struct ath_softc *sc)
216 {
217 struct ath_hw *ah = sc->sc_ah;
218 bool ret = true;
219
220 ieee80211_stop_queues(sc->hw);
221 ath_stop_ani(sc);
222 ath9k_hw_disable_interrupts(ah);
223
224 if (AR_SREV_9300_20_OR_LATER(ah)) {
225 ret &= ath_stoprecv(sc);
226 ret &= ath_drain_all_txq(sc);
227 } else {
228 ret &= ath_drain_all_txq(sc);
229 ret &= ath_stoprecv(sc);
230 }
231
232 return ret;
233 }
234
ath_complete_reset(struct ath_softc * sc,bool start)235 static bool ath_complete_reset(struct ath_softc *sc, bool start)
236 {
237 struct ath_hw *ah = sc->sc_ah;
238 struct ath_common *common = ath9k_hw_common(ah);
239 unsigned long flags;
240
241 ath9k_calculate_summary_state(sc, sc->cur_chan);
242 ath_startrecv(sc);
243 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
244 sc->cur_chan->txpower,
245 &sc->cur_chan->cur_txpower);
246 clear_bit(ATH_OP_HW_RESET, &common->op_flags);
247
248 if (!sc->cur_chan->offchannel && start) {
249 /* restore per chanctx TSF timer */
250 if (sc->cur_chan->tsf_val) {
251 u32 offset;
252
253 offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts,
254 NULL);
255 ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);
256 }
257
258
259 if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
260 goto work;
261
262 if (ah->opmode == NL80211_IFTYPE_STATION &&
263 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
264 spin_lock_irqsave(&sc->sc_pm_lock, flags);
265 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
266 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
267 } else {
268 ath9k_set_beacon(sc);
269 }
270 work:
271 ath_restart_work(sc);
272 ath_txq_schedule_all(sc);
273 }
274
275 sc->gtt_cnt = 0;
276
277 ath9k_hw_set_interrupts(ah);
278 ath9k_hw_enable_interrupts(ah);
279 ieee80211_wake_queues(sc->hw);
280 ath9k_p2p_ps_timer(sc);
281
282 return true;
283 }
284
ath_reset_internal(struct ath_softc * sc,struct ath9k_channel * hchan)285 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
286 {
287 struct ath_hw *ah = sc->sc_ah;
288 struct ath_common *common = ath9k_hw_common(ah);
289 struct ath9k_hw_cal_data *caldata = NULL;
290 bool fastcc = true;
291 int r;
292
293 __ath_cancel_work(sc);
294
295 disable_irq(sc->irq);
296 tasklet_disable(&sc->intr_tq);
297 tasklet_disable(&sc->bcon_tasklet);
298 spin_lock_bh(&sc->sc_pcu_lock);
299
300 if (!sc->cur_chan->offchannel) {
301 fastcc = false;
302 caldata = &sc->cur_chan->caldata;
303 }
304
305 if (!hchan) {
306 fastcc = false;
307 hchan = ah->curchan;
308 }
309
310 if (!hchan) {
311 fastcc = false;
312 hchan = ath9k_cmn_get_channel(sc->hw, ah, &sc->cur_chan->chandef);
313 }
314
315 if (!ath_prepare_reset(sc))
316 fastcc = false;
317
318 if (ath9k_is_chanctx_enabled())
319 fastcc = false;
320
321 spin_lock_bh(&sc->chan_lock);
322 sc->cur_chandef = sc->cur_chan->chandef;
323 spin_unlock_bh(&sc->chan_lock);
324
325 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
326 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
327
328 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
329 if (r) {
330 ath_err(common,
331 "Unable to reset channel, reset status %d\n", r);
332
333 ath9k_hw_enable_interrupts(ah);
334 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
335
336 goto out;
337 }
338
339 if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
340 sc->cur_chan->offchannel)
341 ath9k_mci_set_txpower(sc, true, false);
342
343 if (!ath_complete_reset(sc, true))
344 r = -EIO;
345
346 out:
347 enable_irq(sc->irq);
348 spin_unlock_bh(&sc->sc_pcu_lock);
349 tasklet_enable(&sc->bcon_tasklet);
350 tasklet_enable(&sc->intr_tq);
351
352 return r;
353 }
354
ath_node_attach(struct ath_softc * sc,struct ieee80211_sta * sta,struct ieee80211_vif * vif)355 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
356 struct ieee80211_vif *vif)
357 {
358 struct ath_node *an;
359 an = (struct ath_node *)sta->drv_priv;
360
361 an->sc = sc;
362 an->sta = sta;
363 an->vif = vif;
364 memset(&an->key_idx, 0, sizeof(an->key_idx));
365
366 ath_tx_node_init(sc, an);
367
368 ath_dynack_node_init(sc->sc_ah, an);
369 }
370
ath_node_detach(struct ath_softc * sc,struct ieee80211_sta * sta)371 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
372 {
373 struct ath_node *an = (struct ath_node *)sta->drv_priv;
374 ath_tx_node_cleanup(sc, an);
375
376 ath_dynack_node_deinit(sc->sc_ah, an);
377 }
378
ath9k_tasklet(struct tasklet_struct * t)379 void ath9k_tasklet(struct tasklet_struct *t)
380 {
381 struct ath_softc *sc = from_tasklet(sc, t, intr_tq);
382 struct ath_hw *ah = sc->sc_ah;
383 struct ath_common *common = ath9k_hw_common(ah);
384 enum ath_reset_type type;
385 unsigned long flags;
386 u32 status;
387 u32 rxmask;
388
389 spin_lock_irqsave(&sc->intr_lock, flags);
390 status = sc->intrstatus;
391 sc->intrstatus = 0;
392 spin_unlock_irqrestore(&sc->intr_lock, flags);
393
394 ath9k_ps_wakeup(sc);
395 spin_lock(&sc->sc_pcu_lock);
396
397 if (status & ATH9K_INT_FATAL) {
398 type = RESET_TYPE_FATAL_INT;
399 ath9k_queue_reset(sc, type);
400 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
401 goto out;
402 }
403
404 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
405 (status & ATH9K_INT_BB_WATCHDOG)) {
406 spin_lock_irqsave(&common->cc_lock, flags);
407 ath_hw_cycle_counters_update(common);
408 ar9003_hw_bb_watchdog_dbg_info(ah);
409 spin_unlock_irqrestore(&common->cc_lock, flags);
410
411 if (ar9003_hw_bb_watchdog_check(ah)) {
412 type = RESET_TYPE_BB_WATCHDOG;
413 ath9k_queue_reset(sc, type);
414
415 ath_dbg(common, RESET,
416 "BB_WATCHDOG: Skipping interrupts\n");
417 goto out;
418 }
419 }
420
421 if (status & ATH9K_INT_GTT) {
422 sc->gtt_cnt++;
423
424 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
425 type = RESET_TYPE_TX_GTT;
426 ath9k_queue_reset(sc, type);
427 ath_dbg(common, RESET,
428 "GTT: Skipping interrupts\n");
429 goto out;
430 }
431 }
432
433 spin_lock_irqsave(&sc->sc_pm_lock, flags);
434 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
435 /*
436 * TSF sync does not look correct; remain awake to sync with
437 * the next Beacon.
438 */
439 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
440 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
441 }
442 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
443
444 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
445 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
446 ATH9K_INT_RXORN);
447 else
448 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
449
450 if (status & rxmask) {
451 /* Check for high priority Rx first */
452 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
453 (status & ATH9K_INT_RXHP))
454 ath_rx_tasklet(sc, 0, true);
455
456 ath_rx_tasklet(sc, 0, false);
457 }
458
459 if (status & ATH9K_INT_TX) {
460 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
461 /*
462 * For EDMA chips, TX completion is enabled for the
463 * beacon queue, so if a beacon has been transmitted
464 * successfully after a GTT interrupt, the GTT counter
465 * gets reset to zero here.
466 */
467 sc->gtt_cnt = 0;
468
469 ath_tx_edma_tasklet(sc);
470 } else {
471 ath_tx_tasklet(sc);
472 }
473
474 wake_up(&sc->tx_wait);
475 }
476
477 if (status & ATH9K_INT_GENTIMER)
478 ath_gen_timer_isr(sc->sc_ah);
479
480 ath9k_btcoex_handle_interrupt(sc, status);
481
482 /* re-enable hardware interrupt */
483 ath9k_hw_resume_interrupts(ah);
484 out:
485 spin_unlock(&sc->sc_pcu_lock);
486 ath9k_ps_restore(sc);
487 }
488
ath_isr(int irq,void * dev)489 irqreturn_t ath_isr(int irq, void *dev)
490 {
491 #define SCHED_INTR ( \
492 ATH9K_INT_FATAL | \
493 ATH9K_INT_BB_WATCHDOG | \
494 ATH9K_INT_RXORN | \
495 ATH9K_INT_RXEOL | \
496 ATH9K_INT_RX | \
497 ATH9K_INT_RXLP | \
498 ATH9K_INT_RXHP | \
499 ATH9K_INT_TX | \
500 ATH9K_INT_BMISS | \
501 ATH9K_INT_CST | \
502 ATH9K_INT_GTT | \
503 ATH9K_INT_TSFOOR | \
504 ATH9K_INT_GENTIMER | \
505 ATH9K_INT_MCI)
506
507 struct ath_softc *sc = dev;
508 struct ath_hw *ah = sc->sc_ah;
509 struct ath_common *common = ath9k_hw_common(ah);
510 enum ath9k_int status;
511 u32 sync_cause = 0;
512 bool sched = false;
513
514 /*
515 * The hardware is not ready/present, don't
516 * touch anything. Note this can happen early
517 * on if the IRQ is shared.
518 */
519 if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags))
520 return IRQ_NONE;
521
522 /* shared irq, not for us */
523 if (!ath9k_hw_intrpend(ah))
524 return IRQ_NONE;
525
526 /*
527 * Figure out the reason(s) for the interrupt. Note
528 * that the hal returns a pseudo-ISR that may include
529 * bits we haven't explicitly enabled so we mask the
530 * value to insure we only process bits we requested.
531 */
532 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
533 ath9k_debug_sync_cause(sc, sync_cause);
534 status &= ah->imask; /* discard unasked-for bits */
535
536 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
537 return IRQ_HANDLED;
538
539 /*
540 * If there are no status bits set, then this interrupt was not
541 * for me (should have been caught above).
542 */
543 if (!status)
544 return IRQ_NONE;
545
546 /* Cache the status */
547 spin_lock(&sc->intr_lock);
548 sc->intrstatus |= status;
549 spin_unlock(&sc->intr_lock);
550
551 if (status & SCHED_INTR)
552 sched = true;
553
554 /*
555 * If a FATAL interrupt is received, we have to reset the chip
556 * immediately.
557 */
558 if (status & ATH9K_INT_FATAL)
559 goto chip_reset;
560
561 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
562 (status & ATH9K_INT_BB_WATCHDOG))
563 goto chip_reset;
564
565 if (status & ATH9K_INT_SWBA)
566 tasklet_schedule(&sc->bcon_tasklet);
567
568 if (status & ATH9K_INT_TXURN)
569 ath9k_hw_updatetxtriglevel(ah, true);
570
571 if (status & ATH9K_INT_RXEOL) {
572 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
573 ath9k_hw_set_interrupts(ah);
574 }
575
576 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
577 if (status & ATH9K_INT_TIM_TIMER) {
578 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
579 goto chip_reset;
580 /* Clear RxAbort bit so that we can
581 * receive frames */
582 ath9k_setpower(sc, ATH9K_PM_AWAKE);
583 spin_lock(&sc->sc_pm_lock);
584 ath9k_hw_setrxabort(sc->sc_ah, 0);
585 sc->ps_flags |= PS_WAIT_FOR_BEACON;
586 spin_unlock(&sc->sc_pm_lock);
587 }
588
589 chip_reset:
590
591 ath_debug_stat_interrupt(sc, status);
592
593 if (sched) {
594 /* turn off every interrupt */
595 ath9k_hw_kill_interrupts(ah);
596 tasklet_schedule(&sc->intr_tq);
597 }
598
599 return IRQ_HANDLED;
600
601 #undef SCHED_INTR
602 }
603
604 /*
605 * This function is called when a HW reset cannot be deferred
606 * and has to be immediate.
607 */
ath_reset(struct ath_softc * sc,struct ath9k_channel * hchan)608 int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan)
609 {
610 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
611 int r;
612
613 ath9k_hw_kill_interrupts(sc->sc_ah);
614 set_bit(ATH_OP_HW_RESET, &common->op_flags);
615
616 ath9k_ps_wakeup(sc);
617 r = ath_reset_internal(sc, hchan);
618 ath9k_ps_restore(sc);
619
620 return r;
621 }
622
623 /*
624 * When a HW reset can be deferred, it is added to the
625 * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before
626 * queueing.
627 */
ath9k_queue_reset(struct ath_softc * sc,enum ath_reset_type type)628 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
629 {
630 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
631 #ifdef CONFIG_ATH9K_DEBUGFS
632 RESET_STAT_INC(sc, type);
633 #endif
634 ath9k_hw_kill_interrupts(sc->sc_ah);
635 set_bit(ATH_OP_HW_RESET, &common->op_flags);
636 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
637 }
638
ath_reset_work(struct work_struct * work)639 void ath_reset_work(struct work_struct *work)
640 {
641 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
642
643 ath9k_ps_wakeup(sc);
644 ath_reset_internal(sc, NULL);
645 ath9k_ps_restore(sc);
646 }
647
648 /**********************/
649 /* mac80211 callbacks */
650 /**********************/
651
ath9k_start(struct ieee80211_hw * hw)652 static int ath9k_start(struct ieee80211_hw *hw)
653 {
654 struct ath_softc *sc = hw->priv;
655 struct ath_hw *ah = sc->sc_ah;
656 struct ath_common *common = ath9k_hw_common(ah);
657 struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;
658 struct ath_chanctx *ctx = sc->cur_chan;
659 struct ath9k_channel *init_channel;
660 int r;
661
662 ath_dbg(common, CONFIG,
663 "Starting driver with initial channel: %d MHz\n",
664 curchan->center_freq);
665
666 ath9k_ps_wakeup(sc);
667 mutex_lock(&sc->mutex);
668
669 init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
670 sc->cur_chandef = hw->conf.chandef;
671
672 /* Reset SERDES registers */
673 ath9k_hw_configpcipowersave(ah, false);
674
675 /*
676 * The basic interface to setting the hardware in a good
677 * state is ``reset''. On return the hardware is known to
678 * be powered up and with interrupts disabled. This must
679 * be followed by initialization of the appropriate bits
680 * and then setup of the interrupt mask.
681 */
682 spin_lock_bh(&sc->sc_pcu_lock);
683
684 atomic_set(&ah->intr_ref_cnt, -1);
685
686 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
687 if (r) {
688 ath_err(common,
689 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
690 r, curchan->center_freq);
691 ah->reset_power_on = false;
692 }
693
694 /* Setup our intr mask. */
695 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
696 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
697 ATH9K_INT_GLOBAL;
698
699 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
700 ah->imask |= ATH9K_INT_RXHP |
701 ATH9K_INT_RXLP;
702 else
703 ah->imask |= ATH9K_INT_RX;
704
705 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
706 ah->imask |= ATH9K_INT_BB_WATCHDOG;
707
708 /*
709 * Enable GTT interrupts only for AR9003/AR9004 chips
710 * for now.
711 */
712 if (AR_SREV_9300_20_OR_LATER(ah))
713 ah->imask |= ATH9K_INT_GTT;
714
715 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
716 ah->imask |= ATH9K_INT_CST;
717
718 ath_mci_enable(sc);
719
720 clear_bit(ATH_OP_INVALID, &common->op_flags);
721 sc->sc_ah->is_monitoring = false;
722
723 if (!ath_complete_reset(sc, false))
724 ah->reset_power_on = false;
725
726 if (ah->led_pin >= 0) {
727 ath9k_hw_set_gpio(ah, ah->led_pin,
728 (ah->config.led_active_high) ? 1 : 0);
729 ath9k_hw_gpio_request_out(ah, ah->led_pin, NULL,
730 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
731 }
732
733 /*
734 * Reset key cache to sane defaults (all entries cleared) instead of
735 * semi-random values after suspend/resume.
736 */
737 ath9k_cmn_init_crypto(sc->sc_ah);
738
739 ath9k_hw_reset_tsf(ah);
740
741 spin_unlock_bh(&sc->sc_pcu_lock);
742
743 ath9k_rng_start(sc);
744
745 mutex_unlock(&sc->mutex);
746
747 ath9k_ps_restore(sc);
748
749 return 0;
750 }
751
ath9k_tx(struct ieee80211_hw * hw,struct ieee80211_tx_control * control,struct sk_buff * skb)752 static void ath9k_tx(struct ieee80211_hw *hw,
753 struct ieee80211_tx_control *control,
754 struct sk_buff *skb)
755 {
756 struct ath_softc *sc = hw->priv;
757 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
758 struct ath_tx_control txctl;
759 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
760 unsigned long flags;
761
762 if (sc->ps_enabled) {
763 /*
764 * mac80211 does not set PM field for normal data frames, so we
765 * need to update that based on the current PS mode.
766 */
767 if (ieee80211_is_data(hdr->frame_control) &&
768 !ieee80211_is_nullfunc(hdr->frame_control) &&
769 !ieee80211_has_pm(hdr->frame_control)) {
770 ath_dbg(common, PS,
771 "Add PM=1 for a TX frame while in PS mode\n");
772 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
773 }
774 }
775
776 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
777 /*
778 * We are using PS-Poll and mac80211 can request TX while in
779 * power save mode. Need to wake up hardware for the TX to be
780 * completed and if needed, also for RX of buffered frames.
781 */
782 ath9k_ps_wakeup(sc);
783 spin_lock_irqsave(&sc->sc_pm_lock, flags);
784 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
785 ath9k_hw_setrxabort(sc->sc_ah, 0);
786 if (ieee80211_is_pspoll(hdr->frame_control)) {
787 ath_dbg(common, PS,
788 "Sending PS-Poll to pick a buffered frame\n");
789 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
790 } else {
791 ath_dbg(common, PS, "Wake up to complete TX\n");
792 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
793 }
794 /*
795 * The actual restore operation will happen only after
796 * the ps_flags bit is cleared. We are just dropping
797 * the ps_usecount here.
798 */
799 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
800 ath9k_ps_restore(sc);
801 }
802
803 /*
804 * Cannot tx while the hardware is in full sleep, it first needs a full
805 * chip reset to recover from that
806 */
807 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
808 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
809 goto exit;
810 }
811
812 memset(&txctl, 0, sizeof(struct ath_tx_control));
813 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
814 txctl.sta = control->sta;
815
816 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
817
818 if (ath_tx_start(hw, skb, &txctl) != 0) {
819 ath_dbg(common, XMIT, "TX failed\n");
820 TX_STAT_INC(sc, txctl.txq->axq_qnum, txfailed);
821 goto exit;
822 }
823
824 return;
825 exit:
826 ieee80211_free_txskb(hw, skb);
827 }
828
ath9k_txq_list_has_key(struct list_head * txq_list,u32 keyix)829 static bool ath9k_txq_list_has_key(struct list_head *txq_list, u32 keyix)
830 {
831 struct ath_buf *bf;
832 struct ieee80211_tx_info *txinfo;
833 struct ath_frame_info *fi;
834
835 list_for_each_entry(bf, txq_list, list) {
836 if (bf->bf_state.stale || !bf->bf_mpdu)
837 continue;
838
839 txinfo = IEEE80211_SKB_CB(bf->bf_mpdu);
840 fi = (struct ath_frame_info *)&txinfo->rate_driver_data[0];
841 if (fi->keyix == keyix)
842 return true;
843 }
844
845 return false;
846 }
847
ath9k_txq_has_key(struct ath_softc * sc,u32 keyix)848 static bool ath9k_txq_has_key(struct ath_softc *sc, u32 keyix)
849 {
850 struct ath_hw *ah = sc->sc_ah;
851 int i;
852 struct ath_txq *txq;
853 bool key_in_use = false;
854
855 for (i = 0; !key_in_use && i < ATH9K_NUM_TX_QUEUES; i++) {
856 if (!ATH_TXQ_SETUP(sc, i))
857 continue;
858 txq = &sc->tx.txq[i];
859 if (!txq->axq_depth)
860 continue;
861 if (!ath9k_hw_numtxpending(ah, txq->axq_qnum))
862 continue;
863
864 ath_txq_lock(sc, txq);
865 key_in_use = ath9k_txq_list_has_key(&txq->axq_q, keyix);
866 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
867 int idx = txq->txq_tailidx;
868
869 while (!key_in_use &&
870 !list_empty(&txq->txq_fifo[idx])) {
871 key_in_use = ath9k_txq_list_has_key(
872 &txq->txq_fifo[idx], keyix);
873 INCR(idx, ATH_TXFIFO_DEPTH);
874 }
875 }
876 ath_txq_unlock(sc, txq);
877 }
878
879 return key_in_use;
880 }
881
ath9k_pending_key_del(struct ath_softc * sc,u8 keyix)882 static void ath9k_pending_key_del(struct ath_softc *sc, u8 keyix)
883 {
884 struct ath_hw *ah = sc->sc_ah;
885 struct ath_common *common = ath9k_hw_common(ah);
886
887 if (!test_bit(keyix, ah->pending_del_keymap) ||
888 ath9k_txq_has_key(sc, keyix))
889 return;
890
891 /* No more TXQ frames point to this key cache entry, so delete it. */
892 clear_bit(keyix, ah->pending_del_keymap);
893 ath_key_delete(common, keyix);
894 }
895
ath9k_stop(struct ieee80211_hw * hw)896 static void ath9k_stop(struct ieee80211_hw *hw)
897 {
898 struct ath_softc *sc = hw->priv;
899 struct ath_hw *ah = sc->sc_ah;
900 struct ath_common *common = ath9k_hw_common(ah);
901 bool prev_idle;
902 int i;
903
904 ath9k_deinit_channel_context(sc);
905
906 mutex_lock(&sc->mutex);
907
908 ath9k_rng_stop(sc);
909
910 ath_cancel_work(sc);
911
912 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
913 ath_dbg(common, ANY, "Device not present\n");
914 mutex_unlock(&sc->mutex);
915 return;
916 }
917
918 /* Ensure HW is awake when we try to shut it down. */
919 ath9k_ps_wakeup(sc);
920
921 spin_lock_bh(&sc->sc_pcu_lock);
922
923 /* prevent tasklets to enable interrupts once we disable them */
924 ah->imask &= ~ATH9K_INT_GLOBAL;
925
926 /* make sure h/w will not generate any interrupt
927 * before setting the invalid flag. */
928 ath9k_hw_disable_interrupts(ah);
929
930 spin_unlock_bh(&sc->sc_pcu_lock);
931
932 /* we can now sync irq and kill any running tasklets, since we already
933 * disabled interrupts and not holding a spin lock */
934 synchronize_irq(sc->irq);
935 tasklet_kill(&sc->intr_tq);
936 tasklet_kill(&sc->bcon_tasklet);
937
938 prev_idle = sc->ps_idle;
939 sc->ps_idle = true;
940
941 spin_lock_bh(&sc->sc_pcu_lock);
942
943 if (ah->led_pin >= 0) {
944 ath9k_hw_set_gpio(ah, ah->led_pin,
945 (ah->config.led_active_high) ? 0 : 1);
946 ath9k_hw_gpio_request_in(ah, ah->led_pin, NULL);
947 }
948
949 ath_prepare_reset(sc);
950
951 if (sc->rx.frag) {
952 dev_kfree_skb_any(sc->rx.frag);
953 sc->rx.frag = NULL;
954 }
955
956 if (!ah->curchan)
957 ah->curchan = ath9k_cmn_get_channel(hw, ah,
958 &sc->cur_chan->chandef);
959
960 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
961
962 set_bit(ATH_OP_INVALID, &common->op_flags);
963
964 ath9k_hw_phy_disable(ah);
965
966 ath9k_hw_configpcipowersave(ah, true);
967
968 spin_unlock_bh(&sc->sc_pcu_lock);
969
970 for (i = 0; i < ATH_KEYMAX; i++)
971 ath9k_pending_key_del(sc, i);
972
973 /* Clear key cache entries explicitly to get rid of any potentially
974 * remaining keys.
975 */
976 ath9k_cmn_init_crypto(sc->sc_ah);
977
978 ath9k_ps_restore(sc);
979
980 sc->ps_idle = prev_idle;
981
982 mutex_unlock(&sc->mutex);
983
984 ath_dbg(common, CONFIG, "Driver halt\n");
985 }
986
ath9k_uses_beacons(int type)987 static bool ath9k_uses_beacons(int type)
988 {
989 switch (type) {
990 case NL80211_IFTYPE_AP:
991 case NL80211_IFTYPE_ADHOC:
992 case NL80211_IFTYPE_MESH_POINT:
993 return true;
994 default:
995 return false;
996 }
997 }
998
ath9k_vif_iter_set_beacon(struct ath9k_vif_iter_data * iter_data,struct ieee80211_vif * vif)999 static void ath9k_vif_iter_set_beacon(struct ath9k_vif_iter_data *iter_data,
1000 struct ieee80211_vif *vif)
1001 {
1002 /* Use the first (configured) interface, but prefering AP interfaces. */
1003 if (!iter_data->primary_beacon_vif) {
1004 iter_data->primary_beacon_vif = vif;
1005 } else {
1006 if (iter_data->primary_beacon_vif->type != NL80211_IFTYPE_AP &&
1007 vif->type == NL80211_IFTYPE_AP)
1008 iter_data->primary_beacon_vif = vif;
1009 }
1010
1011 iter_data->beacons = true;
1012 iter_data->nbcnvifs += 1;
1013 }
1014
ath9k_vif_iter(struct ath9k_vif_iter_data * iter_data,u8 * mac,struct ieee80211_vif * vif)1015 static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data,
1016 u8 *mac, struct ieee80211_vif *vif)
1017 {
1018 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
1019 int i;
1020
1021 if (iter_data->has_hw_macaddr) {
1022 for (i = 0; i < ETH_ALEN; i++)
1023 iter_data->mask[i] &=
1024 ~(iter_data->hw_macaddr[i] ^ mac[i]);
1025 } else {
1026 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
1027 iter_data->has_hw_macaddr = true;
1028 }
1029
1030 if (!vif->bss_conf.use_short_slot)
1031 iter_data->slottime = 20;
1032
1033 switch (vif->type) {
1034 case NL80211_IFTYPE_AP:
1035 iter_data->naps++;
1036 if (vif->bss_conf.enable_beacon)
1037 ath9k_vif_iter_set_beacon(iter_data, vif);
1038 break;
1039 case NL80211_IFTYPE_STATION:
1040 iter_data->nstations++;
1041 if (avp->assoc && !iter_data->primary_sta)
1042 iter_data->primary_sta = vif;
1043 break;
1044 case NL80211_IFTYPE_OCB:
1045 iter_data->nocbs++;
1046 break;
1047 case NL80211_IFTYPE_ADHOC:
1048 iter_data->nadhocs++;
1049 if (vif->bss_conf.enable_beacon)
1050 ath9k_vif_iter_set_beacon(iter_data, vif);
1051 break;
1052 case NL80211_IFTYPE_MESH_POINT:
1053 iter_data->nmeshes++;
1054 if (vif->bss_conf.enable_beacon)
1055 ath9k_vif_iter_set_beacon(iter_data, vif);
1056 break;
1057 case NL80211_IFTYPE_WDS:
1058 iter_data->nwds++;
1059 break;
1060 default:
1061 break;
1062 }
1063 }
1064
ath9k_update_bssid_mask(struct ath_softc * sc,struct ath_chanctx * ctx,struct ath9k_vif_iter_data * iter_data)1065 static void ath9k_update_bssid_mask(struct ath_softc *sc,
1066 struct ath_chanctx *ctx,
1067 struct ath9k_vif_iter_data *iter_data)
1068 {
1069 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1070 struct ath_vif *avp;
1071 int i;
1072
1073 if (!ath9k_is_chanctx_enabled())
1074 return;
1075
1076 list_for_each_entry(avp, &ctx->vifs, list) {
1077 if (ctx->nvifs_assigned != 1)
1078 continue;
1079
1080 if (!iter_data->has_hw_macaddr)
1081 continue;
1082
1083 ether_addr_copy(common->curbssid, avp->bssid);
1084
1085 /* perm_addr will be used as the p2p device address. */
1086 for (i = 0; i < ETH_ALEN; i++)
1087 iter_data->mask[i] &=
1088 ~(iter_data->hw_macaddr[i] ^
1089 sc->hw->wiphy->perm_addr[i]);
1090 }
1091 }
1092
1093 /* Called with sc->mutex held. */
ath9k_calculate_iter_data(struct ath_softc * sc,struct ath_chanctx * ctx,struct ath9k_vif_iter_data * iter_data)1094 void ath9k_calculate_iter_data(struct ath_softc *sc,
1095 struct ath_chanctx *ctx,
1096 struct ath9k_vif_iter_data *iter_data)
1097 {
1098 struct ath_vif *avp;
1099
1100 /*
1101 * The hardware will use primary station addr together with the
1102 * BSSID mask when matching addresses.
1103 */
1104 memset(iter_data, 0, sizeof(*iter_data));
1105 eth_broadcast_addr(iter_data->mask);
1106 iter_data->slottime = 9;
1107
1108 list_for_each_entry(avp, &ctx->vifs, list)
1109 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
1110
1111 ath9k_update_bssid_mask(sc, ctx, iter_data);
1112 }
1113
ath9k_set_assoc_state(struct ath_softc * sc,struct ieee80211_vif * vif,bool changed)1114 static void ath9k_set_assoc_state(struct ath_softc *sc,
1115 struct ieee80211_vif *vif, bool changed)
1116 {
1117 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1118 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
1119 unsigned long flags;
1120
1121 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1122
1123 ether_addr_copy(common->curbssid, avp->bssid);
1124 common->curaid = avp->aid;
1125 ath9k_hw_write_associd(sc->sc_ah);
1126
1127 if (changed) {
1128 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
1129 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1130
1131 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1132 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1133 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1134 }
1135
1136 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1137 ath9k_mci_update_wlan_channels(sc, false);
1138
1139 ath_dbg(common, CONFIG,
1140 "Primary Station interface: %pM, BSSID: %pM\n",
1141 vif->addr, common->curbssid);
1142 }
1143
1144 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
ath9k_set_offchannel_state(struct ath_softc * sc)1145 static void ath9k_set_offchannel_state(struct ath_softc *sc)
1146 {
1147 struct ath_hw *ah = sc->sc_ah;
1148 struct ath_common *common = ath9k_hw_common(ah);
1149 struct ieee80211_vif *vif = NULL;
1150
1151 ath9k_ps_wakeup(sc);
1152
1153 if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)
1154 vif = sc->offchannel.scan_vif;
1155 else
1156 vif = sc->offchannel.roc_vif;
1157
1158 if (WARN_ON(!vif))
1159 goto exit;
1160
1161 eth_zero_addr(common->curbssid);
1162 eth_broadcast_addr(common->bssidmask);
1163 memcpy(common->macaddr, vif->addr, ETH_ALEN);
1164 common->curaid = 0;
1165 ah->opmode = vif->type;
1166 ah->imask &= ~ATH9K_INT_SWBA;
1167 ah->imask &= ~ATH9K_INT_TSFOOR;
1168 ah->slottime = 9;
1169
1170 ath_hw_setbssidmask(common);
1171 ath9k_hw_setopmode(ah);
1172 ath9k_hw_write_associd(sc->sc_ah);
1173 ath9k_hw_set_interrupts(ah);
1174 ath9k_hw_init_global_settings(ah);
1175
1176 exit:
1177 ath9k_ps_restore(sc);
1178 }
1179 #endif
1180
1181 /* Called with sc->mutex held. */
ath9k_calculate_summary_state(struct ath_softc * sc,struct ath_chanctx * ctx)1182 void ath9k_calculate_summary_state(struct ath_softc *sc,
1183 struct ath_chanctx *ctx)
1184 {
1185 struct ath_hw *ah = sc->sc_ah;
1186 struct ath_common *common = ath9k_hw_common(ah);
1187 struct ath9k_vif_iter_data iter_data;
1188
1189 ath_chanctx_check_active(sc, ctx);
1190
1191 if (ctx != sc->cur_chan)
1192 return;
1193
1194 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1195 if (ctx == &sc->offchannel.chan)
1196 return ath9k_set_offchannel_state(sc);
1197 #endif
1198
1199 ath9k_ps_wakeup(sc);
1200 ath9k_calculate_iter_data(sc, ctx, &iter_data);
1201
1202 if (iter_data.has_hw_macaddr)
1203 memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN);
1204
1205 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1206 ath_hw_setbssidmask(common);
1207
1208 if (iter_data.naps > 0) {
1209 ath9k_hw_set_tsfadjust(ah, true);
1210 ah->opmode = NL80211_IFTYPE_AP;
1211 } else {
1212 ath9k_hw_set_tsfadjust(ah, false);
1213 if (iter_data.beacons)
1214 ath9k_beacon_ensure_primary_slot(sc);
1215
1216 if (iter_data.nmeshes)
1217 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1218 else if (iter_data.nocbs)
1219 ah->opmode = NL80211_IFTYPE_OCB;
1220 else if (iter_data.nwds)
1221 ah->opmode = NL80211_IFTYPE_AP;
1222 else if (iter_data.nadhocs)
1223 ah->opmode = NL80211_IFTYPE_ADHOC;
1224 else
1225 ah->opmode = NL80211_IFTYPE_STATION;
1226 }
1227
1228 ath9k_hw_setopmode(ah);
1229
1230 ctx->switch_after_beacon = false;
1231 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
1232 ah->imask |= ATH9K_INT_TSFOOR;
1233 else {
1234 ah->imask &= ~ATH9K_INT_TSFOOR;
1235 if (iter_data.naps == 1 && iter_data.beacons)
1236 ctx->switch_after_beacon = true;
1237 }
1238
1239 if (ah->opmode == NL80211_IFTYPE_STATION) {
1240 bool changed = (iter_data.primary_sta != ctx->primary_sta);
1241
1242 if (iter_data.primary_sta) {
1243 iter_data.primary_beacon_vif = iter_data.primary_sta;
1244 iter_data.beacons = true;
1245 ath9k_set_assoc_state(sc, iter_data.primary_sta,
1246 changed);
1247 ctx->primary_sta = iter_data.primary_sta;
1248 } else {
1249 ctx->primary_sta = NULL;
1250 eth_zero_addr(common->curbssid);
1251 common->curaid = 0;
1252 ath9k_hw_write_associd(sc->sc_ah);
1253 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1254 ath9k_mci_update_wlan_channels(sc, true);
1255 }
1256 }
1257 sc->nbcnvifs = iter_data.nbcnvifs;
1258 ath9k_beacon_config(sc, iter_data.primary_beacon_vif,
1259 iter_data.beacons);
1260 ath9k_hw_set_interrupts(ah);
1261
1262 if (ah->slottime != iter_data.slottime) {
1263 ah->slottime = iter_data.slottime;
1264 ath9k_hw_init_global_settings(ah);
1265 }
1266
1267 if (iter_data.primary_sta)
1268 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1269 else
1270 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1271
1272 ath_dbg(common, CONFIG,
1273 "macaddr: %pM, bssid: %pM, bssidmask: %pM\n",
1274 common->macaddr, common->curbssid, common->bssidmask);
1275
1276 ath9k_ps_restore(sc);
1277 }
1278
ath9k_tpc_vif_iter(void * data,u8 * mac,struct ieee80211_vif * vif)1279 static void ath9k_tpc_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1280 {
1281 int *power = data;
1282
1283 if (vif->bss_conf.txpower == INT_MIN)
1284 return;
1285
1286 if (*power < vif->bss_conf.txpower)
1287 *power = vif->bss_conf.txpower;
1288 }
1289
1290 /* Called with sc->mutex held. */
ath9k_set_txpower(struct ath_softc * sc,struct ieee80211_vif * vif)1291 void ath9k_set_txpower(struct ath_softc *sc, struct ieee80211_vif *vif)
1292 {
1293 int power;
1294 struct ath_hw *ah = sc->sc_ah;
1295 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
1296
1297 ath9k_ps_wakeup(sc);
1298 if (ah->tpc_enabled) {
1299 power = (vif) ? vif->bss_conf.txpower : -1;
1300 ieee80211_iterate_active_interfaces_atomic(
1301 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
1302 ath9k_tpc_vif_iter, &power);
1303 if (power == -1)
1304 power = sc->hw->conf.power_level;
1305 } else {
1306 power = sc->hw->conf.power_level;
1307 }
1308 sc->cur_chan->txpower = 2 * power;
1309 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
1310 sc->cur_chan->cur_txpower = reg->max_power_level;
1311 ath9k_ps_restore(sc);
1312 }
1313
ath9k_assign_hw_queues(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1314 static void ath9k_assign_hw_queues(struct ieee80211_hw *hw,
1315 struct ieee80211_vif *vif)
1316 {
1317 int i;
1318
1319 if (!ath9k_is_chanctx_enabled())
1320 return;
1321
1322 for (i = 0; i < IEEE80211_NUM_ACS; i++)
1323 vif->hw_queue[i] = i;
1324
1325 if (vif->type == NL80211_IFTYPE_AP ||
1326 vif->type == NL80211_IFTYPE_MESH_POINT)
1327 vif->cab_queue = hw->queues - 2;
1328 else
1329 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
1330 }
1331
ath9k_add_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1332 static int ath9k_add_interface(struct ieee80211_hw *hw,
1333 struct ieee80211_vif *vif)
1334 {
1335 struct ath_softc *sc = hw->priv;
1336 struct ath_hw *ah = sc->sc_ah;
1337 struct ath_common *common = ath9k_hw_common(ah);
1338 struct ath_vif *avp = (void *)vif->drv_priv;
1339 struct ath_node *an = &avp->mcast_node;
1340
1341 mutex_lock(&sc->mutex);
1342 if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
1343 if (sc->cur_chan->nvifs >= 1) {
1344 mutex_unlock(&sc->mutex);
1345 return -EOPNOTSUPP;
1346 }
1347 sc->tx99_vif = vif;
1348 }
1349
1350 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
1351 sc->cur_chan->nvifs++;
1352
1353 if (vif->type == NL80211_IFTYPE_STATION && ath9k_is_chanctx_enabled())
1354 vif->driver_flags |= IEEE80211_VIF_GET_NOA_UPDATE;
1355
1356 if (ath9k_uses_beacons(vif->type))
1357 ath9k_beacon_assign_slot(sc, vif);
1358
1359 avp->vif = vif;
1360 if (!ath9k_is_chanctx_enabled()) {
1361 avp->chanctx = sc->cur_chan;
1362 list_add_tail(&avp->list, &avp->chanctx->vifs);
1363 }
1364
1365 ath9k_calculate_summary_state(sc, avp->chanctx);
1366
1367 ath9k_assign_hw_queues(hw, vif);
1368
1369 ath9k_set_txpower(sc, vif);
1370
1371 an->sc = sc;
1372 an->sta = NULL;
1373 an->vif = vif;
1374 an->no_ps_filter = true;
1375 ath_tx_node_init(sc, an);
1376
1377 mutex_unlock(&sc->mutex);
1378 return 0;
1379 }
1380
ath9k_change_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif,enum nl80211_iftype new_type,bool p2p)1381 static int ath9k_change_interface(struct ieee80211_hw *hw,
1382 struct ieee80211_vif *vif,
1383 enum nl80211_iftype new_type,
1384 bool p2p)
1385 {
1386 struct ath_softc *sc = hw->priv;
1387 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1388 struct ath_vif *avp = (void *)vif->drv_priv;
1389
1390 mutex_lock(&sc->mutex);
1391
1392 if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
1393 mutex_unlock(&sc->mutex);
1394 return -EOPNOTSUPP;
1395 }
1396
1397 ath_dbg(common, CONFIG, "Change Interface\n");
1398
1399 if (ath9k_uses_beacons(vif->type))
1400 ath9k_beacon_remove_slot(sc, vif);
1401
1402 vif->type = new_type;
1403 vif->p2p = p2p;
1404
1405 if (ath9k_uses_beacons(vif->type))
1406 ath9k_beacon_assign_slot(sc, vif);
1407
1408 ath9k_assign_hw_queues(hw, vif);
1409 ath9k_calculate_summary_state(sc, avp->chanctx);
1410
1411 ath9k_set_txpower(sc, vif);
1412
1413 mutex_unlock(&sc->mutex);
1414 return 0;
1415 }
1416
ath9k_remove_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1417 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1418 struct ieee80211_vif *vif)
1419 {
1420 struct ath_softc *sc = hw->priv;
1421 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1422 struct ath_vif *avp = (void *)vif->drv_priv;
1423
1424 ath_dbg(common, CONFIG, "Detach Interface\n");
1425
1426 mutex_lock(&sc->mutex);
1427
1428 ath9k_p2p_remove_vif(sc, vif);
1429
1430 sc->cur_chan->nvifs--;
1431 sc->tx99_vif = NULL;
1432 if (!ath9k_is_chanctx_enabled())
1433 list_del(&avp->list);
1434
1435 if (ath9k_uses_beacons(vif->type))
1436 ath9k_beacon_remove_slot(sc, vif);
1437
1438 ath_tx_node_cleanup(sc, &avp->mcast_node);
1439
1440 ath9k_calculate_summary_state(sc, avp->chanctx);
1441
1442 ath9k_set_txpower(sc, NULL);
1443
1444 mutex_unlock(&sc->mutex);
1445 }
1446
ath9k_enable_ps(struct ath_softc * sc)1447 static void ath9k_enable_ps(struct ath_softc *sc)
1448 {
1449 struct ath_hw *ah = sc->sc_ah;
1450 struct ath_common *common = ath9k_hw_common(ah);
1451
1452 if (IS_ENABLED(CONFIG_ATH9K_TX99))
1453 return;
1454
1455 sc->ps_enabled = true;
1456 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1457 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1458 ah->imask |= ATH9K_INT_TIM_TIMER;
1459 ath9k_hw_set_interrupts(ah);
1460 }
1461 ath9k_hw_setrxabort(ah, 1);
1462 }
1463 ath_dbg(common, PS, "PowerSave enabled\n");
1464 }
1465
ath9k_disable_ps(struct ath_softc * sc)1466 static void ath9k_disable_ps(struct ath_softc *sc)
1467 {
1468 struct ath_hw *ah = sc->sc_ah;
1469 struct ath_common *common = ath9k_hw_common(ah);
1470
1471 if (IS_ENABLED(CONFIG_ATH9K_TX99))
1472 return;
1473
1474 sc->ps_enabled = false;
1475 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1476 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1477 ath9k_hw_setrxabort(ah, 0);
1478 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1479 PS_WAIT_FOR_CAB |
1480 PS_WAIT_FOR_PSPOLL_DATA |
1481 PS_WAIT_FOR_TX_ACK);
1482 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1483 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1484 ath9k_hw_set_interrupts(ah);
1485 }
1486 }
1487 ath_dbg(common, PS, "PowerSave disabled\n");
1488 }
1489
ath9k_config(struct ieee80211_hw * hw,u32 changed)1490 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1491 {
1492 struct ath_softc *sc = hw->priv;
1493 struct ath_hw *ah = sc->sc_ah;
1494 struct ath_common *common = ath9k_hw_common(ah);
1495 struct ieee80211_conf *conf = &hw->conf;
1496 struct ath_chanctx *ctx = sc->cur_chan;
1497
1498 ath9k_ps_wakeup(sc);
1499 mutex_lock(&sc->mutex);
1500
1501 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1502 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1503 if (sc->ps_idle) {
1504 ath_cancel_work(sc);
1505 ath9k_stop_btcoex(sc);
1506 } else {
1507 ath9k_start_btcoex(sc);
1508 /*
1509 * The chip needs a reset to properly wake up from
1510 * full sleep
1511 */
1512 ath_chanctx_set_channel(sc, ctx, &ctx->chandef);
1513 }
1514 }
1515
1516 /*
1517 * We just prepare to enable PS. We have to wait until our AP has
1518 * ACK'd our null data frame to disable RX otherwise we'll ignore
1519 * those ACKs and end up retransmitting the same null data frames.
1520 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1521 */
1522 if (changed & IEEE80211_CONF_CHANGE_PS) {
1523 unsigned long flags;
1524 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1525 if (conf->flags & IEEE80211_CONF_PS)
1526 ath9k_enable_ps(sc);
1527 else
1528 ath9k_disable_ps(sc);
1529 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1530 }
1531
1532 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1533 if (conf->flags & IEEE80211_CONF_MONITOR) {
1534 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1535 sc->sc_ah->is_monitoring = true;
1536 } else {
1537 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1538 sc->sc_ah->is_monitoring = false;
1539 }
1540 }
1541
1542 if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
1543 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
1544 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
1545 }
1546
1547 if (changed & IEEE80211_CONF_CHANGE_POWER)
1548 ath9k_set_txpower(sc, NULL);
1549
1550 mutex_unlock(&sc->mutex);
1551 ath9k_ps_restore(sc);
1552
1553 return 0;
1554 }
1555
1556 #define SUPPORTED_FILTERS \
1557 (FIF_ALLMULTI | \
1558 FIF_CONTROL | \
1559 FIF_PSPOLL | \
1560 FIF_OTHER_BSS | \
1561 FIF_BCN_PRBRESP_PROMISC | \
1562 FIF_PROBE_REQ | \
1563 FIF_MCAST_ACTION | \
1564 FIF_FCSFAIL)
1565
1566 /* FIXME: sc->sc_full_reset ? */
ath9k_configure_filter(struct ieee80211_hw * hw,unsigned int changed_flags,unsigned int * total_flags,u64 multicast)1567 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1568 unsigned int changed_flags,
1569 unsigned int *total_flags,
1570 u64 multicast)
1571 {
1572 struct ath_softc *sc = hw->priv;
1573 struct ath_chanctx *ctx;
1574 u32 rfilt;
1575
1576 changed_flags &= SUPPORTED_FILTERS;
1577 *total_flags &= SUPPORTED_FILTERS;
1578
1579 spin_lock_bh(&sc->chan_lock);
1580 ath_for_each_chanctx(sc, ctx)
1581 ctx->rxfilter = *total_flags;
1582 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1583 sc->offchannel.chan.rxfilter = *total_flags;
1584 #endif
1585 spin_unlock_bh(&sc->chan_lock);
1586
1587 ath9k_ps_wakeup(sc);
1588 rfilt = ath_calcrxfilter(sc);
1589 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1590 ath9k_ps_restore(sc);
1591
1592 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1593 rfilt);
1594 }
1595
ath9k_sta_add(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1596 static int ath9k_sta_add(struct ieee80211_hw *hw,
1597 struct ieee80211_vif *vif,
1598 struct ieee80211_sta *sta)
1599 {
1600 struct ath_softc *sc = hw->priv;
1601 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1602 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1603 struct ieee80211_key_conf ps_key = { };
1604 int key;
1605
1606 ath_node_attach(sc, sta, vif);
1607
1608 if (vif->type != NL80211_IFTYPE_AP &&
1609 vif->type != NL80211_IFTYPE_AP_VLAN)
1610 return 0;
1611
1612 key = ath_key_config(common, vif, sta, &ps_key);
1613 if (key > 0) {
1614 an->ps_key = key;
1615 an->key_idx[0] = key;
1616 }
1617
1618 return 0;
1619 }
1620
ath9k_del_ps_key(struct ath_softc * sc,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1621 static void ath9k_del_ps_key(struct ath_softc *sc,
1622 struct ieee80211_vif *vif,
1623 struct ieee80211_sta *sta)
1624 {
1625 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1626 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1627
1628 if (!an->ps_key)
1629 return;
1630
1631 ath_key_delete(common, an->ps_key);
1632 an->ps_key = 0;
1633 an->key_idx[0] = 0;
1634 }
1635
ath9k_sta_remove(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1636 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1637 struct ieee80211_vif *vif,
1638 struct ieee80211_sta *sta)
1639 {
1640 struct ath_softc *sc = hw->priv;
1641
1642 ath9k_del_ps_key(sc, vif, sta);
1643 ath_node_detach(sc, sta);
1644
1645 return 0;
1646 }
1647
ath9k_sta_state(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta,enum ieee80211_sta_state old_state,enum ieee80211_sta_state new_state)1648 static int ath9k_sta_state(struct ieee80211_hw *hw,
1649 struct ieee80211_vif *vif,
1650 struct ieee80211_sta *sta,
1651 enum ieee80211_sta_state old_state,
1652 enum ieee80211_sta_state new_state)
1653 {
1654 struct ath_softc *sc = hw->priv;
1655 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1656 int ret = 0;
1657
1658 if (old_state == IEEE80211_STA_NOTEXIST &&
1659 new_state == IEEE80211_STA_NONE) {
1660 ret = ath9k_sta_add(hw, vif, sta);
1661 ath_dbg(common, CONFIG,
1662 "Add station: %pM\n", sta->addr);
1663 } else if (old_state == IEEE80211_STA_NONE &&
1664 new_state == IEEE80211_STA_NOTEXIST) {
1665 ret = ath9k_sta_remove(hw, vif, sta);
1666 ath_dbg(common, CONFIG,
1667 "Remove station: %pM\n", sta->addr);
1668 }
1669
1670 if (ath9k_is_chanctx_enabled()) {
1671 if (vif->type == NL80211_IFTYPE_STATION) {
1672 if (old_state == IEEE80211_STA_ASSOC &&
1673 new_state == IEEE80211_STA_AUTHORIZED)
1674 ath_chanctx_event(sc, vif,
1675 ATH_CHANCTX_EVENT_AUTHORIZED);
1676 }
1677 }
1678
1679 return ret;
1680 }
1681
ath9k_sta_set_tx_filter(struct ath_hw * ah,struct ath_node * an,bool set)1682 static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
1683 struct ath_node *an,
1684 bool set)
1685 {
1686 int i;
1687
1688 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1689 if (!an->key_idx[i])
1690 continue;
1691 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
1692 }
1693 }
1694
ath9k_sta_notify(struct ieee80211_hw * hw,struct ieee80211_vif * vif,enum sta_notify_cmd cmd,struct ieee80211_sta * sta)1695 static void ath9k_sta_notify(struct ieee80211_hw *hw,
1696 struct ieee80211_vif *vif,
1697 enum sta_notify_cmd cmd,
1698 struct ieee80211_sta *sta)
1699 {
1700 struct ath_softc *sc = hw->priv;
1701 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1702
1703 switch (cmd) {
1704 case STA_NOTIFY_SLEEP:
1705 an->sleeping = true;
1706 ath_tx_aggr_sleep(sta, sc, an);
1707 ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
1708 break;
1709 case STA_NOTIFY_AWAKE:
1710 ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
1711 an->sleeping = false;
1712 ath_tx_aggr_wakeup(sc, an);
1713 break;
1714 }
1715 }
1716
ath9k_conf_tx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u16 queue,const struct ieee80211_tx_queue_params * params)1717 static int ath9k_conf_tx(struct ieee80211_hw *hw,
1718 struct ieee80211_vif *vif, u16 queue,
1719 const struct ieee80211_tx_queue_params *params)
1720 {
1721 struct ath_softc *sc = hw->priv;
1722 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1723 struct ath_txq *txq;
1724 struct ath9k_tx_queue_info qi;
1725 int ret = 0;
1726
1727 if (queue >= IEEE80211_NUM_ACS)
1728 return 0;
1729
1730 txq = sc->tx.txq_map[queue];
1731
1732 ath9k_ps_wakeup(sc);
1733 mutex_lock(&sc->mutex);
1734
1735 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1736
1737 qi.tqi_aifs = params->aifs;
1738 qi.tqi_cwmin = params->cw_min;
1739 qi.tqi_cwmax = params->cw_max;
1740 qi.tqi_burstTime = params->txop * 32;
1741
1742 ath_dbg(common, CONFIG,
1743 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1744 queue, txq->axq_qnum, params->aifs, params->cw_min,
1745 params->cw_max, params->txop);
1746
1747 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
1748 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1749 if (ret)
1750 ath_err(common, "TXQ Update failed\n");
1751
1752 mutex_unlock(&sc->mutex);
1753 ath9k_ps_restore(sc);
1754
1755 return ret;
1756 }
1757
ath9k_set_key(struct ieee80211_hw * hw,enum set_key_cmd cmd,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct ieee80211_key_conf * key)1758 static int ath9k_set_key(struct ieee80211_hw *hw,
1759 enum set_key_cmd cmd,
1760 struct ieee80211_vif *vif,
1761 struct ieee80211_sta *sta,
1762 struct ieee80211_key_conf *key)
1763 {
1764 struct ath_softc *sc = hw->priv;
1765 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1766 struct ath_node *an = NULL;
1767 int ret = 0, i;
1768
1769 if (ath9k_modparam_nohwcrypt)
1770 return -ENOSPC;
1771
1772 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1773 vif->type == NL80211_IFTYPE_MESH_POINT) &&
1774 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1775 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1776 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1777 /*
1778 * For now, disable hw crypto for the RSN IBSS group keys. This
1779 * could be optimized in the future to use a modified key cache
1780 * design to support per-STA RX GTK, but until that gets
1781 * implemented, use of software crypto for group addressed
1782 * frames is a acceptable to allow RSN IBSS to be used.
1783 */
1784 return -EOPNOTSUPP;
1785 }
1786
1787 /* There may be MPDUs queued for the outgoing PTK key. Flush queues to
1788 * make sure these are not send unencrypted or with a wrong (new) key
1789 */
1790 if (cmd == DISABLE_KEY && key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
1791 ieee80211_stop_queues(hw);
1792 ath9k_flush(hw, vif, 0, true);
1793 ieee80211_wake_queues(hw);
1794 }
1795
1796 mutex_lock(&sc->mutex);
1797 ath9k_ps_wakeup(sc);
1798 ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
1799 if (sta)
1800 an = (struct ath_node *)sta->drv_priv;
1801
1802 /* Delete pending key cache entries if no more frames are pointing to
1803 * them in TXQs.
1804 */
1805 for (i = 0; i < ATH_KEYMAX; i++)
1806 ath9k_pending_key_del(sc, i);
1807
1808 switch (cmd) {
1809 case SET_KEY:
1810 if (sta)
1811 ath9k_del_ps_key(sc, vif, sta);
1812
1813 key->hw_key_idx = 0;
1814 ret = ath_key_config(common, vif, sta, key);
1815 if (ret >= 0) {
1816 key->hw_key_idx = ret;
1817 /* push IV and Michael MIC generation to stack */
1818 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1819 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1820 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1821 if (sc->sc_ah->sw_mgmt_crypto_tx &&
1822 key->cipher == WLAN_CIPHER_SUITE_CCMP)
1823 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
1824 ret = 0;
1825 }
1826 if (an && key->hw_key_idx) {
1827 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1828 if (an->key_idx[i])
1829 continue;
1830 an->key_idx[i] = key->hw_key_idx;
1831 break;
1832 }
1833 WARN_ON(i == ARRAY_SIZE(an->key_idx));
1834 }
1835 break;
1836 case DISABLE_KEY:
1837 if (ath9k_txq_has_key(sc, key->hw_key_idx)) {
1838 /* Delay key cache entry deletion until there are no
1839 * remaining TXQ frames pointing to this entry.
1840 */
1841 set_bit(key->hw_key_idx, sc->sc_ah->pending_del_keymap);
1842 ath_hw_keysetmac(common, key->hw_key_idx, NULL);
1843 } else {
1844 ath_key_delete(common, key->hw_key_idx);
1845 }
1846 if (an) {
1847 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1848 if (an->key_idx[i] != key->hw_key_idx)
1849 continue;
1850 an->key_idx[i] = 0;
1851 break;
1852 }
1853 }
1854 key->hw_key_idx = 0;
1855 break;
1856 default:
1857 ret = -EINVAL;
1858 }
1859
1860 ath9k_ps_restore(sc);
1861 mutex_unlock(&sc->mutex);
1862
1863 return ret;
1864 }
1865
ath9k_bss_info_changed(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_bss_conf * bss_conf,u32 changed)1866 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1867 struct ieee80211_vif *vif,
1868 struct ieee80211_bss_conf *bss_conf,
1869 u32 changed)
1870 {
1871 #define CHECK_ANI \
1872 (BSS_CHANGED_ASSOC | \
1873 BSS_CHANGED_IBSS | \
1874 BSS_CHANGED_BEACON_ENABLED)
1875
1876 struct ath_softc *sc = hw->priv;
1877 struct ath_hw *ah = sc->sc_ah;
1878 struct ath_common *common = ath9k_hw_common(ah);
1879 struct ath_vif *avp = (void *)vif->drv_priv;
1880 int slottime;
1881
1882 ath9k_ps_wakeup(sc);
1883 mutex_lock(&sc->mutex);
1884
1885 if (changed & BSS_CHANGED_ASSOC) {
1886 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1887 bss_conf->bssid, bss_conf->assoc);
1888
1889 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1890 avp->aid = bss_conf->aid;
1891 avp->assoc = bss_conf->assoc;
1892
1893 ath9k_calculate_summary_state(sc, avp->chanctx);
1894 }
1895
1896 if ((changed & BSS_CHANGED_IBSS) ||
1897 (changed & BSS_CHANGED_OCB)) {
1898 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1899 common->curaid = bss_conf->aid;
1900 ath9k_hw_write_associd(sc->sc_ah);
1901 }
1902
1903 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1904 (changed & BSS_CHANGED_BEACON_INT) ||
1905 (changed & BSS_CHANGED_BEACON_INFO)) {
1906 ath9k_calculate_summary_state(sc, avp->chanctx);
1907 }
1908
1909 if ((avp->chanctx == sc->cur_chan) &&
1910 (changed & BSS_CHANGED_ERP_SLOT)) {
1911 if (bss_conf->use_short_slot)
1912 slottime = 9;
1913 else
1914 slottime = 20;
1915
1916 if (vif->type == NL80211_IFTYPE_AP) {
1917 /*
1918 * Defer update, so that connected stations can adjust
1919 * their settings at the same time.
1920 * See beacon.c for more details
1921 */
1922 sc->beacon.slottime = slottime;
1923 sc->beacon.updateslot = UPDATE;
1924 } else {
1925 ah->slottime = slottime;
1926 ath9k_hw_init_global_settings(ah);
1927 }
1928 }
1929
1930 if (changed & BSS_CHANGED_P2P_PS)
1931 ath9k_p2p_bss_info_changed(sc, vif);
1932
1933 if (changed & CHECK_ANI)
1934 ath_check_ani(sc);
1935
1936 if (changed & BSS_CHANGED_TXPOWER) {
1937 ath_dbg(common, CONFIG, "vif %pM power %d dbm power_type %d\n",
1938 vif->addr, bss_conf->txpower, bss_conf->txpower_type);
1939 ath9k_set_txpower(sc, vif);
1940 }
1941
1942 mutex_unlock(&sc->mutex);
1943 ath9k_ps_restore(sc);
1944
1945 #undef CHECK_ANI
1946 }
1947
ath9k_get_tsf(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1948 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1949 {
1950 struct ath_softc *sc = hw->priv;
1951 struct ath_vif *avp = (void *)vif->drv_priv;
1952 u64 tsf;
1953
1954 mutex_lock(&sc->mutex);
1955 ath9k_ps_wakeup(sc);
1956 /* Get current TSF either from HW or kernel time. */
1957 if (sc->cur_chan == avp->chanctx) {
1958 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1959 } else {
1960 tsf = sc->cur_chan->tsf_val +
1961 ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, NULL);
1962 }
1963 tsf += le64_to_cpu(avp->tsf_adjust);
1964 ath9k_ps_restore(sc);
1965 mutex_unlock(&sc->mutex);
1966
1967 return tsf;
1968 }
1969
ath9k_set_tsf(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u64 tsf)1970 static void ath9k_set_tsf(struct ieee80211_hw *hw,
1971 struct ieee80211_vif *vif,
1972 u64 tsf)
1973 {
1974 struct ath_softc *sc = hw->priv;
1975 struct ath_vif *avp = (void *)vif->drv_priv;
1976
1977 mutex_lock(&sc->mutex);
1978 ath9k_ps_wakeup(sc);
1979 tsf -= le64_to_cpu(avp->tsf_adjust);
1980 ktime_get_raw_ts64(&avp->chanctx->tsf_ts);
1981 if (sc->cur_chan == avp->chanctx)
1982 ath9k_hw_settsf64(sc->sc_ah, tsf);
1983 avp->chanctx->tsf_val = tsf;
1984 ath9k_ps_restore(sc);
1985 mutex_unlock(&sc->mutex);
1986 }
1987
ath9k_reset_tsf(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1988 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1989 {
1990 struct ath_softc *sc = hw->priv;
1991 struct ath_vif *avp = (void *)vif->drv_priv;
1992
1993 mutex_lock(&sc->mutex);
1994
1995 ath9k_ps_wakeup(sc);
1996 ktime_get_raw_ts64(&avp->chanctx->tsf_ts);
1997 if (sc->cur_chan == avp->chanctx)
1998 ath9k_hw_reset_tsf(sc->sc_ah);
1999 avp->chanctx->tsf_val = 0;
2000 ath9k_ps_restore(sc);
2001
2002 mutex_unlock(&sc->mutex);
2003 }
2004
ath9k_ampdu_action(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_ampdu_params * params)2005 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2006 struct ieee80211_vif *vif,
2007 struct ieee80211_ampdu_params *params)
2008 {
2009 struct ath_softc *sc = hw->priv;
2010 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2011 bool flush = false;
2012 int ret = 0;
2013 struct ieee80211_sta *sta = params->sta;
2014 struct ath_node *an = (struct ath_node *)sta->drv_priv;
2015 enum ieee80211_ampdu_mlme_action action = params->action;
2016 u16 tid = params->tid;
2017 u16 *ssn = ¶ms->ssn;
2018 struct ath_atx_tid *atid;
2019
2020 mutex_lock(&sc->mutex);
2021
2022 switch (action) {
2023 case IEEE80211_AMPDU_RX_START:
2024 break;
2025 case IEEE80211_AMPDU_RX_STOP:
2026 break;
2027 case IEEE80211_AMPDU_TX_START:
2028 if (ath9k_is_chanctx_enabled()) {
2029 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2030 ret = -EBUSY;
2031 break;
2032 }
2033 }
2034 ath9k_ps_wakeup(sc);
2035 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2036 if (!ret)
2037 ret = IEEE80211_AMPDU_TX_START_IMMEDIATE;
2038 ath9k_ps_restore(sc);
2039 break;
2040 case IEEE80211_AMPDU_TX_STOP_FLUSH:
2041 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
2042 flush = true;
2043 fallthrough;
2044 case IEEE80211_AMPDU_TX_STOP_CONT:
2045 ath9k_ps_wakeup(sc);
2046 ath_tx_aggr_stop(sc, sta, tid);
2047 if (!flush)
2048 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2049 ath9k_ps_restore(sc);
2050 break;
2051 case IEEE80211_AMPDU_TX_OPERATIONAL:
2052 atid = ath_node_to_tid(an, tid);
2053 atid->baw_size = IEEE80211_MIN_AMPDU_BUF <<
2054 sta->ht_cap.ampdu_factor;
2055 break;
2056 default:
2057 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
2058 }
2059
2060 mutex_unlock(&sc->mutex);
2061
2062 return ret;
2063 }
2064
ath9k_get_survey(struct ieee80211_hw * hw,int idx,struct survey_info * survey)2065 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2066 struct survey_info *survey)
2067 {
2068 struct ath_softc *sc = hw->priv;
2069 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2070 struct ieee80211_supported_band *sband;
2071 struct ieee80211_channel *chan;
2072 unsigned long flags;
2073 int pos;
2074
2075 if (IS_ENABLED(CONFIG_ATH9K_TX99))
2076 return -EOPNOTSUPP;
2077
2078 spin_lock_irqsave(&common->cc_lock, flags);
2079 if (idx == 0)
2080 ath_update_survey_stats(sc);
2081
2082 sband = hw->wiphy->bands[NL80211_BAND_2GHZ];
2083 if (sband && idx >= sband->n_channels) {
2084 idx -= sband->n_channels;
2085 sband = NULL;
2086 }
2087
2088 if (!sband)
2089 sband = hw->wiphy->bands[NL80211_BAND_5GHZ];
2090
2091 if (!sband || idx >= sband->n_channels) {
2092 spin_unlock_irqrestore(&common->cc_lock, flags);
2093 return -ENOENT;
2094 }
2095
2096 chan = &sband->channels[idx];
2097 pos = chan->hw_value;
2098 memcpy(survey, &sc->survey[pos], sizeof(*survey));
2099 survey->channel = chan;
2100 spin_unlock_irqrestore(&common->cc_lock, flags);
2101
2102 return 0;
2103 }
2104
ath9k_enable_dynack(struct ath_softc * sc)2105 static void ath9k_enable_dynack(struct ath_softc *sc)
2106 {
2107 #ifdef CONFIG_ATH9K_DYNACK
2108 u32 rfilt;
2109 struct ath_hw *ah = sc->sc_ah;
2110
2111 ath_dynack_reset(ah);
2112
2113 ah->dynack.enabled = true;
2114 rfilt = ath_calcrxfilter(sc);
2115 ath9k_hw_setrxfilter(ah, rfilt);
2116 #endif
2117 }
2118
ath9k_set_coverage_class(struct ieee80211_hw * hw,s16 coverage_class)2119 static void ath9k_set_coverage_class(struct ieee80211_hw *hw,
2120 s16 coverage_class)
2121 {
2122 struct ath_softc *sc = hw->priv;
2123 struct ath_hw *ah = sc->sc_ah;
2124
2125 if (IS_ENABLED(CONFIG_ATH9K_TX99))
2126 return;
2127
2128 mutex_lock(&sc->mutex);
2129
2130 if (coverage_class >= 0) {
2131 ah->coverage_class = coverage_class;
2132 if (ah->dynack.enabled) {
2133 u32 rfilt;
2134
2135 ah->dynack.enabled = false;
2136 rfilt = ath_calcrxfilter(sc);
2137 ath9k_hw_setrxfilter(ah, rfilt);
2138 }
2139 ath9k_ps_wakeup(sc);
2140 ath9k_hw_init_global_settings(ah);
2141 ath9k_ps_restore(sc);
2142 } else if (!ah->dynack.enabled) {
2143 ath9k_enable_dynack(sc);
2144 }
2145
2146 mutex_unlock(&sc->mutex);
2147 }
2148
ath9k_has_tx_pending(struct ath_softc * sc,bool sw_pending)2149 static bool ath9k_has_tx_pending(struct ath_softc *sc,
2150 bool sw_pending)
2151 {
2152 int i, npend = 0;
2153
2154 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2155 if (!ATH_TXQ_SETUP(sc, i))
2156 continue;
2157
2158 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i],
2159 sw_pending);
2160 if (npend)
2161 break;
2162 }
2163
2164 return !!npend;
2165 }
2166
ath9k_flush(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u32 queues,bool drop)2167 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2168 u32 queues, bool drop)
2169 {
2170 struct ath_softc *sc = hw->priv;
2171 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2172
2173 if (ath9k_is_chanctx_enabled()) {
2174 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2175 goto flush;
2176
2177 /*
2178 * If MCC is active, extend the flush timeout
2179 * and wait for the HW/SW queues to become
2180 * empty. This needs to be done outside the
2181 * sc->mutex lock to allow the channel scheduler
2182 * to switch channel contexts.
2183 *
2184 * The vif queues have been stopped in mac80211,
2185 * so there won't be any incoming frames.
2186 */
2187 __ath9k_flush(hw, queues, drop, true, true);
2188 return;
2189 }
2190 flush:
2191 mutex_lock(&sc->mutex);
2192 __ath9k_flush(hw, queues, drop, true, false);
2193 mutex_unlock(&sc->mutex);
2194 }
2195
__ath9k_flush(struct ieee80211_hw * hw,u32 queues,bool drop,bool sw_pending,bool timeout_override)2196 void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop,
2197 bool sw_pending, bool timeout_override)
2198 {
2199 struct ath_softc *sc = hw->priv;
2200 struct ath_hw *ah = sc->sc_ah;
2201 struct ath_common *common = ath9k_hw_common(ah);
2202 int timeout;
2203 bool drain_txq;
2204
2205 cancel_delayed_work_sync(&sc->hw_check_work);
2206
2207 if (ah->ah_flags & AH_UNPLUGGED) {
2208 ath_dbg(common, ANY, "Device has been unplugged!\n");
2209 return;
2210 }
2211
2212 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
2213 ath_dbg(common, ANY, "Device not present\n");
2214 return;
2215 }
2216
2217 spin_lock_bh(&sc->chan_lock);
2218 if (timeout_override)
2219 timeout = HZ / 5;
2220 else
2221 timeout = sc->cur_chan->flush_timeout;
2222 spin_unlock_bh(&sc->chan_lock);
2223
2224 ath_dbg(common, CHAN_CTX,
2225 "Flush timeout: %d\n", jiffies_to_msecs(timeout));
2226
2227 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending),
2228 timeout) > 0)
2229 drop = false;
2230
2231 if (drop) {
2232 ath9k_ps_wakeup(sc);
2233 spin_lock_bh(&sc->sc_pcu_lock);
2234 drain_txq = ath_drain_all_txq(sc);
2235 spin_unlock_bh(&sc->sc_pcu_lock);
2236
2237 if (!drain_txq)
2238 ath_reset(sc, NULL);
2239
2240 ath9k_ps_restore(sc);
2241 }
2242
2243 ieee80211_queue_delayed_work(hw, &sc->hw_check_work,
2244 ATH_HW_CHECK_POLL_INT);
2245 }
2246
ath9k_tx_frames_pending(struct ieee80211_hw * hw)2247 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2248 {
2249 struct ath_softc *sc = hw->priv;
2250
2251 return ath9k_has_tx_pending(sc, true);
2252 }
2253
ath9k_tx_last_beacon(struct ieee80211_hw * hw)2254 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
2255 {
2256 struct ath_softc *sc = hw->priv;
2257 struct ath_hw *ah = sc->sc_ah;
2258 struct ieee80211_vif *vif;
2259 struct ath_vif *avp;
2260 struct ath_buf *bf;
2261 struct ath_tx_status ts;
2262 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2263 int status;
2264
2265 vif = sc->beacon.bslot[0];
2266 if (!vif)
2267 return 0;
2268
2269 if (!vif->bss_conf.enable_beacon)
2270 return 0;
2271
2272 avp = (void *)vif->drv_priv;
2273
2274 if (!sc->beacon.tx_processed && !edma) {
2275 tasklet_disable(&sc->bcon_tasklet);
2276
2277 bf = avp->av_bcbuf;
2278 if (!bf || !bf->bf_mpdu)
2279 goto skip;
2280
2281 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2282 if (status == -EINPROGRESS)
2283 goto skip;
2284
2285 sc->beacon.tx_processed = true;
2286 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2287
2288 skip:
2289 tasklet_enable(&sc->bcon_tasklet);
2290 }
2291
2292 return sc->beacon.tx_last;
2293 }
2294
ath9k_get_stats(struct ieee80211_hw * hw,struct ieee80211_low_level_stats * stats)2295 static int ath9k_get_stats(struct ieee80211_hw *hw,
2296 struct ieee80211_low_level_stats *stats)
2297 {
2298 struct ath_softc *sc = hw->priv;
2299 struct ath_hw *ah = sc->sc_ah;
2300 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2301
2302 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2303 stats->dot11RTSFailureCount = mib_stats->rts_bad;
2304 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2305 stats->dot11RTSSuccessCount = mib_stats->rts_good;
2306 return 0;
2307 }
2308
fill_chainmask(u32 cap,u32 new)2309 static u32 fill_chainmask(u32 cap, u32 new)
2310 {
2311 u32 filled = 0;
2312 int i;
2313
2314 for (i = 0; cap && new; i++, cap >>= 1) {
2315 if (!(cap & BIT(0)))
2316 continue;
2317
2318 if (new & BIT(0))
2319 filled |= BIT(i);
2320
2321 new >>= 1;
2322 }
2323
2324 return filled;
2325 }
2326
validate_antenna_mask(struct ath_hw * ah,u32 val)2327 static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
2328 {
2329 if (AR_SREV_9300_20_OR_LATER(ah))
2330 return true;
2331
2332 switch (val & 0x7) {
2333 case 0x1:
2334 case 0x3:
2335 case 0x7:
2336 return true;
2337 case 0x2:
2338 return (ah->caps.rx_chainmask == 1);
2339 default:
2340 return false;
2341 }
2342 }
2343
ath9k_set_antenna(struct ieee80211_hw * hw,u32 tx_ant,u32 rx_ant)2344 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2345 {
2346 struct ath_softc *sc = hw->priv;
2347 struct ath_hw *ah = sc->sc_ah;
2348
2349 if (ah->caps.rx_chainmask != 1)
2350 rx_ant |= tx_ant;
2351
2352 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
2353 return -EINVAL;
2354
2355 sc->ant_rx = rx_ant;
2356 sc->ant_tx = tx_ant;
2357
2358 if (ah->caps.rx_chainmask == 1)
2359 return 0;
2360
2361 /* AR9100 runs into calibration issues if not all rx chains are enabled */
2362 if (AR_SREV_9100(ah))
2363 ah->rxchainmask = 0x7;
2364 else
2365 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2366
2367 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
2368 ath9k_cmn_reload_chainmask(ah);
2369
2370 return 0;
2371 }
2372
ath9k_get_antenna(struct ieee80211_hw * hw,u32 * tx_ant,u32 * rx_ant)2373 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2374 {
2375 struct ath_softc *sc = hw->priv;
2376
2377 *tx_ant = sc->ant_tx;
2378 *rx_ant = sc->ant_rx;
2379 return 0;
2380 }
2381
ath9k_sw_scan_start(struct ieee80211_hw * hw,struct ieee80211_vif * vif,const u8 * mac_addr)2382 static void ath9k_sw_scan_start(struct ieee80211_hw *hw,
2383 struct ieee80211_vif *vif,
2384 const u8 *mac_addr)
2385 {
2386 struct ath_softc *sc = hw->priv;
2387 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2388 set_bit(ATH_OP_SCANNING, &common->op_flags);
2389 }
2390
ath9k_sw_scan_complete(struct ieee80211_hw * hw,struct ieee80211_vif * vif)2391 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw,
2392 struct ieee80211_vif *vif)
2393 {
2394 struct ath_softc *sc = hw->priv;
2395 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2396 clear_bit(ATH_OP_SCANNING, &common->op_flags);
2397 }
2398
2399 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
2400
ath9k_cancel_pending_offchannel(struct ath_softc * sc)2401 static void ath9k_cancel_pending_offchannel(struct ath_softc *sc)
2402 {
2403 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2404
2405 if (sc->offchannel.roc_vif) {
2406 ath_dbg(common, CHAN_CTX,
2407 "%s: Aborting RoC\n", __func__);
2408
2409 del_timer_sync(&sc->offchannel.timer);
2410 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2411 ath_roc_complete(sc, ATH_ROC_COMPLETE_ABORT);
2412 }
2413
2414 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2415 ath_dbg(common, CHAN_CTX,
2416 "%s: Aborting HW scan\n", __func__);
2417
2418 del_timer_sync(&sc->offchannel.timer);
2419 ath_scan_complete(sc, true);
2420 }
2421 }
2422
ath9k_hw_scan(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_scan_request * hw_req)2423 static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2424 struct ieee80211_scan_request *hw_req)
2425 {
2426 struct cfg80211_scan_request *req = &hw_req->req;
2427 struct ath_softc *sc = hw->priv;
2428 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2429 int ret = 0;
2430
2431 mutex_lock(&sc->mutex);
2432
2433 if (WARN_ON(sc->offchannel.scan_req)) {
2434 ret = -EBUSY;
2435 goto out;
2436 }
2437
2438 ath9k_ps_wakeup(sc);
2439 set_bit(ATH_OP_SCANNING, &common->op_flags);
2440 sc->offchannel.scan_vif = vif;
2441 sc->offchannel.scan_req = req;
2442 sc->offchannel.scan_idx = 0;
2443
2444 ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
2445 vif->addr);
2446
2447 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2448 ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
2449 ath_offchannel_next(sc);
2450 }
2451
2452 out:
2453 mutex_unlock(&sc->mutex);
2454
2455 return ret;
2456 }
2457
ath9k_cancel_hw_scan(struct ieee80211_hw * hw,struct ieee80211_vif * vif)2458 static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
2459 struct ieee80211_vif *vif)
2460 {
2461 struct ath_softc *sc = hw->priv;
2462 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2463
2464 ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
2465
2466 mutex_lock(&sc->mutex);
2467 del_timer_sync(&sc->offchannel.timer);
2468 ath_scan_complete(sc, true);
2469 mutex_unlock(&sc->mutex);
2470 }
2471
ath9k_remain_on_channel(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_channel * chan,int duration,enum ieee80211_roc_type type)2472 static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
2473 struct ieee80211_vif *vif,
2474 struct ieee80211_channel *chan, int duration,
2475 enum ieee80211_roc_type type)
2476 {
2477 struct ath_softc *sc = hw->priv;
2478 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2479 int ret = 0;
2480
2481 mutex_lock(&sc->mutex);
2482
2483 if (WARN_ON(sc->offchannel.roc_vif)) {
2484 ret = -EBUSY;
2485 goto out;
2486 }
2487
2488 ath9k_ps_wakeup(sc);
2489 sc->offchannel.roc_vif = vif;
2490 sc->offchannel.roc_chan = chan;
2491 sc->offchannel.roc_duration = duration;
2492
2493 ath_dbg(common, CHAN_CTX,
2494 "RoC request on vif: %pM, type: %d duration: %d\n",
2495 vif->addr, type, duration);
2496
2497 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2498 ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
2499 ath_offchannel_next(sc);
2500 }
2501
2502 out:
2503 mutex_unlock(&sc->mutex);
2504
2505 return ret;
2506 }
2507
ath9k_cancel_remain_on_channel(struct ieee80211_hw * hw,struct ieee80211_vif * vif)2508 static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw,
2509 struct ieee80211_vif *vif)
2510 {
2511 struct ath_softc *sc = hw->priv;
2512 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2513
2514 mutex_lock(&sc->mutex);
2515
2516 ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
2517 del_timer_sync(&sc->offchannel.timer);
2518
2519 if (sc->offchannel.roc_vif) {
2520 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2521 ath_roc_complete(sc, ATH_ROC_COMPLETE_CANCEL);
2522 }
2523
2524 mutex_unlock(&sc->mutex);
2525
2526 return 0;
2527 }
2528
ath9k_add_chanctx(struct ieee80211_hw * hw,struct ieee80211_chanctx_conf * conf)2529 static int ath9k_add_chanctx(struct ieee80211_hw *hw,
2530 struct ieee80211_chanctx_conf *conf)
2531 {
2532 struct ath_softc *sc = hw->priv;
2533 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2534 struct ath_chanctx *ctx, **ptr;
2535 int pos;
2536
2537 mutex_lock(&sc->mutex);
2538
2539 ath_for_each_chanctx(sc, ctx) {
2540 if (ctx->assigned)
2541 continue;
2542
2543 ptr = (void *) conf->drv_priv;
2544 *ptr = ctx;
2545 ctx->assigned = true;
2546 pos = ctx - &sc->chanctx[0];
2547 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
2548
2549 ath_dbg(common, CHAN_CTX,
2550 "Add channel context: %d MHz\n",
2551 conf->def.chan->center_freq);
2552
2553 ath_chanctx_set_channel(sc, ctx, &conf->def);
2554
2555 mutex_unlock(&sc->mutex);
2556 return 0;
2557 }
2558
2559 mutex_unlock(&sc->mutex);
2560 return -ENOSPC;
2561 }
2562
2563
ath9k_remove_chanctx(struct ieee80211_hw * hw,struct ieee80211_chanctx_conf * conf)2564 static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
2565 struct ieee80211_chanctx_conf *conf)
2566 {
2567 struct ath_softc *sc = hw->priv;
2568 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2569 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2570
2571 mutex_lock(&sc->mutex);
2572
2573 ath_dbg(common, CHAN_CTX,
2574 "Remove channel context: %d MHz\n",
2575 conf->def.chan->center_freq);
2576
2577 ctx->assigned = false;
2578 ctx->hw_queue_base = 0;
2579 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
2580
2581 mutex_unlock(&sc->mutex);
2582 }
2583
ath9k_change_chanctx(struct ieee80211_hw * hw,struct ieee80211_chanctx_conf * conf,u32 changed)2584 static void ath9k_change_chanctx(struct ieee80211_hw *hw,
2585 struct ieee80211_chanctx_conf *conf,
2586 u32 changed)
2587 {
2588 struct ath_softc *sc = hw->priv;
2589 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2590 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2591
2592 mutex_lock(&sc->mutex);
2593 ath_dbg(common, CHAN_CTX,
2594 "Change channel context: %d MHz\n",
2595 conf->def.chan->center_freq);
2596 ath_chanctx_set_channel(sc, ctx, &conf->def);
2597 mutex_unlock(&sc->mutex);
2598 }
2599
ath9k_assign_vif_chanctx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_chanctx_conf * conf)2600 static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
2601 struct ieee80211_vif *vif,
2602 struct ieee80211_chanctx_conf *conf)
2603 {
2604 struct ath_softc *sc = hw->priv;
2605 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2606 struct ath_vif *avp = (void *)vif->drv_priv;
2607 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2608 int i;
2609
2610 ath9k_cancel_pending_offchannel(sc);
2611
2612 mutex_lock(&sc->mutex);
2613
2614 ath_dbg(common, CHAN_CTX,
2615 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
2616 vif->addr, vif->type, vif->p2p,
2617 conf->def.chan->center_freq);
2618
2619 avp->chanctx = ctx;
2620 ctx->nvifs_assigned++;
2621 list_add_tail(&avp->list, &ctx->vifs);
2622 ath9k_calculate_summary_state(sc, ctx);
2623 for (i = 0; i < IEEE80211_NUM_ACS; i++)
2624 vif->hw_queue[i] = ctx->hw_queue_base + i;
2625
2626 mutex_unlock(&sc->mutex);
2627
2628 return 0;
2629 }
2630
ath9k_unassign_vif_chanctx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_chanctx_conf * conf)2631 static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
2632 struct ieee80211_vif *vif,
2633 struct ieee80211_chanctx_conf *conf)
2634 {
2635 struct ath_softc *sc = hw->priv;
2636 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2637 struct ath_vif *avp = (void *)vif->drv_priv;
2638 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2639 int ac;
2640
2641 ath9k_cancel_pending_offchannel(sc);
2642
2643 mutex_lock(&sc->mutex);
2644
2645 ath_dbg(common, CHAN_CTX,
2646 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
2647 vif->addr, vif->type, vif->p2p,
2648 conf->def.chan->center_freq);
2649
2650 avp->chanctx = NULL;
2651 ctx->nvifs_assigned--;
2652 list_del(&avp->list);
2653 ath9k_calculate_summary_state(sc, ctx);
2654 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
2655 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
2656
2657 mutex_unlock(&sc->mutex);
2658 }
2659
ath9k_mgd_prepare_tx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u16 duration)2660 static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,
2661 struct ieee80211_vif *vif,
2662 u16 duration)
2663 {
2664 struct ath_softc *sc = hw->priv;
2665 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2666 struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;
2667 struct ath_beacon_config *cur_conf;
2668 struct ath_chanctx *go_ctx;
2669 unsigned long timeout;
2670 bool changed = false;
2671 u32 beacon_int;
2672
2673 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2674 return;
2675
2676 if (!avp->chanctx)
2677 return;
2678
2679 mutex_lock(&sc->mutex);
2680
2681 spin_lock_bh(&sc->chan_lock);
2682 if (sc->next_chan || (sc->cur_chan != avp->chanctx))
2683 changed = true;
2684 spin_unlock_bh(&sc->chan_lock);
2685
2686 if (!changed)
2687 goto out;
2688
2689 ath9k_cancel_pending_offchannel(sc);
2690
2691 go_ctx = ath_is_go_chanctx_present(sc);
2692
2693 if (go_ctx) {
2694 /*
2695 * Wait till the GO interface gets a chance
2696 * to send out an NoA.
2697 */
2698 spin_lock_bh(&sc->chan_lock);
2699 sc->sched.mgd_prepare_tx = true;
2700 cur_conf = &go_ctx->beacon;
2701 beacon_int = TU_TO_USEC(cur_conf->beacon_interval);
2702 spin_unlock_bh(&sc->chan_lock);
2703
2704 timeout = usecs_to_jiffies(beacon_int * 2);
2705 init_completion(&sc->go_beacon);
2706
2707 mutex_unlock(&sc->mutex);
2708
2709 if (wait_for_completion_timeout(&sc->go_beacon,
2710 timeout) == 0) {
2711 ath_dbg(common, CHAN_CTX,
2712 "Failed to send new NoA\n");
2713
2714 spin_lock_bh(&sc->chan_lock);
2715 sc->sched.mgd_prepare_tx = false;
2716 spin_unlock_bh(&sc->chan_lock);
2717 }
2718
2719 mutex_lock(&sc->mutex);
2720 }
2721
2722 ath_dbg(common, CHAN_CTX,
2723 "%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n",
2724 __func__, vif->addr);
2725
2726 spin_lock_bh(&sc->chan_lock);
2727 sc->next_chan = avp->chanctx;
2728 sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;
2729 spin_unlock_bh(&sc->chan_lock);
2730
2731 ath_chanctx_set_next(sc, true);
2732 out:
2733 mutex_unlock(&sc->mutex);
2734 }
2735
ath9k_fill_chanctx_ops(void)2736 void ath9k_fill_chanctx_ops(void)
2737 {
2738 if (!ath9k_is_chanctx_enabled())
2739 return;
2740
2741 ath9k_ops.hw_scan = ath9k_hw_scan;
2742 ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan;
2743 ath9k_ops.remain_on_channel = ath9k_remain_on_channel;
2744 ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
2745 ath9k_ops.add_chanctx = ath9k_add_chanctx;
2746 ath9k_ops.remove_chanctx = ath9k_remove_chanctx;
2747 ath9k_ops.change_chanctx = ath9k_change_chanctx;
2748 ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx;
2749 ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx;
2750 ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx;
2751 }
2752
2753 #endif
2754
ath9k_get_txpower(struct ieee80211_hw * hw,struct ieee80211_vif * vif,int * dbm)2755 static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2756 int *dbm)
2757 {
2758 struct ath_softc *sc = hw->priv;
2759 struct ath_vif *avp = (void *)vif->drv_priv;
2760
2761 mutex_lock(&sc->mutex);
2762 if (avp->chanctx)
2763 *dbm = avp->chanctx->cur_txpower;
2764 else
2765 *dbm = sc->cur_chan->cur_txpower;
2766 mutex_unlock(&sc->mutex);
2767
2768 *dbm /= 2;
2769
2770 return 0;
2771 }
2772
2773 struct ieee80211_ops ath9k_ops = {
2774 .tx = ath9k_tx,
2775 .start = ath9k_start,
2776 .stop = ath9k_stop,
2777 .add_interface = ath9k_add_interface,
2778 .change_interface = ath9k_change_interface,
2779 .remove_interface = ath9k_remove_interface,
2780 .config = ath9k_config,
2781 .configure_filter = ath9k_configure_filter,
2782 .sta_state = ath9k_sta_state,
2783 .sta_notify = ath9k_sta_notify,
2784 .conf_tx = ath9k_conf_tx,
2785 .bss_info_changed = ath9k_bss_info_changed,
2786 .set_key = ath9k_set_key,
2787 .get_tsf = ath9k_get_tsf,
2788 .set_tsf = ath9k_set_tsf,
2789 .reset_tsf = ath9k_reset_tsf,
2790 .ampdu_action = ath9k_ampdu_action,
2791 .get_survey = ath9k_get_survey,
2792 .rfkill_poll = ath9k_rfkill_poll_state,
2793 .set_coverage_class = ath9k_set_coverage_class,
2794 .flush = ath9k_flush,
2795 .tx_frames_pending = ath9k_tx_frames_pending,
2796 .tx_last_beacon = ath9k_tx_last_beacon,
2797 .release_buffered_frames = ath9k_release_buffered_frames,
2798 .get_stats = ath9k_get_stats,
2799 .set_antenna = ath9k_set_antenna,
2800 .get_antenna = ath9k_get_antenna,
2801
2802 #ifdef CONFIG_ATH9K_WOW
2803 .suspend = ath9k_suspend,
2804 .resume = ath9k_resume,
2805 .set_wakeup = ath9k_set_wakeup,
2806 #endif
2807
2808 #ifdef CONFIG_ATH9K_DEBUGFS
2809 .get_et_sset_count = ath9k_get_et_sset_count,
2810 .get_et_stats = ath9k_get_et_stats,
2811 .get_et_strings = ath9k_get_et_strings,
2812 #endif
2813
2814 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
2815 .sta_add_debugfs = ath9k_sta_add_debugfs,
2816 #endif
2817 .sw_scan_start = ath9k_sw_scan_start,
2818 .sw_scan_complete = ath9k_sw_scan_complete,
2819 .get_txpower = ath9k_get_txpower,
2820 .wake_tx_queue = ath9k_wake_tx_queue,
2821 };
2822