1 /*
2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40
41 #include <linux/slab.h>
42 #include "pm8001_sas.h"
43 #include "pm8001_chips.h"
44 #include "pm80xx_hwi.h"
45
46 static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING;
47 module_param(logging_level, ulong, 0644);
48 MODULE_PARM_DESC(logging_level, " bits for enabling logging info.");
49
50 static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120;
51 module_param(link_rate, ulong, 0644);
52 MODULE_PARM_DESC(link_rate, "Enable link rate.\n"
53 " 1: Link rate 1.5G\n"
54 " 2: Link rate 3.0G\n"
55 " 4: Link rate 6.0G\n"
56 " 8: Link rate 12.0G\n");
57
58 static struct scsi_transport_template *pm8001_stt;
59 static int pm8001_init_ccb_tag(struct pm8001_hba_info *, struct Scsi_Host *, struct pci_dev *);
60
61 /*
62 * chip info structure to identify chip key functionality as
63 * encryption available/not, no of ports, hw specific function ref
64 */
65 static const struct pm8001_chip_info pm8001_chips[] = {
66 [chip_8001] = {0, 8, &pm8001_8001_dispatch,},
67 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,},
68 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,},
69 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,},
70 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,},
71 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,},
72 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,},
73 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,},
74 [chip_8006] = {0, 16, &pm8001_80xx_dispatch,},
75 [chip_8070] = {0, 8, &pm8001_80xx_dispatch,},
76 [chip_8072] = {0, 16, &pm8001_80xx_dispatch,},
77 };
78 static int pm8001_id;
79
80 LIST_HEAD(hba_list);
81
82 struct workqueue_struct *pm8001_wq;
83
84 /*
85 * The main structure which LLDD must register for scsi core.
86 */
87 static struct scsi_host_template pm8001_sht = {
88 .module = THIS_MODULE,
89 .name = DRV_NAME,
90 .queuecommand = sas_queuecommand,
91 .dma_need_drain = ata_scsi_dma_need_drain,
92 .target_alloc = sas_target_alloc,
93 .slave_configure = sas_slave_configure,
94 .scan_finished = pm8001_scan_finished,
95 .scan_start = pm8001_scan_start,
96 .change_queue_depth = sas_change_queue_depth,
97 .bios_param = sas_bios_param,
98 .can_queue = 1,
99 .this_id = -1,
100 .sg_tablesize = PM8001_MAX_DMA_SG,
101 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
102 .eh_device_reset_handler = sas_eh_device_reset_handler,
103 .eh_target_reset_handler = sas_eh_target_reset_handler,
104 .slave_alloc = sas_slave_alloc,
105 .target_destroy = sas_target_destroy,
106 .ioctl = sas_ioctl,
107 #ifdef CONFIG_COMPAT
108 .compat_ioctl = sas_ioctl,
109 #endif
110 .shost_attrs = pm8001_host_attrs,
111 .track_queue_depth = 1,
112 };
113
114 /*
115 * Sas layer call this function to execute specific task.
116 */
117 static struct sas_domain_function_template pm8001_transport_ops = {
118 .lldd_dev_found = pm8001_dev_found,
119 .lldd_dev_gone = pm8001_dev_gone,
120
121 .lldd_execute_task = pm8001_queue_command,
122 .lldd_control_phy = pm8001_phy_control,
123
124 .lldd_abort_task = pm8001_abort_task,
125 .lldd_abort_task_set = pm8001_abort_task_set,
126 .lldd_clear_aca = pm8001_clear_aca,
127 .lldd_clear_task_set = pm8001_clear_task_set,
128 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset,
129 .lldd_lu_reset = pm8001_lu_reset,
130 .lldd_query_task = pm8001_query_task,
131 };
132
133 /**
134 * pm8001_phy_init - initiate our adapter phys
135 * @pm8001_ha: our hba structure.
136 * @phy_id: phy id.
137 */
pm8001_phy_init(struct pm8001_hba_info * pm8001_ha,int phy_id)138 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
139 {
140 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
141 struct asd_sas_phy *sas_phy = &phy->sas_phy;
142 phy->phy_state = PHY_LINK_DISABLE;
143 phy->pm8001_ha = pm8001_ha;
144 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
145 sas_phy->class = SAS;
146 sas_phy->iproto = SAS_PROTOCOL_ALL;
147 sas_phy->tproto = 0;
148 sas_phy->type = PHY_TYPE_PHYSICAL;
149 sas_phy->role = PHY_ROLE_INITIATOR;
150 sas_phy->oob_mode = OOB_NOT_CONNECTED;
151 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
152 sas_phy->id = phy_id;
153 sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr;
154 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
155 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
156 sas_phy->lldd_phy = phy;
157 }
158
159 /**
160 * pm8001_free - free hba
161 * @pm8001_ha: our hba structure.
162 */
pm8001_free(struct pm8001_hba_info * pm8001_ha)163 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
164 {
165 int i;
166
167 if (!pm8001_ha)
168 return;
169
170 for (i = 0; i < USI_MAX_MEMCNT; i++) {
171 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
172 dma_free_coherent(&pm8001_ha->pdev->dev,
173 (pm8001_ha->memoryMap.region[i].total_len +
174 pm8001_ha->memoryMap.region[i].alignment),
175 pm8001_ha->memoryMap.region[i].virt_ptr,
176 pm8001_ha->memoryMap.region[i].phys_addr);
177 }
178 }
179 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
180 flush_workqueue(pm8001_wq);
181 kfree(pm8001_ha->tags);
182 kfree(pm8001_ha);
183 }
184
185 #ifdef PM8001_USE_TASKLET
186
187 /**
188 * tasklet for 64 msi-x interrupt handler
189 * @opaque: the passed general host adapter struct
190 * Note: pm8001_tasklet is common for pm8001 & pm80xx
191 */
pm8001_tasklet(unsigned long opaque)192 static void pm8001_tasklet(unsigned long opaque)
193 {
194 struct pm8001_hba_info *pm8001_ha;
195 struct isr_param *irq_vector;
196
197 irq_vector = (struct isr_param *)opaque;
198 pm8001_ha = irq_vector->drv_inst;
199 if (unlikely(!pm8001_ha))
200 BUG_ON(1);
201 PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
202 }
203 #endif
204
205 /**
206 * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
207 * It obtains the vector number and calls the equivalent bottom
208 * half or services directly.
209 * @irq: interrupt number
210 * @opaque: the passed outbound queue/vector. Host structure is
211 * retrieved from the same.
212 */
pm8001_interrupt_handler_msix(int irq,void * opaque)213 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
214 {
215 struct isr_param *irq_vector;
216 struct pm8001_hba_info *pm8001_ha;
217 irqreturn_t ret = IRQ_HANDLED;
218 irq_vector = (struct isr_param *)opaque;
219 pm8001_ha = irq_vector->drv_inst;
220
221 if (unlikely(!pm8001_ha))
222 return IRQ_NONE;
223 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
224 return IRQ_NONE;
225 #ifdef PM8001_USE_TASKLET
226 tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
227 #else
228 ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
229 #endif
230 return ret;
231 }
232
233 /**
234 * pm8001_interrupt_handler_intx - main INTx interrupt handler.
235 * @irq: interrupt number
236 * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure.
237 */
238
pm8001_interrupt_handler_intx(int irq,void * dev_id)239 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
240 {
241 struct pm8001_hba_info *pm8001_ha;
242 irqreturn_t ret = IRQ_HANDLED;
243 struct sas_ha_struct *sha = dev_id;
244 pm8001_ha = sha->lldd_ha;
245 if (unlikely(!pm8001_ha))
246 return IRQ_NONE;
247 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
248 return IRQ_NONE;
249
250 #ifdef PM8001_USE_TASKLET
251 tasklet_schedule(&pm8001_ha->tasklet[0]);
252 #else
253 ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
254 #endif
255 return ret;
256 }
257
258 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha);
259 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha);
260
261 /**
262 * pm8001_alloc - initiate our hba structure and 6 DMAs area.
263 * @pm8001_ha: our hba structure.
264 * @ent: PCI device ID structure to match on
265 */
pm8001_alloc(struct pm8001_hba_info * pm8001_ha,const struct pci_device_id * ent)266 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
267 const struct pci_device_id *ent)
268 {
269 int i, count = 0, rc = 0;
270 u32 ci_offset, ib_offset, ob_offset, pi_offset;
271 struct inbound_queue_table *circularQ;
272
273 spin_lock_init(&pm8001_ha->lock);
274 spin_lock_init(&pm8001_ha->bitmap_lock);
275 pm8001_dbg(pm8001_ha, INIT, "pm8001_alloc: PHY:%x\n",
276 pm8001_ha->chip->n_phy);
277
278 /* Setup Interrupt */
279 rc = pm8001_setup_irq(pm8001_ha);
280 if (rc) {
281 pm8001_dbg(pm8001_ha, FAIL,
282 "pm8001_setup_irq failed [ret: %d]\n", rc);
283 goto err_out_shost;
284 }
285 /* Request Interrupt */
286 rc = pm8001_request_irq(pm8001_ha);
287 if (rc)
288 goto err_out_shost;
289
290 count = pm8001_ha->max_q_num;
291 /* Queues are chosen based on the number of cores/msix availability */
292 ib_offset = pm8001_ha->ib_offset = USI_MAX_MEMCNT_BASE;
293 ci_offset = pm8001_ha->ci_offset = ib_offset + count;
294 ob_offset = pm8001_ha->ob_offset = ci_offset + count;
295 pi_offset = pm8001_ha->pi_offset = ob_offset + count;
296 pm8001_ha->max_memcnt = pi_offset + count;
297
298 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
299 pm8001_phy_init(pm8001_ha, i);
300 pm8001_ha->port[i].wide_port_phymap = 0;
301 pm8001_ha->port[i].port_attached = 0;
302 pm8001_ha->port[i].port_state = 0;
303 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
304 }
305
306 /* MPI Memory region 1 for AAP Event Log for fw */
307 pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
308 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
309 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
310 pm8001_ha->memoryMap.region[AAP1].alignment = 32;
311
312 /* MPI Memory region 2 for IOP Event Log for fw */
313 pm8001_ha->memoryMap.region[IOP].num_elements = 1;
314 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
315 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
316 pm8001_ha->memoryMap.region[IOP].alignment = 32;
317
318 for (i = 0; i < count; i++) {
319 circularQ = &pm8001_ha->inbnd_q_tbl[i];
320 spin_lock_init(&circularQ->iq_lock);
321 /* MPI Memory region 3 for consumer Index of inbound queues */
322 pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1;
323 pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4;
324 pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4;
325 pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4;
326
327 if ((ent->driver_data) != chip_8001) {
328 /* MPI Memory region 5 inbound queues */
329 pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
330 PM8001_MPI_QUEUE;
331 pm8001_ha->memoryMap.region[ib_offset+i].element_size
332 = 128;
333 pm8001_ha->memoryMap.region[ib_offset+i].total_len =
334 PM8001_MPI_QUEUE * 128;
335 pm8001_ha->memoryMap.region[ib_offset+i].alignment
336 = 128;
337 } else {
338 pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
339 PM8001_MPI_QUEUE;
340 pm8001_ha->memoryMap.region[ib_offset+i].element_size
341 = 64;
342 pm8001_ha->memoryMap.region[ib_offset+i].total_len =
343 PM8001_MPI_QUEUE * 64;
344 pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64;
345 }
346 }
347
348 for (i = 0; i < count; i++) {
349 /* MPI Memory region 4 for producer Index of outbound queues */
350 pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1;
351 pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4;
352 pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4;
353 pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4;
354
355 if (ent->driver_data != chip_8001) {
356 /* MPI Memory region 6 Outbound queues */
357 pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
358 PM8001_MPI_QUEUE;
359 pm8001_ha->memoryMap.region[ob_offset+i].element_size
360 = 128;
361 pm8001_ha->memoryMap.region[ob_offset+i].total_len =
362 PM8001_MPI_QUEUE * 128;
363 pm8001_ha->memoryMap.region[ob_offset+i].alignment
364 = 128;
365 } else {
366 /* MPI Memory region 6 Outbound queues */
367 pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
368 PM8001_MPI_QUEUE;
369 pm8001_ha->memoryMap.region[ob_offset+i].element_size
370 = 64;
371 pm8001_ha->memoryMap.region[ob_offset+i].total_len =
372 PM8001_MPI_QUEUE * 64;
373 pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64;
374 }
375
376 }
377 /* Memory region write DMA*/
378 pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
379 pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
380 pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
381
382 /* Memory region for fw flash */
383 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
384
385 pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
386 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
387 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
388 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
389 for (i = 0; i < pm8001_ha->max_memcnt; i++) {
390 if (pm8001_mem_alloc(pm8001_ha->pdev,
391 &pm8001_ha->memoryMap.region[i].virt_ptr,
392 &pm8001_ha->memoryMap.region[i].phys_addr,
393 &pm8001_ha->memoryMap.region[i].phys_addr_hi,
394 &pm8001_ha->memoryMap.region[i].phys_addr_lo,
395 pm8001_ha->memoryMap.region[i].total_len,
396 pm8001_ha->memoryMap.region[i].alignment) != 0) {
397 pm8001_dbg(pm8001_ha, FAIL,
398 "Mem%d alloc failed\n",
399 i);
400 goto err_out;
401 }
402 }
403
404 /* Memory region for devices*/
405 pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES
406 * sizeof(struct pm8001_device), GFP_KERNEL);
407 if (!pm8001_ha->devices) {
408 rc = -ENOMEM;
409 goto err_out_nodev;
410 }
411 for (i = 0; i < PM8001_MAX_DEVICES; i++) {
412 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
413 pm8001_ha->devices[i].id = i;
414 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
415 atomic_set(&pm8001_ha->devices[i].running_req, 0);
416 }
417 pm8001_ha->flags = PM8001F_INIT_TIME;
418 /* Initialize tags */
419 pm8001_tag_init(pm8001_ha);
420 return 0;
421
422 err_out_shost:
423 scsi_remove_host(pm8001_ha->shost);
424 err_out_nodev:
425 for (i = 0; i < pm8001_ha->max_memcnt; i++) {
426 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
427 pci_free_consistent(pm8001_ha->pdev,
428 (pm8001_ha->memoryMap.region[i].total_len +
429 pm8001_ha->memoryMap.region[i].alignment),
430 pm8001_ha->memoryMap.region[i].virt_ptr,
431 pm8001_ha->memoryMap.region[i].phys_addr);
432 }
433 }
434 err_out:
435 return 1;
436 }
437
438 /**
439 * pm8001_ioremap - remap the pci high physical address to kernal virtual
440 * address so that we can access them.
441 * @pm8001_ha:our hba structure.
442 */
pm8001_ioremap(struct pm8001_hba_info * pm8001_ha)443 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
444 {
445 u32 bar;
446 u32 logicalBar = 0;
447 struct pci_dev *pdev;
448
449 pdev = pm8001_ha->pdev;
450 /* map pci mem (PMC pci base 0-3)*/
451 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
452 /*
453 ** logical BARs for SPC:
454 ** bar 0 and 1 - logical BAR0
455 ** bar 2 and 3 - logical BAR1
456 ** bar4 - logical BAR2
457 ** bar5 - logical BAR3
458 ** Skip the appropriate assignments:
459 */
460 if ((bar == 1) || (bar == 3))
461 continue;
462 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
463 pm8001_ha->io_mem[logicalBar].membase =
464 pci_resource_start(pdev, bar);
465 pm8001_ha->io_mem[logicalBar].memsize =
466 pci_resource_len(pdev, bar);
467 pm8001_ha->io_mem[logicalBar].memvirtaddr =
468 ioremap(pm8001_ha->io_mem[logicalBar].membase,
469 pm8001_ha->io_mem[logicalBar].memsize);
470 pm8001_dbg(pm8001_ha, INIT,
471 "PCI: bar %d, logicalBar %d\n",
472 bar, logicalBar);
473 pm8001_dbg(pm8001_ha, INIT,
474 "base addr %llx virt_addr=%llx len=%d\n",
475 (u64)pm8001_ha->io_mem[logicalBar].membase,
476 (u64)(unsigned long)
477 pm8001_ha->io_mem[logicalBar].memvirtaddr,
478 pm8001_ha->io_mem[logicalBar].memsize);
479 } else {
480 pm8001_ha->io_mem[logicalBar].membase = 0;
481 pm8001_ha->io_mem[logicalBar].memsize = 0;
482 pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL;
483 }
484 logicalBar++;
485 }
486 return 0;
487 }
488
489 /**
490 * pm8001_pci_alloc - initialize our ha card structure
491 * @pdev: pci device.
492 * @ent: ent
493 * @shost: scsi host struct which has been initialized before.
494 */
pm8001_pci_alloc(struct pci_dev * pdev,const struct pci_device_id * ent,struct Scsi_Host * shost)495 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
496 const struct pci_device_id *ent,
497 struct Scsi_Host *shost)
498
499 {
500 struct pm8001_hba_info *pm8001_ha;
501 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
502 int j;
503
504 pm8001_ha = sha->lldd_ha;
505 if (!pm8001_ha)
506 return NULL;
507
508 pm8001_ha->pdev = pdev;
509 pm8001_ha->dev = &pdev->dev;
510 pm8001_ha->chip_id = ent->driver_data;
511 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
512 pm8001_ha->irq = pdev->irq;
513 pm8001_ha->sas = sha;
514 pm8001_ha->shost = shost;
515 pm8001_ha->id = pm8001_id++;
516 pm8001_ha->logging_level = logging_level;
517 pm8001_ha->non_fatal_count = 0;
518 if (link_rate >= 1 && link_rate <= 15)
519 pm8001_ha->link_rate = (link_rate << 8);
520 else {
521 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 |
522 LINKRATE_60 | LINKRATE_120;
523 pm8001_dbg(pm8001_ha, FAIL,
524 "Setting link rate to default value\n");
525 }
526 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
527 /* IOMB size is 128 for 8088/89 controllers */
528 if (pm8001_ha->chip_id != chip_8001)
529 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
530 else
531 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
532
533 #ifdef PM8001_USE_TASKLET
534 /* Tasklet for non msi-x interrupt handler */
535 if ((!pdev->msix_cap || !pci_msi_enabled())
536 || (pm8001_ha->chip_id == chip_8001))
537 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
538 (unsigned long)&(pm8001_ha->irq_vector[0]));
539 else
540 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
541 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
542 (unsigned long)&(pm8001_ha->irq_vector[j]));
543 #endif
544 pm8001_ioremap(pm8001_ha);
545 if (!pm8001_alloc(pm8001_ha, ent))
546 return pm8001_ha;
547 pm8001_free(pm8001_ha);
548 return NULL;
549 }
550
551 /**
552 * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
553 * @pdev: pci device.
554 */
pci_go_44(struct pci_dev * pdev)555 static int pci_go_44(struct pci_dev *pdev)
556 {
557 int rc;
558
559 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
560 if (rc) {
561 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
562 if (rc)
563 dev_printk(KERN_ERR, &pdev->dev,
564 "32-bit DMA enable failed\n");
565 }
566 return rc;
567 }
568
569 /**
570 * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
571 * @shost: scsi host which has been allocated outside.
572 * @chip_info: our ha struct.
573 */
pm8001_prep_sas_ha_init(struct Scsi_Host * shost,const struct pm8001_chip_info * chip_info)574 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
575 const struct pm8001_chip_info *chip_info)
576 {
577 int phy_nr, port_nr;
578 struct asd_sas_phy **arr_phy;
579 struct asd_sas_port **arr_port;
580 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
581
582 phy_nr = chip_info->n_phy;
583 port_nr = phy_nr;
584 memset(sha, 0x00, sizeof(*sha));
585 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
586 if (!arr_phy)
587 goto exit;
588 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
589 if (!arr_port)
590 goto exit_free2;
591
592 sha->sas_phy = arr_phy;
593 sha->sas_port = arr_port;
594 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
595 if (!sha->lldd_ha)
596 goto exit_free1;
597
598 shost->transportt = pm8001_stt;
599 shost->max_id = PM8001_MAX_DEVICES;
600 shost->max_lun = 8;
601 shost->max_channel = 0;
602 shost->unique_id = pm8001_id;
603 shost->max_cmd_len = 16;
604 shost->can_queue = PM8001_CAN_QUEUE;
605 shost->cmd_per_lun = 32;
606 return 0;
607 exit_free1:
608 kfree(arr_port);
609 exit_free2:
610 kfree(arr_phy);
611 exit:
612 return -1;
613 }
614
615 /**
616 * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
617 * @shost: scsi host which has been allocated outside
618 * @chip_info: our ha struct.
619 */
pm8001_post_sas_ha_init(struct Scsi_Host * shost,const struct pm8001_chip_info * chip_info)620 static void pm8001_post_sas_ha_init(struct Scsi_Host *shost,
621 const struct pm8001_chip_info *chip_info)
622 {
623 int i = 0;
624 struct pm8001_hba_info *pm8001_ha;
625 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
626
627 pm8001_ha = sha->lldd_ha;
628 for (i = 0; i < chip_info->n_phy; i++) {
629 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
630 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
631 sha->sas_phy[i]->sas_addr =
632 (u8 *)&pm8001_ha->phy[i].dev_sas_addr;
633 }
634 sha->sas_ha_name = DRV_NAME;
635 sha->dev = pm8001_ha->dev;
636 sha->strict_wide_ports = 1;
637 sha->lldd_module = THIS_MODULE;
638 sha->sas_addr = &pm8001_ha->sas_addr[0];
639 sha->num_phys = chip_info->n_phy;
640 sha->core.shost = shost;
641 }
642
643 /**
644 * pm8001_init_sas_add - initialize sas address
645 * @pm8001_ha: our ha struct.
646 *
647 * Currently we just set the fixed SAS address to our HBA,for manufacture,
648 * it should read from the EEPROM
649 */
pm8001_init_sas_add(struct pm8001_hba_info * pm8001_ha)650 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
651 {
652 u8 i, j;
653 u8 sas_add[8];
654 #ifdef PM8001_READ_VPD
655 /* For new SPC controllers WWN is stored in flash vpd
656 * For SPC/SPCve controllers WWN is stored in EEPROM
657 * For Older SPC WWN is stored in NVMD
658 */
659 DECLARE_COMPLETION_ONSTACK(completion);
660 struct pm8001_ioctl_payload payload;
661 u16 deviceid;
662 int rc;
663
664 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
665 pm8001_ha->nvmd_completion = &completion;
666
667 if (pm8001_ha->chip_id == chip_8001) {
668 if (deviceid == 0x8081 || deviceid == 0x0042) {
669 payload.minor_function = 4;
670 payload.rd_length = 4096;
671 } else {
672 payload.minor_function = 0;
673 payload.rd_length = 128;
674 }
675 } else if ((pm8001_ha->chip_id == chip_8070 ||
676 pm8001_ha->chip_id == chip_8072) &&
677 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
678 payload.minor_function = 4;
679 payload.rd_length = 4096;
680 } else {
681 payload.minor_function = 1;
682 payload.rd_length = 4096;
683 }
684 payload.offset = 0;
685 payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL);
686 if (!payload.func_specific) {
687 pm8001_dbg(pm8001_ha, INIT, "mem alloc fail\n");
688 return;
689 }
690 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
691 if (rc) {
692 kfree(payload.func_specific);
693 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
694 return;
695 }
696 wait_for_completion(&completion);
697
698 for (i = 0, j = 0; i <= 7; i++, j++) {
699 if (pm8001_ha->chip_id == chip_8001) {
700 if (deviceid == 0x8081)
701 pm8001_ha->sas_addr[j] =
702 payload.func_specific[0x704 + i];
703 else if (deviceid == 0x0042)
704 pm8001_ha->sas_addr[j] =
705 payload.func_specific[0x010 + i];
706 } else if ((pm8001_ha->chip_id == chip_8070 ||
707 pm8001_ha->chip_id == chip_8072) &&
708 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
709 pm8001_ha->sas_addr[j] =
710 payload.func_specific[0x010 + i];
711 } else
712 pm8001_ha->sas_addr[j] =
713 payload.func_specific[0x804 + i];
714 }
715 memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE);
716 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
717 if (i && ((i % 4) == 0))
718 sas_add[7] = sas_add[7] + 4;
719 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
720 sas_add, SAS_ADDR_SIZE);
721 pm8001_dbg(pm8001_ha, INIT, "phy %d sas_addr = %016llx\n", i,
722 pm8001_ha->phy[i].dev_sas_addr);
723 }
724 kfree(payload.func_specific);
725 #else
726 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
727 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
728 pm8001_ha->phy[i].dev_sas_addr =
729 cpu_to_be64((u64)
730 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
731 }
732 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
733 SAS_ADDR_SIZE);
734 #endif
735 }
736
737 /*
738 * pm8001_get_phy_settings_info : Read phy setting values.
739 * @pm8001_ha : our hba.
740 */
pm8001_get_phy_settings_info(struct pm8001_hba_info * pm8001_ha)741 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
742 {
743
744 #ifdef PM8001_READ_VPD
745 /*OPTION ROM FLASH read for the SPC cards */
746 DECLARE_COMPLETION_ONSTACK(completion);
747 struct pm8001_ioctl_payload payload;
748 int rc;
749
750 pm8001_ha->nvmd_completion = &completion;
751 /* SAS ADDRESS read from flash / EEPROM */
752 payload.minor_function = 6;
753 payload.offset = 0;
754 payload.rd_length = 4096;
755 payload.func_specific = kzalloc(4096, GFP_KERNEL);
756 if (!payload.func_specific)
757 return -ENOMEM;
758 /* Read phy setting values from flash */
759 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
760 if (rc) {
761 kfree(payload.func_specific);
762 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
763 return -ENOMEM;
764 }
765 wait_for_completion(&completion);
766 pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
767 kfree(payload.func_specific);
768 #endif
769 return 0;
770 }
771
772 struct pm8001_mpi3_phy_pg_trx_config {
773 u32 LaneLosCfg;
774 u32 LanePgaCfg1;
775 u32 LanePisoCfg1;
776 u32 LanePisoCfg2;
777 u32 LanePisoCfg3;
778 u32 LanePisoCfg4;
779 u32 LanePisoCfg5;
780 u32 LanePisoCfg6;
781 u32 LaneBctCtrl;
782 };
783
784 /**
785 * pm8001_get_internal_phy_settings : Retrieves the internal PHY settings
786 * @pm8001_ha : our adapter
787 * @phycfg : PHY config page to populate
788 */
789 static
pm8001_get_internal_phy_settings(struct pm8001_hba_info * pm8001_ha,struct pm8001_mpi3_phy_pg_trx_config * phycfg)790 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
791 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
792 {
793 phycfg->LaneLosCfg = 0x00000132;
794 phycfg->LanePgaCfg1 = 0x00203949;
795 phycfg->LanePisoCfg1 = 0x000000FF;
796 phycfg->LanePisoCfg2 = 0xFF000001;
797 phycfg->LanePisoCfg3 = 0xE7011300;
798 phycfg->LanePisoCfg4 = 0x631C40C0;
799 phycfg->LanePisoCfg5 = 0xF8102036;
800 phycfg->LanePisoCfg6 = 0xF74A1000;
801 phycfg->LaneBctCtrl = 0x00FB33F8;
802 }
803
804 /**
805 * pm8001_get_external_phy_settings : Retrieves the external PHY settings
806 * @pm8001_ha : our adapter
807 * @phycfg : PHY config page to populate
808 */
809 static
pm8001_get_external_phy_settings(struct pm8001_hba_info * pm8001_ha,struct pm8001_mpi3_phy_pg_trx_config * phycfg)810 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
811 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
812 {
813 phycfg->LaneLosCfg = 0x00000132;
814 phycfg->LanePgaCfg1 = 0x00203949;
815 phycfg->LanePisoCfg1 = 0x000000FF;
816 phycfg->LanePisoCfg2 = 0xFF000001;
817 phycfg->LanePisoCfg3 = 0xE7011300;
818 phycfg->LanePisoCfg4 = 0x63349140;
819 phycfg->LanePisoCfg5 = 0xF8102036;
820 phycfg->LanePisoCfg6 = 0xF80D9300;
821 phycfg->LaneBctCtrl = 0x00FB33F8;
822 }
823
824 /**
825 * pm8001_get_phy_mask : Retrieves the mask that denotes if a PHY is int/ext
826 * @pm8001_ha : our adapter
827 * @phymask : The PHY mask
828 */
829 static
pm8001_get_phy_mask(struct pm8001_hba_info * pm8001_ha,int * phymask)830 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
831 {
832 switch (pm8001_ha->pdev->subsystem_device) {
833 case 0x0070: /* H1280 - 8 external 0 internal */
834 case 0x0072: /* H12F0 - 16 external 0 internal */
835 *phymask = 0x0000;
836 break;
837
838 case 0x0071: /* H1208 - 0 external 8 internal */
839 case 0x0073: /* H120F - 0 external 16 internal */
840 *phymask = 0xFFFF;
841 break;
842
843 case 0x0080: /* H1244 - 4 external 4 internal */
844 *phymask = 0x00F0;
845 break;
846
847 case 0x0081: /* H1248 - 4 external 8 internal */
848 *phymask = 0x0FF0;
849 break;
850
851 case 0x0082: /* H1288 - 8 external 8 internal */
852 *phymask = 0xFF00;
853 break;
854
855 default:
856 pm8001_dbg(pm8001_ha, INIT,
857 "Unknown subsystem device=0x%.04x\n",
858 pm8001_ha->pdev->subsystem_device);
859 }
860 }
861
862 /**
863 * pm8001_set_phy_settings_ven_117c_12Gb : Configure ATTO 12Gb PHY settings
864 * @pm8001_ha : our adapter
865 */
866 static
pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info * pm8001_ha)867 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
868 {
869 struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
870 struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
871 int phymask = 0;
872 int i = 0;
873
874 memset(&phycfg_int, 0, sizeof(phycfg_int));
875 memset(&phycfg_ext, 0, sizeof(phycfg_ext));
876
877 pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
878 pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
879 pm8001_get_phy_mask(pm8001_ha, &phymask);
880
881 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
882 if (phymask & (1 << i)) {/* Internal PHY */
883 pm8001_set_phy_profile_single(pm8001_ha, i,
884 sizeof(phycfg_int) / sizeof(u32),
885 (u32 *)&phycfg_int);
886
887 } else { /* External PHY */
888 pm8001_set_phy_profile_single(pm8001_ha, i,
889 sizeof(phycfg_ext) / sizeof(u32),
890 (u32 *)&phycfg_ext);
891 }
892 }
893
894 return 0;
895 }
896
897 /**
898 * pm8001_configure_phy_settings : Configures PHY settings based on vendor ID.
899 * @pm8001_ha : our hba.
900 */
pm8001_configure_phy_settings(struct pm8001_hba_info * pm8001_ha)901 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
902 {
903 switch (pm8001_ha->pdev->subsystem_vendor) {
904 case PCI_VENDOR_ID_ATTO:
905 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */
906 return 0;
907 else
908 return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
909
910 case PCI_VENDOR_ID_ADAPTEC2:
911 case 0:
912 return 0;
913
914 default:
915 return pm8001_get_phy_settings_info(pm8001_ha);
916 }
917 }
918
919 #ifdef PM8001_USE_MSIX
920 /**
921 * pm8001_setup_msix - enable MSI-X interrupt
922 * @pm8001_ha: our ha struct.
923 */
pm8001_setup_msix(struct pm8001_hba_info * pm8001_ha)924 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
925 {
926 u32 number_of_intr;
927 int rc, cpu_online_count;
928 unsigned int allocated_irq_vectors;
929
930 /* SPCv controllers supports 64 msi-x */
931 if (pm8001_ha->chip_id == chip_8001) {
932 number_of_intr = 1;
933 } else {
934 number_of_intr = PM8001_MAX_MSIX_VEC;
935 }
936
937 cpu_online_count = num_online_cpus();
938 number_of_intr = min_t(int, cpu_online_count, number_of_intr);
939 rc = pci_alloc_irq_vectors(pm8001_ha->pdev, number_of_intr,
940 number_of_intr, PCI_IRQ_MSIX);
941 allocated_irq_vectors = rc;
942 if (rc < 0)
943 return rc;
944
945 /* Assigns the number of interrupts */
946 number_of_intr = min_t(int, allocated_irq_vectors, number_of_intr);
947 pm8001_ha->number_of_intr = number_of_intr;
948
949 /* Maximum queue number updating in HBA structure */
950 pm8001_ha->max_q_num = number_of_intr;
951
952 pm8001_dbg(pm8001_ha, INIT,
953 "pci_alloc_irq_vectors request ret:%d no of intr %d\n",
954 rc, pm8001_ha->number_of_intr);
955 return 0;
956 }
957
pm8001_request_msix(struct pm8001_hba_info * pm8001_ha)958 static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha)
959 {
960 u32 i = 0, j = 0;
961 int flag = 0, rc = 0;
962
963 if (pm8001_ha->chip_id != chip_8001)
964 flag &= ~IRQF_SHARED;
965
966 pm8001_dbg(pm8001_ha, INIT,
967 "pci_enable_msix request number of intr %d\n",
968 pm8001_ha->number_of_intr);
969
970 for (i = 0; i < pm8001_ha->number_of_intr; i++) {
971 snprintf(pm8001_ha->intr_drvname[i],
972 sizeof(pm8001_ha->intr_drvname[0]),
973 "%s-%d", pm8001_ha->name, i);
974 pm8001_ha->irq_vector[i].irq_id = i;
975 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
976
977 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i),
978 pm8001_interrupt_handler_msix, flag,
979 pm8001_ha->intr_drvname[i],
980 &(pm8001_ha->irq_vector[i]));
981 if (rc) {
982 for (j = 0; j < i; j++) {
983 free_irq(pci_irq_vector(pm8001_ha->pdev, i),
984 &(pm8001_ha->irq_vector[i]));
985 }
986 pci_free_irq_vectors(pm8001_ha->pdev);
987 break;
988 }
989 }
990
991 return rc;
992 }
993 #endif
994
pm8001_setup_irq(struct pm8001_hba_info * pm8001_ha)995 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha)
996 {
997 struct pci_dev *pdev;
998
999 pdev = pm8001_ha->pdev;
1000
1001 #ifdef PM8001_USE_MSIX
1002 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
1003 return pm8001_setup_msix(pm8001_ha);
1004 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1005 #endif
1006 return 0;
1007 }
1008
1009 /**
1010 * pm8001_request_irq - register interrupt
1011 * @pm8001_ha: our ha struct.
1012 */
pm8001_request_irq(struct pm8001_hba_info * pm8001_ha)1013 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
1014 {
1015 struct pci_dev *pdev;
1016 int rc;
1017
1018 pdev = pm8001_ha->pdev;
1019
1020 #ifdef PM8001_USE_MSIX
1021 if (pdev->msix_cap && pci_msi_enabled())
1022 return pm8001_request_msix(pm8001_ha);
1023 else {
1024 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1025 goto intx;
1026 }
1027 #endif
1028
1029 intx:
1030 /* initialize the INT-X interrupt */
1031 pm8001_ha->irq_vector[0].irq_id = 0;
1032 pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
1033 rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
1034 pm8001_ha->name, SHOST_TO_SAS_HA(pm8001_ha->shost));
1035 return rc;
1036 }
1037
1038 /**
1039 * pm8001_pci_probe - probe supported device
1040 * @pdev: pci device which kernel has been prepared for.
1041 * @ent: pci device id
1042 *
1043 * This function is the main initialization function, when register a new
1044 * pci driver it is invoked, all struct an hardware initilization should be done
1045 * here, also, register interrupt
1046 */
pm8001_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1047 static int pm8001_pci_probe(struct pci_dev *pdev,
1048 const struct pci_device_id *ent)
1049 {
1050 unsigned int rc;
1051 u32 pci_reg;
1052 u8 i = 0;
1053 struct pm8001_hba_info *pm8001_ha;
1054 struct Scsi_Host *shost = NULL;
1055 const struct pm8001_chip_info *chip;
1056 struct sas_ha_struct *sha;
1057
1058 dev_printk(KERN_INFO, &pdev->dev,
1059 "pm80xx: driver version %s\n", DRV_VERSION);
1060 rc = pci_enable_device(pdev);
1061 if (rc)
1062 goto err_out_enable;
1063 pci_set_master(pdev);
1064 /*
1065 * Enable pci slot busmaster by setting pci command register.
1066 * This is required by FW for Cyclone card.
1067 */
1068
1069 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
1070 pci_reg |= 0x157;
1071 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
1072 rc = pci_request_regions(pdev, DRV_NAME);
1073 if (rc)
1074 goto err_out_disable;
1075 rc = pci_go_44(pdev);
1076 if (rc)
1077 goto err_out_regions;
1078
1079 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
1080 if (!shost) {
1081 rc = -ENOMEM;
1082 goto err_out_regions;
1083 }
1084 chip = &pm8001_chips[ent->driver_data];
1085 sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
1086 if (!sha) {
1087 rc = -ENOMEM;
1088 goto err_out_free_host;
1089 }
1090 SHOST_TO_SAS_HA(shost) = sha;
1091
1092 rc = pm8001_prep_sas_ha_init(shost, chip);
1093 if (rc) {
1094 rc = -ENOMEM;
1095 goto err_out_free;
1096 }
1097 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1098 /* ent->driver variable is used to differentiate between controllers */
1099 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1100 if (!pm8001_ha) {
1101 rc = -ENOMEM;
1102 goto err_out_free;
1103 }
1104
1105 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1106 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1107 if (rc) {
1108 pm8001_dbg(pm8001_ha, FAIL,
1109 "chip_init failed [ret: %d]\n", rc);
1110 goto err_out_ha_free;
1111 }
1112
1113 rc = pm8001_init_ccb_tag(pm8001_ha, shost, pdev);
1114 if (rc)
1115 goto err_out_enable;
1116
1117 rc = scsi_add_host(shost, &pdev->dev);
1118 if (rc)
1119 goto err_out_ha_free;
1120
1121 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1122 if (pm8001_ha->chip_id != chip_8001) {
1123 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1124 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1125 /* setup thermal configuration. */
1126 pm80xx_set_thermal_config(pm8001_ha);
1127 }
1128
1129 pm8001_init_sas_add(pm8001_ha);
1130 /* phy setting support for motherboard controller */
1131 rc = pm8001_configure_phy_settings(pm8001_ha);
1132 if (rc)
1133 goto err_out_shost;
1134
1135 pm8001_post_sas_ha_init(shost, chip);
1136 rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1137 if (rc) {
1138 pm8001_dbg(pm8001_ha, FAIL,
1139 "sas_register_ha failed [ret: %d]\n", rc);
1140 goto err_out_shost;
1141 }
1142 list_add_tail(&pm8001_ha->list, &hba_list);
1143 pm8001_ha->flags = PM8001F_RUN_TIME;
1144 scsi_scan_host(pm8001_ha->shost);
1145 return 0;
1146
1147 err_out_shost:
1148 scsi_remove_host(pm8001_ha->shost);
1149 err_out_ha_free:
1150 pm8001_free(pm8001_ha);
1151 err_out_free:
1152 kfree(sha);
1153 err_out_free_host:
1154 scsi_host_put(shost);
1155 err_out_regions:
1156 pci_release_regions(pdev);
1157 err_out_disable:
1158 pci_disable_device(pdev);
1159 err_out_enable:
1160 return rc;
1161 }
1162
1163 /*
1164 * pm8001_init_ccb_tag - allocate memory to CCB and tag.
1165 * @pm8001_ha: our hba card information.
1166 * @shost: scsi host which has been allocated outside.
1167 */
1168 static int
pm8001_init_ccb_tag(struct pm8001_hba_info * pm8001_ha,struct Scsi_Host * shost,struct pci_dev * pdev)1169 pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha, struct Scsi_Host *shost,
1170 struct pci_dev *pdev)
1171 {
1172 int i = 0;
1173 u32 max_out_io, ccb_count;
1174 u32 can_queue;
1175
1176 max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io;
1177 ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io);
1178
1179 /* Update to the scsi host*/
1180 can_queue = ccb_count - PM8001_RESERVE_SLOT;
1181 shost->can_queue = can_queue;
1182
1183 pm8001_ha->tags = kzalloc(ccb_count, GFP_KERNEL);
1184 if (!pm8001_ha->tags)
1185 goto err_out;
1186
1187 /* Memory region for ccb_info*/
1188 pm8001_ha->ccb_info = (struct pm8001_ccb_info *)
1189 kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL);
1190 if (!pm8001_ha->ccb_info) {
1191 pm8001_dbg(pm8001_ha, FAIL,
1192 "Unable to allocate memory for ccb\n");
1193 goto err_out_noccb;
1194 }
1195 for (i = 0; i < ccb_count; i++) {
1196 pm8001_ha->ccb_info[i].buf_prd = pci_alloc_consistent(pdev,
1197 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1198 &pm8001_ha->ccb_info[i].ccb_dma_handle);
1199 if (!pm8001_ha->ccb_info[i].buf_prd) {
1200 pm8001_dbg(pm8001_ha, FAIL,
1201 "pm80xx: ccb prd memory allocation error\n");
1202 goto err_out;
1203 }
1204 pm8001_ha->ccb_info[i].task = NULL;
1205 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
1206 pm8001_ha->ccb_info[i].device = NULL;
1207 ++pm8001_ha->tags_num;
1208 }
1209 return 0;
1210
1211 err_out_noccb:
1212 kfree(pm8001_ha->devices);
1213 err_out:
1214 return -ENOMEM;
1215 }
1216
pm8001_pci_remove(struct pci_dev * pdev)1217 static void pm8001_pci_remove(struct pci_dev *pdev)
1218 {
1219 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1220 struct pm8001_hba_info *pm8001_ha;
1221 int i, j;
1222 pm8001_ha = sha->lldd_ha;
1223 sas_unregister_ha(sha);
1224 sas_remove_host(pm8001_ha->shost);
1225 list_del(&pm8001_ha->list);
1226 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1227 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1228
1229 #ifdef PM8001_USE_MSIX
1230 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1231 synchronize_irq(pci_irq_vector(pdev, i));
1232 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1233 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1234 pci_free_irq_vectors(pdev);
1235 #else
1236 free_irq(pm8001_ha->irq, sha);
1237 #endif
1238 #ifdef PM8001_USE_TASKLET
1239 /* For non-msix and msix interrupts */
1240 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1241 (pm8001_ha->chip_id == chip_8001))
1242 tasklet_kill(&pm8001_ha->tasklet[0]);
1243 else
1244 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1245 tasklet_kill(&pm8001_ha->tasklet[j]);
1246 #endif
1247 scsi_host_put(pm8001_ha->shost);
1248 pm8001_free(pm8001_ha);
1249 kfree(sha->sas_phy);
1250 kfree(sha->sas_port);
1251 kfree(sha);
1252 pci_release_regions(pdev);
1253 pci_disable_device(pdev);
1254 }
1255
1256 /**
1257 * pm8001_pci_suspend - power management suspend main entry point
1258 * @pdev: PCI device struct
1259 * @state: PM state change to (usually PCI_D3)
1260 *
1261 * Returns 0 success, anything else error.
1262 */
pm8001_pci_suspend(struct pci_dev * pdev,pm_message_t state)1263 static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1264 {
1265 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1266 struct pm8001_hba_info *pm8001_ha;
1267 int i, j;
1268 u32 device_state;
1269 pm8001_ha = sha->lldd_ha;
1270 sas_suspend_ha(sha);
1271 flush_workqueue(pm8001_wq);
1272 scsi_block_requests(pm8001_ha->shost);
1273 if (!pdev->pm_cap) {
1274 dev_err(&pdev->dev, " PCI PM not supported\n");
1275 return -ENODEV;
1276 }
1277 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1278 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1279 #ifdef PM8001_USE_MSIX
1280 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1281 synchronize_irq(pci_irq_vector(pdev, i));
1282 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1283 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1284 pci_free_irq_vectors(pdev);
1285 #else
1286 free_irq(pm8001_ha->irq, sha);
1287 #endif
1288 #ifdef PM8001_USE_TASKLET
1289 /* For non-msix and msix interrupts */
1290 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1291 (pm8001_ha->chip_id == chip_8001))
1292 tasklet_kill(&pm8001_ha->tasklet[0]);
1293 else
1294 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1295 tasklet_kill(&pm8001_ha->tasklet[j]);
1296 #endif
1297 device_state = pci_choose_state(pdev, state);
1298 pm8001_printk("pdev=0x%p, slot=%s, entering "
1299 "operating state [D%d]\n", pdev,
1300 pm8001_ha->name, device_state);
1301 pci_save_state(pdev);
1302 pci_disable_device(pdev);
1303 pci_set_power_state(pdev, device_state);
1304 return 0;
1305 }
1306
1307 /**
1308 * pm8001_pci_resume - power management resume main entry point
1309 * @pdev: PCI device struct
1310 *
1311 * Returns 0 success, anything else error.
1312 */
pm8001_pci_resume(struct pci_dev * pdev)1313 static int pm8001_pci_resume(struct pci_dev *pdev)
1314 {
1315 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1316 struct pm8001_hba_info *pm8001_ha;
1317 int rc;
1318 u8 i = 0, j;
1319 u32 device_state;
1320 DECLARE_COMPLETION_ONSTACK(completion);
1321 pm8001_ha = sha->lldd_ha;
1322 device_state = pdev->current_state;
1323
1324 pm8001_printk("pdev=0x%p, slot=%s, resuming from previous "
1325 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state);
1326
1327 pci_set_power_state(pdev, PCI_D0);
1328 pci_enable_wake(pdev, PCI_D0, 0);
1329 pci_restore_state(pdev);
1330 rc = pci_enable_device(pdev);
1331 if (rc) {
1332 pm8001_printk("slot=%s Enable device failed during resume\n",
1333 pm8001_ha->name);
1334 goto err_out_enable;
1335 }
1336
1337 pci_set_master(pdev);
1338 rc = pci_go_44(pdev);
1339 if (rc)
1340 goto err_out_disable;
1341 sas_prep_resume_ha(sha);
1342 /* chip soft rst only for spc */
1343 if (pm8001_ha->chip_id == chip_8001) {
1344 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1345 pm8001_dbg(pm8001_ha, INIT, "chip soft reset successful\n");
1346 }
1347 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1348 if (rc)
1349 goto err_out_disable;
1350
1351 /* disable all the interrupt bits */
1352 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1353
1354 rc = pm8001_request_irq(pm8001_ha);
1355 if (rc)
1356 goto err_out_disable;
1357 #ifdef PM8001_USE_TASKLET
1358 /* Tasklet for non msi-x interrupt handler */
1359 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1360 (pm8001_ha->chip_id == chip_8001))
1361 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1362 (unsigned long)&(pm8001_ha->irq_vector[0]));
1363 else
1364 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1365 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1366 (unsigned long)&(pm8001_ha->irq_vector[j]));
1367 #endif
1368 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1369 if (pm8001_ha->chip_id != chip_8001) {
1370 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1371 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1372 }
1373
1374 /* Chip documentation for the 8070 and 8072 SPCv */
1375 /* states that a 500ms minimum delay is required */
1376 /* before issuing commands. Otherwise, the firmware */
1377 /* will enter an unrecoverable state. */
1378
1379 if (pm8001_ha->chip_id == chip_8070 ||
1380 pm8001_ha->chip_id == chip_8072) {
1381 mdelay(500);
1382 }
1383
1384 /* Spin up the PHYs */
1385
1386 pm8001_ha->flags = PM8001F_RUN_TIME;
1387 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1388 pm8001_ha->phy[i].enable_completion = &completion;
1389 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1390 wait_for_completion(&completion);
1391 }
1392 sas_resume_ha(sha);
1393 return 0;
1394
1395 err_out_disable:
1396 scsi_remove_host(pm8001_ha->shost);
1397 pci_disable_device(pdev);
1398 err_out_enable:
1399 return rc;
1400 }
1401
1402 /* update of pci device, vendor id and driver data with
1403 * unique value for each of the controller
1404 */
1405 static struct pci_device_id pm8001_pci_table[] = {
1406 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1407 { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1408 { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1409 { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1410 /* Support for SPC/SPCv/SPCve controllers */
1411 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1412 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1413 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1414 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1415 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1416 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1417 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1418 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1419 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1420 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1421 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1422 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1423 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1424 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1425 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1426 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1427 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1428 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1429 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1430 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1431 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1432 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1433 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1434 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1435 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1436 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1437 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1438 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1439 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1440 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1441 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1442 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1443 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1444 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1445 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1446 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1447 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1448 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1449 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1450 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1451 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1452 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1453 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1454 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1455 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1456 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1457 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1458 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1459 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1460 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1461 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1462 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1463 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1464 { PCI_VENDOR_ID_ATTO, 0x8070,
1465 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1466 { PCI_VENDOR_ID_ATTO, 0x8070,
1467 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1468 { PCI_VENDOR_ID_ATTO, 0x8072,
1469 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1470 { PCI_VENDOR_ID_ATTO, 0x8072,
1471 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1472 { PCI_VENDOR_ID_ATTO, 0x8070,
1473 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1474 { PCI_VENDOR_ID_ATTO, 0x8072,
1475 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1476 { PCI_VENDOR_ID_ATTO, 0x8072,
1477 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1478 {} /* terminate list */
1479 };
1480
1481 static struct pci_driver pm8001_pci_driver = {
1482 .name = DRV_NAME,
1483 .id_table = pm8001_pci_table,
1484 .probe = pm8001_pci_probe,
1485 .remove = pm8001_pci_remove,
1486 .suspend = pm8001_pci_suspend,
1487 .resume = pm8001_pci_resume,
1488 };
1489
1490 /**
1491 * pm8001_init - initialize scsi transport template
1492 */
pm8001_init(void)1493 static int __init pm8001_init(void)
1494 {
1495 int rc = -ENOMEM;
1496
1497 pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1498 if (!pm8001_wq)
1499 goto err;
1500
1501 pm8001_id = 0;
1502 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1503 if (!pm8001_stt)
1504 goto err_wq;
1505 rc = pci_register_driver(&pm8001_pci_driver);
1506 if (rc)
1507 goto err_tp;
1508 return 0;
1509
1510 err_tp:
1511 sas_release_transport(pm8001_stt);
1512 err_wq:
1513 destroy_workqueue(pm8001_wq);
1514 err:
1515 return rc;
1516 }
1517
pm8001_exit(void)1518 static void __exit pm8001_exit(void)
1519 {
1520 pci_unregister_driver(&pm8001_pci_driver);
1521 sas_release_transport(pm8001_stt);
1522 destroy_workqueue(pm8001_wq);
1523 }
1524
1525 module_init(pm8001_init);
1526 module_exit(pm8001_exit);
1527
1528 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1529 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1530 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1531 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1532 MODULE_DESCRIPTION(
1533 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1534 "SAS/SATA controller driver");
1535 MODULE_VERSION(DRV_VERSION);
1536 MODULE_LICENSE("GPL");
1537 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1538
1539