1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * QLogic Fibre Channel HBA Driver
4 * Copyright (c) 2003-2014 QLogic Corporation
5 */
6 #include "qla_def.h"
7
8 #include <linux/moduleparam.h>
9 #include <linux/vmalloc.h>
10 #include <linux/delay.h>
11 #include <linux/kthread.h>
12 #include <linux/mutex.h>
13 #include <linux/kobject.h>
14 #include <linux/slab.h>
15 #include <linux/blk-mq-pci.h>
16 #include <linux/refcount.h>
17 #include <linux/crash_dump.h>
18
19 #include <scsi/scsi_tcq.h>
20 #include <scsi/scsicam.h>
21 #include <scsi/scsi_transport.h>
22 #include <scsi/scsi_transport_fc.h>
23
24 #include "qla_target.h"
25
26 /*
27 * Driver version
28 */
29 char qla2x00_version_str[40];
30
31 static int apidev_major;
32
33 /*
34 * SRB allocation cache
35 */
36 struct kmem_cache *srb_cachep;
37
38 int ql2xfulldump_on_mpifail;
39 module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR);
40 MODULE_PARM_DESC(ql2xfulldump_on_mpifail,
41 "Set this to take full dump on MPI hang.");
42
43 int ql2xenforce_iocb_limit = 1;
44 module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR);
45 MODULE_PARM_DESC(ql2xenforce_iocb_limit,
46 "Enforce IOCB throttling, to avoid FW congestion. (default: 1)");
47
48 /*
49 * CT6 CTX allocation cache
50 */
51 static struct kmem_cache *ctx_cachep;
52 /*
53 * error level for logging
54 */
55 uint ql_errlev = 0x8001;
56
57 static int ql2xenableclass2;
58 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
59 MODULE_PARM_DESC(ql2xenableclass2,
60 "Specify if Class 2 operations are supported from the very "
61 "beginning. Default is 0 - class 2 not supported.");
62
63
64 int ql2xlogintimeout = 20;
65 module_param(ql2xlogintimeout, int, S_IRUGO);
66 MODULE_PARM_DESC(ql2xlogintimeout,
67 "Login timeout value in seconds.");
68
69 int qlport_down_retry;
70 module_param(qlport_down_retry, int, S_IRUGO);
71 MODULE_PARM_DESC(qlport_down_retry,
72 "Maximum number of command retries to a port that returns "
73 "a PORT-DOWN status.");
74
75 int ql2xplogiabsentdevice;
76 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
77 MODULE_PARM_DESC(ql2xplogiabsentdevice,
78 "Option to enable PLOGI to devices that are not present after "
79 "a Fabric scan. This is needed for several broken switches. "
80 "Default is 0 - no PLOGI. 1 - perform PLOGI.");
81
82 int ql2xloginretrycount;
83 module_param(ql2xloginretrycount, int, S_IRUGO);
84 MODULE_PARM_DESC(ql2xloginretrycount,
85 "Specify an alternate value for the NVRAM login retry count.");
86
87 int ql2xallocfwdump = 1;
88 module_param(ql2xallocfwdump, int, S_IRUGO);
89 MODULE_PARM_DESC(ql2xallocfwdump,
90 "Option to enable allocation of memory for a firmware dump "
91 "during HBA initialization. Memory allocation requirements "
92 "vary by ISP type. Default is 1 - allocate memory.");
93
94 int ql2xextended_error_logging;
95 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
96 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
97 MODULE_PARM_DESC(ql2xextended_error_logging,
98 "Option to enable extended error logging,\n"
99 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
100 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
101 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
102 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
103 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
104 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
105 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
106 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
107 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
108 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
109 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
110 "\t\t0x1e400000 - Preferred value for capturing essential "
111 "debug information (equivalent to old "
112 "ql2xextended_error_logging=1).\n"
113 "\t\tDo LOGICAL OR of the value to enable more than one level");
114
115 int ql2xshiftctondsd = 6;
116 module_param(ql2xshiftctondsd, int, S_IRUGO);
117 MODULE_PARM_DESC(ql2xshiftctondsd,
118 "Set to control shifting of command type processing "
119 "based on total number of SG elements.");
120
121 int ql2xfdmienable = 1;
122 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
123 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
124 MODULE_PARM_DESC(ql2xfdmienable,
125 "Enables FDMI registrations. "
126 "0 - no FDMI registrations. "
127 "1 - provide FDMI registrations (default).");
128
129 #define MAX_Q_DEPTH 64
130 static int ql2xmaxqdepth = MAX_Q_DEPTH;
131 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
132 MODULE_PARM_DESC(ql2xmaxqdepth,
133 "Maximum queue depth to set for each LUN. "
134 "Default is 64.");
135
136 int ql2xenabledif = 2;
137 module_param(ql2xenabledif, int, S_IRUGO);
138 MODULE_PARM_DESC(ql2xenabledif,
139 " Enable T10-CRC-DIF:\n"
140 " Default is 2.\n"
141 " 0 -- No DIF Support\n"
142 " 1 -- Enable DIF for all types\n"
143 " 2 -- Enable DIF for all types, except Type 0.\n");
144
145 #if (IS_ENABLED(CONFIG_NVME_FC))
146 int ql2xnvmeenable = 1;
147 #else
148 int ql2xnvmeenable;
149 #endif
150 module_param(ql2xnvmeenable, int, 0644);
151 MODULE_PARM_DESC(ql2xnvmeenable,
152 "Enables NVME support. "
153 "0 - no NVMe. Default is Y");
154
155 int ql2xenablehba_err_chk = 2;
156 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
157 MODULE_PARM_DESC(ql2xenablehba_err_chk,
158 " Enable T10-CRC-DIF Error isolation by HBA:\n"
159 " Default is 2.\n"
160 " 0 -- Error isolation disabled\n"
161 " 1 -- Error isolation enabled only for DIX Type 0\n"
162 " 2 -- Error isolation enabled for all Types\n");
163
164 int ql2xiidmaenable = 1;
165 module_param(ql2xiidmaenable, int, S_IRUGO);
166 MODULE_PARM_DESC(ql2xiidmaenable,
167 "Enables iIDMA settings "
168 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
169
170 int ql2xmqsupport = 1;
171 module_param(ql2xmqsupport, int, S_IRUGO);
172 MODULE_PARM_DESC(ql2xmqsupport,
173 "Enable on demand multiple queue pairs support "
174 "Default is 1 for supported. "
175 "Set it to 0 to turn off mq qpair support.");
176
177 int ql2xfwloadbin;
178 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
179 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
180 MODULE_PARM_DESC(ql2xfwloadbin,
181 "Option to specify location from which to load ISP firmware:.\n"
182 " 2 -- load firmware via the request_firmware() (hotplug).\n"
183 " interface.\n"
184 " 1 -- load firmware from flash.\n"
185 " 0 -- use default semantics.\n");
186
187 int ql2xetsenable;
188 module_param(ql2xetsenable, int, S_IRUGO);
189 MODULE_PARM_DESC(ql2xetsenable,
190 "Enables firmware ETS burst."
191 "Default is 0 - skip ETS enablement.");
192
193 int ql2xdbwr = 1;
194 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
195 MODULE_PARM_DESC(ql2xdbwr,
196 "Option to specify scheme for request queue posting.\n"
197 " 0 -- Regular doorbell.\n"
198 " 1 -- CAMRAM doorbell (faster).\n");
199
200 int ql2xtargetreset = 1;
201 module_param(ql2xtargetreset, int, S_IRUGO);
202 MODULE_PARM_DESC(ql2xtargetreset,
203 "Enable target reset."
204 "Default is 1 - use hw defaults.");
205
206 int ql2xgffidenable;
207 module_param(ql2xgffidenable, int, S_IRUGO);
208 MODULE_PARM_DESC(ql2xgffidenable,
209 "Enables GFF_ID checks of port type. "
210 "Default is 0 - Do not use GFF_ID information.");
211
212 int ql2xasynctmfenable = 1;
213 module_param(ql2xasynctmfenable, int, S_IRUGO);
214 MODULE_PARM_DESC(ql2xasynctmfenable,
215 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
216 "Default is 1 - Issue TM IOCBs via mailbox mechanism.");
217
218 int ql2xdontresethba;
219 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
220 MODULE_PARM_DESC(ql2xdontresethba,
221 "Option to specify reset behaviour.\n"
222 " 0 (Default) -- Reset on failure.\n"
223 " 1 -- Do not reset on failure.\n");
224
225 uint64_t ql2xmaxlun = MAX_LUNS;
226 module_param(ql2xmaxlun, ullong, S_IRUGO);
227 MODULE_PARM_DESC(ql2xmaxlun,
228 "Defines the maximum LU number to register with the SCSI "
229 "midlayer. Default is 65535.");
230
231 int ql2xmdcapmask = 0x1F;
232 module_param(ql2xmdcapmask, int, S_IRUGO);
233 MODULE_PARM_DESC(ql2xmdcapmask,
234 "Set the Minidump driver capture mask level. "
235 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
236
237 int ql2xmdenable = 1;
238 module_param(ql2xmdenable, int, S_IRUGO);
239 MODULE_PARM_DESC(ql2xmdenable,
240 "Enable/disable MiniDump. "
241 "0 - MiniDump disabled. "
242 "1 (Default) - MiniDump enabled.");
243
244 int ql2xexlogins;
245 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
246 MODULE_PARM_DESC(ql2xexlogins,
247 "Number of extended Logins. "
248 "0 (Default)- Disabled.");
249
250 int ql2xexchoffld = 1024;
251 module_param(ql2xexchoffld, uint, 0644);
252 MODULE_PARM_DESC(ql2xexchoffld,
253 "Number of target exchanges.");
254
255 int ql2xiniexchg = 1024;
256 module_param(ql2xiniexchg, uint, 0644);
257 MODULE_PARM_DESC(ql2xiniexchg,
258 "Number of initiator exchanges.");
259
260 int ql2xfwholdabts;
261 module_param(ql2xfwholdabts, int, S_IRUGO);
262 MODULE_PARM_DESC(ql2xfwholdabts,
263 "Allow FW to hold status IOCB until ABTS rsp received. "
264 "0 (Default) Do not set fw option. "
265 "1 - Set fw option to hold ABTS.");
266
267 int ql2xmvasynctoatio = 1;
268 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
269 MODULE_PARM_DESC(ql2xmvasynctoatio,
270 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
271 "0 (Default). Do not move IOCBs"
272 "1 - Move IOCBs.");
273
274 int ql2xautodetectsfp = 1;
275 module_param(ql2xautodetectsfp, int, 0444);
276 MODULE_PARM_DESC(ql2xautodetectsfp,
277 "Detect SFP range and set appropriate distance.\n"
278 "1 (Default): Enable\n");
279
280 int ql2xenablemsix = 1;
281 module_param(ql2xenablemsix, int, 0444);
282 MODULE_PARM_DESC(ql2xenablemsix,
283 "Set to enable MSI or MSI-X interrupt mechanism.\n"
284 " Default is 1, enable MSI-X interrupt mechanism.\n"
285 " 0 -- enable traditional pin-based mechanism.\n"
286 " 1 -- enable MSI-X interrupt mechanism.\n"
287 " 2 -- enable MSI interrupt mechanism.\n");
288
289 int qla2xuseresexchforels;
290 module_param(qla2xuseresexchforels, int, 0444);
291 MODULE_PARM_DESC(qla2xuseresexchforels,
292 "Reserve 1/2 of emergency exchanges for ELS.\n"
293 " 0 (default): disabled");
294
295 static int ql2xprotmask;
296 module_param(ql2xprotmask, int, 0644);
297 MODULE_PARM_DESC(ql2xprotmask,
298 "Override DIF/DIX protection capabilities mask\n"
299 "Default is 0 which sets protection mask based on "
300 "capabilities reported by HBA firmware.\n");
301
302 static int ql2xprotguard;
303 module_param(ql2xprotguard, int, 0644);
304 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n"
305 " 0 -- Let HBA firmware decide\n"
306 " 1 -- Force T10 CRC\n"
307 " 2 -- Force IP checksum\n");
308
309 int ql2xdifbundlinginternalbuffers;
310 module_param(ql2xdifbundlinginternalbuffers, int, 0644);
311 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers,
312 "Force using internal buffers for DIF information\n"
313 "0 (Default). Based on check.\n"
314 "1 Force using internal buffers\n");
315
316 int ql2xsmartsan;
317 module_param(ql2xsmartsan, int, 0444);
318 module_param_named(smartsan, ql2xsmartsan, int, 0444);
319 MODULE_PARM_DESC(ql2xsmartsan,
320 "Send SmartSAN Management Attributes for FDMI Registration."
321 " Default is 0 - No SmartSAN registration,"
322 " 1 - Register SmartSAN Management Attributes.");
323
324 int ql2xrdpenable;
325 module_param(ql2xrdpenable, int, 0444);
326 module_param_named(rdpenable, ql2xrdpenable, int, 0444);
327 MODULE_PARM_DESC(ql2xrdpenable,
328 "Enables RDP responses. "
329 "0 - no RDP responses (default). "
330 "1 - provide RDP responses.");
331
332 static void qla2x00_clear_drv_active(struct qla_hw_data *);
333 static void qla2x00_free_device(scsi_qla_host_t *);
334 static int qla2xxx_map_queues(struct Scsi_Host *shost);
335 static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
336
337
338 static struct scsi_transport_template *qla2xxx_transport_template = NULL;
339 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
340
341 /* TODO Convert to inlines
342 *
343 * Timer routines
344 */
345
346 __inline__ void
qla2x00_start_timer(scsi_qla_host_t * vha,unsigned long interval)347 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
348 {
349 timer_setup(&vha->timer, qla2x00_timer, 0);
350 vha->timer.expires = jiffies + interval * HZ;
351 add_timer(&vha->timer);
352 vha->timer_active = 1;
353 }
354
355 static inline void
qla2x00_restart_timer(scsi_qla_host_t * vha,unsigned long interval)356 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
357 {
358 /* Currently used for 82XX only. */
359 if (vha->device_flags & DFLG_DEV_FAILED) {
360 ql_dbg(ql_dbg_timer, vha, 0x600d,
361 "Device in a failed state, returning.\n");
362 return;
363 }
364
365 mod_timer(&vha->timer, jiffies + interval * HZ);
366 }
367
368 static __inline__ void
qla2x00_stop_timer(scsi_qla_host_t * vha)369 qla2x00_stop_timer(scsi_qla_host_t *vha)
370 {
371 del_timer_sync(&vha->timer);
372 vha->timer_active = 0;
373 }
374
375 static int qla2x00_do_dpc(void *data);
376
377 static void qla2x00_rst_aen(scsi_qla_host_t *);
378
379 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
380 struct req_que **, struct rsp_que **);
381 static void qla2x00_free_fw_dump(struct qla_hw_data *);
382 static void qla2x00_mem_free(struct qla_hw_data *);
383 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
384 struct qla_qpair *qpair);
385
386 /* -------------------------------------------------------------------------- */
qla_init_base_qpair(struct scsi_qla_host * vha,struct req_que * req,struct rsp_que * rsp)387 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
388 struct rsp_que *rsp)
389 {
390 struct qla_hw_data *ha = vha->hw;
391
392 rsp->qpair = ha->base_qpair;
393 rsp->req = req;
394 ha->base_qpair->hw = ha;
395 ha->base_qpair->req = req;
396 ha->base_qpair->rsp = rsp;
397 ha->base_qpair->vha = vha;
398 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
399 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
400 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
401 ha->base_qpair->srb_mempool = ha->srb_mempool;
402 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
403 ha->base_qpair->enable_class_2 = ql2xenableclass2;
404 /* init qpair to this cpu. Will adjust at run time. */
405 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
406 ha->base_qpair->pdev = ha->pdev;
407
408 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
409 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
410 }
411
qla2x00_alloc_queues(struct qla_hw_data * ha,struct req_que * req,struct rsp_que * rsp)412 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
413 struct rsp_que *rsp)
414 {
415 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
416
417 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
418 GFP_KERNEL);
419 if (!ha->req_q_map) {
420 ql_log(ql_log_fatal, vha, 0x003b,
421 "Unable to allocate memory for request queue ptrs.\n");
422 goto fail_req_map;
423 }
424
425 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
426 GFP_KERNEL);
427 if (!ha->rsp_q_map) {
428 ql_log(ql_log_fatal, vha, 0x003c,
429 "Unable to allocate memory for response queue ptrs.\n");
430 goto fail_rsp_map;
431 }
432
433 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
434 if (ha->base_qpair == NULL) {
435 ql_log(ql_log_warn, vha, 0x00e0,
436 "Failed to allocate base queue pair memory.\n");
437 goto fail_base_qpair;
438 }
439
440 qla_init_base_qpair(vha, req, rsp);
441
442 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
443 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
444 GFP_KERNEL);
445 if (!ha->queue_pair_map) {
446 ql_log(ql_log_fatal, vha, 0x0180,
447 "Unable to allocate memory for queue pair ptrs.\n");
448 goto fail_qpair_map;
449 }
450 }
451
452 /*
453 * Make sure we record at least the request and response queue zero in
454 * case we need to free them if part of the probe fails.
455 */
456 ha->rsp_q_map[0] = rsp;
457 ha->req_q_map[0] = req;
458 set_bit(0, ha->rsp_qid_map);
459 set_bit(0, ha->req_qid_map);
460 return 0;
461
462 fail_qpair_map:
463 kfree(ha->base_qpair);
464 ha->base_qpair = NULL;
465 fail_base_qpair:
466 kfree(ha->rsp_q_map);
467 ha->rsp_q_map = NULL;
468 fail_rsp_map:
469 kfree(ha->req_q_map);
470 ha->req_q_map = NULL;
471 fail_req_map:
472 return -ENOMEM;
473 }
474
qla2x00_free_req_que(struct qla_hw_data * ha,struct req_que * req)475 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
476 {
477 if (IS_QLAFX00(ha)) {
478 if (req && req->ring_fx00)
479 dma_free_coherent(&ha->pdev->dev,
480 (req->length_fx00 + 1) * sizeof(request_t),
481 req->ring_fx00, req->dma_fx00);
482 } else if (req && req->ring)
483 dma_free_coherent(&ha->pdev->dev,
484 (req->length + 1) * sizeof(request_t),
485 req->ring, req->dma);
486
487 if (req)
488 kfree(req->outstanding_cmds);
489
490 kfree(req);
491 }
492
qla2x00_free_rsp_que(struct qla_hw_data * ha,struct rsp_que * rsp)493 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
494 {
495 if (IS_QLAFX00(ha)) {
496 if (rsp && rsp->ring_fx00)
497 dma_free_coherent(&ha->pdev->dev,
498 (rsp->length_fx00 + 1) * sizeof(request_t),
499 rsp->ring_fx00, rsp->dma_fx00);
500 } else if (rsp && rsp->ring) {
501 dma_free_coherent(&ha->pdev->dev,
502 (rsp->length + 1) * sizeof(response_t),
503 rsp->ring, rsp->dma);
504 }
505 kfree(rsp);
506 }
507
qla2x00_free_queues(struct qla_hw_data * ha)508 static void qla2x00_free_queues(struct qla_hw_data *ha)
509 {
510 struct req_que *req;
511 struct rsp_que *rsp;
512 int cnt;
513 unsigned long flags;
514
515 if (ha->queue_pair_map) {
516 kfree(ha->queue_pair_map);
517 ha->queue_pair_map = NULL;
518 }
519 if (ha->base_qpair) {
520 kfree(ha->base_qpair);
521 ha->base_qpair = NULL;
522 }
523
524 spin_lock_irqsave(&ha->hardware_lock, flags);
525 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
526 if (!test_bit(cnt, ha->req_qid_map))
527 continue;
528
529 req = ha->req_q_map[cnt];
530 clear_bit(cnt, ha->req_qid_map);
531 ha->req_q_map[cnt] = NULL;
532
533 spin_unlock_irqrestore(&ha->hardware_lock, flags);
534 qla2x00_free_req_que(ha, req);
535 spin_lock_irqsave(&ha->hardware_lock, flags);
536 }
537 spin_unlock_irqrestore(&ha->hardware_lock, flags);
538
539 kfree(ha->req_q_map);
540 ha->req_q_map = NULL;
541
542
543 spin_lock_irqsave(&ha->hardware_lock, flags);
544 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
545 if (!test_bit(cnt, ha->rsp_qid_map))
546 continue;
547
548 rsp = ha->rsp_q_map[cnt];
549 clear_bit(cnt, ha->rsp_qid_map);
550 ha->rsp_q_map[cnt] = NULL;
551 spin_unlock_irqrestore(&ha->hardware_lock, flags);
552 qla2x00_free_rsp_que(ha, rsp);
553 spin_lock_irqsave(&ha->hardware_lock, flags);
554 }
555 spin_unlock_irqrestore(&ha->hardware_lock, flags);
556
557 kfree(ha->rsp_q_map);
558 ha->rsp_q_map = NULL;
559 }
560
561 static char *
qla2x00_pci_info_str(struct scsi_qla_host * vha,char * str,size_t str_len)562 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
563 {
564 struct qla_hw_data *ha = vha->hw;
565 static const char *const pci_bus_modes[] = {
566 "33", "66", "100", "133",
567 };
568 uint16_t pci_bus;
569
570 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
571 if (pci_bus) {
572 snprintf(str, str_len, "PCI-X (%s MHz)",
573 pci_bus_modes[pci_bus]);
574 } else {
575 pci_bus = (ha->pci_attr & BIT_8) >> 8;
576 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]);
577 }
578
579 return str;
580 }
581
582 static char *
qla24xx_pci_info_str(struct scsi_qla_host * vha,char * str,size_t str_len)583 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
584 {
585 static const char *const pci_bus_modes[] = {
586 "33", "66", "100", "133",
587 };
588 struct qla_hw_data *ha = vha->hw;
589 uint32_t pci_bus;
590
591 if (pci_is_pcie(ha->pdev)) {
592 uint32_t lstat, lspeed, lwidth;
593 const char *speed_str;
594
595 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
596 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
597 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
598
599 switch (lspeed) {
600 case 1:
601 speed_str = "2.5GT/s";
602 break;
603 case 2:
604 speed_str = "5.0GT/s";
605 break;
606 case 3:
607 speed_str = "8.0GT/s";
608 break;
609 case 4:
610 speed_str = "16.0GT/s";
611 break;
612 default:
613 speed_str = "<unknown>";
614 break;
615 }
616 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth);
617
618 return str;
619 }
620
621 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
622 if (pci_bus == 0 || pci_bus == 8)
623 snprintf(str, str_len, "PCI (%s MHz)",
624 pci_bus_modes[pci_bus >> 3]);
625 else
626 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)",
627 pci_bus & 4 ? 2 : 1,
628 pci_bus_modes[pci_bus & 3]);
629
630 return str;
631 }
632
633 static char *
qla2x00_fw_version_str(struct scsi_qla_host * vha,char * str,size_t size)634 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
635 {
636 char un_str[10];
637 struct qla_hw_data *ha = vha->hw;
638
639 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
640 ha->fw_minor_version, ha->fw_subminor_version);
641
642 if (ha->fw_attributes & BIT_9) {
643 strcat(str, "FLX");
644 return (str);
645 }
646
647 switch (ha->fw_attributes & 0xFF) {
648 case 0x7:
649 strcat(str, "EF");
650 break;
651 case 0x17:
652 strcat(str, "TP");
653 break;
654 case 0x37:
655 strcat(str, "IP");
656 break;
657 case 0x77:
658 strcat(str, "VI");
659 break;
660 default:
661 sprintf(un_str, "(%x)", ha->fw_attributes);
662 strcat(str, un_str);
663 break;
664 }
665 if (ha->fw_attributes & 0x100)
666 strcat(str, "X");
667
668 return (str);
669 }
670
671 static char *
qla24xx_fw_version_str(struct scsi_qla_host * vha,char * str,size_t size)672 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
673 {
674 struct qla_hw_data *ha = vha->hw;
675
676 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
677 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
678 return str;
679 }
680
qla2x00_sp_free_dma(srb_t * sp)681 void qla2x00_sp_free_dma(srb_t *sp)
682 {
683 struct qla_hw_data *ha = sp->vha->hw;
684 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
685
686 if (sp->flags & SRB_DMA_VALID) {
687 scsi_dma_unmap(cmd);
688 sp->flags &= ~SRB_DMA_VALID;
689 }
690
691 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
692 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
693 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
694 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
695 }
696
697 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
698 /* List assured to be having elements */
699 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
700 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
701 }
702
703 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
704 struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
705
706 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
707 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
708 }
709
710 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
711 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx;
712
713 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
714 ctx1->fcp_cmnd_dma);
715 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
716 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
717 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
718 mempool_free(ctx1, ha->ctx_mempool);
719 }
720 }
721
qla2x00_sp_compl(srb_t * sp,int res)722 void qla2x00_sp_compl(srb_t *sp, int res)
723 {
724 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
725 struct completion *comp = sp->comp;
726
727 sp->free(sp);
728 cmd->result = res;
729 CMD_SP(cmd) = NULL;
730 cmd->scsi_done(cmd);
731 if (comp)
732 complete(comp);
733 }
734
qla2xxx_qpair_sp_free_dma(srb_t * sp)735 void qla2xxx_qpair_sp_free_dma(srb_t *sp)
736 {
737 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
738 struct qla_hw_data *ha = sp->fcport->vha->hw;
739
740 if (sp->flags & SRB_DMA_VALID) {
741 scsi_dma_unmap(cmd);
742 sp->flags &= ~SRB_DMA_VALID;
743 }
744
745 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
746 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
747 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
748 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
749 }
750
751 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
752 /* List assured to be having elements */
753 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
754 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
755 }
756
757 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) {
758 struct crc_context *difctx = sp->u.scmd.crc_ctx;
759 struct dsd_dma *dif_dsd, *nxt_dsd;
760
761 list_for_each_entry_safe(dif_dsd, nxt_dsd,
762 &difctx->ldif_dma_hndl_list, list) {
763 list_del(&dif_dsd->list);
764 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr,
765 dif_dsd->dsd_list_dma);
766 kfree(dif_dsd);
767 difctx->no_dif_bundl--;
768 }
769
770 list_for_each_entry_safe(dif_dsd, nxt_dsd,
771 &difctx->ldif_dsd_list, list) {
772 list_del(&dif_dsd->list);
773 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr,
774 dif_dsd->dsd_list_dma);
775 kfree(dif_dsd);
776 difctx->no_ldif_dsd--;
777 }
778
779 if (difctx->no_ldif_dsd) {
780 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
781 "%s: difctx->no_ldif_dsd=%x\n",
782 __func__, difctx->no_ldif_dsd);
783 }
784
785 if (difctx->no_dif_bundl) {
786 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
787 "%s: difctx->no_dif_bundl=%x\n",
788 __func__, difctx->no_dif_bundl);
789 }
790 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID;
791 }
792
793 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
794 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx;
795
796 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
797 ctx1->fcp_cmnd_dma);
798 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
799 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
800 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
801 mempool_free(ctx1, ha->ctx_mempool);
802 sp->flags &= ~SRB_FCP_CMND_DMA_VALID;
803 }
804
805 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
806 struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
807
808 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
809 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
810 }
811 }
812
qla2xxx_qpair_sp_compl(srb_t * sp,int res)813 void qla2xxx_qpair_sp_compl(srb_t *sp, int res)
814 {
815 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
816 struct completion *comp = sp->comp;
817
818 sp->free(sp);
819 cmd->result = res;
820 CMD_SP(cmd) = NULL;
821 cmd->scsi_done(cmd);
822 if (comp)
823 complete(comp);
824 }
825
826 static int
qla2xxx_queuecommand(struct Scsi_Host * host,struct scsi_cmnd * cmd)827 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
828 {
829 scsi_qla_host_t *vha = shost_priv(host);
830 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
831 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
832 struct qla_hw_data *ha = vha->hw;
833 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
834 srb_t *sp;
835 int rval;
836
837 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) ||
838 WARN_ON_ONCE(!rport)) {
839 cmd->result = DID_NO_CONNECT << 16;
840 goto qc24_fail_command;
841 }
842
843 if (ha->mqenable) {
844 uint32_t tag;
845 uint16_t hwq;
846 struct qla_qpair *qpair = NULL;
847
848 tag = blk_mq_unique_tag(cmd->request);
849 hwq = blk_mq_unique_tag_to_hwq(tag);
850 qpair = ha->queue_pair_map[hwq];
851
852 if (qpair)
853 return qla2xxx_mqueuecommand(host, cmd, qpair);
854 }
855
856 if (ha->flags.eeh_busy) {
857 if (ha->flags.pci_channel_io_perm_failure) {
858 ql_dbg(ql_dbg_aer, vha, 0x9010,
859 "PCI Channel IO permanent failure, exiting "
860 "cmd=%p.\n", cmd);
861 cmd->result = DID_NO_CONNECT << 16;
862 } else {
863 ql_dbg(ql_dbg_aer, vha, 0x9011,
864 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
865 cmd->result = DID_REQUEUE << 16;
866 }
867 goto qc24_fail_command;
868 }
869
870 rval = fc_remote_port_chkready(rport);
871 if (rval) {
872 cmd->result = rval;
873 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
874 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
875 cmd, rval);
876 goto qc24_fail_command;
877 }
878
879 if (!vha->flags.difdix_supported &&
880 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
881 ql_dbg(ql_dbg_io, vha, 0x3004,
882 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
883 cmd);
884 cmd->result = DID_NO_CONNECT << 16;
885 goto qc24_fail_command;
886 }
887
888 if (!fcport) {
889 cmd->result = DID_NO_CONNECT << 16;
890 goto qc24_fail_command;
891 }
892
893 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
894 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
895 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
896 ql_dbg(ql_dbg_io, vha, 0x3005,
897 "Returning DNC, fcport_state=%d loop_state=%d.\n",
898 atomic_read(&fcport->state),
899 atomic_read(&base_vha->loop_state));
900 cmd->result = DID_NO_CONNECT << 16;
901 goto qc24_fail_command;
902 }
903 goto qc24_target_busy;
904 }
905
906 /*
907 * Return target busy if we've received a non-zero retry_delay_timer
908 * in a FCP_RSP.
909 */
910 if (fcport->retry_delay_timestamp == 0) {
911 /* retry delay not set */
912 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
913 fcport->retry_delay_timestamp = 0;
914 else
915 goto qc24_target_busy;
916
917 sp = scsi_cmd_priv(cmd);
918 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport);
919
920 sp->u.scmd.cmd = cmd;
921 sp->type = SRB_SCSI_CMD;
922
923 CMD_SP(cmd) = (void *)sp;
924 sp->free = qla2x00_sp_free_dma;
925 sp->done = qla2x00_sp_compl;
926
927 rval = ha->isp_ops->start_scsi(sp);
928 if (rval != QLA_SUCCESS) {
929 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
930 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
931 goto qc24_host_busy_free_sp;
932 }
933
934 return 0;
935
936 qc24_host_busy_free_sp:
937 sp->free(sp);
938
939 qc24_target_busy:
940 return SCSI_MLQUEUE_TARGET_BUSY;
941
942 qc24_fail_command:
943 cmd->scsi_done(cmd);
944
945 return 0;
946 }
947
948 /* For MQ supported I/O */
949 int
qla2xxx_mqueuecommand(struct Scsi_Host * host,struct scsi_cmnd * cmd,struct qla_qpair * qpair)950 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
951 struct qla_qpair *qpair)
952 {
953 scsi_qla_host_t *vha = shost_priv(host);
954 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
955 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
956 struct qla_hw_data *ha = vha->hw;
957 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
958 srb_t *sp;
959 int rval;
960
961 rval = rport ? fc_remote_port_chkready(rport) : FC_PORTSTATE_OFFLINE;
962 if (rval) {
963 cmd->result = rval;
964 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
965 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
966 cmd, rval);
967 goto qc24_fail_command;
968 }
969
970 if (!fcport) {
971 cmd->result = DID_NO_CONNECT << 16;
972 goto qc24_fail_command;
973 }
974
975 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
976 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
977 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
978 ql_dbg(ql_dbg_io, vha, 0x3077,
979 "Returning DNC, fcport_state=%d loop_state=%d.\n",
980 atomic_read(&fcport->state),
981 atomic_read(&base_vha->loop_state));
982 cmd->result = DID_NO_CONNECT << 16;
983 goto qc24_fail_command;
984 }
985 goto qc24_target_busy;
986 }
987
988 /*
989 * Return target busy if we've received a non-zero retry_delay_timer
990 * in a FCP_RSP.
991 */
992 if (fcport->retry_delay_timestamp == 0) {
993 /* retry delay not set */
994 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
995 fcport->retry_delay_timestamp = 0;
996 else
997 goto qc24_target_busy;
998
999 sp = scsi_cmd_priv(cmd);
1000 qla2xxx_init_sp(sp, vha, qpair, fcport);
1001
1002 sp->u.scmd.cmd = cmd;
1003 sp->type = SRB_SCSI_CMD;
1004 CMD_SP(cmd) = (void *)sp;
1005 sp->free = qla2xxx_qpair_sp_free_dma;
1006 sp->done = qla2xxx_qpair_sp_compl;
1007
1008 rval = ha->isp_ops->start_scsi_mq(sp);
1009 if (rval != QLA_SUCCESS) {
1010 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1011 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1012 goto qc24_host_busy_free_sp;
1013 }
1014
1015 return 0;
1016
1017 qc24_host_busy_free_sp:
1018 sp->free(sp);
1019
1020 qc24_target_busy:
1021 return SCSI_MLQUEUE_TARGET_BUSY;
1022
1023 qc24_fail_command:
1024 cmd->scsi_done(cmd);
1025
1026 return 0;
1027 }
1028
1029 /*
1030 * qla2x00_eh_wait_on_command
1031 * Waits for the command to be returned by the Firmware for some
1032 * max time.
1033 *
1034 * Input:
1035 * cmd = Scsi Command to wait on.
1036 *
1037 * Return:
1038 * Completed in time : QLA_SUCCESS
1039 * Did not complete in time : QLA_FUNCTION_FAILED
1040 */
1041 static int
qla2x00_eh_wait_on_command(struct scsi_cmnd * cmd)1042 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1043 {
1044 #define ABORT_POLLING_PERIOD 1000
1045 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
1046 unsigned long wait_iter = ABORT_WAIT_ITER;
1047 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1048 struct qla_hw_data *ha = vha->hw;
1049 int ret = QLA_SUCCESS;
1050
1051 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
1052 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1053 "Return:eh_wait.\n");
1054 return ret;
1055 }
1056
1057 while (CMD_SP(cmd) && wait_iter--) {
1058 msleep(ABORT_POLLING_PERIOD);
1059 }
1060 if (CMD_SP(cmd))
1061 ret = QLA_FUNCTION_FAILED;
1062
1063 return ret;
1064 }
1065
1066 /*
1067 * qla2x00_wait_for_hba_online
1068 * Wait till the HBA is online after going through
1069 * <= MAX_RETRIES_OF_ISP_ABORT or
1070 * finally HBA is disabled ie marked offline
1071 *
1072 * Input:
1073 * ha - pointer to host adapter structure
1074 *
1075 * Note:
1076 * Does context switching-Release SPIN_LOCK
1077 * (if any) before calling this routine.
1078 *
1079 * Return:
1080 * Success (Adapter is online) : 0
1081 * Failed (Adapter is offline/disabled) : 1
1082 */
1083 int
qla2x00_wait_for_hba_online(scsi_qla_host_t * vha)1084 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1085 {
1086 int return_status;
1087 unsigned long wait_online;
1088 struct qla_hw_data *ha = vha->hw;
1089 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1090
1091 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1092 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1093 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1094 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1095 ha->dpc_active) && time_before(jiffies, wait_online)) {
1096
1097 msleep(1000);
1098 }
1099 if (base_vha->flags.online)
1100 return_status = QLA_SUCCESS;
1101 else
1102 return_status = QLA_FUNCTION_FAILED;
1103
1104 return (return_status);
1105 }
1106
test_fcport_count(scsi_qla_host_t * vha)1107 static inline int test_fcport_count(scsi_qla_host_t *vha)
1108 {
1109 struct qla_hw_data *ha = vha->hw;
1110 unsigned long flags;
1111 int res;
1112
1113 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
1114 ql_dbg(ql_dbg_init, vha, 0x00ec,
1115 "tgt %p, fcport_count=%d\n",
1116 vha, vha->fcport_count);
1117 res = (vha->fcport_count == 0);
1118 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1119
1120 return res;
1121 }
1122
1123 /*
1124 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1125 * it has dependency on UNLOADING flag to stop device discovery
1126 */
1127 void
qla2x00_wait_for_sess_deletion(scsi_qla_host_t * vha)1128 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1129 {
1130 u8 i;
1131
1132 qla2x00_mark_all_devices_lost(vha);
1133
1134 for (i = 0; i < 10; i++) {
1135 if (wait_event_timeout(vha->fcport_waitQ,
1136 test_fcport_count(vha), HZ) > 0)
1137 break;
1138 }
1139
1140 flush_workqueue(vha->hw->wq);
1141 }
1142
1143 /*
1144 * qla2x00_wait_for_hba_ready
1145 * Wait till the HBA is ready before doing driver unload
1146 *
1147 * Input:
1148 * ha - pointer to host adapter structure
1149 *
1150 * Note:
1151 * Does context switching-Release SPIN_LOCK
1152 * (if any) before calling this routine.
1153 *
1154 */
1155 static void
qla2x00_wait_for_hba_ready(scsi_qla_host_t * vha)1156 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
1157 {
1158 struct qla_hw_data *ha = vha->hw;
1159 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1160
1161 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1162 ha->flags.mbox_busy) ||
1163 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1164 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1165 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1166 break;
1167 msleep(1000);
1168 }
1169 }
1170
1171 int
qla2x00_wait_for_chip_reset(scsi_qla_host_t * vha)1172 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1173 {
1174 int return_status;
1175 unsigned long wait_reset;
1176 struct qla_hw_data *ha = vha->hw;
1177 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1178
1179 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1180 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1181 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1182 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1183 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1184
1185 msleep(1000);
1186
1187 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1188 ha->flags.chip_reset_done)
1189 break;
1190 }
1191 if (ha->flags.chip_reset_done)
1192 return_status = QLA_SUCCESS;
1193 else
1194 return_status = QLA_FUNCTION_FAILED;
1195
1196 return return_status;
1197 }
1198
1199 #define ISP_REG_DISCONNECT 0xffffffffU
1200 /**************************************************************************
1201 * qla2x00_isp_reg_stat
1202 *
1203 * Description:
1204 * Read the host status register of ISP before aborting the command.
1205 *
1206 * Input:
1207 * ha = pointer to host adapter structure.
1208 *
1209 *
1210 * Returns:
1211 * Either true or false.
1212 *
1213 * Note: Return true if there is register disconnect.
1214 **************************************************************************/
1215 static inline
qla2x00_isp_reg_stat(struct qla_hw_data * ha)1216 uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1217 {
1218 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1219 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
1220
1221 if (IS_P3P_TYPE(ha))
1222 return ((rd_reg_dword(®82->host_int)) == ISP_REG_DISCONNECT);
1223 else
1224 return ((rd_reg_dword(®->host_status)) ==
1225 ISP_REG_DISCONNECT);
1226 }
1227
1228 /**************************************************************************
1229 * qla2xxx_eh_abort
1230 *
1231 * Description:
1232 * The abort function will abort the specified command.
1233 *
1234 * Input:
1235 * cmd = Linux SCSI command packet to be aborted.
1236 *
1237 * Returns:
1238 * Either SUCCESS or FAILED.
1239 *
1240 * Note:
1241 * Only return FAILED if command not returned by firmware.
1242 **************************************************************************/
1243 static int
qla2xxx_eh_abort(struct scsi_cmnd * cmd)1244 qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1245 {
1246 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1247 DECLARE_COMPLETION_ONSTACK(comp);
1248 srb_t *sp;
1249 int ret;
1250 unsigned int id;
1251 uint64_t lun;
1252 int rval;
1253 struct qla_hw_data *ha = vha->hw;
1254 uint32_t ratov_j;
1255 struct qla_qpair *qpair;
1256 unsigned long flags;
1257
1258 if (qla2x00_isp_reg_stat(ha)) {
1259 ql_log(ql_log_info, vha, 0x8042,
1260 "PCI/Register disconnect, exiting.\n");
1261 return FAILED;
1262 }
1263
1264 ret = fc_block_scsi_eh(cmd);
1265 if (ret != 0)
1266 return ret;
1267
1268 sp = scsi_cmd_priv(cmd);
1269 qpair = sp->qpair;
1270
1271 if ((sp->fcport && sp->fcport->deleted) || !qpair)
1272 return SUCCESS;
1273
1274 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1275 sp->comp = ∁
1276 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1277
1278
1279 id = cmd->device->id;
1280 lun = cmd->device->lun;
1281
1282 ql_dbg(ql_dbg_taskm, vha, 0x8002,
1283 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1284 vha->host_no, id, lun, sp, cmd, sp->handle);
1285
1286 /*
1287 * Abort will release the original Command/sp from FW. Let the
1288 * original command call scsi_done. In return, he will wakeup
1289 * this sleeping thread.
1290 */
1291 rval = ha->isp_ops->abort_command(sp);
1292
1293 ql_dbg(ql_dbg_taskm, vha, 0x8003,
1294 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval);
1295
1296 /* Wait for the command completion. */
1297 ratov_j = ha->r_a_tov/10 * 4 * 1000;
1298 ratov_j = msecs_to_jiffies(ratov_j);
1299 switch (rval) {
1300 case QLA_SUCCESS:
1301 if (!wait_for_completion_timeout(&comp, ratov_j)) {
1302 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1303 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1304 __func__, ha->r_a_tov/10);
1305 ret = FAILED;
1306 } else {
1307 ret = SUCCESS;
1308 }
1309 break;
1310 default:
1311 ret = FAILED;
1312 break;
1313 }
1314
1315 sp->comp = NULL;
1316
1317 ql_log(ql_log_info, vha, 0x801c,
1318 "Abort command issued nexus=%ld:%d:%llu -- %x.\n",
1319 vha->host_no, id, lun, ret);
1320
1321 return ret;
1322 }
1323
1324 /*
1325 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED.
1326 */
1327 int
qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t * vha,unsigned int t,uint64_t l,enum nexus_wait_type type)1328 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1329 uint64_t l, enum nexus_wait_type type)
1330 {
1331 int cnt, match, status;
1332 unsigned long flags;
1333 struct qla_hw_data *ha = vha->hw;
1334 struct req_que *req;
1335 srb_t *sp;
1336 struct scsi_cmnd *cmd;
1337
1338 status = QLA_SUCCESS;
1339
1340 spin_lock_irqsave(&ha->hardware_lock, flags);
1341 req = vha->req;
1342 for (cnt = 1; status == QLA_SUCCESS &&
1343 cnt < req->num_outstanding_cmds; cnt++) {
1344 sp = req->outstanding_cmds[cnt];
1345 if (!sp)
1346 continue;
1347 if (sp->type != SRB_SCSI_CMD)
1348 continue;
1349 if (vha->vp_idx != sp->vha->vp_idx)
1350 continue;
1351 match = 0;
1352 cmd = GET_CMD_SP(sp);
1353 switch (type) {
1354 case WAIT_HOST:
1355 match = 1;
1356 break;
1357 case WAIT_TARGET:
1358 match = cmd->device->id == t;
1359 break;
1360 case WAIT_LUN:
1361 match = (cmd->device->id == t &&
1362 cmd->device->lun == l);
1363 break;
1364 }
1365 if (!match)
1366 continue;
1367
1368 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1369 status = qla2x00_eh_wait_on_command(cmd);
1370 spin_lock_irqsave(&ha->hardware_lock, flags);
1371 }
1372 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1373
1374 return status;
1375 }
1376
1377 static char *reset_errors[] = {
1378 "HBA not online",
1379 "HBA not ready",
1380 "Task management failed",
1381 "Waiting for command completions",
1382 };
1383
1384 static int
__qla2xxx_eh_generic_reset(char * name,enum nexus_wait_type type,struct scsi_cmnd * cmd,int (* do_reset)(struct fc_port *,uint64_t,int))1385 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
1386 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1387 {
1388 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1389 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1390 int err;
1391
1392 if (!fcport) {
1393 return FAILED;
1394 }
1395
1396 err = fc_block_scsi_eh(cmd);
1397 if (err != 0)
1398 return err;
1399
1400 if (fcport->deleted)
1401 return SUCCESS;
1402
1403 ql_log(ql_log_info, vha, 0x8009,
1404 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
1405 cmd->device->id, cmd->device->lun, cmd);
1406
1407 err = 0;
1408 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1409 ql_log(ql_log_warn, vha, 0x800a,
1410 "Wait for hba online failed for cmd=%p.\n", cmd);
1411 goto eh_reset_failed;
1412 }
1413 err = 2;
1414 if (do_reset(fcport, cmd->device->lun, 1)
1415 != QLA_SUCCESS) {
1416 ql_log(ql_log_warn, vha, 0x800c,
1417 "do_reset failed for cmd=%p.\n", cmd);
1418 goto eh_reset_failed;
1419 }
1420 err = 3;
1421 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
1422 cmd->device->lun, type) != QLA_SUCCESS) {
1423 ql_log(ql_log_warn, vha, 0x800d,
1424 "wait for pending cmds failed for cmd=%p.\n", cmd);
1425 goto eh_reset_failed;
1426 }
1427
1428 ql_log(ql_log_info, vha, 0x800e,
1429 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
1430 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
1431
1432 return SUCCESS;
1433
1434 eh_reset_failed:
1435 ql_log(ql_log_info, vha, 0x800f,
1436 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
1437 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1438 cmd);
1439 return FAILED;
1440 }
1441
1442 static int
qla2xxx_eh_device_reset(struct scsi_cmnd * cmd)1443 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1444 {
1445 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1446 struct qla_hw_data *ha = vha->hw;
1447
1448 if (qla2x00_isp_reg_stat(ha)) {
1449 ql_log(ql_log_info, vha, 0x803e,
1450 "PCI/Register disconnect, exiting.\n");
1451 return FAILED;
1452 }
1453
1454 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1455 ha->isp_ops->lun_reset);
1456 }
1457
1458 static int
qla2xxx_eh_target_reset(struct scsi_cmnd * cmd)1459 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1460 {
1461 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1462 struct qla_hw_data *ha = vha->hw;
1463
1464 if (qla2x00_isp_reg_stat(ha)) {
1465 ql_log(ql_log_info, vha, 0x803f,
1466 "PCI/Register disconnect, exiting.\n");
1467 return FAILED;
1468 }
1469
1470 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1471 ha->isp_ops->target_reset);
1472 }
1473
1474 /**************************************************************************
1475 * qla2xxx_eh_bus_reset
1476 *
1477 * Description:
1478 * The bus reset function will reset the bus and abort any executing
1479 * commands.
1480 *
1481 * Input:
1482 * cmd = Linux SCSI command packet of the command that cause the
1483 * bus reset.
1484 *
1485 * Returns:
1486 * SUCCESS/FAILURE (defined as macro in scsi.h).
1487 *
1488 **************************************************************************/
1489 static int
qla2xxx_eh_bus_reset(struct scsi_cmnd * cmd)1490 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1491 {
1492 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1493 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1494 int ret = FAILED;
1495 unsigned int id;
1496 uint64_t lun;
1497 struct qla_hw_data *ha = vha->hw;
1498
1499 if (qla2x00_isp_reg_stat(ha)) {
1500 ql_log(ql_log_info, vha, 0x8040,
1501 "PCI/Register disconnect, exiting.\n");
1502 return FAILED;
1503 }
1504
1505 id = cmd->device->id;
1506 lun = cmd->device->lun;
1507
1508 if (!fcport) {
1509 return ret;
1510 }
1511
1512 ret = fc_block_scsi_eh(cmd);
1513 if (ret != 0)
1514 return ret;
1515 ret = FAILED;
1516
1517 if (qla2x00_chip_is_down(vha))
1518 return ret;
1519
1520 ql_log(ql_log_info, vha, 0x8012,
1521 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1522
1523 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1524 ql_log(ql_log_fatal, vha, 0x8013,
1525 "Wait for hba online failed board disabled.\n");
1526 goto eh_bus_reset_done;
1527 }
1528
1529 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1530 ret = SUCCESS;
1531
1532 if (ret == FAILED)
1533 goto eh_bus_reset_done;
1534
1535 /* Flush outstanding commands. */
1536 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1537 QLA_SUCCESS) {
1538 ql_log(ql_log_warn, vha, 0x8014,
1539 "Wait for pending commands failed.\n");
1540 ret = FAILED;
1541 }
1542
1543 eh_bus_reset_done:
1544 ql_log(ql_log_warn, vha, 0x802b,
1545 "BUS RESET %s nexus=%ld:%d:%llu.\n",
1546 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1547
1548 return ret;
1549 }
1550
1551 /**************************************************************************
1552 * qla2xxx_eh_host_reset
1553 *
1554 * Description:
1555 * The reset function will reset the Adapter.
1556 *
1557 * Input:
1558 * cmd = Linux SCSI command packet of the command that cause the
1559 * adapter reset.
1560 *
1561 * Returns:
1562 * Either SUCCESS or FAILED.
1563 *
1564 * Note:
1565 **************************************************************************/
1566 static int
qla2xxx_eh_host_reset(struct scsi_cmnd * cmd)1567 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1568 {
1569 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1570 struct qla_hw_data *ha = vha->hw;
1571 int ret = FAILED;
1572 unsigned int id;
1573 uint64_t lun;
1574 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1575
1576 if (qla2x00_isp_reg_stat(ha)) {
1577 ql_log(ql_log_info, vha, 0x8041,
1578 "PCI/Register disconnect, exiting.\n");
1579 schedule_work(&ha->board_disable);
1580 return SUCCESS;
1581 }
1582
1583 id = cmd->device->id;
1584 lun = cmd->device->lun;
1585
1586 ql_log(ql_log_info, vha, 0x8018,
1587 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1588
1589 /*
1590 * No point in issuing another reset if one is active. Also do not
1591 * attempt a reset if we are updating flash.
1592 */
1593 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
1594 goto eh_host_reset_lock;
1595
1596 if (vha != base_vha) {
1597 if (qla2x00_vp_abort_isp(vha))
1598 goto eh_host_reset_lock;
1599 } else {
1600 if (IS_P3P_TYPE(vha->hw)) {
1601 if (!qla82xx_fcoe_ctx_reset(vha)) {
1602 /* Ctx reset success */
1603 ret = SUCCESS;
1604 goto eh_host_reset_lock;
1605 }
1606 /* fall thru if ctx reset failed */
1607 }
1608 if (ha->wq)
1609 flush_workqueue(ha->wq);
1610
1611 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1612 if (ha->isp_ops->abort_isp(base_vha)) {
1613 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1614 /* failed. schedule dpc to try */
1615 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1616
1617 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1618 ql_log(ql_log_warn, vha, 0x802a,
1619 "wait for hba online failed.\n");
1620 goto eh_host_reset_lock;
1621 }
1622 }
1623 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1624 }
1625
1626 /* Waiting for command to be returned to OS.*/
1627 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1628 QLA_SUCCESS)
1629 ret = SUCCESS;
1630
1631 eh_host_reset_lock:
1632 ql_log(ql_log_info, vha, 0x8017,
1633 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
1634 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1635
1636 return ret;
1637 }
1638
1639 /*
1640 * qla2x00_loop_reset
1641 * Issue loop reset.
1642 *
1643 * Input:
1644 * ha = adapter block pointer.
1645 *
1646 * Returns:
1647 * 0 = success
1648 */
1649 int
qla2x00_loop_reset(scsi_qla_host_t * vha)1650 qla2x00_loop_reset(scsi_qla_host_t *vha)
1651 {
1652 int ret;
1653 struct fc_port *fcport;
1654 struct qla_hw_data *ha = vha->hw;
1655
1656 if (IS_QLAFX00(ha)) {
1657 return qlafx00_loop_reset(vha);
1658 }
1659
1660 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
1661 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1662 if (fcport->port_type != FCT_TARGET)
1663 continue;
1664
1665 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1666 if (ret != QLA_SUCCESS) {
1667 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1668 "Bus Reset failed: Reset=%d "
1669 "d_id=%x.\n", ret, fcport->d_id.b24);
1670 }
1671 }
1672 }
1673
1674
1675 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1676 atomic_set(&vha->loop_state, LOOP_DOWN);
1677 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1678 qla2x00_mark_all_devices_lost(vha);
1679 ret = qla2x00_full_login_lip(vha);
1680 if (ret != QLA_SUCCESS) {
1681 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1682 "full_login_lip=%d.\n", ret);
1683 }
1684 }
1685
1686 if (ha->flags.enable_lip_reset) {
1687 ret = qla2x00_lip_reset(vha);
1688 if (ret != QLA_SUCCESS)
1689 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1690 "lip_reset failed (%d).\n", ret);
1691 }
1692
1693 /* Issue marker command only when we are going to start the I/O */
1694 vha->marker_needed = 1;
1695
1696 return QLA_SUCCESS;
1697 }
1698
1699 /*
1700 * The caller must ensure that no completion interrupts will happen
1701 * while this function is in progress.
1702 */
qla2x00_abort_srb(struct qla_qpair * qp,srb_t * sp,const int res,unsigned long * flags)1703 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res,
1704 unsigned long *flags)
1705 __releases(qp->qp_lock_ptr)
1706 __acquires(qp->qp_lock_ptr)
1707 {
1708 DECLARE_COMPLETION_ONSTACK(comp);
1709 scsi_qla_host_t *vha = qp->vha;
1710 struct qla_hw_data *ha = vha->hw;
1711 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
1712 int rval;
1713 bool ret_cmd;
1714 uint32_t ratov_j;
1715
1716 lockdep_assert_held(qp->qp_lock_ptr);
1717
1718 if (qla2x00_chip_is_down(vha)) {
1719 sp->done(sp, res);
1720 return;
1721 }
1722
1723 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS ||
1724 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy &&
1725 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
1726 !qla2x00_isp_reg_stat(ha))) {
1727 if (sp->comp) {
1728 sp->done(sp, res);
1729 return;
1730 }
1731
1732 sp->comp = ∁
1733 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
1734
1735 rval = ha->isp_ops->abort_command(sp);
1736 /* Wait for command completion. */
1737 ret_cmd = false;
1738 ratov_j = ha->r_a_tov/10 * 4 * 1000;
1739 ratov_j = msecs_to_jiffies(ratov_j);
1740 switch (rval) {
1741 case QLA_SUCCESS:
1742 if (wait_for_completion_timeout(&comp, ratov_j)) {
1743 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1744 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1745 __func__, ha->r_a_tov/10);
1746 ret_cmd = true;
1747 }
1748 /* else FW return SP to driver */
1749 break;
1750 default:
1751 ret_cmd = true;
1752 break;
1753 }
1754
1755 spin_lock_irqsave(qp->qp_lock_ptr, *flags);
1756 if (ret_cmd && blk_mq_request_started(cmd->request))
1757 sp->done(sp, res);
1758 } else {
1759 sp->done(sp, res);
1760 }
1761 }
1762
1763 /*
1764 * The caller must ensure that no completion interrupts will happen
1765 * while this function is in progress.
1766 */
1767 static void
__qla2x00_abort_all_cmds(struct qla_qpair * qp,int res)1768 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
1769 {
1770 int cnt;
1771 unsigned long flags;
1772 srb_t *sp;
1773 scsi_qla_host_t *vha = qp->vha;
1774 struct qla_hw_data *ha = vha->hw;
1775 struct req_que *req;
1776 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1777 struct qla_tgt_cmd *cmd;
1778
1779 if (!ha->req_q_map)
1780 return;
1781 spin_lock_irqsave(qp->qp_lock_ptr, flags);
1782 req = qp->req;
1783 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1784 sp = req->outstanding_cmds[cnt];
1785 if (sp) {
1786 switch (sp->cmd_type) {
1787 case TYPE_SRB:
1788 qla2x00_abort_srb(qp, sp, res, &flags);
1789 break;
1790 case TYPE_TGT_CMD:
1791 if (!vha->hw->tgt.tgt_ops || !tgt ||
1792 qla_ini_mode_enabled(vha)) {
1793 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003,
1794 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1795 vha->dpc_flags);
1796 continue;
1797 }
1798 cmd = (struct qla_tgt_cmd *)sp;
1799 cmd->aborted = 1;
1800 break;
1801 case TYPE_TGT_TMCMD:
1802 /* Skip task management functions. */
1803 break;
1804 default:
1805 break;
1806 }
1807 req->outstanding_cmds[cnt] = NULL;
1808 }
1809 }
1810 spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1811 }
1812
1813 /*
1814 * The caller must ensure that no completion interrupts will happen
1815 * while this function is in progress.
1816 */
1817 void
qla2x00_abort_all_cmds(scsi_qla_host_t * vha,int res)1818 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1819 {
1820 int que;
1821 struct qla_hw_data *ha = vha->hw;
1822
1823 /* Continue only if initialization complete. */
1824 if (!ha->base_qpair)
1825 return;
1826 __qla2x00_abort_all_cmds(ha->base_qpair, res);
1827
1828 if (!ha->queue_pair_map)
1829 return;
1830 for (que = 0; que < ha->max_qpairs; que++) {
1831 if (!ha->queue_pair_map[que])
1832 continue;
1833
1834 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1835 }
1836 }
1837
1838 static int
qla2xxx_slave_alloc(struct scsi_device * sdev)1839 qla2xxx_slave_alloc(struct scsi_device *sdev)
1840 {
1841 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1842
1843 if (!rport || fc_remote_port_chkready(rport))
1844 return -ENXIO;
1845
1846 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1847
1848 return 0;
1849 }
1850
1851 static int
qla2xxx_slave_configure(struct scsi_device * sdev)1852 qla2xxx_slave_configure(struct scsi_device *sdev)
1853 {
1854 scsi_qla_host_t *vha = shost_priv(sdev->host);
1855 struct req_que *req = vha->req;
1856
1857 if (IS_T10_PI_CAPABLE(vha->hw))
1858 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1859
1860 scsi_change_queue_depth(sdev, req->max_q_depth);
1861 return 0;
1862 }
1863
1864 static void
qla2xxx_slave_destroy(struct scsi_device * sdev)1865 qla2xxx_slave_destroy(struct scsi_device *sdev)
1866 {
1867 sdev->hostdata = NULL;
1868 }
1869
1870 /**
1871 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1872 * @ha: HA context
1873 *
1874 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1875 * supported addressing method.
1876 */
1877 static void
qla2x00_config_dma_addressing(struct qla_hw_data * ha)1878 qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1879 {
1880 /* Assume a 32bit DMA mask. */
1881 ha->flags.enable_64bit_addressing = 0;
1882
1883 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1884 /* Any upper-dword bits set? */
1885 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1886 !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1887 /* Ok, a 64bit DMA mask is applicable. */
1888 ha->flags.enable_64bit_addressing = 1;
1889 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1890 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1891 return;
1892 }
1893 }
1894
1895 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1896 dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1897 }
1898
1899 static void
qla2x00_enable_intrs(struct qla_hw_data * ha)1900 qla2x00_enable_intrs(struct qla_hw_data *ha)
1901 {
1902 unsigned long flags = 0;
1903 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1904
1905 spin_lock_irqsave(&ha->hardware_lock, flags);
1906 ha->interrupts_on = 1;
1907 /* enable risc and host interrupts */
1908 wrt_reg_word(®->ictrl, ICR_EN_INT | ICR_EN_RISC);
1909 rd_reg_word(®->ictrl);
1910 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1911
1912 }
1913
1914 static void
qla2x00_disable_intrs(struct qla_hw_data * ha)1915 qla2x00_disable_intrs(struct qla_hw_data *ha)
1916 {
1917 unsigned long flags = 0;
1918 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1919
1920 spin_lock_irqsave(&ha->hardware_lock, flags);
1921 ha->interrupts_on = 0;
1922 /* disable risc and host interrupts */
1923 wrt_reg_word(®->ictrl, 0);
1924 rd_reg_word(®->ictrl);
1925 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1926 }
1927
1928 static void
qla24xx_enable_intrs(struct qla_hw_data * ha)1929 qla24xx_enable_intrs(struct qla_hw_data *ha)
1930 {
1931 unsigned long flags = 0;
1932 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1933
1934 spin_lock_irqsave(&ha->hardware_lock, flags);
1935 ha->interrupts_on = 1;
1936 wrt_reg_dword(®->ictrl, ICRX_EN_RISC_INT);
1937 rd_reg_dword(®->ictrl);
1938 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1939 }
1940
1941 static void
qla24xx_disable_intrs(struct qla_hw_data * ha)1942 qla24xx_disable_intrs(struct qla_hw_data *ha)
1943 {
1944 unsigned long flags = 0;
1945 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1946
1947 if (IS_NOPOLLING_TYPE(ha))
1948 return;
1949 spin_lock_irqsave(&ha->hardware_lock, flags);
1950 ha->interrupts_on = 0;
1951 wrt_reg_dword(®->ictrl, 0);
1952 rd_reg_dword(®->ictrl);
1953 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1954 }
1955
1956 static int
qla2x00_iospace_config(struct qla_hw_data * ha)1957 qla2x00_iospace_config(struct qla_hw_data *ha)
1958 {
1959 resource_size_t pio;
1960 uint16_t msix;
1961
1962 if (pci_request_selected_regions(ha->pdev, ha->bars,
1963 QLA2XXX_DRIVER_NAME)) {
1964 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1965 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1966 pci_name(ha->pdev));
1967 goto iospace_error_exit;
1968 }
1969 if (!(ha->bars & 1))
1970 goto skip_pio;
1971
1972 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1973 pio = pci_resource_start(ha->pdev, 0);
1974 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1975 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1976 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1977 "Invalid pci I/O region size (%s).\n",
1978 pci_name(ha->pdev));
1979 pio = 0;
1980 }
1981 } else {
1982 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1983 "Region #0 no a PIO resource (%s).\n",
1984 pci_name(ha->pdev));
1985 pio = 0;
1986 }
1987 ha->pio_address = pio;
1988 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1989 "PIO address=%llu.\n",
1990 (unsigned long long)ha->pio_address);
1991
1992 skip_pio:
1993 /* Use MMIO operations for all accesses. */
1994 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1995 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1996 "Region #1 not an MMIO resource (%s), aborting.\n",
1997 pci_name(ha->pdev));
1998 goto iospace_error_exit;
1999 }
2000 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
2001 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
2002 "Invalid PCI mem region size (%s), aborting.\n",
2003 pci_name(ha->pdev));
2004 goto iospace_error_exit;
2005 }
2006
2007 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
2008 if (!ha->iobase) {
2009 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
2010 "Cannot remap MMIO (%s), aborting.\n",
2011 pci_name(ha->pdev));
2012 goto iospace_error_exit;
2013 }
2014
2015 /* Determine queue resources */
2016 ha->max_req_queues = ha->max_rsp_queues = 1;
2017 ha->msix_count = QLA_BASE_VECTORS;
2018
2019 /* Check if FW supports MQ or not */
2020 if (!(ha->fw_attributes & BIT_6))
2021 goto mqiobase_exit;
2022
2023 if (!ql2xmqsupport || !ql2xnvmeenable ||
2024 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
2025 goto mqiobase_exit;
2026
2027 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
2028 pci_resource_len(ha->pdev, 3));
2029 if (ha->mqiobase) {
2030 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2031 "MQIO Base=%p.\n", ha->mqiobase);
2032 /* Read MSIX vector size of the board */
2033 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
2034 ha->msix_count = msix + 1;
2035 /* Max queues are bounded by available msix vectors */
2036 /* MB interrupt uses 1 vector */
2037 ha->max_req_queues = ha->msix_count - 1;
2038 ha->max_rsp_queues = ha->max_req_queues;
2039 /* Queue pairs is the max value minus the base queue pair */
2040 ha->max_qpairs = ha->max_rsp_queues - 1;
2041 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2042 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2043
2044 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
2045 "MSI-X vector count: %d.\n", ha->msix_count);
2046 } else
2047 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2048 "BAR 3 not enabled.\n");
2049
2050 mqiobase_exit:
2051 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
2052 "MSIX Count: %d.\n", ha->msix_count);
2053 return (0);
2054
2055 iospace_error_exit:
2056 return (-ENOMEM);
2057 }
2058
2059
2060 static int
qla83xx_iospace_config(struct qla_hw_data * ha)2061 qla83xx_iospace_config(struct qla_hw_data *ha)
2062 {
2063 uint16_t msix;
2064
2065 if (pci_request_selected_regions(ha->pdev, ha->bars,
2066 QLA2XXX_DRIVER_NAME)) {
2067 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2068 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2069 pci_name(ha->pdev));
2070
2071 goto iospace_error_exit;
2072 }
2073
2074 /* Use MMIO operations for all accesses. */
2075 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2076 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2077 "Invalid pci I/O region size (%s).\n",
2078 pci_name(ha->pdev));
2079 goto iospace_error_exit;
2080 }
2081 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2082 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2083 "Invalid PCI mem region size (%s), aborting\n",
2084 pci_name(ha->pdev));
2085 goto iospace_error_exit;
2086 }
2087
2088 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2089 if (!ha->iobase) {
2090 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2091 "Cannot remap MMIO (%s), aborting.\n",
2092 pci_name(ha->pdev));
2093 goto iospace_error_exit;
2094 }
2095
2096 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2097 /* 83XX 26XX always use MQ type access for queues
2098 * - mbar 2, a.k.a region 4 */
2099 ha->max_req_queues = ha->max_rsp_queues = 1;
2100 ha->msix_count = QLA_BASE_VECTORS;
2101 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2102 pci_resource_len(ha->pdev, 4));
2103
2104 if (!ha->mqiobase) {
2105 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2106 "BAR2/region4 not enabled\n");
2107 goto mqiobase_exit;
2108 }
2109
2110 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2111 pci_resource_len(ha->pdev, 2));
2112 if (ha->msixbase) {
2113 /* Read MSIX vector size of the board */
2114 pci_read_config_word(ha->pdev,
2115 QLA_83XX_PCI_MSIX_CONTROL, &msix);
2116 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
2117 /*
2118 * By default, driver uses at least two msix vectors
2119 * (default & rspq)
2120 */
2121 if (ql2xmqsupport || ql2xnvmeenable) {
2122 /* MB interrupt uses 1 vector */
2123 ha->max_req_queues = ha->msix_count - 1;
2124
2125 /* ATIOQ needs 1 vector. That's 1 less QPair */
2126 if (QLA_TGT_MODE_ENABLED())
2127 ha->max_req_queues--;
2128
2129 ha->max_rsp_queues = ha->max_req_queues;
2130
2131 /* Queue pairs is the max value minus
2132 * the base queue pair */
2133 ha->max_qpairs = ha->max_req_queues - 1;
2134 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
2135 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2136 }
2137 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
2138 "MSI-X vector count: %d.\n", ha->msix_count);
2139 } else
2140 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2141 "BAR 1 not enabled.\n");
2142
2143 mqiobase_exit:
2144 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
2145 "MSIX Count: %d.\n", ha->msix_count);
2146 return 0;
2147
2148 iospace_error_exit:
2149 return -ENOMEM;
2150 }
2151
2152 static struct isp_operations qla2100_isp_ops = {
2153 .pci_config = qla2100_pci_config,
2154 .reset_chip = qla2x00_reset_chip,
2155 .chip_diag = qla2x00_chip_diag,
2156 .config_rings = qla2x00_config_rings,
2157 .reset_adapter = qla2x00_reset_adapter,
2158 .nvram_config = qla2x00_nvram_config,
2159 .update_fw_options = qla2x00_update_fw_options,
2160 .load_risc = qla2x00_load_risc,
2161 .pci_info_str = qla2x00_pci_info_str,
2162 .fw_version_str = qla2x00_fw_version_str,
2163 .intr_handler = qla2100_intr_handler,
2164 .enable_intrs = qla2x00_enable_intrs,
2165 .disable_intrs = qla2x00_disable_intrs,
2166 .abort_command = qla2x00_abort_command,
2167 .target_reset = qla2x00_abort_target,
2168 .lun_reset = qla2x00_lun_reset,
2169 .fabric_login = qla2x00_login_fabric,
2170 .fabric_logout = qla2x00_fabric_logout,
2171 .calc_req_entries = qla2x00_calc_iocbs_32,
2172 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2173 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2174 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2175 .read_nvram = qla2x00_read_nvram_data,
2176 .write_nvram = qla2x00_write_nvram_data,
2177 .fw_dump = qla2100_fw_dump,
2178 .beacon_on = NULL,
2179 .beacon_off = NULL,
2180 .beacon_blink = NULL,
2181 .read_optrom = qla2x00_read_optrom_data,
2182 .write_optrom = qla2x00_write_optrom_data,
2183 .get_flash_version = qla2x00_get_flash_version,
2184 .start_scsi = qla2x00_start_scsi,
2185 .start_scsi_mq = NULL,
2186 .abort_isp = qla2x00_abort_isp,
2187 .iospace_config = qla2x00_iospace_config,
2188 .initialize_adapter = qla2x00_initialize_adapter,
2189 };
2190
2191 static struct isp_operations qla2300_isp_ops = {
2192 .pci_config = qla2300_pci_config,
2193 .reset_chip = qla2x00_reset_chip,
2194 .chip_diag = qla2x00_chip_diag,
2195 .config_rings = qla2x00_config_rings,
2196 .reset_adapter = qla2x00_reset_adapter,
2197 .nvram_config = qla2x00_nvram_config,
2198 .update_fw_options = qla2x00_update_fw_options,
2199 .load_risc = qla2x00_load_risc,
2200 .pci_info_str = qla2x00_pci_info_str,
2201 .fw_version_str = qla2x00_fw_version_str,
2202 .intr_handler = qla2300_intr_handler,
2203 .enable_intrs = qla2x00_enable_intrs,
2204 .disable_intrs = qla2x00_disable_intrs,
2205 .abort_command = qla2x00_abort_command,
2206 .target_reset = qla2x00_abort_target,
2207 .lun_reset = qla2x00_lun_reset,
2208 .fabric_login = qla2x00_login_fabric,
2209 .fabric_logout = qla2x00_fabric_logout,
2210 .calc_req_entries = qla2x00_calc_iocbs_32,
2211 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2212 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2213 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2214 .read_nvram = qla2x00_read_nvram_data,
2215 .write_nvram = qla2x00_write_nvram_data,
2216 .fw_dump = qla2300_fw_dump,
2217 .beacon_on = qla2x00_beacon_on,
2218 .beacon_off = qla2x00_beacon_off,
2219 .beacon_blink = qla2x00_beacon_blink,
2220 .read_optrom = qla2x00_read_optrom_data,
2221 .write_optrom = qla2x00_write_optrom_data,
2222 .get_flash_version = qla2x00_get_flash_version,
2223 .start_scsi = qla2x00_start_scsi,
2224 .start_scsi_mq = NULL,
2225 .abort_isp = qla2x00_abort_isp,
2226 .iospace_config = qla2x00_iospace_config,
2227 .initialize_adapter = qla2x00_initialize_adapter,
2228 };
2229
2230 static struct isp_operations qla24xx_isp_ops = {
2231 .pci_config = qla24xx_pci_config,
2232 .reset_chip = qla24xx_reset_chip,
2233 .chip_diag = qla24xx_chip_diag,
2234 .config_rings = qla24xx_config_rings,
2235 .reset_adapter = qla24xx_reset_adapter,
2236 .nvram_config = qla24xx_nvram_config,
2237 .update_fw_options = qla24xx_update_fw_options,
2238 .load_risc = qla24xx_load_risc,
2239 .pci_info_str = qla24xx_pci_info_str,
2240 .fw_version_str = qla24xx_fw_version_str,
2241 .intr_handler = qla24xx_intr_handler,
2242 .enable_intrs = qla24xx_enable_intrs,
2243 .disable_intrs = qla24xx_disable_intrs,
2244 .abort_command = qla24xx_abort_command,
2245 .target_reset = qla24xx_abort_target,
2246 .lun_reset = qla24xx_lun_reset,
2247 .fabric_login = qla24xx_login_fabric,
2248 .fabric_logout = qla24xx_fabric_logout,
2249 .calc_req_entries = NULL,
2250 .build_iocbs = NULL,
2251 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2252 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2253 .read_nvram = qla24xx_read_nvram_data,
2254 .write_nvram = qla24xx_write_nvram_data,
2255 .fw_dump = qla24xx_fw_dump,
2256 .beacon_on = qla24xx_beacon_on,
2257 .beacon_off = qla24xx_beacon_off,
2258 .beacon_blink = qla24xx_beacon_blink,
2259 .read_optrom = qla24xx_read_optrom_data,
2260 .write_optrom = qla24xx_write_optrom_data,
2261 .get_flash_version = qla24xx_get_flash_version,
2262 .start_scsi = qla24xx_start_scsi,
2263 .start_scsi_mq = NULL,
2264 .abort_isp = qla2x00_abort_isp,
2265 .iospace_config = qla2x00_iospace_config,
2266 .initialize_adapter = qla2x00_initialize_adapter,
2267 };
2268
2269 static struct isp_operations qla25xx_isp_ops = {
2270 .pci_config = qla25xx_pci_config,
2271 .reset_chip = qla24xx_reset_chip,
2272 .chip_diag = qla24xx_chip_diag,
2273 .config_rings = qla24xx_config_rings,
2274 .reset_adapter = qla24xx_reset_adapter,
2275 .nvram_config = qla24xx_nvram_config,
2276 .update_fw_options = qla24xx_update_fw_options,
2277 .load_risc = qla24xx_load_risc,
2278 .pci_info_str = qla24xx_pci_info_str,
2279 .fw_version_str = qla24xx_fw_version_str,
2280 .intr_handler = qla24xx_intr_handler,
2281 .enable_intrs = qla24xx_enable_intrs,
2282 .disable_intrs = qla24xx_disable_intrs,
2283 .abort_command = qla24xx_abort_command,
2284 .target_reset = qla24xx_abort_target,
2285 .lun_reset = qla24xx_lun_reset,
2286 .fabric_login = qla24xx_login_fabric,
2287 .fabric_logout = qla24xx_fabric_logout,
2288 .calc_req_entries = NULL,
2289 .build_iocbs = NULL,
2290 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2291 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2292 .read_nvram = qla25xx_read_nvram_data,
2293 .write_nvram = qla25xx_write_nvram_data,
2294 .fw_dump = qla25xx_fw_dump,
2295 .beacon_on = qla24xx_beacon_on,
2296 .beacon_off = qla24xx_beacon_off,
2297 .beacon_blink = qla24xx_beacon_blink,
2298 .read_optrom = qla25xx_read_optrom_data,
2299 .write_optrom = qla24xx_write_optrom_data,
2300 .get_flash_version = qla24xx_get_flash_version,
2301 .start_scsi = qla24xx_dif_start_scsi,
2302 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2303 .abort_isp = qla2x00_abort_isp,
2304 .iospace_config = qla2x00_iospace_config,
2305 .initialize_adapter = qla2x00_initialize_adapter,
2306 };
2307
2308 static struct isp_operations qla81xx_isp_ops = {
2309 .pci_config = qla25xx_pci_config,
2310 .reset_chip = qla24xx_reset_chip,
2311 .chip_diag = qla24xx_chip_diag,
2312 .config_rings = qla24xx_config_rings,
2313 .reset_adapter = qla24xx_reset_adapter,
2314 .nvram_config = qla81xx_nvram_config,
2315 .update_fw_options = qla24xx_update_fw_options,
2316 .load_risc = qla81xx_load_risc,
2317 .pci_info_str = qla24xx_pci_info_str,
2318 .fw_version_str = qla24xx_fw_version_str,
2319 .intr_handler = qla24xx_intr_handler,
2320 .enable_intrs = qla24xx_enable_intrs,
2321 .disable_intrs = qla24xx_disable_intrs,
2322 .abort_command = qla24xx_abort_command,
2323 .target_reset = qla24xx_abort_target,
2324 .lun_reset = qla24xx_lun_reset,
2325 .fabric_login = qla24xx_login_fabric,
2326 .fabric_logout = qla24xx_fabric_logout,
2327 .calc_req_entries = NULL,
2328 .build_iocbs = NULL,
2329 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2330 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2331 .read_nvram = NULL,
2332 .write_nvram = NULL,
2333 .fw_dump = qla81xx_fw_dump,
2334 .beacon_on = qla24xx_beacon_on,
2335 .beacon_off = qla24xx_beacon_off,
2336 .beacon_blink = qla83xx_beacon_blink,
2337 .read_optrom = qla25xx_read_optrom_data,
2338 .write_optrom = qla24xx_write_optrom_data,
2339 .get_flash_version = qla24xx_get_flash_version,
2340 .start_scsi = qla24xx_dif_start_scsi,
2341 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2342 .abort_isp = qla2x00_abort_isp,
2343 .iospace_config = qla2x00_iospace_config,
2344 .initialize_adapter = qla2x00_initialize_adapter,
2345 };
2346
2347 static struct isp_operations qla82xx_isp_ops = {
2348 .pci_config = qla82xx_pci_config,
2349 .reset_chip = qla82xx_reset_chip,
2350 .chip_diag = qla24xx_chip_diag,
2351 .config_rings = qla82xx_config_rings,
2352 .reset_adapter = qla24xx_reset_adapter,
2353 .nvram_config = qla81xx_nvram_config,
2354 .update_fw_options = qla24xx_update_fw_options,
2355 .load_risc = qla82xx_load_risc,
2356 .pci_info_str = qla24xx_pci_info_str,
2357 .fw_version_str = qla24xx_fw_version_str,
2358 .intr_handler = qla82xx_intr_handler,
2359 .enable_intrs = qla82xx_enable_intrs,
2360 .disable_intrs = qla82xx_disable_intrs,
2361 .abort_command = qla24xx_abort_command,
2362 .target_reset = qla24xx_abort_target,
2363 .lun_reset = qla24xx_lun_reset,
2364 .fabric_login = qla24xx_login_fabric,
2365 .fabric_logout = qla24xx_fabric_logout,
2366 .calc_req_entries = NULL,
2367 .build_iocbs = NULL,
2368 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2369 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2370 .read_nvram = qla24xx_read_nvram_data,
2371 .write_nvram = qla24xx_write_nvram_data,
2372 .fw_dump = qla82xx_fw_dump,
2373 .beacon_on = qla82xx_beacon_on,
2374 .beacon_off = qla82xx_beacon_off,
2375 .beacon_blink = NULL,
2376 .read_optrom = qla82xx_read_optrom_data,
2377 .write_optrom = qla82xx_write_optrom_data,
2378 .get_flash_version = qla82xx_get_flash_version,
2379 .start_scsi = qla82xx_start_scsi,
2380 .start_scsi_mq = NULL,
2381 .abort_isp = qla82xx_abort_isp,
2382 .iospace_config = qla82xx_iospace_config,
2383 .initialize_adapter = qla2x00_initialize_adapter,
2384 };
2385
2386 static struct isp_operations qla8044_isp_ops = {
2387 .pci_config = qla82xx_pci_config,
2388 .reset_chip = qla82xx_reset_chip,
2389 .chip_diag = qla24xx_chip_diag,
2390 .config_rings = qla82xx_config_rings,
2391 .reset_adapter = qla24xx_reset_adapter,
2392 .nvram_config = qla81xx_nvram_config,
2393 .update_fw_options = qla24xx_update_fw_options,
2394 .load_risc = qla82xx_load_risc,
2395 .pci_info_str = qla24xx_pci_info_str,
2396 .fw_version_str = qla24xx_fw_version_str,
2397 .intr_handler = qla8044_intr_handler,
2398 .enable_intrs = qla82xx_enable_intrs,
2399 .disable_intrs = qla82xx_disable_intrs,
2400 .abort_command = qla24xx_abort_command,
2401 .target_reset = qla24xx_abort_target,
2402 .lun_reset = qla24xx_lun_reset,
2403 .fabric_login = qla24xx_login_fabric,
2404 .fabric_logout = qla24xx_fabric_logout,
2405 .calc_req_entries = NULL,
2406 .build_iocbs = NULL,
2407 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2408 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2409 .read_nvram = NULL,
2410 .write_nvram = NULL,
2411 .fw_dump = qla8044_fw_dump,
2412 .beacon_on = qla82xx_beacon_on,
2413 .beacon_off = qla82xx_beacon_off,
2414 .beacon_blink = NULL,
2415 .read_optrom = qla8044_read_optrom_data,
2416 .write_optrom = qla8044_write_optrom_data,
2417 .get_flash_version = qla82xx_get_flash_version,
2418 .start_scsi = qla82xx_start_scsi,
2419 .start_scsi_mq = NULL,
2420 .abort_isp = qla8044_abort_isp,
2421 .iospace_config = qla82xx_iospace_config,
2422 .initialize_adapter = qla2x00_initialize_adapter,
2423 };
2424
2425 static struct isp_operations qla83xx_isp_ops = {
2426 .pci_config = qla25xx_pci_config,
2427 .reset_chip = qla24xx_reset_chip,
2428 .chip_diag = qla24xx_chip_diag,
2429 .config_rings = qla24xx_config_rings,
2430 .reset_adapter = qla24xx_reset_adapter,
2431 .nvram_config = qla81xx_nvram_config,
2432 .update_fw_options = qla24xx_update_fw_options,
2433 .load_risc = qla81xx_load_risc,
2434 .pci_info_str = qla24xx_pci_info_str,
2435 .fw_version_str = qla24xx_fw_version_str,
2436 .intr_handler = qla24xx_intr_handler,
2437 .enable_intrs = qla24xx_enable_intrs,
2438 .disable_intrs = qla24xx_disable_intrs,
2439 .abort_command = qla24xx_abort_command,
2440 .target_reset = qla24xx_abort_target,
2441 .lun_reset = qla24xx_lun_reset,
2442 .fabric_login = qla24xx_login_fabric,
2443 .fabric_logout = qla24xx_fabric_logout,
2444 .calc_req_entries = NULL,
2445 .build_iocbs = NULL,
2446 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2447 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2448 .read_nvram = NULL,
2449 .write_nvram = NULL,
2450 .fw_dump = qla83xx_fw_dump,
2451 .beacon_on = qla24xx_beacon_on,
2452 .beacon_off = qla24xx_beacon_off,
2453 .beacon_blink = qla83xx_beacon_blink,
2454 .read_optrom = qla25xx_read_optrom_data,
2455 .write_optrom = qla24xx_write_optrom_data,
2456 .get_flash_version = qla24xx_get_flash_version,
2457 .start_scsi = qla24xx_dif_start_scsi,
2458 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2459 .abort_isp = qla2x00_abort_isp,
2460 .iospace_config = qla83xx_iospace_config,
2461 .initialize_adapter = qla2x00_initialize_adapter,
2462 };
2463
2464 static struct isp_operations qlafx00_isp_ops = {
2465 .pci_config = qlafx00_pci_config,
2466 .reset_chip = qlafx00_soft_reset,
2467 .chip_diag = qlafx00_chip_diag,
2468 .config_rings = qlafx00_config_rings,
2469 .reset_adapter = qlafx00_soft_reset,
2470 .nvram_config = NULL,
2471 .update_fw_options = NULL,
2472 .load_risc = NULL,
2473 .pci_info_str = qlafx00_pci_info_str,
2474 .fw_version_str = qlafx00_fw_version_str,
2475 .intr_handler = qlafx00_intr_handler,
2476 .enable_intrs = qlafx00_enable_intrs,
2477 .disable_intrs = qlafx00_disable_intrs,
2478 .abort_command = qla24xx_async_abort_command,
2479 .target_reset = qlafx00_abort_target,
2480 .lun_reset = qlafx00_lun_reset,
2481 .fabric_login = NULL,
2482 .fabric_logout = NULL,
2483 .calc_req_entries = NULL,
2484 .build_iocbs = NULL,
2485 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2486 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2487 .read_nvram = qla24xx_read_nvram_data,
2488 .write_nvram = qla24xx_write_nvram_data,
2489 .fw_dump = NULL,
2490 .beacon_on = qla24xx_beacon_on,
2491 .beacon_off = qla24xx_beacon_off,
2492 .beacon_blink = NULL,
2493 .read_optrom = qla24xx_read_optrom_data,
2494 .write_optrom = qla24xx_write_optrom_data,
2495 .get_flash_version = qla24xx_get_flash_version,
2496 .start_scsi = qlafx00_start_scsi,
2497 .start_scsi_mq = NULL,
2498 .abort_isp = qlafx00_abort_isp,
2499 .iospace_config = qlafx00_iospace_config,
2500 .initialize_adapter = qlafx00_initialize_adapter,
2501 };
2502
2503 static struct isp_operations qla27xx_isp_ops = {
2504 .pci_config = qla25xx_pci_config,
2505 .reset_chip = qla24xx_reset_chip,
2506 .chip_diag = qla24xx_chip_diag,
2507 .config_rings = qla24xx_config_rings,
2508 .reset_adapter = qla24xx_reset_adapter,
2509 .nvram_config = qla81xx_nvram_config,
2510 .update_fw_options = qla24xx_update_fw_options,
2511 .load_risc = qla81xx_load_risc,
2512 .pci_info_str = qla24xx_pci_info_str,
2513 .fw_version_str = qla24xx_fw_version_str,
2514 .intr_handler = qla24xx_intr_handler,
2515 .enable_intrs = qla24xx_enable_intrs,
2516 .disable_intrs = qla24xx_disable_intrs,
2517 .abort_command = qla24xx_abort_command,
2518 .target_reset = qla24xx_abort_target,
2519 .lun_reset = qla24xx_lun_reset,
2520 .fabric_login = qla24xx_login_fabric,
2521 .fabric_logout = qla24xx_fabric_logout,
2522 .calc_req_entries = NULL,
2523 .build_iocbs = NULL,
2524 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2525 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2526 .read_nvram = NULL,
2527 .write_nvram = NULL,
2528 .fw_dump = qla27xx_fwdump,
2529 .mpi_fw_dump = qla27xx_mpi_fwdump,
2530 .beacon_on = qla24xx_beacon_on,
2531 .beacon_off = qla24xx_beacon_off,
2532 .beacon_blink = qla83xx_beacon_blink,
2533 .read_optrom = qla25xx_read_optrom_data,
2534 .write_optrom = qla24xx_write_optrom_data,
2535 .get_flash_version = qla24xx_get_flash_version,
2536 .start_scsi = qla24xx_dif_start_scsi,
2537 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2538 .abort_isp = qla2x00_abort_isp,
2539 .iospace_config = qla83xx_iospace_config,
2540 .initialize_adapter = qla2x00_initialize_adapter,
2541 };
2542
2543 static inline void
qla2x00_set_isp_flags(struct qla_hw_data * ha)2544 qla2x00_set_isp_flags(struct qla_hw_data *ha)
2545 {
2546 ha->device_type = DT_EXTENDED_IDS;
2547 switch (ha->pdev->device) {
2548 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2549 ha->isp_type |= DT_ISP2100;
2550 ha->device_type &= ~DT_EXTENDED_IDS;
2551 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2552 break;
2553 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2554 ha->isp_type |= DT_ISP2200;
2555 ha->device_type &= ~DT_EXTENDED_IDS;
2556 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2557 break;
2558 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2559 ha->isp_type |= DT_ISP2300;
2560 ha->device_type |= DT_ZIO_SUPPORTED;
2561 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2562 break;
2563 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2564 ha->isp_type |= DT_ISP2312;
2565 ha->device_type |= DT_ZIO_SUPPORTED;
2566 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2567 break;
2568 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2569 ha->isp_type |= DT_ISP2322;
2570 ha->device_type |= DT_ZIO_SUPPORTED;
2571 if (ha->pdev->subsystem_vendor == 0x1028 &&
2572 ha->pdev->subsystem_device == 0x0170)
2573 ha->device_type |= DT_OEM_001;
2574 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2575 break;
2576 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2577 ha->isp_type |= DT_ISP6312;
2578 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2579 break;
2580 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2581 ha->isp_type |= DT_ISP6322;
2582 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2583 break;
2584 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2585 ha->isp_type |= DT_ISP2422;
2586 ha->device_type |= DT_ZIO_SUPPORTED;
2587 ha->device_type |= DT_FWI2;
2588 ha->device_type |= DT_IIDMA;
2589 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2590 break;
2591 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2592 ha->isp_type |= DT_ISP2432;
2593 ha->device_type |= DT_ZIO_SUPPORTED;
2594 ha->device_type |= DT_FWI2;
2595 ha->device_type |= DT_IIDMA;
2596 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2597 break;
2598 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2599 ha->isp_type |= DT_ISP8432;
2600 ha->device_type |= DT_ZIO_SUPPORTED;
2601 ha->device_type |= DT_FWI2;
2602 ha->device_type |= DT_IIDMA;
2603 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2604 break;
2605 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2606 ha->isp_type |= DT_ISP5422;
2607 ha->device_type |= DT_FWI2;
2608 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2609 break;
2610 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2611 ha->isp_type |= DT_ISP5432;
2612 ha->device_type |= DT_FWI2;
2613 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2614 break;
2615 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2616 ha->isp_type |= DT_ISP2532;
2617 ha->device_type |= DT_ZIO_SUPPORTED;
2618 ha->device_type |= DT_FWI2;
2619 ha->device_type |= DT_IIDMA;
2620 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2621 break;
2622 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2623 ha->isp_type |= DT_ISP8001;
2624 ha->device_type |= DT_ZIO_SUPPORTED;
2625 ha->device_type |= DT_FWI2;
2626 ha->device_type |= DT_IIDMA;
2627 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2628 break;
2629 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2630 ha->isp_type |= DT_ISP8021;
2631 ha->device_type |= DT_ZIO_SUPPORTED;
2632 ha->device_type |= DT_FWI2;
2633 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2634 /* Initialize 82XX ISP flags */
2635 qla82xx_init_flags(ha);
2636 break;
2637 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2638 ha->isp_type |= DT_ISP8044;
2639 ha->device_type |= DT_ZIO_SUPPORTED;
2640 ha->device_type |= DT_FWI2;
2641 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2642 /* Initialize 82XX ISP flags */
2643 qla82xx_init_flags(ha);
2644 break;
2645 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2646 ha->isp_type |= DT_ISP2031;
2647 ha->device_type |= DT_ZIO_SUPPORTED;
2648 ha->device_type |= DT_FWI2;
2649 ha->device_type |= DT_IIDMA;
2650 ha->device_type |= DT_T10_PI;
2651 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2652 break;
2653 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2654 ha->isp_type |= DT_ISP8031;
2655 ha->device_type |= DT_ZIO_SUPPORTED;
2656 ha->device_type |= DT_FWI2;
2657 ha->device_type |= DT_IIDMA;
2658 ha->device_type |= DT_T10_PI;
2659 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2660 break;
2661 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2662 ha->isp_type |= DT_ISPFX00;
2663 break;
2664 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2665 ha->isp_type |= DT_ISP2071;
2666 ha->device_type |= DT_ZIO_SUPPORTED;
2667 ha->device_type |= DT_FWI2;
2668 ha->device_type |= DT_IIDMA;
2669 ha->device_type |= DT_T10_PI;
2670 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2671 break;
2672 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2673 ha->isp_type |= DT_ISP2271;
2674 ha->device_type |= DT_ZIO_SUPPORTED;
2675 ha->device_type |= DT_FWI2;
2676 ha->device_type |= DT_IIDMA;
2677 ha->device_type |= DT_T10_PI;
2678 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2679 break;
2680 case PCI_DEVICE_ID_QLOGIC_ISP2261:
2681 ha->isp_type |= DT_ISP2261;
2682 ha->device_type |= DT_ZIO_SUPPORTED;
2683 ha->device_type |= DT_FWI2;
2684 ha->device_type |= DT_IIDMA;
2685 ha->device_type |= DT_T10_PI;
2686 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2687 break;
2688 case PCI_DEVICE_ID_QLOGIC_ISP2081:
2689 case PCI_DEVICE_ID_QLOGIC_ISP2089:
2690 ha->isp_type |= DT_ISP2081;
2691 ha->device_type |= DT_ZIO_SUPPORTED;
2692 ha->device_type |= DT_FWI2;
2693 ha->device_type |= DT_IIDMA;
2694 ha->device_type |= DT_T10_PI;
2695 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2696 break;
2697 case PCI_DEVICE_ID_QLOGIC_ISP2281:
2698 case PCI_DEVICE_ID_QLOGIC_ISP2289:
2699 ha->isp_type |= DT_ISP2281;
2700 ha->device_type |= DT_ZIO_SUPPORTED;
2701 ha->device_type |= DT_FWI2;
2702 ha->device_type |= DT_IIDMA;
2703 ha->device_type |= DT_T10_PI;
2704 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2705 break;
2706 }
2707
2708 if (IS_QLA82XX(ha))
2709 ha->port_no = ha->portnum & 1;
2710 else {
2711 /* Get adapter physical port no from interrupt pin register. */
2712 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2713 if (IS_QLA25XX(ha) || IS_QLA2031(ha) ||
2714 IS_QLA27XX(ha) || IS_QLA28XX(ha))
2715 ha->port_no--;
2716 else
2717 ha->port_no = !(ha->port_no & 1);
2718 }
2719
2720 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2721 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2722 ha->device_type, ha->port_no, ha->fw_srisc_address);
2723 }
2724
2725 static void
qla2xxx_scan_start(struct Scsi_Host * shost)2726 qla2xxx_scan_start(struct Scsi_Host *shost)
2727 {
2728 scsi_qla_host_t *vha = shost_priv(shost);
2729
2730 if (vha->hw->flags.running_gold_fw)
2731 return;
2732
2733 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2734 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2735 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2736 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2737 }
2738
2739 static int
qla2xxx_scan_finished(struct Scsi_Host * shost,unsigned long time)2740 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2741 {
2742 scsi_qla_host_t *vha = shost_priv(shost);
2743
2744 if (test_bit(UNLOADING, &vha->dpc_flags))
2745 return 1;
2746 if (!vha->host)
2747 return 1;
2748 if (time > vha->hw->loop_reset_delay * HZ)
2749 return 1;
2750
2751 return atomic_read(&vha->loop_state) == LOOP_READY;
2752 }
2753
qla2x00_iocb_work_fn(struct work_struct * work)2754 static void qla2x00_iocb_work_fn(struct work_struct *work)
2755 {
2756 struct scsi_qla_host *vha = container_of(work,
2757 struct scsi_qla_host, iocb_work);
2758 struct qla_hw_data *ha = vha->hw;
2759 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2760 int i = 2;
2761 unsigned long flags;
2762
2763 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2764 return;
2765
2766 while (!list_empty(&vha->work_list) && i > 0) {
2767 qla2x00_do_work(vha);
2768 i--;
2769 }
2770
2771 spin_lock_irqsave(&vha->work_lock, flags);
2772 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2773 spin_unlock_irqrestore(&vha->work_lock, flags);
2774 }
2775
2776 /*
2777 * PCI driver interface
2778 */
2779 static int
qla2x00_probe_one(struct pci_dev * pdev,const struct pci_device_id * id)2780 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2781 {
2782 int ret = -ENODEV;
2783 struct Scsi_Host *host;
2784 scsi_qla_host_t *base_vha = NULL;
2785 struct qla_hw_data *ha;
2786 char pci_info[30];
2787 char fw_str[30], wq_name[30];
2788 struct scsi_host_template *sht;
2789 int bars, mem_only = 0;
2790 uint16_t req_length = 0, rsp_length = 0;
2791 struct req_que *req = NULL;
2792 struct rsp_que *rsp = NULL;
2793 int i;
2794
2795 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2796 sht = &qla2xxx_driver_template;
2797 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2798 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2799 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2800 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2801 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2802 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2803 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2804 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2805 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2806 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2807 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2808 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2809 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2810 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2811 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 ||
2812 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 ||
2813 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 ||
2814 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 ||
2815 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) {
2816 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2817 mem_only = 1;
2818 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2819 "Mem only adapter.\n");
2820 }
2821 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2822 "Bars=%d.\n", bars);
2823
2824 if (mem_only) {
2825 if (pci_enable_device_mem(pdev))
2826 return ret;
2827 } else {
2828 if (pci_enable_device(pdev))
2829 return ret;
2830 }
2831
2832 if (is_kdump_kernel()) {
2833 ql2xmqsupport = 0;
2834 ql2xallocfwdump = 0;
2835 }
2836
2837 /* This may fail but that's ok */
2838 pci_enable_pcie_error_reporting(pdev);
2839
2840 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2841 if (!ha) {
2842 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2843 "Unable to allocate memory for ha.\n");
2844 goto disable_device;
2845 }
2846 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2847 "Memory allocated for ha=%p.\n", ha);
2848 ha->pdev = pdev;
2849 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2850 spin_lock_init(&ha->tgt.q_full_lock);
2851 spin_lock_init(&ha->tgt.sess_lock);
2852 spin_lock_init(&ha->tgt.atio_lock);
2853
2854 atomic_set(&ha->nvme_active_aen_cnt, 0);
2855
2856 /* Clear our data area */
2857 ha->bars = bars;
2858 ha->mem_only = mem_only;
2859 spin_lock_init(&ha->hardware_lock);
2860 spin_lock_init(&ha->vport_slock);
2861 mutex_init(&ha->selflogin_lock);
2862 mutex_init(&ha->optrom_mutex);
2863
2864 /* Set ISP-type information. */
2865 qla2x00_set_isp_flags(ha);
2866
2867 /* Set EEH reset type to fundamental if required by hba */
2868 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2869 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
2870 pdev->needs_freset = 1;
2871
2872 ha->prev_topology = 0;
2873 ha->init_cb_size = sizeof(init_cb_t);
2874 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2875 ha->optrom_size = OPTROM_SIZE_2300;
2876 ha->max_exchg = FW_MAX_EXCHANGES_CNT;
2877 atomic_set(&ha->num_pend_mbx_stage1, 0);
2878 atomic_set(&ha->num_pend_mbx_stage2, 0);
2879 atomic_set(&ha->num_pend_mbx_stage3, 0);
2880 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD);
2881 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD;
2882
2883 /* Assign ISP specific operations. */
2884 if (IS_QLA2100(ha)) {
2885 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2886 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
2887 req_length = REQUEST_ENTRY_CNT_2100;
2888 rsp_length = RESPONSE_ENTRY_CNT_2100;
2889 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2890 ha->gid_list_info_size = 4;
2891 ha->flash_conf_off = ~0;
2892 ha->flash_data_off = ~0;
2893 ha->nvram_conf_off = ~0;
2894 ha->nvram_data_off = ~0;
2895 ha->isp_ops = &qla2100_isp_ops;
2896 } else if (IS_QLA2200(ha)) {
2897 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2898 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
2899 req_length = REQUEST_ENTRY_CNT_2200;
2900 rsp_length = RESPONSE_ENTRY_CNT_2100;
2901 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2902 ha->gid_list_info_size = 4;
2903 ha->flash_conf_off = ~0;
2904 ha->flash_data_off = ~0;
2905 ha->nvram_conf_off = ~0;
2906 ha->nvram_data_off = ~0;
2907 ha->isp_ops = &qla2100_isp_ops;
2908 } else if (IS_QLA23XX(ha)) {
2909 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2910 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2911 req_length = REQUEST_ENTRY_CNT_2200;
2912 rsp_length = RESPONSE_ENTRY_CNT_2300;
2913 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2914 ha->gid_list_info_size = 6;
2915 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2916 ha->optrom_size = OPTROM_SIZE_2322;
2917 ha->flash_conf_off = ~0;
2918 ha->flash_data_off = ~0;
2919 ha->nvram_conf_off = ~0;
2920 ha->nvram_data_off = ~0;
2921 ha->isp_ops = &qla2300_isp_ops;
2922 } else if (IS_QLA24XX_TYPE(ha)) {
2923 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2924 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2925 req_length = REQUEST_ENTRY_CNT_24XX;
2926 rsp_length = RESPONSE_ENTRY_CNT_2300;
2927 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2928 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2929 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2930 ha->gid_list_info_size = 8;
2931 ha->optrom_size = OPTROM_SIZE_24XX;
2932 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
2933 ha->isp_ops = &qla24xx_isp_ops;
2934 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2935 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2936 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2937 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2938 } else if (IS_QLA25XX(ha)) {
2939 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2940 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2941 req_length = REQUEST_ENTRY_CNT_24XX;
2942 rsp_length = RESPONSE_ENTRY_CNT_2300;
2943 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2944 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2945 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2946 ha->gid_list_info_size = 8;
2947 ha->optrom_size = OPTROM_SIZE_25XX;
2948 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2949 ha->isp_ops = &qla25xx_isp_ops;
2950 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2951 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2952 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2953 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2954 } else if (IS_QLA81XX(ha)) {
2955 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2956 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2957 req_length = REQUEST_ENTRY_CNT_24XX;
2958 rsp_length = RESPONSE_ENTRY_CNT_2300;
2959 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2960 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2961 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2962 ha->gid_list_info_size = 8;
2963 ha->optrom_size = OPTROM_SIZE_81XX;
2964 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2965 ha->isp_ops = &qla81xx_isp_ops;
2966 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2967 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2968 ha->nvram_conf_off = ~0;
2969 ha->nvram_data_off = ~0;
2970 } else if (IS_QLA82XX(ha)) {
2971 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2972 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2973 req_length = REQUEST_ENTRY_CNT_82XX;
2974 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2975 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2976 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2977 ha->gid_list_info_size = 8;
2978 ha->optrom_size = OPTROM_SIZE_82XX;
2979 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2980 ha->isp_ops = &qla82xx_isp_ops;
2981 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2982 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2983 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2984 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2985 } else if (IS_QLA8044(ha)) {
2986 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2987 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2988 req_length = REQUEST_ENTRY_CNT_82XX;
2989 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2990 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2991 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2992 ha->gid_list_info_size = 8;
2993 ha->optrom_size = OPTROM_SIZE_83XX;
2994 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2995 ha->isp_ops = &qla8044_isp_ops;
2996 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2997 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2998 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2999 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3000 } else if (IS_QLA83XX(ha)) {
3001 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3002 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3003 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3004 req_length = REQUEST_ENTRY_CNT_83XX;
3005 rsp_length = RESPONSE_ENTRY_CNT_83XX;
3006 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3007 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3008 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3009 ha->gid_list_info_size = 8;
3010 ha->optrom_size = OPTROM_SIZE_83XX;
3011 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3012 ha->isp_ops = &qla83xx_isp_ops;
3013 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3014 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3015 ha->nvram_conf_off = ~0;
3016 ha->nvram_data_off = ~0;
3017 } else if (IS_QLAFX00(ha)) {
3018 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
3019 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
3020 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
3021 req_length = REQUEST_ENTRY_CNT_FX00;
3022 rsp_length = RESPONSE_ENTRY_CNT_FX00;
3023 ha->isp_ops = &qlafx00_isp_ops;
3024 ha->port_down_retry_count = 30; /* default value */
3025 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
3026 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
3027 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
3028 ha->mr.fw_hbt_en = 1;
3029 ha->mr.host_info_resend = false;
3030 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
3031 } else if (IS_QLA27XX(ha)) {
3032 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3033 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3034 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3035 req_length = REQUEST_ENTRY_CNT_83XX;
3036 rsp_length = RESPONSE_ENTRY_CNT_83XX;
3037 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3038 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3039 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3040 ha->gid_list_info_size = 8;
3041 ha->optrom_size = OPTROM_SIZE_83XX;
3042 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3043 ha->isp_ops = &qla27xx_isp_ops;
3044 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3045 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3046 ha->nvram_conf_off = ~0;
3047 ha->nvram_data_off = ~0;
3048 } else if (IS_QLA28XX(ha)) {
3049 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3050 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3051 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3052 req_length = REQUEST_ENTRY_CNT_24XX;
3053 rsp_length = RESPONSE_ENTRY_CNT_2300;
3054 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3055 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3056 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3057 ha->gid_list_info_size = 8;
3058 ha->optrom_size = OPTROM_SIZE_28XX;
3059 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3060 ha->isp_ops = &qla27xx_isp_ops;
3061 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX;
3062 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX;
3063 ha->nvram_conf_off = ~0;
3064 ha->nvram_data_off = ~0;
3065 }
3066
3067 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
3068 "mbx_count=%d, req_length=%d, "
3069 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
3070 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
3071 "max_fibre_devices=%d.\n",
3072 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
3073 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
3074 ha->nvram_npiv_size, ha->max_fibre_devices);
3075 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
3076 "isp_ops=%p, flash_conf_off=%d, "
3077 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
3078 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3079 ha->nvram_conf_off, ha->nvram_data_off);
3080
3081 /* Configure PCI I/O space */
3082 ret = ha->isp_ops->iospace_config(ha);
3083 if (ret)
3084 goto iospace_config_failed;
3085
3086 ql_log_pci(ql_log_info, pdev, 0x001d,
3087 "Found an ISP%04X irq %d iobase 0x%p.\n",
3088 pdev->device, pdev->irq, ha->iobase);
3089 mutex_init(&ha->vport_lock);
3090 mutex_init(&ha->mq_lock);
3091 init_completion(&ha->mbx_cmd_comp);
3092 complete(&ha->mbx_cmd_comp);
3093 init_completion(&ha->mbx_intr_comp);
3094 init_completion(&ha->dcbx_comp);
3095 init_completion(&ha->lb_portup_comp);
3096
3097 set_bit(0, (unsigned long *) ha->vp_idx_map);
3098
3099 qla2x00_config_dma_addressing(ha);
3100 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3101 "64 Bit addressing is %s.\n",
3102 ha->flags.enable_64bit_addressing ? "enable" :
3103 "disable");
3104 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
3105 if (ret) {
3106 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3107 "Failed to allocate memory for adapter, aborting.\n");
3108
3109 goto probe_hw_failed;
3110 }
3111
3112 req->max_q_depth = MAX_Q_DEPTH;
3113 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
3114 req->max_q_depth = ql2xmaxqdepth;
3115
3116
3117 base_vha = qla2x00_create_host(sht, ha);
3118 if (!base_vha) {
3119 ret = -ENOMEM;
3120 goto probe_hw_failed;
3121 }
3122
3123 pci_set_drvdata(pdev, base_vha);
3124 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3125
3126 host = base_vha->host;
3127 base_vha->req = req;
3128 if (IS_QLA2XXX_MIDTYPE(ha))
3129 base_vha->mgmt_svr_loop_id =
3130 qla2x00_reserve_mgmt_server_loop_id(base_vha);
3131 else
3132 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3133 base_vha->vp_idx;
3134
3135 /* Setup fcport template structure. */
3136 ha->mr.fcport.vha = base_vha;
3137 ha->mr.fcport.port_type = FCT_UNKNOWN;
3138 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3139 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3140 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3141 ha->mr.fcport.scan_state = 1;
3142
3143 /* Set the SG table size based on ISP type */
3144 if (!IS_FWI2_CAPABLE(ha)) {
3145 if (IS_QLA2100(ha))
3146 host->sg_tablesize = 32;
3147 } else {
3148 if (!IS_QLA82XX(ha))
3149 host->sg_tablesize = QLA_SG_ALL;
3150 }
3151 host->max_id = ha->max_fibre_devices;
3152 host->cmd_per_lun = 3;
3153 host->unique_id = host->host_no;
3154 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
3155 host->max_cmd_len = 32;
3156 else
3157 host->max_cmd_len = MAX_CMDSZ;
3158 host->max_channel = MAX_BUSES - 1;
3159 /* Older HBAs support only 16-bit LUNs */
3160 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3161 ql2xmaxlun > 0xffff)
3162 host->max_lun = 0xffff;
3163 else
3164 host->max_lun = ql2xmaxlun;
3165 host->transportt = qla2xxx_transport_template;
3166 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
3167
3168 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3169 "max_id=%d this_id=%d "
3170 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
3171 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
3172 host->this_id, host->cmd_per_lun, host->unique_id,
3173 host->max_cmd_len, host->max_channel, host->max_lun,
3174 host->transportt, sht->vendor_id);
3175
3176 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
3177
3178 /* Set up the irqs */
3179 ret = qla2x00_request_irqs(ha, rsp);
3180 if (ret)
3181 goto probe_failed;
3182
3183 /* Alloc arrays of request and response ring ptrs */
3184 ret = qla2x00_alloc_queues(ha, req, rsp);
3185 if (ret) {
3186 ql_log(ql_log_fatal, base_vha, 0x003d,
3187 "Failed to allocate memory for queue pointers..."
3188 "aborting.\n");
3189 ret = -ENODEV;
3190 goto probe_failed;
3191 }
3192
3193 if (ha->mqenable) {
3194 /* number of hardware queues supported by blk/scsi-mq*/
3195 host->nr_hw_queues = ha->max_qpairs;
3196
3197 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3198 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
3199 } else {
3200 if (ql2xnvmeenable) {
3201 host->nr_hw_queues = ha->max_qpairs;
3202 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3203 "FC-NVMe support is enabled, HW queues=%d\n",
3204 host->nr_hw_queues);
3205 } else {
3206 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3207 "blk/scsi-mq disabled.\n");
3208 }
3209 }
3210
3211 qlt_probe_one_stage1(base_vha, ha);
3212
3213 pci_save_state(pdev);
3214
3215 /* Assign back pointers */
3216 rsp->req = req;
3217 req->rsp = rsp;
3218
3219 if (IS_QLAFX00(ha)) {
3220 ha->rsp_q_map[0] = rsp;
3221 ha->req_q_map[0] = req;
3222 set_bit(0, ha->req_qid_map);
3223 set_bit(0, ha->rsp_qid_map);
3224 }
3225
3226 /* FWI2-capable only. */
3227 req->req_q_in = &ha->iobase->isp24.req_q_in;
3228 req->req_q_out = &ha->iobase->isp24.req_q_out;
3229 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3230 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
3231 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3232 IS_QLA28XX(ha)) {
3233 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3234 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3235 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3236 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
3237 }
3238
3239 if (IS_QLAFX00(ha)) {
3240 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3241 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3242 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3243 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3244 }
3245
3246 if (IS_P3P_TYPE(ha)) {
3247 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3248 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3249 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3250 }
3251
3252 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3253 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3254 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3255 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3256 "req->req_q_in=%p req->req_q_out=%p "
3257 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3258 req->req_q_in, req->req_q_out,
3259 rsp->rsp_q_in, rsp->rsp_q_out);
3260 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3261 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3262 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3263 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3264 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3265 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
3266
3267 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0);
3268 if (unlikely(!ha->wq)) {
3269 ret = -ENOMEM;
3270 goto probe_failed;
3271 }
3272
3273 if (ha->isp_ops->initialize_adapter(base_vha)) {
3274 ql_log(ql_log_fatal, base_vha, 0x00d6,
3275 "Failed to initialize adapter - Adapter flags %x.\n",
3276 base_vha->device_flags);
3277
3278 if (IS_QLA82XX(ha)) {
3279 qla82xx_idc_lock(ha);
3280 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3281 QLA8XXX_DEV_FAILED);
3282 qla82xx_idc_unlock(ha);
3283 ql_log(ql_log_fatal, base_vha, 0x00d7,
3284 "HW State: FAILED.\n");
3285 } else if (IS_QLA8044(ha)) {
3286 qla8044_idc_lock(ha);
3287 qla8044_wr_direct(base_vha,
3288 QLA8044_CRB_DEV_STATE_INDEX,
3289 QLA8XXX_DEV_FAILED);
3290 qla8044_idc_unlock(ha);
3291 ql_log(ql_log_fatal, base_vha, 0x0150,
3292 "HW State: FAILED.\n");
3293 }
3294
3295 ret = -ENODEV;
3296 goto probe_failed;
3297 }
3298
3299 if (IS_QLAFX00(ha))
3300 host->can_queue = QLAFX00_MAX_CANQUEUE;
3301 else
3302 host->can_queue = req->num_outstanding_cmds - 10;
3303
3304 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3305 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3306 host->can_queue, base_vha->req,
3307 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3308
3309 if (ha->mqenable) {
3310 bool startit = false;
3311
3312 if (QLA_TGT_MODE_ENABLED())
3313 startit = false;
3314
3315 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED)
3316 startit = true;
3317
3318 /* Create start of day qpairs for Block MQ */
3319 for (i = 0; i < ha->max_qpairs; i++)
3320 qla2xxx_create_qpair(base_vha, 5, 0, startit);
3321 }
3322 qla_init_iocb_limit(base_vha);
3323
3324 if (ha->flags.running_gold_fw)
3325 goto skip_dpc;
3326
3327 /*
3328 * Startup the kernel thread for this host adapter
3329 */
3330 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
3331 "%s_dpc", base_vha->host_str);
3332 if (IS_ERR(ha->dpc_thread)) {
3333 ql_log(ql_log_fatal, base_vha, 0x00ed,
3334 "Failed to start DPC thread.\n");
3335 ret = PTR_ERR(ha->dpc_thread);
3336 ha->dpc_thread = NULL;
3337 goto probe_failed;
3338 }
3339 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3340 "DPC thread started successfully.\n");
3341
3342 /*
3343 * If we're not coming up in initiator mode, we might sit for
3344 * a while without waking up the dpc thread, which leads to a
3345 * stuck process warning. So just kick the dpc once here and
3346 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3347 */
3348 qla2xxx_wake_dpc(base_vha);
3349
3350 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3351
3352 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3353 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3354 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3355 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3356
3357 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3358 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3359 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3360 INIT_WORK(&ha->idc_state_handler,
3361 qla83xx_idc_state_handler_work);
3362 INIT_WORK(&ha->nic_core_unrecoverable,
3363 qla83xx_nic_core_unrecoverable_work);
3364 }
3365
3366 skip_dpc:
3367 list_add_tail(&base_vha->list, &ha->vp_list);
3368 base_vha->host->irq = ha->pdev->irq;
3369
3370 /* Initialized the timer */
3371 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
3372 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3373 "Started qla2x00_timer with "
3374 "interval=%d.\n", WATCH_INTERVAL);
3375 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3376 "Detected hba at address=%p.\n",
3377 ha);
3378
3379 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
3380 if (ha->fw_attributes & BIT_4) {
3381 int prot = 0, guard;
3382
3383 base_vha->flags.difdix_supported = 1;
3384 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3385 "Registering for DIF/DIX type 1 and 3 protection.\n");
3386 if (ql2xenabledif == 1)
3387 prot = SHOST_DIX_TYPE0_PROTECTION;
3388 if (ql2xprotmask)
3389 scsi_host_set_prot(host, ql2xprotmask);
3390 else
3391 scsi_host_set_prot(host,
3392 prot | SHOST_DIF_TYPE1_PROTECTION
3393 | SHOST_DIF_TYPE2_PROTECTION
3394 | SHOST_DIF_TYPE3_PROTECTION
3395 | SHOST_DIX_TYPE1_PROTECTION
3396 | SHOST_DIX_TYPE2_PROTECTION
3397 | SHOST_DIX_TYPE3_PROTECTION);
3398
3399 guard = SHOST_DIX_GUARD_CRC;
3400
3401 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3402 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3403 guard |= SHOST_DIX_GUARD_IP;
3404
3405 if (ql2xprotguard)
3406 scsi_host_set_guard(host, ql2xprotguard);
3407 else
3408 scsi_host_set_guard(host, guard);
3409 } else
3410 base_vha->flags.difdix_supported = 0;
3411 }
3412
3413 ha->isp_ops->enable_intrs(ha);
3414
3415 if (IS_QLAFX00(ha)) {
3416 ret = qlafx00_fx_disc(base_vha,
3417 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3418 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3419 QLA_SG_ALL : 128;
3420 }
3421
3422 ret = scsi_add_host(host, &pdev->dev);
3423 if (ret)
3424 goto probe_failed;
3425
3426 base_vha->flags.init_done = 1;
3427 base_vha->flags.online = 1;
3428 ha->prev_minidump_failed = 0;
3429
3430 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3431 "Init done and hba is online.\n");
3432
3433 if (qla_ini_mode_enabled(base_vha) ||
3434 qla_dual_mode_enabled(base_vha))
3435 scsi_scan_host(host);
3436 else
3437 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3438 "skipping scsi_scan_host() for non-initiator port\n");
3439
3440 qla2x00_alloc_sysfs_attr(base_vha);
3441
3442 if (IS_QLAFX00(ha)) {
3443 ret = qlafx00_fx_disc(base_vha,
3444 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3445
3446 /* Register system information */
3447 ret = qlafx00_fx_disc(base_vha,
3448 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3449 }
3450
3451 qla2x00_init_host_attr(base_vha);
3452
3453 qla2x00_dfs_setup(base_vha);
3454
3455 ql_log(ql_log_info, base_vha, 0x00fb,
3456 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
3457 ql_log(ql_log_info, base_vha, 0x00fc,
3458 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3459 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info,
3460 sizeof(pci_info)),
3461 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3462 base_vha->host_no,
3463 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
3464
3465 qlt_add_target(ha, base_vha);
3466
3467 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3468
3469 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3470 return -ENODEV;
3471
3472 return 0;
3473
3474 probe_failed:
3475 if (base_vha->gnl.l) {
3476 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3477 base_vha->gnl.l, base_vha->gnl.ldma);
3478 base_vha->gnl.l = NULL;
3479 }
3480
3481 if (base_vha->timer_active)
3482 qla2x00_stop_timer(base_vha);
3483 base_vha->flags.online = 0;
3484 if (ha->dpc_thread) {
3485 struct task_struct *t = ha->dpc_thread;
3486
3487 ha->dpc_thread = NULL;
3488 kthread_stop(t);
3489 }
3490
3491 qla2x00_free_device(base_vha);
3492 scsi_host_put(base_vha->host);
3493 /*
3494 * Need to NULL out local req/rsp after
3495 * qla2x00_free_device => qla2x00_free_queues frees
3496 * what these are pointing to. Or else we'll
3497 * fall over below in qla2x00_free_req/rsp_que.
3498 */
3499 req = NULL;
3500 rsp = NULL;
3501
3502 probe_hw_failed:
3503 qla2x00_mem_free(ha);
3504 qla2x00_free_req_que(ha, req);
3505 qla2x00_free_rsp_que(ha, rsp);
3506 qla2x00_clear_drv_active(ha);
3507
3508 iospace_config_failed:
3509 if (IS_P3P_TYPE(ha)) {
3510 if (!ha->nx_pcibase)
3511 iounmap((device_reg_t *)ha->nx_pcibase);
3512 if (!ql2xdbwr)
3513 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3514 } else {
3515 if (ha->iobase)
3516 iounmap(ha->iobase);
3517 if (ha->cregbase)
3518 iounmap(ha->cregbase);
3519 }
3520 pci_release_selected_regions(ha->pdev, ha->bars);
3521 kfree(ha);
3522
3523 disable_device:
3524 pci_disable_device(pdev);
3525 return ret;
3526 }
3527
__qla_set_remove_flag(scsi_qla_host_t * base_vha)3528 static void __qla_set_remove_flag(scsi_qla_host_t *base_vha)
3529 {
3530 scsi_qla_host_t *vp;
3531 unsigned long flags;
3532 struct qla_hw_data *ha;
3533
3534 if (!base_vha)
3535 return;
3536
3537 ha = base_vha->hw;
3538
3539 spin_lock_irqsave(&ha->vport_slock, flags);
3540 list_for_each_entry(vp, &ha->vp_list, list)
3541 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags);
3542
3543 /*
3544 * Indicate device removal to prevent future board_disable
3545 * and wait until any pending board_disable has completed.
3546 */
3547 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3548 spin_unlock_irqrestore(&ha->vport_slock, flags);
3549 }
3550
3551 static void
qla2x00_shutdown(struct pci_dev * pdev)3552 qla2x00_shutdown(struct pci_dev *pdev)
3553 {
3554 scsi_qla_host_t *vha;
3555 struct qla_hw_data *ha;
3556
3557 vha = pci_get_drvdata(pdev);
3558 ha = vha->hw;
3559
3560 ql_log(ql_log_info, vha, 0xfffa,
3561 "Adapter shutdown\n");
3562
3563 /*
3564 * Prevent future board_disable and wait
3565 * until any pending board_disable has completed.
3566 */
3567 __qla_set_remove_flag(vha);
3568 cancel_work_sync(&ha->board_disable);
3569
3570 if (!atomic_read(&pdev->enable_cnt))
3571 return;
3572
3573 /* Notify ISPFX00 firmware */
3574 if (IS_QLAFX00(ha))
3575 qlafx00_driver_shutdown(vha, 20);
3576
3577 /* Turn-off FCE trace */
3578 if (ha->flags.fce_enabled) {
3579 qla2x00_disable_fce_trace(vha, NULL, NULL);
3580 ha->flags.fce_enabled = 0;
3581 }
3582
3583 /* Turn-off EFT trace */
3584 if (ha->eft)
3585 qla2x00_disable_eft_trace(vha);
3586
3587 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3588 IS_QLA28XX(ha)) {
3589 if (ha->flags.fw_started)
3590 qla2x00_abort_isp_cleanup(vha);
3591 } else {
3592 /* Stop currently executing firmware. */
3593 qla2x00_try_to_stop_firmware(vha);
3594 }
3595
3596 /* Disable timer */
3597 if (vha->timer_active)
3598 qla2x00_stop_timer(vha);
3599
3600 /* Turn adapter off line */
3601 vha->flags.online = 0;
3602
3603 /* turn-off interrupts on the card */
3604 if (ha->interrupts_on) {
3605 vha->flags.init_done = 0;
3606 ha->isp_ops->disable_intrs(ha);
3607 }
3608
3609 qla2x00_free_irqs(vha);
3610
3611 qla2x00_free_fw_dump(ha);
3612
3613 pci_disable_device(pdev);
3614 ql_log(ql_log_info, vha, 0xfffe,
3615 "Adapter shutdown successfully.\n");
3616 }
3617
3618 /* Deletes all the virtual ports for a given ha */
3619 static void
qla2x00_delete_all_vps(struct qla_hw_data * ha,scsi_qla_host_t * base_vha)3620 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
3621 {
3622 scsi_qla_host_t *vha;
3623 unsigned long flags;
3624
3625 mutex_lock(&ha->vport_lock);
3626 while (ha->cur_vport_count) {
3627 spin_lock_irqsave(&ha->vport_slock, flags);
3628
3629 BUG_ON(base_vha->list.next == &ha->vp_list);
3630 /* This assumes first entry in ha->vp_list is always base vha */
3631 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
3632 scsi_host_get(vha->host);
3633
3634 spin_unlock_irqrestore(&ha->vport_slock, flags);
3635 mutex_unlock(&ha->vport_lock);
3636
3637 qla_nvme_delete(vha);
3638
3639 fc_vport_terminate(vha->fc_vport);
3640 scsi_host_put(vha->host);
3641
3642 mutex_lock(&ha->vport_lock);
3643 }
3644 mutex_unlock(&ha->vport_lock);
3645 }
3646
3647 /* Stops all deferred work threads */
3648 static void
qla2x00_destroy_deferred_work(struct qla_hw_data * ha)3649 qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3650 {
3651 /* Cancel all work and destroy DPC workqueues */
3652 if (ha->dpc_lp_wq) {
3653 cancel_work_sync(&ha->idc_aen);
3654 destroy_workqueue(ha->dpc_lp_wq);
3655 ha->dpc_lp_wq = NULL;
3656 }
3657
3658 if (ha->dpc_hp_wq) {
3659 cancel_work_sync(&ha->nic_core_reset);
3660 cancel_work_sync(&ha->idc_state_handler);
3661 cancel_work_sync(&ha->nic_core_unrecoverable);
3662 destroy_workqueue(ha->dpc_hp_wq);
3663 ha->dpc_hp_wq = NULL;
3664 }
3665
3666 /* Kill the kernel thread for this host */
3667 if (ha->dpc_thread) {
3668 struct task_struct *t = ha->dpc_thread;
3669
3670 /*
3671 * qla2xxx_wake_dpc checks for ->dpc_thread
3672 * so we need to zero it out.
3673 */
3674 ha->dpc_thread = NULL;
3675 kthread_stop(t);
3676 }
3677 }
3678
3679 static void
qla2x00_unmap_iobases(struct qla_hw_data * ha)3680 qla2x00_unmap_iobases(struct qla_hw_data *ha)
3681 {
3682 if (IS_QLA82XX(ha)) {
3683
3684 iounmap((device_reg_t *)ha->nx_pcibase);
3685 if (!ql2xdbwr)
3686 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3687 } else {
3688 if (ha->iobase)
3689 iounmap(ha->iobase);
3690
3691 if (ha->cregbase)
3692 iounmap(ha->cregbase);
3693
3694 if (ha->mqiobase)
3695 iounmap(ha->mqiobase);
3696
3697 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&
3698 ha->msixbase)
3699 iounmap(ha->msixbase);
3700 }
3701 }
3702
3703 static void
qla2x00_clear_drv_active(struct qla_hw_data * ha)3704 qla2x00_clear_drv_active(struct qla_hw_data *ha)
3705 {
3706 if (IS_QLA8044(ha)) {
3707 qla8044_idc_lock(ha);
3708 qla8044_clear_drv_active(ha);
3709 qla8044_idc_unlock(ha);
3710 } else if (IS_QLA82XX(ha)) {
3711 qla82xx_idc_lock(ha);
3712 qla82xx_clear_drv_active(ha);
3713 qla82xx_idc_unlock(ha);
3714 }
3715 }
3716
3717 static void
qla2x00_remove_one(struct pci_dev * pdev)3718 qla2x00_remove_one(struct pci_dev *pdev)
3719 {
3720 scsi_qla_host_t *base_vha;
3721 struct qla_hw_data *ha;
3722
3723 base_vha = pci_get_drvdata(pdev);
3724 ha = base_vha->hw;
3725 ql_log(ql_log_info, base_vha, 0xb079,
3726 "Removing driver\n");
3727 __qla_set_remove_flag(base_vha);
3728 cancel_work_sync(&ha->board_disable);
3729
3730 /*
3731 * If the PCI device is disabled then there was a PCI-disconnect and
3732 * qla2x00_disable_board_on_pci_error has taken care of most of the
3733 * resources.
3734 */
3735 if (!atomic_read(&pdev->enable_cnt)) {
3736 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3737 base_vha->gnl.l, base_vha->gnl.ldma);
3738 base_vha->gnl.l = NULL;
3739 scsi_host_put(base_vha->host);
3740 kfree(ha);
3741 pci_set_drvdata(pdev, NULL);
3742 return;
3743 }
3744 qla2x00_wait_for_hba_ready(base_vha);
3745
3746 /*
3747 * if UNLOADING flag is already set, then continue unload,
3748 * where it was set first.
3749 */
3750 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
3751 return;
3752
3753 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3754 IS_QLA28XX(ha)) {
3755 if (ha->flags.fw_started)
3756 qla2x00_abort_isp_cleanup(base_vha);
3757 } else if (!IS_QLAFX00(ha)) {
3758 if (IS_QLA8031(ha)) {
3759 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3760 "Clearing fcoe driver presence.\n");
3761 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3762 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3763 "Error while clearing DRV-Presence.\n");
3764 }
3765
3766 qla2x00_try_to_stop_firmware(base_vha);
3767 }
3768
3769 qla2x00_wait_for_sess_deletion(base_vha);
3770
3771 qla_nvme_delete(base_vha);
3772
3773 dma_free_coherent(&ha->pdev->dev,
3774 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
3775
3776 base_vha->gnl.l = NULL;
3777
3778 vfree(base_vha->scan.l);
3779
3780 if (IS_QLAFX00(ha))
3781 qlafx00_driver_shutdown(base_vha, 20);
3782
3783 qla2x00_delete_all_vps(ha, base_vha);
3784
3785 qla2x00_dfs_remove(base_vha);
3786
3787 qla84xx_put_chip(base_vha);
3788
3789 /* Disable timer */
3790 if (base_vha->timer_active)
3791 qla2x00_stop_timer(base_vha);
3792
3793 base_vha->flags.online = 0;
3794
3795 /* free DMA memory */
3796 if (ha->exlogin_buf)
3797 qla2x00_free_exlogin_buffer(ha);
3798
3799 /* free DMA memory */
3800 if (ha->exchoffld_buf)
3801 qla2x00_free_exchoffld_buffer(ha);
3802
3803 qla2x00_destroy_deferred_work(ha);
3804
3805 qlt_remove_target(ha, base_vha);
3806
3807 qla2x00_free_sysfs_attr(base_vha, true);
3808
3809 fc_remove_host(base_vha->host);
3810 qlt_remove_target_resources(ha);
3811
3812 scsi_remove_host(base_vha->host);
3813
3814 qla2x00_free_device(base_vha);
3815
3816 qla2x00_clear_drv_active(ha);
3817
3818 scsi_host_put(base_vha->host);
3819
3820 qla2x00_unmap_iobases(ha);
3821
3822 pci_release_selected_regions(ha->pdev, ha->bars);
3823 kfree(ha);
3824
3825 pci_disable_pcie_error_reporting(pdev);
3826
3827 pci_disable_device(pdev);
3828 }
3829
3830 static inline void
qla24xx_free_purex_list(struct purex_list * list)3831 qla24xx_free_purex_list(struct purex_list *list)
3832 {
3833 struct list_head *item, *next;
3834 ulong flags;
3835
3836 spin_lock_irqsave(&list->lock, flags);
3837 list_for_each_safe(item, next, &list->head) {
3838 list_del(item);
3839 kfree(list_entry(item, struct purex_item, list));
3840 }
3841 spin_unlock_irqrestore(&list->lock, flags);
3842 }
3843
3844 static void
qla2x00_free_device(scsi_qla_host_t * vha)3845 qla2x00_free_device(scsi_qla_host_t *vha)
3846 {
3847 struct qla_hw_data *ha = vha->hw;
3848
3849 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3850
3851 /* Disable timer */
3852 if (vha->timer_active)
3853 qla2x00_stop_timer(vha);
3854
3855 qla25xx_delete_queues(vha);
3856 vha->flags.online = 0;
3857
3858 /* turn-off interrupts on the card */
3859 if (ha->interrupts_on) {
3860 vha->flags.init_done = 0;
3861 ha->isp_ops->disable_intrs(ha);
3862 }
3863
3864 qla2x00_free_fcports(vha);
3865
3866 qla2x00_free_irqs(vha);
3867
3868 /* Flush the work queue and remove it */
3869 if (ha->wq) {
3870 flush_workqueue(ha->wq);
3871 destroy_workqueue(ha->wq);
3872 ha->wq = NULL;
3873 }
3874
3875
3876 qla24xx_free_purex_list(&vha->purex_list);
3877
3878 qla2x00_mem_free(ha);
3879
3880 qla82xx_md_free(vha);
3881
3882 qla2x00_free_queues(ha);
3883 }
3884
qla2x00_free_fcports(struct scsi_qla_host * vha)3885 void qla2x00_free_fcports(struct scsi_qla_host *vha)
3886 {
3887 fc_port_t *fcport, *tfcport;
3888
3889 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list)
3890 qla2x00_free_fcport(fcport);
3891 }
3892
3893 static inline void
qla2x00_schedule_rport_del(struct scsi_qla_host * vha,fc_port_t * fcport)3894 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport)
3895 {
3896 int now;
3897
3898 if (!fcport->rport)
3899 return;
3900
3901 if (fcport->rport) {
3902 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3903 "%s %8phN. rport %p roles %x\n",
3904 __func__, fcport->port_name, fcport->rport,
3905 fcport->rport->roles);
3906 fc_remote_port_delete(fcport->rport);
3907 }
3908 qlt_do_generation_tick(vha, &now);
3909 }
3910
3911 /*
3912 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3913 *
3914 * Input: ha = adapter block pointer. fcport = port structure pointer.
3915 *
3916 * Return: None.
3917 *
3918 * Context:
3919 */
qla2x00_mark_device_lost(scsi_qla_host_t * vha,fc_port_t * fcport,int do_login)3920 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
3921 int do_login)
3922 {
3923 if (IS_QLAFX00(vha->hw)) {
3924 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3925 qla2x00_schedule_rport_del(vha, fcport);
3926 return;
3927 }
3928
3929 if (atomic_read(&fcport->state) == FCS_ONLINE &&
3930 vha->vp_idx == fcport->vha->vp_idx) {
3931 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3932 qla2x00_schedule_rport_del(vha, fcport);
3933 }
3934 /*
3935 * We may need to retry the login, so don't change the state of the
3936 * port but do the retries.
3937 */
3938 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
3939 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3940
3941 if (!do_login)
3942 return;
3943
3944 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3945 }
3946
3947 void
qla2x00_mark_all_devices_lost(scsi_qla_host_t * vha)3948 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha)
3949 {
3950 fc_port_t *fcport;
3951
3952 ql_dbg(ql_dbg_disc, vha, 0x20f1,
3953 "Mark all dev lost\n");
3954
3955 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3956 fcport->scan_state = 0;
3957 qlt_schedule_sess_for_deletion(fcport);
3958 }
3959 }
3960
qla2x00_set_reserved_loop_ids(struct qla_hw_data * ha)3961 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha)
3962 {
3963 int i;
3964
3965 if (IS_FWI2_CAPABLE(ha))
3966 return;
3967
3968 for (i = 0; i < SNS_FIRST_LOOP_ID; i++)
3969 set_bit(i, ha->loop_id_map);
3970 set_bit(MANAGEMENT_SERVER, ha->loop_id_map);
3971 set_bit(BROADCAST, ha->loop_id_map);
3972 }
3973
3974 /*
3975 * qla2x00_mem_alloc
3976 * Allocates adapter memory.
3977 *
3978 * Returns:
3979 * 0 = success.
3980 * !0 = failure.
3981 */
3982 static int
qla2x00_mem_alloc(struct qla_hw_data * ha,uint16_t req_len,uint16_t rsp_len,struct req_que ** req,struct rsp_que ** rsp)3983 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3984 struct req_que **req, struct rsp_que **rsp)
3985 {
3986 char name[16];
3987
3988 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
3989 &ha->init_cb_dma, GFP_KERNEL);
3990 if (!ha->init_cb)
3991 goto fail;
3992
3993 if (qlt_mem_alloc(ha) < 0)
3994 goto fail_free_init_cb;
3995
3996 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3997 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
3998 if (!ha->gid_list)
3999 goto fail_free_tgt_mem;
4000
4001 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
4002 if (!ha->srb_mempool)
4003 goto fail_free_gid_list;
4004
4005 if (IS_P3P_TYPE(ha)) {
4006 /* Allocate cache for CT6 Ctx. */
4007 if (!ctx_cachep) {
4008 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
4009 sizeof(struct ct6_dsd), 0,
4010 SLAB_HWCACHE_ALIGN, NULL);
4011 if (!ctx_cachep)
4012 goto fail_free_srb_mempool;
4013 }
4014 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
4015 ctx_cachep);
4016 if (!ha->ctx_mempool)
4017 goto fail_free_srb_mempool;
4018 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
4019 "ctx_cachep=%p ctx_mempool=%p.\n",
4020 ctx_cachep, ha->ctx_mempool);
4021 }
4022
4023 /* Get memory for cached NVRAM */
4024 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
4025 if (!ha->nvram)
4026 goto fail_free_ctx_mempool;
4027
4028 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
4029 ha->pdev->device);
4030 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4031 DMA_POOL_SIZE, 8, 0);
4032 if (!ha->s_dma_pool)
4033 goto fail_free_nvram;
4034
4035 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
4036 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
4037 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
4038
4039 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
4040 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4041 DSD_LIST_DMA_POOL_SIZE, 8, 0);
4042 if (!ha->dl_dma_pool) {
4043 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
4044 "Failed to allocate memory for dl_dma_pool.\n");
4045 goto fail_s_dma_pool;
4046 }
4047
4048 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4049 FCP_CMND_DMA_POOL_SIZE, 8, 0);
4050 if (!ha->fcp_cmnd_dma_pool) {
4051 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
4052 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
4053 goto fail_dl_dma_pool;
4054 }
4055
4056 if (ql2xenabledif) {
4057 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE;
4058 struct dsd_dma *dsd, *nxt;
4059 uint i;
4060 /* Creata a DMA pool of buffers for DIF bundling */
4061 ha->dif_bundl_pool = dma_pool_create(name,
4062 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0);
4063 if (!ha->dif_bundl_pool) {
4064 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4065 "%s: failed create dif_bundl_pool\n",
4066 __func__);
4067 goto fail_dif_bundl_dma_pool;
4068 }
4069
4070 INIT_LIST_HEAD(&ha->pool.good.head);
4071 INIT_LIST_HEAD(&ha->pool.unusable.head);
4072 ha->pool.good.count = 0;
4073 ha->pool.unusable.count = 0;
4074 for (i = 0; i < 128; i++) {
4075 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC);
4076 if (!dsd) {
4077 ql_dbg_pci(ql_dbg_init, ha->pdev,
4078 0xe0ee, "%s: failed alloc dsd\n",
4079 __func__);
4080 return 1;
4081 }
4082 ha->dif_bundle_kallocs++;
4083
4084 dsd->dsd_addr = dma_pool_alloc(
4085 ha->dif_bundl_pool, GFP_ATOMIC,
4086 &dsd->dsd_list_dma);
4087 if (!dsd->dsd_addr) {
4088 ql_dbg_pci(ql_dbg_init, ha->pdev,
4089 0xe0ee,
4090 "%s: failed alloc ->dsd_addr\n",
4091 __func__);
4092 kfree(dsd);
4093 ha->dif_bundle_kallocs--;
4094 continue;
4095 }
4096 ha->dif_bundle_dma_allocs++;
4097
4098 /*
4099 * if DMA buffer crosses 4G boundary,
4100 * put it on bad list
4101 */
4102 if (MSD(dsd->dsd_list_dma) ^
4103 MSD(dsd->dsd_list_dma + bufsize)) {
4104 list_add_tail(&dsd->list,
4105 &ha->pool.unusable.head);
4106 ha->pool.unusable.count++;
4107 } else {
4108 list_add_tail(&dsd->list,
4109 &ha->pool.good.head);
4110 ha->pool.good.count++;
4111 }
4112 }
4113
4114 /* return the good ones back to the pool */
4115 list_for_each_entry_safe(dsd, nxt,
4116 &ha->pool.good.head, list) {
4117 list_del(&dsd->list);
4118 dma_pool_free(ha->dif_bundl_pool,
4119 dsd->dsd_addr, dsd->dsd_list_dma);
4120 ha->dif_bundle_dma_allocs--;
4121 kfree(dsd);
4122 ha->dif_bundle_kallocs--;
4123 }
4124
4125 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4126 "%s: dif dma pool (good=%u unusable=%u)\n",
4127 __func__, ha->pool.good.count,
4128 ha->pool.unusable.count);
4129 }
4130
4131 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
4132 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n",
4133 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool,
4134 ha->dif_bundl_pool);
4135 }
4136
4137 /* Allocate memory for SNS commands */
4138 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
4139 /* Get consistent memory allocated for SNS commands */
4140 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
4141 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
4142 if (!ha->sns_cmd)
4143 goto fail_dma_pool;
4144 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
4145 "sns_cmd: %p.\n", ha->sns_cmd);
4146 } else {
4147 /* Get consistent memory allocated for MS IOCB */
4148 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4149 &ha->ms_iocb_dma);
4150 if (!ha->ms_iocb)
4151 goto fail_dma_pool;
4152 /* Get consistent memory allocated for CT SNS commands */
4153 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
4154 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
4155 if (!ha->ct_sns)
4156 goto fail_free_ms_iocb;
4157 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
4158 "ms_iocb=%p ct_sns=%p.\n",
4159 ha->ms_iocb, ha->ct_sns);
4160 }
4161
4162 /* Allocate memory for request ring */
4163 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
4164 if (!*req) {
4165 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4166 "Failed to allocate memory for req.\n");
4167 goto fail_req;
4168 }
4169 (*req)->length = req_len;
4170 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4171 ((*req)->length + 1) * sizeof(request_t),
4172 &(*req)->dma, GFP_KERNEL);
4173 if (!(*req)->ring) {
4174 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4175 "Failed to allocate memory for req_ring.\n");
4176 goto fail_req_ring;
4177 }
4178 /* Allocate memory for response ring */
4179 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4180 if (!*rsp) {
4181 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4182 "Failed to allocate memory for rsp.\n");
4183 goto fail_rsp;
4184 }
4185 (*rsp)->hw = ha;
4186 (*rsp)->length = rsp_len;
4187 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4188 ((*rsp)->length + 1) * sizeof(response_t),
4189 &(*rsp)->dma, GFP_KERNEL);
4190 if (!(*rsp)->ring) {
4191 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4192 "Failed to allocate memory for rsp_ring.\n");
4193 goto fail_rsp_ring;
4194 }
4195 (*req)->rsp = *rsp;
4196 (*rsp)->req = *req;
4197 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4198 "req=%p req->length=%d req->ring=%p rsp=%p "
4199 "rsp->length=%d rsp->ring=%p.\n",
4200 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4201 (*rsp)->ring);
4202 /* Allocate memory for NVRAM data for vports */
4203 if (ha->nvram_npiv_size) {
4204 ha->npiv_info = kcalloc(ha->nvram_npiv_size,
4205 sizeof(struct qla_npiv_entry),
4206 GFP_KERNEL);
4207 if (!ha->npiv_info) {
4208 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4209 "Failed to allocate memory for npiv_info.\n");
4210 goto fail_npiv_info;
4211 }
4212 } else
4213 ha->npiv_info = NULL;
4214
4215 /* Get consistent memory allocated for EX-INIT-CB. */
4216 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
4217 IS_QLA28XX(ha)) {
4218 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4219 &ha->ex_init_cb_dma);
4220 if (!ha->ex_init_cb)
4221 goto fail_ex_init_cb;
4222 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4223 "ex_init_cb=%p.\n", ha->ex_init_cb);
4224 }
4225
4226 /* Get consistent memory allocated for Special Features-CB. */
4227 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
4228 ha->sf_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4229 &ha->sf_init_cb_dma);
4230 if (!ha->sf_init_cb)
4231 goto fail_sf_init_cb;
4232 memset(ha->sf_init_cb, 0, sizeof(struct init_sf_cb));
4233 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199,
4234 "sf_init_cb=%p.\n", ha->sf_init_cb);
4235 }
4236
4237 INIT_LIST_HEAD(&ha->gbl_dsd_list);
4238
4239 /* Get consistent memory allocated for Async Port-Database. */
4240 if (!IS_FWI2_CAPABLE(ha)) {
4241 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4242 &ha->async_pd_dma);
4243 if (!ha->async_pd)
4244 goto fail_async_pd;
4245 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4246 "async_pd=%p.\n", ha->async_pd);
4247 }
4248
4249 INIT_LIST_HEAD(&ha->vp_list);
4250
4251 /* Allocate memory for our loop_id bitmap */
4252 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
4253 sizeof(long),
4254 GFP_KERNEL);
4255 if (!ha->loop_id_map)
4256 goto fail_loop_id_map;
4257 else {
4258 qla2x00_set_reserved_loop_ids(ha);
4259 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
4260 "loop_id_map=%p.\n", ha->loop_id_map);
4261 }
4262
4263 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4264 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4265 if (!ha->sfp_data) {
4266 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4267 "Unable to allocate memory for SFP read-data.\n");
4268 goto fail_sfp_data;
4269 }
4270
4271 ha->flt = dma_alloc_coherent(&ha->pdev->dev,
4272 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma,
4273 GFP_KERNEL);
4274 if (!ha->flt) {
4275 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4276 "Unable to allocate memory for FLT.\n");
4277 goto fail_flt_buffer;
4278 }
4279
4280 return 0;
4281
4282 fail_flt_buffer:
4283 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4284 ha->sfp_data, ha->sfp_data_dma);
4285 fail_sfp_data:
4286 kfree(ha->loop_id_map);
4287 fail_loop_id_map:
4288 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4289 fail_async_pd:
4290 dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma);
4291 fail_sf_init_cb:
4292 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
4293 fail_ex_init_cb:
4294 kfree(ha->npiv_info);
4295 fail_npiv_info:
4296 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4297 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4298 (*rsp)->ring = NULL;
4299 (*rsp)->dma = 0;
4300 fail_rsp_ring:
4301 kfree(*rsp);
4302 *rsp = NULL;
4303 fail_rsp:
4304 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4305 sizeof(request_t), (*req)->ring, (*req)->dma);
4306 (*req)->ring = NULL;
4307 (*req)->dma = 0;
4308 fail_req_ring:
4309 kfree(*req);
4310 *req = NULL;
4311 fail_req:
4312 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4313 ha->ct_sns, ha->ct_sns_dma);
4314 ha->ct_sns = NULL;
4315 ha->ct_sns_dma = 0;
4316 fail_free_ms_iocb:
4317 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4318 ha->ms_iocb = NULL;
4319 ha->ms_iocb_dma = 0;
4320
4321 if (ha->sns_cmd)
4322 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4323 ha->sns_cmd, ha->sns_cmd_dma);
4324 fail_dma_pool:
4325 if (ql2xenabledif) {
4326 struct dsd_dma *dsd, *nxt;
4327
4328 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4329 list) {
4330 list_del(&dsd->list);
4331 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4332 dsd->dsd_list_dma);
4333 ha->dif_bundle_dma_allocs--;
4334 kfree(dsd);
4335 ha->dif_bundle_kallocs--;
4336 ha->pool.unusable.count--;
4337 }
4338 dma_pool_destroy(ha->dif_bundl_pool);
4339 ha->dif_bundl_pool = NULL;
4340 }
4341
4342 fail_dif_bundl_dma_pool:
4343 if (IS_QLA82XX(ha) || ql2xenabledif) {
4344 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4345 ha->fcp_cmnd_dma_pool = NULL;
4346 }
4347 fail_dl_dma_pool:
4348 if (IS_QLA82XX(ha) || ql2xenabledif) {
4349 dma_pool_destroy(ha->dl_dma_pool);
4350 ha->dl_dma_pool = NULL;
4351 }
4352 fail_s_dma_pool:
4353 dma_pool_destroy(ha->s_dma_pool);
4354 ha->s_dma_pool = NULL;
4355 fail_free_nvram:
4356 kfree(ha->nvram);
4357 ha->nvram = NULL;
4358 fail_free_ctx_mempool:
4359 mempool_destroy(ha->ctx_mempool);
4360 ha->ctx_mempool = NULL;
4361 fail_free_srb_mempool:
4362 mempool_destroy(ha->srb_mempool);
4363 ha->srb_mempool = NULL;
4364 fail_free_gid_list:
4365 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4366 ha->gid_list,
4367 ha->gid_list_dma);
4368 ha->gid_list = NULL;
4369 ha->gid_list_dma = 0;
4370 fail_free_tgt_mem:
4371 qlt_mem_free(ha);
4372 fail_free_init_cb:
4373 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4374 ha->init_cb_dma);
4375 ha->init_cb = NULL;
4376 ha->init_cb_dma = 0;
4377 fail:
4378 ql_log(ql_log_fatal, NULL, 0x0030,
4379 "Memory allocation failure.\n");
4380 return -ENOMEM;
4381 }
4382
4383 int
qla2x00_set_exlogins_buffer(scsi_qla_host_t * vha)4384 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4385 {
4386 int rval;
4387 uint16_t size, max_cnt;
4388 uint32_t temp;
4389 struct qla_hw_data *ha = vha->hw;
4390
4391 /* Return if we don't need to alloacate any extended logins */
4392 if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400)
4393 return QLA_SUCCESS;
4394
4395 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4396 return QLA_SUCCESS;
4397
4398 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4399 max_cnt = 0;
4400 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4401 if (rval != QLA_SUCCESS) {
4402 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4403 "Failed to get exlogin status.\n");
4404 return rval;
4405 }
4406
4407 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
4408 temp *= size;
4409
4410 if (temp != ha->exlogin_size) {
4411 qla2x00_free_exlogin_buffer(ha);
4412 ha->exlogin_size = temp;
4413
4414 ql_log(ql_log_info, vha, 0xd024,
4415 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4416 max_cnt, size, temp);
4417
4418 ql_log(ql_log_info, vha, 0xd025,
4419 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4420
4421 /* Get consistent memory for extended logins */
4422 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4423 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4424 if (!ha->exlogin_buf) {
4425 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
4426 "Failed to allocate memory for exlogin_buf_dma.\n");
4427 return -ENOMEM;
4428 }
4429 }
4430
4431 /* Now configure the dma buffer */
4432 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4433 if (rval) {
4434 ql_log(ql_log_fatal, vha, 0xd033,
4435 "Setup extended login buffer ****FAILED****.\n");
4436 qla2x00_free_exlogin_buffer(ha);
4437 }
4438
4439 return rval;
4440 }
4441
4442 /*
4443 * qla2x00_free_exlogin_buffer
4444 *
4445 * Input:
4446 * ha = adapter block pointer
4447 */
4448 void
qla2x00_free_exlogin_buffer(struct qla_hw_data * ha)4449 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4450 {
4451 if (ha->exlogin_buf) {
4452 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4453 ha->exlogin_buf, ha->exlogin_buf_dma);
4454 ha->exlogin_buf = NULL;
4455 ha->exlogin_size = 0;
4456 }
4457 }
4458
4459 static void
qla2x00_number_of_exch(scsi_qla_host_t * vha,u32 * ret_cnt,u16 max_cnt)4460 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4461 {
4462 u32 temp;
4463 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb;
4464 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4465
4466 if (max_cnt > vha->hw->max_exchg)
4467 max_cnt = vha->hw->max_exchg;
4468
4469 if (qla_ini_mode_enabled(vha)) {
4470 if (vha->ql2xiniexchg > max_cnt)
4471 vha->ql2xiniexchg = max_cnt;
4472
4473 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4474 *ret_cnt = vha->ql2xiniexchg;
4475
4476 } else if (qla_tgt_mode_enabled(vha)) {
4477 if (vha->ql2xexchoffld > max_cnt) {
4478 vha->ql2xexchoffld = max_cnt;
4479 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4480 }
4481
4482 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4483 *ret_cnt = vha->ql2xexchoffld;
4484 } else if (qla_dual_mode_enabled(vha)) {
4485 temp = vha->ql2xiniexchg + vha->ql2xexchoffld;
4486 if (temp > max_cnt) {
4487 vha->ql2xiniexchg -= (temp - max_cnt)/2;
4488 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4489 temp = max_cnt;
4490 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4491 }
4492
4493 if (temp > FW_DEF_EXCHANGES_CNT)
4494 *ret_cnt = temp;
4495 }
4496 }
4497
4498 int
qla2x00_set_exchoffld_buffer(scsi_qla_host_t * vha)4499 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4500 {
4501 int rval;
4502 u16 size, max_cnt;
4503 u32 actual_cnt, totsz;
4504 struct qla_hw_data *ha = vha->hw;
4505
4506 if (!ha->flags.exchoffld_enabled)
4507 return QLA_SUCCESS;
4508
4509 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
4510 return QLA_SUCCESS;
4511
4512 max_cnt = 0;
4513 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4514 if (rval != QLA_SUCCESS) {
4515 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4516 "Failed to get exlogin status.\n");
4517 return rval;
4518 }
4519
4520 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4521 ql_log(ql_log_info, vha, 0xd014,
4522 "Actual exchange offload count: %d.\n", actual_cnt);
4523
4524 totsz = actual_cnt * size;
4525
4526 if (totsz != ha->exchoffld_size) {
4527 qla2x00_free_exchoffld_buffer(ha);
4528 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) {
4529 ha->exchoffld_size = 0;
4530 ha->flags.exchoffld_enabled = 0;
4531 return QLA_SUCCESS;
4532 }
4533
4534 ha->exchoffld_size = totsz;
4535
4536 ql_log(ql_log_info, vha, 0xd016,
4537 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4538 max_cnt, actual_cnt, size, totsz);
4539
4540 ql_log(ql_log_info, vha, 0xd017,
4541 "Exchange Buffers requested size = 0x%x\n",
4542 ha->exchoffld_size);
4543
4544 /* Get consistent memory for extended logins */
4545 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4546 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4547 if (!ha->exchoffld_buf) {
4548 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4549 "Failed to allocate memory for Exchange Offload.\n");
4550
4551 if (ha->max_exchg >
4552 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4553 ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4554 } else if (ha->max_exchg >
4555 (FW_DEF_EXCHANGES_CNT + 512)) {
4556 ha->max_exchg -= 512;
4557 } else {
4558 ha->flags.exchoffld_enabled = 0;
4559 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4560 "Disabling Exchange offload due to lack of memory\n");
4561 }
4562 ha->exchoffld_size = 0;
4563
4564 return -ENOMEM;
4565 }
4566 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) {
4567 /* pathological case */
4568 qla2x00_free_exchoffld_buffer(ha);
4569 ha->exchoffld_size = 0;
4570 ha->flags.exchoffld_enabled = 0;
4571 ql_log(ql_log_info, vha, 0xd016,
4572 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n",
4573 ha->exchoffld_size, actual_cnt, size, totsz);
4574 return 0;
4575 }
4576
4577 /* Now configure the dma buffer */
4578 rval = qla_set_exchoffld_mem_cfg(vha);
4579 if (rval) {
4580 ql_log(ql_log_fatal, vha, 0xd02e,
4581 "Setup exchange offload buffer ****FAILED****.\n");
4582 qla2x00_free_exchoffld_buffer(ha);
4583 } else {
4584 /* re-adjust number of target exchange */
4585 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4586
4587 if (qla_ini_mode_enabled(vha))
4588 icb->exchange_count = 0;
4589 else
4590 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4591 }
4592
4593 return rval;
4594 }
4595
4596 /*
4597 * qla2x00_free_exchoffld_buffer
4598 *
4599 * Input:
4600 * ha = adapter block pointer
4601 */
4602 void
qla2x00_free_exchoffld_buffer(struct qla_hw_data * ha)4603 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4604 {
4605 if (ha->exchoffld_buf) {
4606 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4607 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4608 ha->exchoffld_buf = NULL;
4609 ha->exchoffld_size = 0;
4610 }
4611 }
4612
4613 /*
4614 * qla2x00_free_fw_dump
4615 * Frees fw dump stuff.
4616 *
4617 * Input:
4618 * ha = adapter block pointer
4619 */
4620 static void
qla2x00_free_fw_dump(struct qla_hw_data * ha)4621 qla2x00_free_fw_dump(struct qla_hw_data *ha)
4622 {
4623 struct fwdt *fwdt = ha->fwdt;
4624 uint j;
4625
4626 if (ha->fce)
4627 dma_free_coherent(&ha->pdev->dev,
4628 FCE_SIZE, ha->fce, ha->fce_dma);
4629
4630 if (ha->eft)
4631 dma_free_coherent(&ha->pdev->dev,
4632 EFT_SIZE, ha->eft, ha->eft_dma);
4633
4634 if (ha->fw_dump)
4635 vfree(ha->fw_dump);
4636
4637 ha->fce = NULL;
4638 ha->fce_dma = 0;
4639 ha->flags.fce_enabled = 0;
4640 ha->eft = NULL;
4641 ha->eft_dma = 0;
4642 ha->fw_dumped = false;
4643 ha->fw_dump_cap_flags = 0;
4644 ha->fw_dump_reading = 0;
4645 ha->fw_dump = NULL;
4646 ha->fw_dump_len = 0;
4647
4648 for (j = 0; j < 2; j++, fwdt++) {
4649 if (fwdt->template)
4650 vfree(fwdt->template);
4651 fwdt->template = NULL;
4652 fwdt->length = 0;
4653 }
4654 }
4655
4656 /*
4657 * qla2x00_mem_free
4658 * Frees all adapter allocated memory.
4659 *
4660 * Input:
4661 * ha = adapter block pointer.
4662 */
4663 static void
qla2x00_mem_free(struct qla_hw_data * ha)4664 qla2x00_mem_free(struct qla_hw_data *ha)
4665 {
4666 qla2x00_free_fw_dump(ha);
4667
4668 if (ha->mctp_dump)
4669 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4670 ha->mctp_dump_dma);
4671 ha->mctp_dump = NULL;
4672
4673 mempool_destroy(ha->srb_mempool);
4674 ha->srb_mempool = NULL;
4675
4676 if (ha->dcbx_tlv)
4677 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4678 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4679 ha->dcbx_tlv = NULL;
4680
4681 if (ha->xgmac_data)
4682 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4683 ha->xgmac_data, ha->xgmac_data_dma);
4684 ha->xgmac_data = NULL;
4685
4686 if (ha->sns_cmd)
4687 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4688 ha->sns_cmd, ha->sns_cmd_dma);
4689 ha->sns_cmd = NULL;
4690 ha->sns_cmd_dma = 0;
4691
4692 if (ha->ct_sns)
4693 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4694 ha->ct_sns, ha->ct_sns_dma);
4695 ha->ct_sns = NULL;
4696 ha->ct_sns_dma = 0;
4697
4698 if (ha->sfp_data)
4699 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4700 ha->sfp_data_dma);
4701 ha->sfp_data = NULL;
4702
4703 if (ha->flt)
4704 dma_free_coherent(&ha->pdev->dev,
4705 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE,
4706 ha->flt, ha->flt_dma);
4707 ha->flt = NULL;
4708 ha->flt_dma = 0;
4709
4710 if (ha->ms_iocb)
4711 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4712 ha->ms_iocb = NULL;
4713 ha->ms_iocb_dma = 0;
4714
4715 if (ha->sf_init_cb)
4716 dma_pool_free(ha->s_dma_pool,
4717 ha->sf_init_cb, ha->sf_init_cb_dma);
4718
4719 if (ha->ex_init_cb)
4720 dma_pool_free(ha->s_dma_pool,
4721 ha->ex_init_cb, ha->ex_init_cb_dma);
4722 ha->ex_init_cb = NULL;
4723 ha->ex_init_cb_dma = 0;
4724
4725 if (ha->async_pd)
4726 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4727 ha->async_pd = NULL;
4728 ha->async_pd_dma = 0;
4729
4730 dma_pool_destroy(ha->s_dma_pool);
4731 ha->s_dma_pool = NULL;
4732
4733 if (ha->gid_list)
4734 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4735 ha->gid_list, ha->gid_list_dma);
4736 ha->gid_list = NULL;
4737 ha->gid_list_dma = 0;
4738
4739 if (IS_QLA82XX(ha)) {
4740 if (!list_empty(&ha->gbl_dsd_list)) {
4741 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4742
4743 /* clean up allocated prev pool */
4744 list_for_each_entry_safe(dsd_ptr,
4745 tdsd_ptr, &ha->gbl_dsd_list, list) {
4746 dma_pool_free(ha->dl_dma_pool,
4747 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4748 list_del(&dsd_ptr->list);
4749 kfree(dsd_ptr);
4750 }
4751 }
4752 }
4753
4754 dma_pool_destroy(ha->dl_dma_pool);
4755 ha->dl_dma_pool = NULL;
4756
4757 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4758 ha->fcp_cmnd_dma_pool = NULL;
4759
4760 mempool_destroy(ha->ctx_mempool);
4761 ha->ctx_mempool = NULL;
4762
4763 if (ql2xenabledif && ha->dif_bundl_pool) {
4764 struct dsd_dma *dsd, *nxt;
4765
4766 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4767 list) {
4768 list_del(&dsd->list);
4769 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4770 dsd->dsd_list_dma);
4771 ha->dif_bundle_dma_allocs--;
4772 kfree(dsd);
4773 ha->dif_bundle_kallocs--;
4774 ha->pool.unusable.count--;
4775 }
4776 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) {
4777 list_del(&dsd->list);
4778 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4779 dsd->dsd_list_dma);
4780 ha->dif_bundle_dma_allocs--;
4781 kfree(dsd);
4782 ha->dif_bundle_kallocs--;
4783 }
4784 }
4785
4786 dma_pool_destroy(ha->dif_bundl_pool);
4787 ha->dif_bundl_pool = NULL;
4788
4789 qlt_mem_free(ha);
4790
4791 if (ha->init_cb)
4792 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
4793 ha->init_cb, ha->init_cb_dma);
4794 ha->init_cb = NULL;
4795 ha->init_cb_dma = 0;
4796
4797 vfree(ha->optrom_buffer);
4798 ha->optrom_buffer = NULL;
4799 kfree(ha->nvram);
4800 ha->nvram = NULL;
4801 kfree(ha->npiv_info);
4802 ha->npiv_info = NULL;
4803 kfree(ha->swl);
4804 ha->swl = NULL;
4805 kfree(ha->loop_id_map);
4806 ha->sf_init_cb = NULL;
4807 ha->sf_init_cb_dma = 0;
4808 ha->loop_id_map = NULL;
4809 }
4810
qla2x00_create_host(struct scsi_host_template * sht,struct qla_hw_data * ha)4811 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4812 struct qla_hw_data *ha)
4813 {
4814 struct Scsi_Host *host;
4815 struct scsi_qla_host *vha = NULL;
4816
4817 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
4818 if (!host) {
4819 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4820 "Failed to allocate host from the scsi layer, aborting.\n");
4821 return NULL;
4822 }
4823
4824 /* Clear our data area */
4825 vha = shost_priv(host);
4826 memset(vha, 0, sizeof(scsi_qla_host_t));
4827
4828 vha->host = host;
4829 vha->host_no = host->host_no;
4830 vha->hw = ha;
4831
4832 vha->qlini_mode = ql2x_ini_mode;
4833 vha->ql2xexchoffld = ql2xexchoffld;
4834 vha->ql2xiniexchg = ql2xiniexchg;
4835
4836 INIT_LIST_HEAD(&vha->vp_fcports);
4837 INIT_LIST_HEAD(&vha->work_list);
4838 INIT_LIST_HEAD(&vha->list);
4839 INIT_LIST_HEAD(&vha->qla_cmd_list);
4840 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
4841 INIT_LIST_HEAD(&vha->logo_list);
4842 INIT_LIST_HEAD(&vha->plogi_ack_list);
4843 INIT_LIST_HEAD(&vha->qp_list);
4844 INIT_LIST_HEAD(&vha->gnl.fcports);
4845 INIT_LIST_HEAD(&vha->gpnid_list);
4846 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
4847
4848 INIT_LIST_HEAD(&vha->purex_list.head);
4849 spin_lock_init(&vha->purex_list.lock);
4850
4851 spin_lock_init(&vha->work_lock);
4852 spin_lock_init(&vha->cmd_list_lock);
4853 init_waitqueue_head(&vha->fcport_waitQ);
4854 init_waitqueue_head(&vha->vref_waitq);
4855
4856 vha->gnl.size = sizeof(struct get_name_list_extended) *
4857 (ha->max_loop_id + 1);
4858 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4859 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4860 if (!vha->gnl.l) {
4861 ql_log(ql_log_fatal, vha, 0xd04a,
4862 "Alloc failed for name list.\n");
4863 scsi_host_put(vha->host);
4864 return NULL;
4865 }
4866
4867 /* todo: what about ext login? */
4868 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
4869 vha->scan.l = vmalloc(vha->scan.size);
4870 if (!vha->scan.l) {
4871 ql_log(ql_log_fatal, vha, 0xd04a,
4872 "Alloc failed for scan database.\n");
4873 dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
4874 vha->gnl.l, vha->gnl.ldma);
4875 vha->gnl.l = NULL;
4876 scsi_host_put(vha->host);
4877 return NULL;
4878 }
4879 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
4880
4881 sprintf(vha->host_str, "%s_%lu", QLA2XXX_DRIVER_NAME, vha->host_no);
4882 ql_dbg(ql_dbg_init, vha, 0x0041,
4883 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4884 vha->host, vha->hw, vha,
4885 dev_name(&(ha->pdev->dev)));
4886
4887 return vha;
4888 }
4889
4890 struct qla_work_evt *
qla2x00_alloc_work(struct scsi_qla_host * vha,enum qla_work_type type)4891 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
4892 {
4893 struct qla_work_evt *e;
4894 uint8_t bail;
4895
4896 if (test_bit(UNLOADING, &vha->dpc_flags))
4897 return NULL;
4898
4899 QLA_VHA_MARK_BUSY(vha, bail);
4900 if (bail)
4901 return NULL;
4902
4903 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
4904 if (!e) {
4905 QLA_VHA_MARK_NOT_BUSY(vha);
4906 return NULL;
4907 }
4908
4909 INIT_LIST_HEAD(&e->list);
4910 e->type = type;
4911 e->flags = QLA_EVT_FLAG_FREE;
4912 return e;
4913 }
4914
4915 int
qla2x00_post_work(struct scsi_qla_host * vha,struct qla_work_evt * e)4916 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
4917 {
4918 unsigned long flags;
4919 bool q = false;
4920
4921 spin_lock_irqsave(&vha->work_lock, flags);
4922 list_add_tail(&e->list, &vha->work_list);
4923
4924 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
4925 q = true;
4926
4927 spin_unlock_irqrestore(&vha->work_lock, flags);
4928
4929 if (q)
4930 queue_work(vha->hw->wq, &vha->iocb_work);
4931
4932 return QLA_SUCCESS;
4933 }
4934
4935 int
qla2x00_post_aen_work(struct scsi_qla_host * vha,enum fc_host_event_code code,u32 data)4936 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
4937 u32 data)
4938 {
4939 struct qla_work_evt *e;
4940
4941 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
4942 if (!e)
4943 return QLA_FUNCTION_FAILED;
4944
4945 e->u.aen.code = code;
4946 e->u.aen.data = data;
4947 return qla2x00_post_work(vha, e);
4948 }
4949
4950 int
qla2x00_post_idc_ack_work(struct scsi_qla_host * vha,uint16_t * mb)4951 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4952 {
4953 struct qla_work_evt *e;
4954
4955 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
4956 if (!e)
4957 return QLA_FUNCTION_FAILED;
4958
4959 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
4960 return qla2x00_post_work(vha, e);
4961 }
4962
4963 #define qla2x00_post_async_work(name, type) \
4964 int qla2x00_post_async_##name##_work( \
4965 struct scsi_qla_host *vha, \
4966 fc_port_t *fcport, uint16_t *data) \
4967 { \
4968 struct qla_work_evt *e; \
4969 \
4970 e = qla2x00_alloc_work(vha, type); \
4971 if (!e) \
4972 return QLA_FUNCTION_FAILED; \
4973 \
4974 e->u.logio.fcport = fcport; \
4975 if (data) { \
4976 e->u.logio.data[0] = data[0]; \
4977 e->u.logio.data[1] = data[1]; \
4978 } \
4979 fcport->flags |= FCF_ASYNC_ACTIVE; \
4980 return qla2x00_post_work(vha, e); \
4981 }
4982
4983 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
4984 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4985 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4986 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
4987 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
4988
4989 int
qla2x00_post_uevent_work(struct scsi_qla_host * vha,u32 code)4990 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4991 {
4992 struct qla_work_evt *e;
4993
4994 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4995 if (!e)
4996 return QLA_FUNCTION_FAILED;
4997
4998 e->u.uevent.code = code;
4999 return qla2x00_post_work(vha, e);
5000 }
5001
5002 static void
qla2x00_uevent_emit(struct scsi_qla_host * vha,u32 code)5003 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
5004 {
5005 char event_string[40];
5006 char *envp[] = { event_string, NULL };
5007
5008 switch (code) {
5009 case QLA_UEVENT_CODE_FW_DUMP:
5010 snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu",
5011 vha->host_no);
5012 break;
5013 default:
5014 /* do nothing */
5015 break;
5016 }
5017 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
5018 }
5019
5020 int
qlafx00_post_aenfx_work(struct scsi_qla_host * vha,uint32_t evtcode,uint32_t * data,int cnt)5021 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
5022 uint32_t *data, int cnt)
5023 {
5024 struct qla_work_evt *e;
5025
5026 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
5027 if (!e)
5028 return QLA_FUNCTION_FAILED;
5029
5030 e->u.aenfx.evtcode = evtcode;
5031 e->u.aenfx.count = cnt;
5032 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
5033 return qla2x00_post_work(vha, e);
5034 }
5035
qla24xx_sched_upd_fcport(fc_port_t * fcport)5036 void qla24xx_sched_upd_fcport(fc_port_t *fcport)
5037 {
5038 unsigned long flags;
5039
5040 if (IS_SW_RESV_ADDR(fcport->d_id))
5041 return;
5042
5043 spin_lock_irqsave(&fcport->vha->work_lock, flags);
5044 if (fcport->disc_state == DSC_UPD_FCPORT) {
5045 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5046 return;
5047 }
5048 fcport->jiffies_at_registration = jiffies;
5049 fcport->sec_since_registration = 0;
5050 fcport->next_disc_state = DSC_DELETED;
5051 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT);
5052 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5053
5054 queue_work(system_unbound_wq, &fcport->reg_work);
5055 }
5056
5057 static
qla24xx_create_new_sess(struct scsi_qla_host * vha,struct qla_work_evt * e)5058 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
5059 {
5060 unsigned long flags;
5061 fc_port_t *fcport = NULL, *tfcp;
5062 struct qlt_plogi_ack_t *pla =
5063 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
5064 uint8_t free_fcport = 0;
5065
5066 ql_dbg(ql_dbg_disc, vha, 0xffff,
5067 "%s %d %8phC enter\n",
5068 __func__, __LINE__, e->u.new_sess.port_name);
5069
5070 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5071 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
5072 if (fcport) {
5073 fcport->d_id = e->u.new_sess.id;
5074 if (pla) {
5075 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5076 memcpy(fcport->node_name,
5077 pla->iocb.u.isp24.u.plogi.node_name,
5078 WWN_SIZE);
5079 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
5080 /* we took an extra ref_count to prevent PLOGI ACK when
5081 * fcport/sess has not been created.
5082 */
5083 pla->ref_count--;
5084 }
5085 } else {
5086 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5087 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5088 if (fcport) {
5089 fcport->d_id = e->u.new_sess.id;
5090 fcport->flags |= FCF_FABRIC_DEVICE;
5091 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5092
5093 memcpy(fcport->port_name, e->u.new_sess.port_name,
5094 WWN_SIZE);
5095
5096 fcport->fc4_type = e->u.new_sess.fc4_type;
5097 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) {
5098 fcport->dm_login_expire = jiffies +
5099 QLA_N2N_WAIT_TIME * HZ;
5100 fcport->fc4_type = FS_FC4TYPE_FCP;
5101 fcport->n2n_flag = 1;
5102 if (vha->flags.nvme_enabled)
5103 fcport->fc4_type |= FS_FC4TYPE_NVME;
5104 }
5105
5106 } else {
5107 ql_dbg(ql_dbg_disc, vha, 0xffff,
5108 "%s %8phC mem alloc fail.\n",
5109 __func__, e->u.new_sess.port_name);
5110
5111 if (pla) {
5112 list_del(&pla->list);
5113 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5114 }
5115 return;
5116 }
5117
5118 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5119 /* search again to make sure no one else got ahead */
5120 tfcp = qla2x00_find_fcport_by_wwpn(vha,
5121 e->u.new_sess.port_name, 1);
5122 if (tfcp) {
5123 /* should rarily happen */
5124 ql_dbg(ql_dbg_disc, vha, 0xffff,
5125 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
5126 __func__, tfcp->port_name, tfcp->disc_state,
5127 tfcp->fw_login_state);
5128
5129 free_fcport = 1;
5130 } else {
5131 list_add_tail(&fcport->list, &vha->vp_fcports);
5132
5133 }
5134 if (pla) {
5135 qlt_plogi_ack_link(vha, pla, fcport,
5136 QLT_PLOGI_LINK_SAME_WWN);
5137 pla->ref_count--;
5138 }
5139 }
5140 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5141
5142 if (fcport) {
5143 fcport->id_changed = 1;
5144 fcport->scan_state = QLA_FCPORT_FOUND;
5145 fcport->chip_reset = vha->hw->base_qpair->chip_reset;
5146 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
5147
5148 if (pla) {
5149 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
5150 u16 wd3_lo;
5151
5152 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5153 fcport->local = 0;
5154 fcport->loop_id =
5155 le16_to_cpu(
5156 pla->iocb.u.isp24.nport_handle);
5157 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5158 wd3_lo =
5159 le16_to_cpu(
5160 pla->iocb.u.isp24.u.prli.wd3_lo);
5161
5162 if (wd3_lo & BIT_7)
5163 fcport->conf_compl_supported = 1;
5164
5165 if ((wd3_lo & BIT_4) == 0)
5166 fcport->port_type = FCT_INITIATOR;
5167 else
5168 fcport->port_type = FCT_TARGET;
5169 }
5170 qlt_plogi_ack_unref(vha, pla);
5171 } else {
5172 fc_port_t *dfcp = NULL;
5173
5174 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5175 tfcp = qla2x00_find_fcport_by_nportid(vha,
5176 &e->u.new_sess.id, 1);
5177 if (tfcp && (tfcp != fcport)) {
5178 /*
5179 * We have a conflict fcport with same NportID.
5180 */
5181 ql_dbg(ql_dbg_disc, vha, 0xffff,
5182 "%s %8phC found conflict b4 add. DS %d LS %d\n",
5183 __func__, tfcp->port_name, tfcp->disc_state,
5184 tfcp->fw_login_state);
5185
5186 switch (tfcp->disc_state) {
5187 case DSC_DELETED:
5188 break;
5189 case DSC_DELETE_PEND:
5190 fcport->login_pause = 1;
5191 tfcp->conflict = fcport;
5192 break;
5193 default:
5194 fcport->login_pause = 1;
5195 tfcp->conflict = fcport;
5196 dfcp = tfcp;
5197 break;
5198 }
5199 }
5200 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5201 if (dfcp)
5202 qlt_schedule_sess_for_deletion(tfcp);
5203
5204 if (N2N_TOPO(vha->hw)) {
5205 fcport->flags &= ~FCF_FABRIC_DEVICE;
5206 fcport->keep_nport_handle = 1;
5207 if (vha->flags.nvme_enabled) {
5208 fcport->fc4_type =
5209 (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP);
5210 fcport->n2n_flag = 1;
5211 }
5212 fcport->fw_login_state = 0;
5213
5214 schedule_delayed_work(&vha->scan.scan_work, 5);
5215 } else {
5216 qla24xx_fcport_handle_login(vha, fcport);
5217 }
5218 }
5219 }
5220
5221 if (free_fcport) {
5222 qla2x00_free_fcport(fcport);
5223 if (pla) {
5224 list_del(&pla->list);
5225 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5226 }
5227 }
5228 }
5229
qla_sp_retry(struct scsi_qla_host * vha,struct qla_work_evt * e)5230 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
5231 {
5232 struct srb *sp = e->u.iosb.sp;
5233 int rval;
5234
5235 rval = qla2x00_start_sp(sp);
5236 if (rval != QLA_SUCCESS) {
5237 ql_dbg(ql_dbg_disc, vha, 0x2043,
5238 "%s: %s: Re-issue IOCB failed (%d).\n",
5239 __func__, sp->name, rval);
5240 qla24xx_sp_unmap(vha, sp);
5241 }
5242 }
5243
5244 void
qla2x00_do_work(struct scsi_qla_host * vha)5245 qla2x00_do_work(struct scsi_qla_host *vha)
5246 {
5247 struct qla_work_evt *e, *tmp;
5248 unsigned long flags;
5249 LIST_HEAD(work);
5250 int rc;
5251
5252 spin_lock_irqsave(&vha->work_lock, flags);
5253 list_splice_init(&vha->work_list, &work);
5254 spin_unlock_irqrestore(&vha->work_lock, flags);
5255
5256 list_for_each_entry_safe(e, tmp, &work, list) {
5257 rc = QLA_SUCCESS;
5258 switch (e->type) {
5259 case QLA_EVT_AEN:
5260 fc_host_post_event(vha->host, fc_get_event_number(),
5261 e->u.aen.code, e->u.aen.data);
5262 break;
5263 case QLA_EVT_IDC_ACK:
5264 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
5265 break;
5266 case QLA_EVT_ASYNC_LOGIN:
5267 qla2x00_async_login(vha, e->u.logio.fcport,
5268 e->u.logio.data);
5269 break;
5270 case QLA_EVT_ASYNC_LOGOUT:
5271 rc = qla2x00_async_logout(vha, e->u.logio.fcport);
5272 break;
5273 case QLA_EVT_ASYNC_ADISC:
5274 qla2x00_async_adisc(vha, e->u.logio.fcport,
5275 e->u.logio.data);
5276 break;
5277 case QLA_EVT_UEVENT:
5278 qla2x00_uevent_emit(vha, e->u.uevent.code);
5279 break;
5280 case QLA_EVT_AENFX:
5281 qlafx00_process_aen(vha, e);
5282 break;
5283 case QLA_EVT_GPNID:
5284 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
5285 break;
5286 case QLA_EVT_UNMAP:
5287 qla24xx_sp_unmap(vha, e->u.iosb.sp);
5288 break;
5289 case QLA_EVT_RELOGIN:
5290 qla2x00_relogin(vha);
5291 break;
5292 case QLA_EVT_NEW_SESS:
5293 qla24xx_create_new_sess(vha, e);
5294 break;
5295 case QLA_EVT_GPDB:
5296 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5297 e->u.fcport.opt);
5298 break;
5299 case QLA_EVT_PRLI:
5300 qla24xx_async_prli(vha, e->u.fcport.fcport);
5301 break;
5302 case QLA_EVT_GPSC:
5303 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5304 break;
5305 case QLA_EVT_GNL:
5306 qla24xx_async_gnl(vha, e->u.fcport.fcport);
5307 break;
5308 case QLA_EVT_NACK:
5309 qla24xx_do_nack_work(vha, e);
5310 break;
5311 case QLA_EVT_ASYNC_PRLO:
5312 rc = qla2x00_async_prlo(vha, e->u.logio.fcport);
5313 break;
5314 case QLA_EVT_ASYNC_PRLO_DONE:
5315 qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5316 e->u.logio.data);
5317 break;
5318 case QLA_EVT_GPNFT:
5319 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type,
5320 e->u.gpnft.sp);
5321 break;
5322 case QLA_EVT_GPNFT_DONE:
5323 qla24xx_async_gpnft_done(vha, e->u.iosb.sp);
5324 break;
5325 case QLA_EVT_GNNFT_DONE:
5326 qla24xx_async_gnnft_done(vha, e->u.iosb.sp);
5327 break;
5328 case QLA_EVT_GNNID:
5329 qla24xx_async_gnnid(vha, e->u.fcport.fcport);
5330 break;
5331 case QLA_EVT_GFPNID:
5332 qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5333 break;
5334 case QLA_EVT_SP_RETRY:
5335 qla_sp_retry(vha, e);
5336 break;
5337 case QLA_EVT_IIDMA:
5338 qla_do_iidma_work(vha, e->u.fcport.fcport);
5339 break;
5340 case QLA_EVT_ELS_PLOGI:
5341 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
5342 e->u.fcport.fcport, false);
5343 break;
5344 }
5345
5346 if (rc == EAGAIN) {
5347 /* put 'work' at head of 'vha->work_list' */
5348 spin_lock_irqsave(&vha->work_lock, flags);
5349 list_splice(&work, &vha->work_list);
5350 spin_unlock_irqrestore(&vha->work_lock, flags);
5351 break;
5352 }
5353 list_del_init(&e->list);
5354 if (e->flags & QLA_EVT_FLAG_FREE)
5355 kfree(e);
5356
5357 /* For each work completed decrement vha ref count */
5358 QLA_VHA_MARK_NOT_BUSY(vha);
5359 }
5360 }
5361
qla24xx_post_relogin_work(struct scsi_qla_host * vha)5362 int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5363 {
5364 struct qla_work_evt *e;
5365
5366 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5367
5368 if (!e) {
5369 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5370 return QLA_FUNCTION_FAILED;
5371 }
5372
5373 return qla2x00_post_work(vha, e);
5374 }
5375
5376 /* Relogins all the fcports of a vport
5377 * Context: dpc thread
5378 */
qla2x00_relogin(struct scsi_qla_host * vha)5379 void qla2x00_relogin(struct scsi_qla_host *vha)
5380 {
5381 fc_port_t *fcport;
5382 int status, relogin_needed = 0;
5383 struct event_arg ea;
5384
5385 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5386 /*
5387 * If the port is not ONLINE then try to login
5388 * to it if we haven't run out of retries.
5389 */
5390 if (atomic_read(&fcport->state) != FCS_ONLINE &&
5391 fcport->login_retry) {
5392 if (fcport->scan_state != QLA_FCPORT_FOUND ||
5393 fcport->disc_state == DSC_LOGIN_COMPLETE)
5394 continue;
5395
5396 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5397 fcport->disc_state == DSC_DELETE_PEND) {
5398 relogin_needed = 1;
5399 } else {
5400 if (vha->hw->current_topology != ISP_CFG_NL) {
5401 memset(&ea, 0, sizeof(ea));
5402 ea.fcport = fcport;
5403 qla24xx_handle_relogin_event(vha, &ea);
5404 } else if (vha->hw->current_topology ==
5405 ISP_CFG_NL) {
5406 fcport->login_retry--;
5407 status =
5408 qla2x00_local_device_login(vha,
5409 fcport);
5410 if (status == QLA_SUCCESS) {
5411 fcport->old_loop_id =
5412 fcport->loop_id;
5413 ql_dbg(ql_dbg_disc, vha, 0x2003,
5414 "Port login OK: logged in ID 0x%x.\n",
5415 fcport->loop_id);
5416 qla2x00_update_fcport
5417 (vha, fcport);
5418 } else if (status == 1) {
5419 set_bit(RELOGIN_NEEDED,
5420 &vha->dpc_flags);
5421 /* retry the login again */
5422 ql_dbg(ql_dbg_disc, vha, 0x2007,
5423 "Retrying %d login again loop_id 0x%x.\n",
5424 fcport->login_retry,
5425 fcport->loop_id);
5426 } else {
5427 fcport->login_retry = 0;
5428 }
5429
5430 if (fcport->login_retry == 0 &&
5431 status != QLA_SUCCESS)
5432 qla2x00_clear_loop_id(fcport);
5433 }
5434 }
5435 }
5436 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5437 break;
5438 }
5439
5440 if (relogin_needed)
5441 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5442
5443 ql_dbg(ql_dbg_disc, vha, 0x400e,
5444 "Relogin end.\n");
5445 }
5446
5447 /* Schedule work on any of the dpc-workqueues */
5448 void
qla83xx_schedule_work(scsi_qla_host_t * base_vha,int work_code)5449 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5450 {
5451 struct qla_hw_data *ha = base_vha->hw;
5452
5453 switch (work_code) {
5454 case MBA_IDC_AEN: /* 0x8200 */
5455 if (ha->dpc_lp_wq)
5456 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5457 break;
5458
5459 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5460 if (!ha->flags.nic_core_reset_hdlr_active) {
5461 if (ha->dpc_hp_wq)
5462 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5463 } else
5464 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5465 "NIC Core reset is already active. Skip "
5466 "scheduling it again.\n");
5467 break;
5468 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5469 if (ha->dpc_hp_wq)
5470 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5471 break;
5472 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5473 if (ha->dpc_hp_wq)
5474 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5475 break;
5476 default:
5477 ql_log(ql_log_warn, base_vha, 0xb05f,
5478 "Unknown work-code=0x%x.\n", work_code);
5479 }
5480
5481 return;
5482 }
5483
5484 /* Work: Perform NIC Core Unrecoverable state handling */
5485 void
qla83xx_nic_core_unrecoverable_work(struct work_struct * work)5486 qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5487 {
5488 struct qla_hw_data *ha =
5489 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
5490 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5491 uint32_t dev_state = 0;
5492
5493 qla83xx_idc_lock(base_vha, 0);
5494 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5495 qla83xx_reset_ownership(base_vha);
5496 if (ha->flags.nic_core_reset_owner) {
5497 ha->flags.nic_core_reset_owner = 0;
5498 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5499 QLA8XXX_DEV_FAILED);
5500 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5501 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5502 }
5503 qla83xx_idc_unlock(base_vha, 0);
5504 }
5505
5506 /* Work: Execute IDC state handler */
5507 void
qla83xx_idc_state_handler_work(struct work_struct * work)5508 qla83xx_idc_state_handler_work(struct work_struct *work)
5509 {
5510 struct qla_hw_data *ha =
5511 container_of(work, struct qla_hw_data, idc_state_handler);
5512 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5513 uint32_t dev_state = 0;
5514
5515 qla83xx_idc_lock(base_vha, 0);
5516 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5517 if (dev_state == QLA8XXX_DEV_FAILED ||
5518 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5519 qla83xx_idc_state_handler(base_vha);
5520 qla83xx_idc_unlock(base_vha, 0);
5521 }
5522
5523 static int
qla83xx_check_nic_core_fw_alive(scsi_qla_host_t * base_vha)5524 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5525 {
5526 int rval = QLA_SUCCESS;
5527 unsigned long heart_beat_wait = jiffies + (1 * HZ);
5528 uint32_t heart_beat_counter1, heart_beat_counter2;
5529
5530 do {
5531 if (time_after(jiffies, heart_beat_wait)) {
5532 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5533 "Nic Core f/w is not alive.\n");
5534 rval = QLA_FUNCTION_FAILED;
5535 break;
5536 }
5537
5538 qla83xx_idc_lock(base_vha, 0);
5539 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5540 &heart_beat_counter1);
5541 qla83xx_idc_unlock(base_vha, 0);
5542 msleep(100);
5543 qla83xx_idc_lock(base_vha, 0);
5544 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5545 &heart_beat_counter2);
5546 qla83xx_idc_unlock(base_vha, 0);
5547 } while (heart_beat_counter1 == heart_beat_counter2);
5548
5549 return rval;
5550 }
5551
5552 /* Work: Perform NIC Core Reset handling */
5553 void
qla83xx_nic_core_reset_work(struct work_struct * work)5554 qla83xx_nic_core_reset_work(struct work_struct *work)
5555 {
5556 struct qla_hw_data *ha =
5557 container_of(work, struct qla_hw_data, nic_core_reset);
5558 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5559 uint32_t dev_state = 0;
5560
5561 if (IS_QLA2031(ha)) {
5562 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5563 ql_log(ql_log_warn, base_vha, 0xb081,
5564 "Failed to dump mctp\n");
5565 return;
5566 }
5567
5568 if (!ha->flags.nic_core_reset_hdlr_active) {
5569 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5570 qla83xx_idc_lock(base_vha, 0);
5571 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5572 &dev_state);
5573 qla83xx_idc_unlock(base_vha, 0);
5574 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5575 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5576 "Nic Core f/w is alive.\n");
5577 return;
5578 }
5579 }
5580
5581 ha->flags.nic_core_reset_hdlr_active = 1;
5582 if (qla83xx_nic_core_reset(base_vha)) {
5583 /* NIC Core reset failed. */
5584 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5585 "NIC Core reset failed.\n");
5586 }
5587 ha->flags.nic_core_reset_hdlr_active = 0;
5588 }
5589 }
5590
5591 /* Work: Handle 8200 IDC aens */
5592 void
qla83xx_service_idc_aen(struct work_struct * work)5593 qla83xx_service_idc_aen(struct work_struct *work)
5594 {
5595 struct qla_hw_data *ha =
5596 container_of(work, struct qla_hw_data, idc_aen);
5597 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5598 uint32_t dev_state, idc_control;
5599
5600 qla83xx_idc_lock(base_vha, 0);
5601 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5602 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5603 qla83xx_idc_unlock(base_vha, 0);
5604 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5605 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5606 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5607 "Application requested NIC Core Reset.\n");
5608 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5609 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5610 QLA_SUCCESS) {
5611 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5612 "Other protocol driver requested NIC Core Reset.\n");
5613 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5614 }
5615 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5616 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5617 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5618 }
5619 }
5620
5621 static void
qla83xx_wait_logic(void)5622 qla83xx_wait_logic(void)
5623 {
5624 int i;
5625
5626 /* Yield CPU */
5627 if (!in_interrupt()) {
5628 /*
5629 * Wait about 200ms before retrying again.
5630 * This controls the number of retries for single
5631 * lock operation.
5632 */
5633 msleep(100);
5634 schedule();
5635 } else {
5636 for (i = 0; i < 20; i++)
5637 cpu_relax(); /* This a nop instr on i386 */
5638 }
5639 }
5640
5641 static int
qla83xx_force_lock_recovery(scsi_qla_host_t * base_vha)5642 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5643 {
5644 int rval;
5645 uint32_t data;
5646 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5647 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5648 struct qla_hw_data *ha = base_vha->hw;
5649
5650 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5651 "Trying force recovery of the IDC lock.\n");
5652
5653 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5654 if (rval)
5655 return rval;
5656
5657 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5658 return QLA_SUCCESS;
5659 } else {
5660 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5661 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5662 data);
5663 if (rval)
5664 return rval;
5665
5666 msleep(200);
5667
5668 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5669 &data);
5670 if (rval)
5671 return rval;
5672
5673 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5674 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5675 ~(idc_lck_rcvry_stage_mask));
5676 rval = qla83xx_wr_reg(base_vha,
5677 QLA83XX_IDC_LOCK_RECOVERY, data);
5678 if (rval)
5679 return rval;
5680
5681 /* Forcefully perform IDC UnLock */
5682 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5683 &data);
5684 if (rval)
5685 return rval;
5686 /* Clear lock-id by setting 0xff */
5687 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5688 0xff);
5689 if (rval)
5690 return rval;
5691 /* Clear lock-recovery by setting 0x0 */
5692 rval = qla83xx_wr_reg(base_vha,
5693 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5694 if (rval)
5695 return rval;
5696 } else
5697 return QLA_SUCCESS;
5698 }
5699
5700 return rval;
5701 }
5702
5703 static int
qla83xx_idc_lock_recovery(scsi_qla_host_t * base_vha)5704 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5705 {
5706 int rval = QLA_SUCCESS;
5707 uint32_t o_drv_lockid, n_drv_lockid;
5708 unsigned long lock_recovery_timeout;
5709
5710 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5711 retry_lockid:
5712 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5713 if (rval)
5714 goto exit;
5715
5716 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5717 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5718 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5719 return QLA_SUCCESS;
5720 else
5721 return QLA_FUNCTION_FAILED;
5722 }
5723
5724 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5725 if (rval)
5726 goto exit;
5727
5728 if (o_drv_lockid == n_drv_lockid) {
5729 qla83xx_wait_logic();
5730 goto retry_lockid;
5731 } else
5732 return QLA_SUCCESS;
5733
5734 exit:
5735 return rval;
5736 }
5737
5738 void
qla83xx_idc_lock(scsi_qla_host_t * base_vha,uint16_t requester_id)5739 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5740 {
5741 uint32_t data;
5742 uint32_t lock_owner;
5743 struct qla_hw_data *ha = base_vha->hw;
5744
5745 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5746 retry_lock:
5747 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5748 == QLA_SUCCESS) {
5749 if (data) {
5750 /* Setting lock-id to our function-number */
5751 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5752 ha->portnum);
5753 } else {
5754 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5755 &lock_owner);
5756 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
5757 "Failed to acquire IDC lock, acquired by %d, "
5758 "retrying...\n", lock_owner);
5759
5760 /* Retry/Perform IDC-Lock recovery */
5761 if (qla83xx_idc_lock_recovery(base_vha)
5762 == QLA_SUCCESS) {
5763 qla83xx_wait_logic();
5764 goto retry_lock;
5765 } else
5766 ql_log(ql_log_warn, base_vha, 0xb075,
5767 "IDC Lock recovery FAILED.\n");
5768 }
5769
5770 }
5771
5772 return;
5773 }
5774
5775 static bool
qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host * vha,struct purex_entry_24xx * purex)5776 qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha,
5777 struct purex_entry_24xx *purex)
5778 {
5779 char fwstr[16];
5780 u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0];
5781 struct port_database_24xx *pdb;
5782
5783 /* Domain Controller is always logged-out. */
5784 /* if RDP request is not from Domain Controller: */
5785 if (sid != 0xfffc01)
5786 return false;
5787
5788 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid);
5789
5790 pdb = kzalloc(sizeof(*pdb), GFP_KERNEL);
5791 if (!pdb) {
5792 ql_dbg(ql_dbg_init, vha, 0x0181,
5793 "%s: Failed allocate pdb\n", __func__);
5794 } else if (qla24xx_get_port_database(vha,
5795 le16_to_cpu(purex->nport_handle), pdb)) {
5796 ql_dbg(ql_dbg_init, vha, 0x0181,
5797 "%s: Failed get pdb sid=%x\n", __func__, sid);
5798 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE &&
5799 pdb->current_login_state != PDS_PRLI_COMPLETE) {
5800 ql_dbg(ql_dbg_init, vha, 0x0181,
5801 "%s: Port not logged in sid=%#x\n", __func__, sid);
5802 } else {
5803 /* RDP request is from logged in port */
5804 kfree(pdb);
5805 return false;
5806 }
5807 kfree(pdb);
5808
5809 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr));
5810 fwstr[strcspn(fwstr, " ")] = 0;
5811 /* if FW version allows RDP response length upto 2048 bytes: */
5812 if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0)
5813 return false;
5814
5815 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr);
5816
5817 /* RDP response length is to be reduced to maximum 256 bytes */
5818 return true;
5819 }
5820
5821 /*
5822 * Function Name: qla24xx_process_purex_iocb
5823 *
5824 * Description:
5825 * Prepare a RDP response and send to Fabric switch
5826 *
5827 * PARAMETERS:
5828 * vha: SCSI qla host
5829 * purex: RDP request received by HBA
5830 */
qla24xx_process_purex_rdp(struct scsi_qla_host * vha,struct purex_item * item)5831 void qla24xx_process_purex_rdp(struct scsi_qla_host *vha,
5832 struct purex_item *item)
5833 {
5834 struct qla_hw_data *ha = vha->hw;
5835 struct purex_entry_24xx *purex =
5836 (struct purex_entry_24xx *)&item->iocb;
5837 dma_addr_t rsp_els_dma;
5838 dma_addr_t rsp_payload_dma;
5839 dma_addr_t stat_dma;
5840 dma_addr_t sfp_dma;
5841 struct els_entry_24xx *rsp_els = NULL;
5842 struct rdp_rsp_payload *rsp_payload = NULL;
5843 struct link_statistics *stat = NULL;
5844 uint8_t *sfp = NULL;
5845 uint16_t sfp_flags = 0;
5846 uint rsp_payload_length = sizeof(*rsp_payload);
5847 int rval;
5848
5849 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180,
5850 "%s: Enter\n", __func__);
5851
5852 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181,
5853 "-------- ELS REQ -------\n");
5854 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182,
5855 purex, sizeof(*purex));
5856
5857 if (qla25xx_rdp_rsp_reduce_size(vha, purex)) {
5858 rsp_payload_length =
5859 offsetof(typeof(*rsp_payload), optical_elmt_desc);
5860 ql_dbg(ql_dbg_init, vha, 0x0181,
5861 "Reducing RSP payload length to %u bytes...\n",
5862 rsp_payload_length);
5863 }
5864
5865 rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els),
5866 &rsp_els_dma, GFP_KERNEL);
5867 if (!rsp_els) {
5868 ql_log(ql_log_warn, vha, 0x0183,
5869 "Failed allocate dma buffer ELS RSP.\n");
5870 goto dealloc;
5871 }
5872
5873 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
5874 &rsp_payload_dma, GFP_KERNEL);
5875 if (!rsp_payload) {
5876 ql_log(ql_log_warn, vha, 0x0184,
5877 "Failed allocate dma buffer ELS RSP payload.\n");
5878 goto dealloc;
5879 }
5880
5881 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
5882 &sfp_dma, GFP_KERNEL);
5883
5884 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat),
5885 &stat_dma, GFP_KERNEL);
5886
5887 /* Prepare Response IOCB */
5888 rsp_els->entry_type = ELS_IOCB_TYPE;
5889 rsp_els->entry_count = 1;
5890 rsp_els->sys_define = 0;
5891 rsp_els->entry_status = 0;
5892 rsp_els->handle = 0;
5893 rsp_els->nport_handle = purex->nport_handle;
5894 rsp_els->tx_dsd_count = cpu_to_le16(1);
5895 rsp_els->vp_index = purex->vp_idx;
5896 rsp_els->sof_type = EST_SOFI3;
5897 rsp_els->rx_xchg_address = purex->rx_xchg_addr;
5898 rsp_els->rx_dsd_count = 0;
5899 rsp_els->opcode = purex->els_frame_payload[0];
5900
5901 rsp_els->d_id[0] = purex->s_id[0];
5902 rsp_els->d_id[1] = purex->s_id[1];
5903 rsp_els->d_id[2] = purex->s_id[2];
5904
5905 rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC);
5906 rsp_els->rx_byte_count = 0;
5907 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length);
5908
5909 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address);
5910 rsp_els->tx_len = rsp_els->tx_byte_count;
5911
5912 rsp_els->rx_address = 0;
5913 rsp_els->rx_len = 0;
5914
5915 /* Prepare Response Payload */
5916 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */
5917 rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) -
5918 sizeof(rsp_payload->hdr));
5919
5920 /* Link service Request Info Descriptor */
5921 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1);
5922 rsp_payload->ls_req_info_desc.desc_len =
5923 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc));
5924 rsp_payload->ls_req_info_desc.req_payload_word_0 =
5925 cpu_to_be32p((uint32_t *)purex->els_frame_payload);
5926
5927 /* Link service Request Info Descriptor 2 */
5928 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1);
5929 rsp_payload->ls_req_info_desc2.desc_len =
5930 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2));
5931 rsp_payload->ls_req_info_desc2.req_payload_word_0 =
5932 cpu_to_be32p((uint32_t *)purex->els_frame_payload);
5933
5934
5935 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000);
5936 rsp_payload->sfp_diag_desc.desc_len =
5937 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc));
5938
5939 if (sfp) {
5940 /* SFP Flags */
5941 memset(sfp, 0, SFP_RTDI_LEN);
5942 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0);
5943 if (!rval) {
5944 /* SFP Flags bits 3-0: Port Tx Laser Type */
5945 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5))
5946 sfp_flags |= BIT_0; /* short wave */
5947 else if (sfp[0] & BIT_1)
5948 sfp_flags |= BIT_1; /* long wave 1310nm */
5949 else if (sfp[1] & BIT_4)
5950 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */
5951 }
5952
5953 /* SFP Type */
5954 memset(sfp, 0, SFP_RTDI_LEN);
5955 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0);
5956 if (!rval) {
5957 sfp_flags |= BIT_4; /* optical */
5958 if (sfp[0] == 0x3)
5959 sfp_flags |= BIT_6; /* sfp+ */
5960 }
5961
5962 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags);
5963
5964 /* SFP Diagnostics */
5965 memset(sfp, 0, SFP_RTDI_LEN);
5966 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0);
5967 if (!rval) {
5968 __be16 *trx = (__force __be16 *)sfp; /* already be16 */
5969 rsp_payload->sfp_diag_desc.temperature = trx[0];
5970 rsp_payload->sfp_diag_desc.vcc = trx[1];
5971 rsp_payload->sfp_diag_desc.tx_bias = trx[2];
5972 rsp_payload->sfp_diag_desc.tx_power = trx[3];
5973 rsp_payload->sfp_diag_desc.rx_power = trx[4];
5974 }
5975 }
5976
5977 /* Port Speed Descriptor */
5978 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001);
5979 rsp_payload->port_speed_desc.desc_len =
5980 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc));
5981 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16(
5982 qla25xx_fdmi_port_speed_capability(ha));
5983 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16(
5984 qla25xx_fdmi_port_speed_currently(ha));
5985
5986 /* Link Error Status Descriptor */
5987 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002);
5988 rsp_payload->ls_err_desc.desc_len =
5989 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc));
5990
5991 if (stat) {
5992 rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0);
5993 if (!rval) {
5994 rsp_payload->ls_err_desc.link_fail_cnt =
5995 cpu_to_be32(le32_to_cpu(stat->link_fail_cnt));
5996 rsp_payload->ls_err_desc.loss_sync_cnt =
5997 cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt));
5998 rsp_payload->ls_err_desc.loss_sig_cnt =
5999 cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt));
6000 rsp_payload->ls_err_desc.prim_seq_err_cnt =
6001 cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt));
6002 rsp_payload->ls_err_desc.inval_xmit_word_cnt =
6003 cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt));
6004 rsp_payload->ls_err_desc.inval_crc_cnt =
6005 cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt));
6006 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6;
6007 }
6008 }
6009
6010 /* Portname Descriptor */
6011 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003);
6012 rsp_payload->port_name_diag_desc.desc_len =
6013 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc));
6014 memcpy(rsp_payload->port_name_diag_desc.WWNN,
6015 vha->node_name,
6016 sizeof(rsp_payload->port_name_diag_desc.WWNN));
6017 memcpy(rsp_payload->port_name_diag_desc.WWPN,
6018 vha->port_name,
6019 sizeof(rsp_payload->port_name_diag_desc.WWPN));
6020
6021 /* F-Port Portname Descriptor */
6022 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003);
6023 rsp_payload->port_name_direct_desc.desc_len =
6024 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc));
6025 memcpy(rsp_payload->port_name_direct_desc.WWNN,
6026 vha->fabric_node_name,
6027 sizeof(rsp_payload->port_name_direct_desc.WWNN));
6028 memcpy(rsp_payload->port_name_direct_desc.WWPN,
6029 vha->fabric_port_name,
6030 sizeof(rsp_payload->port_name_direct_desc.WWPN));
6031
6032 /* Bufer Credit Descriptor */
6033 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006);
6034 rsp_payload->buffer_credit_desc.desc_len =
6035 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc));
6036 rsp_payload->buffer_credit_desc.fcport_b2b = 0;
6037 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0);
6038 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0);
6039
6040 if (ha->flags.plogi_template_valid) {
6041 uint32_t tmp =
6042 be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred);
6043 rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp);
6044 }
6045
6046 if (rsp_payload_length < sizeof(*rsp_payload))
6047 goto send;
6048
6049 /* Optical Element Descriptor, Temperature */
6050 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007);
6051 rsp_payload->optical_elmt_desc[0].desc_len =
6052 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6053 /* Optical Element Descriptor, Voltage */
6054 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007);
6055 rsp_payload->optical_elmt_desc[1].desc_len =
6056 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6057 /* Optical Element Descriptor, Tx Bias Current */
6058 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007);
6059 rsp_payload->optical_elmt_desc[2].desc_len =
6060 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6061 /* Optical Element Descriptor, Tx Power */
6062 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007);
6063 rsp_payload->optical_elmt_desc[3].desc_len =
6064 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6065 /* Optical Element Descriptor, Rx Power */
6066 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007);
6067 rsp_payload->optical_elmt_desc[4].desc_len =
6068 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6069
6070 if (sfp) {
6071 memset(sfp, 0, SFP_RTDI_LEN);
6072 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0);
6073 if (!rval) {
6074 __be16 *trx = (__force __be16 *)sfp; /* already be16 */
6075
6076 /* Optical Element Descriptor, Temperature */
6077 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0];
6078 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1];
6079 rsp_payload->optical_elmt_desc[0].high_warn = trx[2];
6080 rsp_payload->optical_elmt_desc[0].low_warn = trx[3];
6081 rsp_payload->optical_elmt_desc[0].element_flags =
6082 cpu_to_be32(1 << 28);
6083
6084 /* Optical Element Descriptor, Voltage */
6085 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4];
6086 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5];
6087 rsp_payload->optical_elmt_desc[1].high_warn = trx[6];
6088 rsp_payload->optical_elmt_desc[1].low_warn = trx[7];
6089 rsp_payload->optical_elmt_desc[1].element_flags =
6090 cpu_to_be32(2 << 28);
6091
6092 /* Optical Element Descriptor, Tx Bias Current */
6093 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8];
6094 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9];
6095 rsp_payload->optical_elmt_desc[2].high_warn = trx[10];
6096 rsp_payload->optical_elmt_desc[2].low_warn = trx[11];
6097 rsp_payload->optical_elmt_desc[2].element_flags =
6098 cpu_to_be32(3 << 28);
6099
6100 /* Optical Element Descriptor, Tx Power */
6101 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12];
6102 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13];
6103 rsp_payload->optical_elmt_desc[3].high_warn = trx[14];
6104 rsp_payload->optical_elmt_desc[3].low_warn = trx[15];
6105 rsp_payload->optical_elmt_desc[3].element_flags =
6106 cpu_to_be32(4 << 28);
6107
6108 /* Optical Element Descriptor, Rx Power */
6109 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16];
6110 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17];
6111 rsp_payload->optical_elmt_desc[4].high_warn = trx[18];
6112 rsp_payload->optical_elmt_desc[4].low_warn = trx[19];
6113 rsp_payload->optical_elmt_desc[4].element_flags =
6114 cpu_to_be32(5 << 28);
6115 }
6116
6117 memset(sfp, 0, SFP_RTDI_LEN);
6118 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0);
6119 if (!rval) {
6120 /* Temperature high/low alarm/warning */
6121 rsp_payload->optical_elmt_desc[0].element_flags |=
6122 cpu_to_be32(
6123 (sfp[0] >> 7 & 1) << 3 |
6124 (sfp[0] >> 6 & 1) << 2 |
6125 (sfp[4] >> 7 & 1) << 1 |
6126 (sfp[4] >> 6 & 1) << 0);
6127
6128 /* Voltage high/low alarm/warning */
6129 rsp_payload->optical_elmt_desc[1].element_flags |=
6130 cpu_to_be32(
6131 (sfp[0] >> 5 & 1) << 3 |
6132 (sfp[0] >> 4 & 1) << 2 |
6133 (sfp[4] >> 5 & 1) << 1 |
6134 (sfp[4] >> 4 & 1) << 0);
6135
6136 /* Tx Bias Current high/low alarm/warning */
6137 rsp_payload->optical_elmt_desc[2].element_flags |=
6138 cpu_to_be32(
6139 (sfp[0] >> 3 & 1) << 3 |
6140 (sfp[0] >> 2 & 1) << 2 |
6141 (sfp[4] >> 3 & 1) << 1 |
6142 (sfp[4] >> 2 & 1) << 0);
6143
6144 /* Tx Power high/low alarm/warning */
6145 rsp_payload->optical_elmt_desc[3].element_flags |=
6146 cpu_to_be32(
6147 (sfp[0] >> 1 & 1) << 3 |
6148 (sfp[0] >> 0 & 1) << 2 |
6149 (sfp[4] >> 1 & 1) << 1 |
6150 (sfp[4] >> 0 & 1) << 0);
6151
6152 /* Rx Power high/low alarm/warning */
6153 rsp_payload->optical_elmt_desc[4].element_flags |=
6154 cpu_to_be32(
6155 (sfp[1] >> 7 & 1) << 3 |
6156 (sfp[1] >> 6 & 1) << 2 |
6157 (sfp[5] >> 7 & 1) << 1 |
6158 (sfp[5] >> 6 & 1) << 0);
6159 }
6160 }
6161
6162 /* Optical Product Data Descriptor */
6163 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008);
6164 rsp_payload->optical_prod_desc.desc_len =
6165 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc));
6166
6167 if (sfp) {
6168 memset(sfp, 0, SFP_RTDI_LEN);
6169 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0);
6170 if (!rval) {
6171 memcpy(rsp_payload->optical_prod_desc.vendor_name,
6172 sfp + 0,
6173 sizeof(rsp_payload->optical_prod_desc.vendor_name));
6174 memcpy(rsp_payload->optical_prod_desc.part_number,
6175 sfp + 20,
6176 sizeof(rsp_payload->optical_prod_desc.part_number));
6177 memcpy(rsp_payload->optical_prod_desc.revision,
6178 sfp + 36,
6179 sizeof(rsp_payload->optical_prod_desc.revision));
6180 memcpy(rsp_payload->optical_prod_desc.serial_number,
6181 sfp + 48,
6182 sizeof(rsp_payload->optical_prod_desc.serial_number));
6183 }
6184
6185 memset(sfp, 0, SFP_RTDI_LEN);
6186 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0);
6187 if (!rval) {
6188 memcpy(rsp_payload->optical_prod_desc.date,
6189 sfp + 0,
6190 sizeof(rsp_payload->optical_prod_desc.date));
6191 }
6192 }
6193
6194 send:
6195 ql_dbg(ql_dbg_init, vha, 0x0183,
6196 "Sending ELS Response to RDP Request...\n");
6197 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184,
6198 "-------- ELS RSP -------\n");
6199 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185,
6200 rsp_els, sizeof(*rsp_els));
6201 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186,
6202 "-------- ELS RSP PAYLOAD -------\n");
6203 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187,
6204 rsp_payload, rsp_payload_length);
6205
6206 rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0);
6207
6208 if (rval) {
6209 ql_log(ql_log_warn, vha, 0x0188,
6210 "%s: iocb failed to execute -> %x\n", __func__, rval);
6211 } else if (rsp_els->comp_status) {
6212 ql_log(ql_log_warn, vha, 0x0189,
6213 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n",
6214 __func__, rsp_els->comp_status,
6215 rsp_els->error_subcode_1, rsp_els->error_subcode_2);
6216 } else {
6217 ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__);
6218 }
6219
6220 dealloc:
6221 if (stat)
6222 dma_free_coherent(&ha->pdev->dev, sizeof(*stat),
6223 stat, stat_dma);
6224 if (sfp)
6225 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
6226 sfp, sfp_dma);
6227 if (rsp_payload)
6228 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
6229 rsp_payload, rsp_payload_dma);
6230 if (rsp_els)
6231 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els),
6232 rsp_els, rsp_els_dma);
6233 }
6234
6235 void
qla24xx_free_purex_item(struct purex_item * item)6236 qla24xx_free_purex_item(struct purex_item *item)
6237 {
6238 if (item == &item->vha->default_item)
6239 memset(&item->vha->default_item, 0, sizeof(struct purex_item));
6240 else
6241 kfree(item);
6242 }
6243
qla24xx_process_purex_list(struct purex_list * list)6244 void qla24xx_process_purex_list(struct purex_list *list)
6245 {
6246 struct list_head head = LIST_HEAD_INIT(head);
6247 struct purex_item *item, *next;
6248 ulong flags;
6249
6250 spin_lock_irqsave(&list->lock, flags);
6251 list_splice_init(&list->head, &head);
6252 spin_unlock_irqrestore(&list->lock, flags);
6253
6254 list_for_each_entry_safe(item, next, &head, list) {
6255 list_del(&item->list);
6256 item->process_item(item->vha, item);
6257 qla24xx_free_purex_item(item);
6258 }
6259 }
6260
6261 void
qla83xx_idc_unlock(scsi_qla_host_t * base_vha,uint16_t requester_id)6262 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
6263 {
6264 #if 0
6265 uint16_t options = (requester_id << 15) | BIT_7;
6266 #endif
6267 uint16_t retry;
6268 uint32_t data;
6269 struct qla_hw_data *ha = base_vha->hw;
6270
6271 /* IDC-unlock implementation using driver-unlock/lock-id
6272 * remote registers
6273 */
6274 retry = 0;
6275 retry_unlock:
6276 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
6277 == QLA_SUCCESS) {
6278 if (data == ha->portnum) {
6279 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
6280 /* Clearing lock-id by setting 0xff */
6281 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
6282 } else if (retry < 10) {
6283 /* SV: XXX: IDC unlock retrying needed here? */
6284
6285 /* Retry for IDC-unlock */
6286 qla83xx_wait_logic();
6287 retry++;
6288 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
6289 "Failed to release IDC lock, retrying=%d\n", retry);
6290 goto retry_unlock;
6291 }
6292 } else if (retry < 10) {
6293 /* Retry for IDC-unlock */
6294 qla83xx_wait_logic();
6295 retry++;
6296 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
6297 "Failed to read drv-lockid, retrying=%d\n", retry);
6298 goto retry_unlock;
6299 }
6300
6301 return;
6302
6303 #if 0
6304 /* XXX: IDC-unlock implementation using access-control mbx */
6305 retry = 0;
6306 retry_unlock2:
6307 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
6308 if (retry < 10) {
6309 /* Retry for IDC-unlock */
6310 qla83xx_wait_logic();
6311 retry++;
6312 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
6313 "Failed to release IDC lock, retrying=%d\n", retry);
6314 goto retry_unlock2;
6315 }
6316 }
6317
6318 return;
6319 #endif
6320 }
6321
6322 int
__qla83xx_set_drv_presence(scsi_qla_host_t * vha)6323 __qla83xx_set_drv_presence(scsi_qla_host_t *vha)
6324 {
6325 int rval = QLA_SUCCESS;
6326 struct qla_hw_data *ha = vha->hw;
6327 uint32_t drv_presence;
6328
6329 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6330 if (rval == QLA_SUCCESS) {
6331 drv_presence |= (1 << ha->portnum);
6332 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6333 drv_presence);
6334 }
6335
6336 return rval;
6337 }
6338
6339 int
qla83xx_set_drv_presence(scsi_qla_host_t * vha)6340 qla83xx_set_drv_presence(scsi_qla_host_t *vha)
6341 {
6342 int rval = QLA_SUCCESS;
6343
6344 qla83xx_idc_lock(vha, 0);
6345 rval = __qla83xx_set_drv_presence(vha);
6346 qla83xx_idc_unlock(vha, 0);
6347
6348 return rval;
6349 }
6350
6351 int
__qla83xx_clear_drv_presence(scsi_qla_host_t * vha)6352 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
6353 {
6354 int rval = QLA_SUCCESS;
6355 struct qla_hw_data *ha = vha->hw;
6356 uint32_t drv_presence;
6357
6358 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6359 if (rval == QLA_SUCCESS) {
6360 drv_presence &= ~(1 << ha->portnum);
6361 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6362 drv_presence);
6363 }
6364
6365 return rval;
6366 }
6367
6368 int
qla83xx_clear_drv_presence(scsi_qla_host_t * vha)6369 qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
6370 {
6371 int rval = QLA_SUCCESS;
6372
6373 qla83xx_idc_lock(vha, 0);
6374 rval = __qla83xx_clear_drv_presence(vha);
6375 qla83xx_idc_unlock(vha, 0);
6376
6377 return rval;
6378 }
6379
6380 static void
qla83xx_need_reset_handler(scsi_qla_host_t * vha)6381 qla83xx_need_reset_handler(scsi_qla_host_t *vha)
6382 {
6383 struct qla_hw_data *ha = vha->hw;
6384 uint32_t drv_ack, drv_presence;
6385 unsigned long ack_timeout;
6386
6387 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
6388 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
6389 while (1) {
6390 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6391 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6392 if ((drv_ack & drv_presence) == drv_presence)
6393 break;
6394
6395 if (time_after_eq(jiffies, ack_timeout)) {
6396 ql_log(ql_log_warn, vha, 0xb067,
6397 "RESET ACK TIMEOUT! drv_presence=0x%x "
6398 "drv_ack=0x%x\n", drv_presence, drv_ack);
6399 /*
6400 * The function(s) which did not ack in time are forced
6401 * to withdraw any further participation in the IDC
6402 * reset.
6403 */
6404 if (drv_ack != drv_presence)
6405 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6406 drv_ack);
6407 break;
6408 }
6409
6410 qla83xx_idc_unlock(vha, 0);
6411 msleep(1000);
6412 qla83xx_idc_lock(vha, 0);
6413 }
6414
6415 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
6416 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
6417 }
6418
6419 static int
qla83xx_device_bootstrap(scsi_qla_host_t * vha)6420 qla83xx_device_bootstrap(scsi_qla_host_t *vha)
6421 {
6422 int rval = QLA_SUCCESS;
6423 uint32_t idc_control;
6424
6425 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
6426 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
6427
6428 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
6429 __qla83xx_get_idc_control(vha, &idc_control);
6430 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
6431 __qla83xx_set_idc_control(vha, 0);
6432
6433 qla83xx_idc_unlock(vha, 0);
6434 rval = qla83xx_restart_nic_firmware(vha);
6435 qla83xx_idc_lock(vha, 0);
6436
6437 if (rval != QLA_SUCCESS) {
6438 ql_log(ql_log_fatal, vha, 0xb06a,
6439 "Failed to restart NIC f/w.\n");
6440 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
6441 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
6442 } else {
6443 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
6444 "Success in restarting nic f/w.\n");
6445 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
6446 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
6447 }
6448
6449 return rval;
6450 }
6451
6452 /* Assumes idc_lock always held on entry */
6453 int
qla83xx_idc_state_handler(scsi_qla_host_t * base_vha)6454 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
6455 {
6456 struct qla_hw_data *ha = base_vha->hw;
6457 int rval = QLA_SUCCESS;
6458 unsigned long dev_init_timeout;
6459 uint32_t dev_state;
6460
6461 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
6462 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
6463
6464 while (1) {
6465
6466 if (time_after_eq(jiffies, dev_init_timeout)) {
6467 ql_log(ql_log_warn, base_vha, 0xb06e,
6468 "Initialization TIMEOUT!\n");
6469 /* Init timeout. Disable further NIC Core
6470 * communication.
6471 */
6472 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
6473 QLA8XXX_DEV_FAILED);
6474 ql_log(ql_log_info, base_vha, 0xb06f,
6475 "HW State: FAILED.\n");
6476 }
6477
6478 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6479 switch (dev_state) {
6480 case QLA8XXX_DEV_READY:
6481 if (ha->flags.nic_core_reset_owner)
6482 qla83xx_idc_audit(base_vha,
6483 IDC_AUDIT_COMPLETION);
6484 ha->flags.nic_core_reset_owner = 0;
6485 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
6486 "Reset_owner reset by 0x%x.\n",
6487 ha->portnum);
6488 goto exit;
6489 case QLA8XXX_DEV_COLD:
6490 if (ha->flags.nic_core_reset_owner)
6491 rval = qla83xx_device_bootstrap(base_vha);
6492 else {
6493 /* Wait for AEN to change device-state */
6494 qla83xx_idc_unlock(base_vha, 0);
6495 msleep(1000);
6496 qla83xx_idc_lock(base_vha, 0);
6497 }
6498 break;
6499 case QLA8XXX_DEV_INITIALIZING:
6500 /* Wait for AEN to change device-state */
6501 qla83xx_idc_unlock(base_vha, 0);
6502 msleep(1000);
6503 qla83xx_idc_lock(base_vha, 0);
6504 break;
6505 case QLA8XXX_DEV_NEED_RESET:
6506 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
6507 qla83xx_need_reset_handler(base_vha);
6508 else {
6509 /* Wait for AEN to change device-state */
6510 qla83xx_idc_unlock(base_vha, 0);
6511 msleep(1000);
6512 qla83xx_idc_lock(base_vha, 0);
6513 }
6514 /* reset timeout value after need reset handler */
6515 dev_init_timeout = jiffies +
6516 (ha->fcoe_dev_init_timeout * HZ);
6517 break;
6518 case QLA8XXX_DEV_NEED_QUIESCENT:
6519 /* XXX: DEBUG for now */
6520 qla83xx_idc_unlock(base_vha, 0);
6521 msleep(1000);
6522 qla83xx_idc_lock(base_vha, 0);
6523 break;
6524 case QLA8XXX_DEV_QUIESCENT:
6525 /* XXX: DEBUG for now */
6526 if (ha->flags.quiesce_owner)
6527 goto exit;
6528
6529 qla83xx_idc_unlock(base_vha, 0);
6530 msleep(1000);
6531 qla83xx_idc_lock(base_vha, 0);
6532 dev_init_timeout = jiffies +
6533 (ha->fcoe_dev_init_timeout * HZ);
6534 break;
6535 case QLA8XXX_DEV_FAILED:
6536 if (ha->flags.nic_core_reset_owner)
6537 qla83xx_idc_audit(base_vha,
6538 IDC_AUDIT_COMPLETION);
6539 ha->flags.nic_core_reset_owner = 0;
6540 __qla83xx_clear_drv_presence(base_vha);
6541 qla83xx_idc_unlock(base_vha, 0);
6542 qla8xxx_dev_failed_handler(base_vha);
6543 rval = QLA_FUNCTION_FAILED;
6544 qla83xx_idc_lock(base_vha, 0);
6545 goto exit;
6546 case QLA8XXX_BAD_VALUE:
6547 qla83xx_idc_unlock(base_vha, 0);
6548 msleep(1000);
6549 qla83xx_idc_lock(base_vha, 0);
6550 break;
6551 default:
6552 ql_log(ql_log_warn, base_vha, 0xb071,
6553 "Unknown Device State: %x.\n", dev_state);
6554 qla83xx_idc_unlock(base_vha, 0);
6555 qla8xxx_dev_failed_handler(base_vha);
6556 rval = QLA_FUNCTION_FAILED;
6557 qla83xx_idc_lock(base_vha, 0);
6558 goto exit;
6559 }
6560 }
6561
6562 exit:
6563 return rval;
6564 }
6565
6566 void
qla2x00_disable_board_on_pci_error(struct work_struct * work)6567 qla2x00_disable_board_on_pci_error(struct work_struct *work)
6568 {
6569 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
6570 board_disable);
6571 struct pci_dev *pdev = ha->pdev;
6572 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6573
6574 ql_log(ql_log_warn, base_vha, 0x015b,
6575 "Disabling adapter.\n");
6576
6577 if (!atomic_read(&pdev->enable_cnt)) {
6578 ql_log(ql_log_info, base_vha, 0xfffc,
6579 "PCI device disabled, no action req for PCI error=%lx\n",
6580 base_vha->pci_flags);
6581 return;
6582 }
6583
6584 /*
6585 * if UNLOADING flag is already set, then continue unload,
6586 * where it was set first.
6587 */
6588 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
6589 return;
6590
6591 qla2x00_wait_for_sess_deletion(base_vha);
6592
6593 qla2x00_delete_all_vps(ha, base_vha);
6594
6595 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6596
6597 qla2x00_dfs_remove(base_vha);
6598
6599 qla84xx_put_chip(base_vha);
6600
6601 if (base_vha->timer_active)
6602 qla2x00_stop_timer(base_vha);
6603
6604 base_vha->flags.online = 0;
6605
6606 qla2x00_destroy_deferred_work(ha);
6607
6608 /*
6609 * Do not try to stop beacon blink as it will issue a mailbox
6610 * command.
6611 */
6612 qla2x00_free_sysfs_attr(base_vha, false);
6613
6614 fc_remove_host(base_vha->host);
6615
6616 scsi_remove_host(base_vha->host);
6617
6618 base_vha->flags.init_done = 0;
6619 qla25xx_delete_queues(base_vha);
6620 qla2x00_free_fcports(base_vha);
6621 qla2x00_free_irqs(base_vha);
6622 qla2x00_mem_free(ha);
6623 qla82xx_md_free(base_vha);
6624 qla2x00_free_queues(ha);
6625
6626 qla2x00_unmap_iobases(ha);
6627
6628 pci_release_selected_regions(ha->pdev, ha->bars);
6629 pci_disable_pcie_error_reporting(pdev);
6630 pci_disable_device(pdev);
6631
6632 /*
6633 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
6634 */
6635 }
6636
6637 /**************************************************************************
6638 * qla2x00_do_dpc
6639 * This kernel thread is a task that is schedule by the interrupt handler
6640 * to perform the background processing for interrupts.
6641 *
6642 * Notes:
6643 * This task always run in the context of a kernel thread. It
6644 * is kick-off by the driver's detect code and starts up
6645 * up one per adapter. It immediately goes to sleep and waits for
6646 * some fibre event. When either the interrupt handler or
6647 * the timer routine detects a event it will one of the task
6648 * bits then wake us up.
6649 **************************************************************************/
6650 static int
qla2x00_do_dpc(void * data)6651 qla2x00_do_dpc(void *data)
6652 {
6653 scsi_qla_host_t *base_vha;
6654 struct qla_hw_data *ha;
6655 uint32_t online;
6656 struct qla_qpair *qpair;
6657
6658 ha = (struct qla_hw_data *)data;
6659 base_vha = pci_get_drvdata(ha->pdev);
6660
6661 set_user_nice(current, MIN_NICE);
6662
6663 set_current_state(TASK_INTERRUPTIBLE);
6664 while (!kthread_should_stop()) {
6665 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
6666 "DPC handler sleeping.\n");
6667
6668 schedule();
6669
6670 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
6671 goto end_loop;
6672
6673 if (ha->flags.eeh_busy) {
6674 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
6675 "eeh_busy=%d.\n", ha->flags.eeh_busy);
6676 goto end_loop;
6677 }
6678
6679 ha->dpc_active = 1;
6680
6681 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
6682 "DPC handler waking up, dpc_flags=0x%lx.\n",
6683 base_vha->dpc_flags);
6684
6685 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6686 break;
6687
6688 if (IS_P3P_TYPE(ha)) {
6689 if (IS_QLA8044(ha)) {
6690 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6691 &base_vha->dpc_flags)) {
6692 qla8044_idc_lock(ha);
6693 qla8044_wr_direct(base_vha,
6694 QLA8044_CRB_DEV_STATE_INDEX,
6695 QLA8XXX_DEV_FAILED);
6696 qla8044_idc_unlock(ha);
6697 ql_log(ql_log_info, base_vha, 0x4004,
6698 "HW State: FAILED.\n");
6699 qla8044_device_state_handler(base_vha);
6700 continue;
6701 }
6702
6703 } else {
6704 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6705 &base_vha->dpc_flags)) {
6706 qla82xx_idc_lock(ha);
6707 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6708 QLA8XXX_DEV_FAILED);
6709 qla82xx_idc_unlock(ha);
6710 ql_log(ql_log_info, base_vha, 0x0151,
6711 "HW State: FAILED.\n");
6712 qla82xx_device_state_handler(base_vha);
6713 continue;
6714 }
6715 }
6716
6717 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
6718 &base_vha->dpc_flags)) {
6719
6720 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
6721 "FCoE context reset scheduled.\n");
6722 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
6723 &base_vha->dpc_flags))) {
6724 if (qla82xx_fcoe_ctx_reset(base_vha)) {
6725 /* FCoE-ctx reset failed.
6726 * Escalate to chip-reset
6727 */
6728 set_bit(ISP_ABORT_NEEDED,
6729 &base_vha->dpc_flags);
6730 }
6731 clear_bit(ABORT_ISP_ACTIVE,
6732 &base_vha->dpc_flags);
6733 }
6734
6735 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
6736 "FCoE context reset end.\n");
6737 }
6738 } else if (IS_QLAFX00(ha)) {
6739 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6740 &base_vha->dpc_flags)) {
6741 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
6742 "Firmware Reset Recovery\n");
6743 if (qlafx00_reset_initialize(base_vha)) {
6744 /* Failed. Abort isp later. */
6745 if (!test_bit(UNLOADING,
6746 &base_vha->dpc_flags)) {
6747 set_bit(ISP_UNRECOVERABLE,
6748 &base_vha->dpc_flags);
6749 ql_dbg(ql_dbg_dpc, base_vha,
6750 0x4021,
6751 "Reset Recovery Failed\n");
6752 }
6753 }
6754 }
6755
6756 if (test_and_clear_bit(FX00_TARGET_SCAN,
6757 &base_vha->dpc_flags)) {
6758 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
6759 "ISPFx00 Target Scan scheduled\n");
6760 if (qlafx00_rescan_isp(base_vha)) {
6761 if (!test_bit(UNLOADING,
6762 &base_vha->dpc_flags))
6763 set_bit(ISP_UNRECOVERABLE,
6764 &base_vha->dpc_flags);
6765 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
6766 "ISPFx00 Target Scan Failed\n");
6767 }
6768 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
6769 "ISPFx00 Target Scan End\n");
6770 }
6771 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
6772 &base_vha->dpc_flags)) {
6773 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
6774 "ISPFx00 Host Info resend scheduled\n");
6775 qlafx00_fx_disc(base_vha,
6776 &base_vha->hw->mr.fcport,
6777 FXDISC_REG_HOST_INFO);
6778 }
6779 }
6780
6781 if (test_and_clear_bit(DETECT_SFP_CHANGE,
6782 &base_vha->dpc_flags)) {
6783 /* Semantic:
6784 * - NO-OP -- await next ISP-ABORT. Preferred method
6785 * to minimize disruptions that will occur
6786 * when a forced chip-reset occurs.
6787 * - Force -- ISP-ABORT scheduled.
6788 */
6789 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */
6790 }
6791
6792 if (test_and_clear_bit
6793 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
6794 !test_bit(UNLOADING, &base_vha->dpc_flags)) {
6795 bool do_reset = true;
6796
6797 switch (base_vha->qlini_mode) {
6798 case QLA2XXX_INI_MODE_ENABLED:
6799 break;
6800 case QLA2XXX_INI_MODE_DISABLED:
6801 if (!qla_tgt_mode_enabled(base_vha) &&
6802 !ha->flags.fw_started)
6803 do_reset = false;
6804 break;
6805 case QLA2XXX_INI_MODE_DUAL:
6806 if (!qla_dual_mode_enabled(base_vha) &&
6807 !ha->flags.fw_started)
6808 do_reset = false;
6809 break;
6810 default:
6811 break;
6812 }
6813
6814 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE,
6815 &base_vha->dpc_flags))) {
6816 base_vha->flags.online = 1;
6817 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
6818 "ISP abort scheduled.\n");
6819 if (ha->isp_ops->abort_isp(base_vha)) {
6820 /* failed. retry later */
6821 set_bit(ISP_ABORT_NEEDED,
6822 &base_vha->dpc_flags);
6823 }
6824 clear_bit(ABORT_ISP_ACTIVE,
6825 &base_vha->dpc_flags);
6826 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
6827 "ISP abort end.\n");
6828 }
6829 }
6830
6831 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) {
6832 if (atomic_read(&base_vha->loop_state) == LOOP_READY) {
6833 qla24xx_process_purex_list
6834 (&base_vha->purex_list);
6835 clear_bit(PROCESS_PUREX_IOCB,
6836 &base_vha->dpc_flags);
6837 }
6838 }
6839
6840 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
6841 &base_vha->dpc_flags)) {
6842 qla2x00_update_fcports(base_vha);
6843 }
6844
6845 if (IS_QLAFX00(ha))
6846 goto loop_resync_check;
6847
6848 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
6849 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
6850 "Quiescence mode scheduled.\n");
6851 if (IS_P3P_TYPE(ha)) {
6852 if (IS_QLA82XX(ha))
6853 qla82xx_device_state_handler(base_vha);
6854 if (IS_QLA8044(ha))
6855 qla8044_device_state_handler(base_vha);
6856 clear_bit(ISP_QUIESCE_NEEDED,
6857 &base_vha->dpc_flags);
6858 if (!ha->flags.quiesce_owner) {
6859 qla2x00_perform_loop_resync(base_vha);
6860 if (IS_QLA82XX(ha)) {
6861 qla82xx_idc_lock(ha);
6862 qla82xx_clear_qsnt_ready(
6863 base_vha);
6864 qla82xx_idc_unlock(ha);
6865 } else if (IS_QLA8044(ha)) {
6866 qla8044_idc_lock(ha);
6867 qla8044_clear_qsnt_ready(
6868 base_vha);
6869 qla8044_idc_unlock(ha);
6870 }
6871 }
6872 } else {
6873 clear_bit(ISP_QUIESCE_NEEDED,
6874 &base_vha->dpc_flags);
6875 qla2x00_quiesce_io(base_vha);
6876 }
6877 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
6878 "Quiescence mode end.\n");
6879 }
6880
6881 if (test_and_clear_bit(RESET_MARKER_NEEDED,
6882 &base_vha->dpc_flags) &&
6883 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
6884
6885 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
6886 "Reset marker scheduled.\n");
6887 qla2x00_rst_aen(base_vha);
6888 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
6889 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
6890 "Reset marker end.\n");
6891 }
6892
6893 /* Retry each device up to login retry count */
6894 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
6895 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
6896 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
6897
6898 if (!base_vha->relogin_jif ||
6899 time_after_eq(jiffies, base_vha->relogin_jif)) {
6900 base_vha->relogin_jif = jiffies + HZ;
6901 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
6902
6903 ql_dbg(ql_dbg_disc, base_vha, 0x400d,
6904 "Relogin scheduled.\n");
6905 qla24xx_post_relogin_work(base_vha);
6906 }
6907 }
6908 loop_resync_check:
6909 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
6910 &base_vha->dpc_flags)) {
6911
6912 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
6913 "Loop resync scheduled.\n");
6914
6915 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
6916 &base_vha->dpc_flags))) {
6917
6918 qla2x00_loop_resync(base_vha);
6919
6920 clear_bit(LOOP_RESYNC_ACTIVE,
6921 &base_vha->dpc_flags);
6922 }
6923
6924 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
6925 "Loop resync end.\n");
6926 }
6927
6928 if (IS_QLAFX00(ha))
6929 goto intr_on_check;
6930
6931 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
6932 atomic_read(&base_vha->loop_state) == LOOP_READY) {
6933 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
6934 qla2xxx_flash_npiv_conf(base_vha);
6935 }
6936
6937 intr_on_check:
6938 if (!ha->interrupts_on)
6939 ha->isp_ops->enable_intrs(ha);
6940
6941 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
6942 &base_vha->dpc_flags)) {
6943 if (ha->beacon_blink_led == 1)
6944 ha->isp_ops->beacon_blink(base_vha);
6945 }
6946
6947 /* qpair online check */
6948 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
6949 &base_vha->dpc_flags)) {
6950 if (ha->flags.eeh_busy ||
6951 ha->flags.pci_channel_io_perm_failure)
6952 online = 0;
6953 else
6954 online = 1;
6955
6956 mutex_lock(&ha->mq_lock);
6957 list_for_each_entry(qpair, &base_vha->qp_list,
6958 qp_list_elem)
6959 qpair->online = online;
6960 mutex_unlock(&ha->mq_lock);
6961 }
6962
6963 if (test_and_clear_bit(SET_NVME_ZIO_THRESHOLD_NEEDED,
6964 &base_vha->dpc_flags)) {
6965 ql_log(ql_log_info, base_vha, 0xffffff,
6966 "nvme: SET ZIO Activity exchange threshold to %d.\n",
6967 ha->nvme_last_rptd_aen);
6968 if (qla27xx_set_zio_threshold(base_vha,
6969 ha->nvme_last_rptd_aen)) {
6970 ql_log(ql_log_info, base_vha, 0xffffff,
6971 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n",
6972 ha->nvme_last_rptd_aen);
6973 }
6974 }
6975
6976 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED,
6977 &base_vha->dpc_flags)) {
6978 ql_log(ql_log_info, base_vha, 0xffffff,
6979 "SET ZIO Activity exchange threshold to %d.\n",
6980 ha->last_zio_threshold);
6981 qla27xx_set_zio_threshold(base_vha,
6982 ha->last_zio_threshold);
6983 }
6984
6985 if (!IS_QLAFX00(ha))
6986 qla2x00_do_dpc_all_vps(base_vha);
6987
6988 if (test_and_clear_bit(N2N_LINK_RESET,
6989 &base_vha->dpc_flags)) {
6990 qla2x00_lip_reset(base_vha);
6991 }
6992
6993 ha->dpc_active = 0;
6994 end_loop:
6995 set_current_state(TASK_INTERRUPTIBLE);
6996 } /* End of while(1) */
6997 __set_current_state(TASK_RUNNING);
6998
6999 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
7000 "DPC handler exiting.\n");
7001
7002 /*
7003 * Make sure that nobody tries to wake us up again.
7004 */
7005 ha->dpc_active = 0;
7006
7007 /* Cleanup any residual CTX SRBs. */
7008 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
7009
7010 return 0;
7011 }
7012
7013 void
qla2xxx_wake_dpc(struct scsi_qla_host * vha)7014 qla2xxx_wake_dpc(struct scsi_qla_host *vha)
7015 {
7016 struct qla_hw_data *ha = vha->hw;
7017 struct task_struct *t = ha->dpc_thread;
7018
7019 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
7020 wake_up_process(t);
7021 }
7022
7023 /*
7024 * qla2x00_rst_aen
7025 * Processes asynchronous reset.
7026 *
7027 * Input:
7028 * ha = adapter block pointer.
7029 */
7030 static void
qla2x00_rst_aen(scsi_qla_host_t * vha)7031 qla2x00_rst_aen(scsi_qla_host_t *vha)
7032 {
7033 if (vha->flags.online && !vha->flags.reset_active &&
7034 !atomic_read(&vha->loop_down_timer) &&
7035 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
7036 do {
7037 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7038
7039 /*
7040 * Issue marker command only when we are going to start
7041 * the I/O.
7042 */
7043 vha->marker_needed = 1;
7044 } while (!atomic_read(&vha->loop_down_timer) &&
7045 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
7046 }
7047 }
7048
7049 /**************************************************************************
7050 * qla2x00_timer
7051 *
7052 * Description:
7053 * One second timer
7054 *
7055 * Context: Interrupt
7056 ***************************************************************************/
7057 void
qla2x00_timer(struct timer_list * t)7058 qla2x00_timer(struct timer_list *t)
7059 {
7060 scsi_qla_host_t *vha = from_timer(vha, t, timer);
7061 unsigned long cpu_flags = 0;
7062 int start_dpc = 0;
7063 int index;
7064 srb_t *sp;
7065 uint16_t w;
7066 struct qla_hw_data *ha = vha->hw;
7067 struct req_que *req;
7068
7069 if (ha->flags.eeh_busy) {
7070 ql_dbg(ql_dbg_timer, vha, 0x6000,
7071 "EEH = %d, restarting timer.\n",
7072 ha->flags.eeh_busy);
7073 qla2x00_restart_timer(vha, WATCH_INTERVAL);
7074 return;
7075 }
7076
7077 /*
7078 * Hardware read to raise pending EEH errors during mailbox waits. If
7079 * the read returns -1 then disable the board.
7080 */
7081 if (!pci_channel_offline(ha->pdev)) {
7082 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
7083 qla2x00_check_reg16_for_disconnect(vha, w);
7084 }
7085
7086 /* Make sure qla82xx_watchdog is run only for physical port */
7087 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
7088 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
7089 start_dpc++;
7090 if (IS_QLA82XX(ha))
7091 qla82xx_watchdog(vha);
7092 else if (IS_QLA8044(ha))
7093 qla8044_watchdog(vha);
7094 }
7095
7096 if (!vha->vp_idx && IS_QLAFX00(ha))
7097 qlafx00_timer_routine(vha);
7098
7099 /* Loop down handler. */
7100 if (atomic_read(&vha->loop_down_timer) > 0 &&
7101 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
7102 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
7103 && vha->flags.online) {
7104
7105 if (atomic_read(&vha->loop_down_timer) ==
7106 vha->loop_down_abort_time) {
7107
7108 ql_log(ql_log_info, vha, 0x6008,
7109 "Loop down - aborting the queues before time expires.\n");
7110
7111 if (!IS_QLA2100(ha) && vha->link_down_timeout)
7112 atomic_set(&vha->loop_state, LOOP_DEAD);
7113
7114 /*
7115 * Schedule an ISP abort to return any FCP2-device
7116 * commands.
7117 */
7118 /* NPIV - scan physical port only */
7119 if (!vha->vp_idx) {
7120 spin_lock_irqsave(&ha->hardware_lock,
7121 cpu_flags);
7122 req = ha->req_q_map[0];
7123 for (index = 1;
7124 index < req->num_outstanding_cmds;
7125 index++) {
7126 fc_port_t *sfcp;
7127
7128 sp = req->outstanding_cmds[index];
7129 if (!sp)
7130 continue;
7131 if (sp->cmd_type != TYPE_SRB)
7132 continue;
7133 if (sp->type != SRB_SCSI_CMD)
7134 continue;
7135 sfcp = sp->fcport;
7136 if (!(sfcp->flags & FCF_FCP2_DEVICE))
7137 continue;
7138
7139 if (IS_QLA82XX(ha))
7140 set_bit(FCOE_CTX_RESET_NEEDED,
7141 &vha->dpc_flags);
7142 else
7143 set_bit(ISP_ABORT_NEEDED,
7144 &vha->dpc_flags);
7145 break;
7146 }
7147 spin_unlock_irqrestore(&ha->hardware_lock,
7148 cpu_flags);
7149 }
7150 start_dpc++;
7151 }
7152
7153 /* if the loop has been down for 4 minutes, reinit adapter */
7154 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
7155 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7156 ql_log(ql_log_warn, vha, 0x6009,
7157 "Loop down - aborting ISP.\n");
7158
7159 if (IS_QLA82XX(ha))
7160 set_bit(FCOE_CTX_RESET_NEEDED,
7161 &vha->dpc_flags);
7162 else
7163 set_bit(ISP_ABORT_NEEDED,
7164 &vha->dpc_flags);
7165 }
7166 }
7167 ql_dbg(ql_dbg_timer, vha, 0x600a,
7168 "Loop down - seconds remaining %d.\n",
7169 atomic_read(&vha->loop_down_timer));
7170 }
7171 /* Check if beacon LED needs to be blinked for physical host only */
7172 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
7173 /* There is no beacon_blink function for ISP82xx */
7174 if (!IS_P3P_TYPE(ha)) {
7175 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
7176 start_dpc++;
7177 }
7178 }
7179
7180 /* Process any deferred work. */
7181 if (!list_empty(&vha->work_list)) {
7182 unsigned long flags;
7183 bool q = false;
7184
7185 spin_lock_irqsave(&vha->work_lock, flags);
7186 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
7187 q = true;
7188 spin_unlock_irqrestore(&vha->work_lock, flags);
7189 if (q)
7190 queue_work(vha->hw->wq, &vha->iocb_work);
7191 }
7192
7193 /*
7194 * FC-NVME
7195 * see if the active AEN count has changed from what was last reported.
7196 */
7197 index = atomic_read(&ha->nvme_active_aen_cnt);
7198 if (!vha->vp_idx &&
7199 (index != ha->nvme_last_rptd_aen) &&
7200 (index >= DEFAULT_ZIO_THRESHOLD) &&
7201 ha->zio_mode == QLA_ZIO_MODE_6 &&
7202 !ha->flags.host_shutting_down) {
7203 ql_log(ql_log_info, vha, 0x3002,
7204 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
7205 ha->nvme_last_rptd_aen);
7206 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
7207 set_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7208 start_dpc++;
7209 }
7210
7211 if (!vha->vp_idx &&
7212 atomic_read(&ha->zio_threshold) != ha->last_zio_threshold &&
7213 IS_ZIO_THRESHOLD_CAPABLE(ha)) {
7214 ql_log(ql_log_info, vha, 0x3002,
7215 "Sched: Set ZIO exchange threshold to %d.\n",
7216 ha->last_zio_threshold);
7217 ha->last_zio_threshold = atomic_read(&ha->zio_threshold);
7218 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7219 start_dpc++;
7220 }
7221
7222 /* Schedule the DPC routine if needed */
7223 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
7224 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
7225 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
7226 start_dpc ||
7227 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
7228 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
7229 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
7230 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
7231 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
7232 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) ||
7233 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) {
7234 ql_dbg(ql_dbg_timer, vha, 0x600b,
7235 "isp_abort_needed=%d loop_resync_needed=%d "
7236 "fcport_update_needed=%d start_dpc=%d "
7237 "reset_marker_needed=%d",
7238 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
7239 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
7240 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
7241 start_dpc,
7242 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
7243 ql_dbg(ql_dbg_timer, vha, 0x600c,
7244 "beacon_blink_needed=%d isp_unrecoverable=%d "
7245 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
7246 "relogin_needed=%d, Process_purex_iocb=%d.\n",
7247 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
7248 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
7249 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
7250 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
7251 test_bit(RELOGIN_NEEDED, &vha->dpc_flags),
7252 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags));
7253 qla2xxx_wake_dpc(vha);
7254 }
7255
7256 qla2x00_restart_timer(vha, WATCH_INTERVAL);
7257 }
7258
7259 /* Firmware interface routines. */
7260
7261 #define FW_ISP21XX 0
7262 #define FW_ISP22XX 1
7263 #define FW_ISP2300 2
7264 #define FW_ISP2322 3
7265 #define FW_ISP24XX 4
7266 #define FW_ISP25XX 5
7267 #define FW_ISP81XX 6
7268 #define FW_ISP82XX 7
7269 #define FW_ISP2031 8
7270 #define FW_ISP8031 9
7271 #define FW_ISP27XX 10
7272 #define FW_ISP28XX 11
7273
7274 #define FW_FILE_ISP21XX "ql2100_fw.bin"
7275 #define FW_FILE_ISP22XX "ql2200_fw.bin"
7276 #define FW_FILE_ISP2300 "ql2300_fw.bin"
7277 #define FW_FILE_ISP2322 "ql2322_fw.bin"
7278 #define FW_FILE_ISP24XX "ql2400_fw.bin"
7279 #define FW_FILE_ISP25XX "ql2500_fw.bin"
7280 #define FW_FILE_ISP81XX "ql8100_fw.bin"
7281 #define FW_FILE_ISP82XX "ql8200_fw.bin"
7282 #define FW_FILE_ISP2031 "ql2600_fw.bin"
7283 #define FW_FILE_ISP8031 "ql8300_fw.bin"
7284 #define FW_FILE_ISP27XX "ql2700_fw.bin"
7285 #define FW_FILE_ISP28XX "ql2800_fw.bin"
7286
7287
7288 static DEFINE_MUTEX(qla_fw_lock);
7289
7290 static struct fw_blob qla_fw_blobs[] = {
7291 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
7292 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
7293 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
7294 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
7295 { .name = FW_FILE_ISP24XX, },
7296 { .name = FW_FILE_ISP25XX, },
7297 { .name = FW_FILE_ISP81XX, },
7298 { .name = FW_FILE_ISP82XX, },
7299 { .name = FW_FILE_ISP2031, },
7300 { .name = FW_FILE_ISP8031, },
7301 { .name = FW_FILE_ISP27XX, },
7302 { .name = FW_FILE_ISP28XX, },
7303 { .name = NULL, },
7304 };
7305
7306 struct fw_blob *
qla2x00_request_firmware(scsi_qla_host_t * vha)7307 qla2x00_request_firmware(scsi_qla_host_t *vha)
7308 {
7309 struct qla_hw_data *ha = vha->hw;
7310 struct fw_blob *blob;
7311
7312 if (IS_QLA2100(ha)) {
7313 blob = &qla_fw_blobs[FW_ISP21XX];
7314 } else if (IS_QLA2200(ha)) {
7315 blob = &qla_fw_blobs[FW_ISP22XX];
7316 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
7317 blob = &qla_fw_blobs[FW_ISP2300];
7318 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
7319 blob = &qla_fw_blobs[FW_ISP2322];
7320 } else if (IS_QLA24XX_TYPE(ha)) {
7321 blob = &qla_fw_blobs[FW_ISP24XX];
7322 } else if (IS_QLA25XX(ha)) {
7323 blob = &qla_fw_blobs[FW_ISP25XX];
7324 } else if (IS_QLA81XX(ha)) {
7325 blob = &qla_fw_blobs[FW_ISP81XX];
7326 } else if (IS_QLA82XX(ha)) {
7327 blob = &qla_fw_blobs[FW_ISP82XX];
7328 } else if (IS_QLA2031(ha)) {
7329 blob = &qla_fw_blobs[FW_ISP2031];
7330 } else if (IS_QLA8031(ha)) {
7331 blob = &qla_fw_blobs[FW_ISP8031];
7332 } else if (IS_QLA27XX(ha)) {
7333 blob = &qla_fw_blobs[FW_ISP27XX];
7334 } else if (IS_QLA28XX(ha)) {
7335 blob = &qla_fw_blobs[FW_ISP28XX];
7336 } else {
7337 return NULL;
7338 }
7339
7340 if (!blob->name)
7341 return NULL;
7342
7343 mutex_lock(&qla_fw_lock);
7344 if (blob->fw)
7345 goto out;
7346
7347 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7348 ql_log(ql_log_warn, vha, 0x0063,
7349 "Failed to load firmware image (%s).\n", blob->name);
7350 blob->fw = NULL;
7351 blob = NULL;
7352 }
7353
7354 out:
7355 mutex_unlock(&qla_fw_lock);
7356 return blob;
7357 }
7358
7359 static void
qla2x00_release_firmware(void)7360 qla2x00_release_firmware(void)
7361 {
7362 struct fw_blob *blob;
7363
7364 mutex_lock(&qla_fw_lock);
7365 for (blob = qla_fw_blobs; blob->name; blob++)
7366 release_firmware(blob->fw);
7367 mutex_unlock(&qla_fw_lock);
7368 }
7369
qla_pci_error_cleanup(scsi_qla_host_t * vha)7370 static void qla_pci_error_cleanup(scsi_qla_host_t *vha)
7371 {
7372 struct qla_hw_data *ha = vha->hw;
7373 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
7374 struct qla_qpair *qpair = NULL;
7375 struct scsi_qla_host *vp;
7376 fc_port_t *fcport;
7377 int i;
7378 unsigned long flags;
7379
7380 ha->chip_reset++;
7381
7382 ha->base_qpair->chip_reset = ha->chip_reset;
7383 for (i = 0; i < ha->max_qpairs; i++) {
7384 if (ha->queue_pair_map[i])
7385 ha->queue_pair_map[i]->chip_reset =
7386 ha->base_qpair->chip_reset;
7387 }
7388
7389 /* purge MBox commands */
7390 if (atomic_read(&ha->num_pend_mbx_stage3)) {
7391 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
7392 complete(&ha->mbx_intr_comp);
7393 }
7394
7395 i = 0;
7396
7397 while (atomic_read(&ha->num_pend_mbx_stage3) ||
7398 atomic_read(&ha->num_pend_mbx_stage2) ||
7399 atomic_read(&ha->num_pend_mbx_stage1)) {
7400 msleep(20);
7401 i++;
7402 if (i > 50)
7403 break;
7404 }
7405
7406 ha->flags.purge_mbox = 0;
7407
7408 mutex_lock(&ha->mq_lock);
7409 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7410 qpair->online = 0;
7411 mutex_unlock(&ha->mq_lock);
7412
7413 qla2x00_mark_all_devices_lost(vha);
7414
7415 spin_lock_irqsave(&ha->vport_slock, flags);
7416 list_for_each_entry(vp, &ha->vp_list, list) {
7417 atomic_inc(&vp->vref_count);
7418 spin_unlock_irqrestore(&ha->vport_slock, flags);
7419 qla2x00_mark_all_devices_lost(vp);
7420 spin_lock_irqsave(&ha->vport_slock, flags);
7421 atomic_dec(&vp->vref_count);
7422 }
7423 spin_unlock_irqrestore(&ha->vport_slock, flags);
7424
7425 /* Clear all async request states across all VPs. */
7426 list_for_each_entry(fcport, &vha->vp_fcports, list)
7427 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7428
7429 spin_lock_irqsave(&ha->vport_slock, flags);
7430 list_for_each_entry(vp, &ha->vp_list, list) {
7431 atomic_inc(&vp->vref_count);
7432 spin_unlock_irqrestore(&ha->vport_slock, flags);
7433 list_for_each_entry(fcport, &vp->vp_fcports, list)
7434 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7435 spin_lock_irqsave(&ha->vport_slock, flags);
7436 atomic_dec(&vp->vref_count);
7437 }
7438 spin_unlock_irqrestore(&ha->vport_slock, flags);
7439 }
7440
7441
7442 static pci_ers_result_t
qla2xxx_pci_error_detected(struct pci_dev * pdev,pci_channel_state_t state)7443 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
7444 {
7445 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
7446 struct qla_hw_data *ha = vha->hw;
7447
7448 ql_dbg(ql_dbg_aer, vha, 0x9000,
7449 "PCI error detected, state %x.\n", state);
7450
7451 if (!atomic_read(&pdev->enable_cnt)) {
7452 ql_log(ql_log_info, vha, 0xffff,
7453 "PCI device is disabled,state %x\n", state);
7454 return PCI_ERS_RESULT_NEED_RESET;
7455 }
7456
7457 switch (state) {
7458 case pci_channel_io_normal:
7459 ha->flags.eeh_busy = 0;
7460 if (ql2xmqsupport || ql2xnvmeenable) {
7461 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
7462 qla2xxx_wake_dpc(vha);
7463 }
7464 return PCI_ERS_RESULT_CAN_RECOVER;
7465 case pci_channel_io_frozen:
7466 ha->flags.eeh_busy = 1;
7467 qla_pci_error_cleanup(vha);
7468 return PCI_ERS_RESULT_NEED_RESET;
7469 case pci_channel_io_perm_failure:
7470 ha->flags.pci_channel_io_perm_failure = 1;
7471 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
7472 if (ql2xmqsupport || ql2xnvmeenable) {
7473 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
7474 qla2xxx_wake_dpc(vha);
7475 }
7476 return PCI_ERS_RESULT_DISCONNECT;
7477 }
7478 return PCI_ERS_RESULT_NEED_RESET;
7479 }
7480
7481 static pci_ers_result_t
qla2xxx_pci_mmio_enabled(struct pci_dev * pdev)7482 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
7483 {
7484 int risc_paused = 0;
7485 uint32_t stat;
7486 unsigned long flags;
7487 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7488 struct qla_hw_data *ha = base_vha->hw;
7489 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
7490 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
7491
7492 if (IS_QLA82XX(ha))
7493 return PCI_ERS_RESULT_RECOVERED;
7494
7495 spin_lock_irqsave(&ha->hardware_lock, flags);
7496 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
7497 stat = rd_reg_word(®->hccr);
7498 if (stat & HCCR_RISC_PAUSE)
7499 risc_paused = 1;
7500 } else if (IS_QLA23XX(ha)) {
7501 stat = rd_reg_dword(®->u.isp2300.host_status);
7502 if (stat & HSR_RISC_PAUSED)
7503 risc_paused = 1;
7504 } else if (IS_FWI2_CAPABLE(ha)) {
7505 stat = rd_reg_dword(®24->host_status);
7506 if (stat & HSRX_RISC_PAUSED)
7507 risc_paused = 1;
7508 }
7509 spin_unlock_irqrestore(&ha->hardware_lock, flags);
7510
7511 if (risc_paused) {
7512 ql_log(ql_log_info, base_vha, 0x9003,
7513 "RISC paused -- mmio_enabled, Dumping firmware.\n");
7514 qla2xxx_dump_fw(base_vha);
7515
7516 return PCI_ERS_RESULT_NEED_RESET;
7517 } else
7518 return PCI_ERS_RESULT_RECOVERED;
7519 }
7520
7521 static pci_ers_result_t
qla2xxx_pci_slot_reset(struct pci_dev * pdev)7522 qla2xxx_pci_slot_reset(struct pci_dev *pdev)
7523 {
7524 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
7525 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7526 struct qla_hw_data *ha = base_vha->hw;
7527 int rc;
7528 struct qla_qpair *qpair = NULL;
7529
7530 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
7531 "Slot Reset.\n");
7532
7533 /* Workaround: qla2xxx driver which access hardware earlier
7534 * needs error state to be pci_channel_io_online.
7535 * Otherwise mailbox command timesout.
7536 */
7537 pdev->error_state = pci_channel_io_normal;
7538
7539 pci_restore_state(pdev);
7540
7541 /* pci_restore_state() clears the saved_state flag of the device
7542 * save restored state which resets saved_state flag
7543 */
7544 pci_save_state(pdev);
7545
7546 if (ha->mem_only)
7547 rc = pci_enable_device_mem(pdev);
7548 else
7549 rc = pci_enable_device(pdev);
7550
7551 if (rc) {
7552 ql_log(ql_log_warn, base_vha, 0x9005,
7553 "Can't re-enable PCI device after reset.\n");
7554 goto exit_slot_reset;
7555 }
7556
7557
7558 if (ha->isp_ops->pci_config(base_vha))
7559 goto exit_slot_reset;
7560
7561 mutex_lock(&ha->mq_lock);
7562 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7563 qpair->online = 1;
7564 mutex_unlock(&ha->mq_lock);
7565
7566 base_vha->flags.online = 1;
7567 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7568 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
7569 ret = PCI_ERS_RESULT_RECOVERED;
7570 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7571
7572
7573 exit_slot_reset:
7574 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
7575 "slot_reset return %x.\n", ret);
7576
7577 return ret;
7578 }
7579
7580 static void
qla2xxx_pci_resume(struct pci_dev * pdev)7581 qla2xxx_pci_resume(struct pci_dev *pdev)
7582 {
7583 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7584 struct qla_hw_data *ha = base_vha->hw;
7585 int ret;
7586
7587 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
7588 "pci_resume.\n");
7589
7590 ha->flags.eeh_busy = 0;
7591
7592 ret = qla2x00_wait_for_hba_online(base_vha);
7593 if (ret != QLA_SUCCESS) {
7594 ql_log(ql_log_fatal, base_vha, 0x9002,
7595 "The device failed to resume I/O from slot/link_reset.\n");
7596 }
7597 }
7598
7599 static void
qla_pci_reset_prepare(struct pci_dev * pdev)7600 qla_pci_reset_prepare(struct pci_dev *pdev)
7601 {
7602 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7603 struct qla_hw_data *ha = base_vha->hw;
7604 struct qla_qpair *qpair;
7605
7606 ql_log(ql_log_warn, base_vha, 0xffff,
7607 "%s.\n", __func__);
7608
7609 /*
7610 * PCI FLR/function reset is about to reset the
7611 * slot. Stop the chip to stop all DMA access.
7612 * It is assumed that pci_reset_done will be called
7613 * after FLR to resume Chip operation.
7614 */
7615 ha->flags.eeh_busy = 1;
7616 mutex_lock(&ha->mq_lock);
7617 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7618 qpair->online = 0;
7619 mutex_unlock(&ha->mq_lock);
7620
7621 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7622 qla2x00_abort_isp_cleanup(base_vha);
7623 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16);
7624 }
7625
7626 static void
qla_pci_reset_done(struct pci_dev * pdev)7627 qla_pci_reset_done(struct pci_dev *pdev)
7628 {
7629 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7630 struct qla_hw_data *ha = base_vha->hw;
7631 struct qla_qpair *qpair;
7632
7633 ql_log(ql_log_warn, base_vha, 0xffff,
7634 "%s.\n", __func__);
7635
7636 /*
7637 * FLR just completed by PCI layer. Resume adapter
7638 */
7639 ha->flags.eeh_busy = 0;
7640 mutex_lock(&ha->mq_lock);
7641 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7642 qpair->online = 1;
7643 mutex_unlock(&ha->mq_lock);
7644
7645 base_vha->flags.online = 1;
7646 ha->isp_ops->abort_isp(base_vha);
7647 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7648 }
7649
qla2xxx_map_queues(struct Scsi_Host * shost)7650 static int qla2xxx_map_queues(struct Scsi_Host *shost)
7651 {
7652 int rc;
7653 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
7654 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
7655
7656 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase)
7657 rc = blk_mq_map_queues(qmap);
7658 else
7659 rc = blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset);
7660 return rc;
7661 }
7662
7663 struct scsi_host_template qla2xxx_driver_template = {
7664 .module = THIS_MODULE,
7665 .name = QLA2XXX_DRIVER_NAME,
7666 .queuecommand = qla2xxx_queuecommand,
7667
7668 .eh_timed_out = fc_eh_timed_out,
7669 .eh_abort_handler = qla2xxx_eh_abort,
7670 .eh_device_reset_handler = qla2xxx_eh_device_reset,
7671 .eh_target_reset_handler = qla2xxx_eh_target_reset,
7672 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
7673 .eh_host_reset_handler = qla2xxx_eh_host_reset,
7674
7675 .slave_configure = qla2xxx_slave_configure,
7676
7677 .slave_alloc = qla2xxx_slave_alloc,
7678 .slave_destroy = qla2xxx_slave_destroy,
7679 .scan_finished = qla2xxx_scan_finished,
7680 .scan_start = qla2xxx_scan_start,
7681 .change_queue_depth = scsi_change_queue_depth,
7682 .map_queues = qla2xxx_map_queues,
7683 .this_id = -1,
7684 .cmd_per_lun = 3,
7685 .sg_tablesize = SG_ALL,
7686
7687 .max_sectors = 0xFFFF,
7688 .shost_attrs = qla2x00_host_attrs,
7689
7690 .supported_mode = MODE_INITIATOR,
7691 .track_queue_depth = 1,
7692 .cmd_size = sizeof(srb_t),
7693 };
7694
7695 static const struct pci_error_handlers qla2xxx_err_handler = {
7696 .error_detected = qla2xxx_pci_error_detected,
7697 .mmio_enabled = qla2xxx_pci_mmio_enabled,
7698 .slot_reset = qla2xxx_pci_slot_reset,
7699 .resume = qla2xxx_pci_resume,
7700 .reset_prepare = qla_pci_reset_prepare,
7701 .reset_done = qla_pci_reset_done,
7702 };
7703
7704 static struct pci_device_id qla2xxx_pci_tbl[] = {
7705 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
7706 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
7707 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
7708 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
7709 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
7710 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
7711 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
7712 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
7713 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
7714 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
7715 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
7716 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
7717 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
7718 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
7719 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
7720 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
7721 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
7722 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7723 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
7724 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
7725 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
7726 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
7727 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) },
7728 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) },
7729 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) },
7730 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) },
7731 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) },
7732 { 0 },
7733 };
7734 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
7735
7736 static struct pci_driver qla2xxx_pci_driver = {
7737 .name = QLA2XXX_DRIVER_NAME,
7738 .driver = {
7739 .owner = THIS_MODULE,
7740 },
7741 .id_table = qla2xxx_pci_tbl,
7742 .probe = qla2x00_probe_one,
7743 .remove = qla2x00_remove_one,
7744 .shutdown = qla2x00_shutdown,
7745 .err_handler = &qla2xxx_err_handler,
7746 };
7747
7748 static const struct file_operations apidev_fops = {
7749 .owner = THIS_MODULE,
7750 .llseek = noop_llseek,
7751 };
7752
7753 /**
7754 * qla2x00_module_init - Module initialization.
7755 **/
7756 static int __init
qla2x00_module_init(void)7757 qla2x00_module_init(void)
7758 {
7759 int ret = 0;
7760
7761 BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64);
7762 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64);
7763 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64);
7764 BUILD_BUG_ON(sizeof(cont_entry_t) != 64);
7765 BUILD_BUG_ON(sizeof(init_cb_t) != 96);
7766 BUILD_BUG_ON(sizeof(mrk_entry_t) != 64);
7767 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64);
7768 BUILD_BUG_ON(sizeof(request_t) != 64);
7769 BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64);
7770 BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64);
7771 BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64);
7772 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64);
7773 BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64);
7774 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64);
7775 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64);
7776 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64);
7777 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64);
7778 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64);
7779 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64);
7780 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64);
7781 BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2344);
7782 BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424);
7783 BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164);
7784 BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260);
7785 BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260);
7786 BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16);
7787 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64);
7788 BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256);
7789 BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24);
7790 BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256);
7791 BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288);
7792 BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216);
7793 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64);
7794 BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64);
7795 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64);
7796 BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64);
7797 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128);
7798 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128);
7799 BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64);
7800 BUILD_BUG_ON(sizeof(struct mbx_entry) != 64);
7801 BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252);
7802 BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64);
7803 BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512);
7804 BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512);
7805 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64);
7806 BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64);
7807 BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64);
7808 BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634);
7809 BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100);
7810 BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976);
7811 BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228);
7812 BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52);
7813 BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172);
7814 BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524);
7815 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8);
7816 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12);
7817 BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24);
7818 BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420);
7819 BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28);
7820 BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32);
7821 BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196);
7822 BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE);
7823 BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128);
7824 BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8);
7825 BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16);
7826 BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24);
7827 BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16);
7828 BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336);
7829 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064);
7830 BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64);
7831 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64);
7832 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64);
7833 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64);
7834 BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52);
7835 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56);
7836 BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64);
7837 BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64);
7838 BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64);
7839 BUILD_BUG_ON(sizeof(sts21_entry_t) != 64);
7840 BUILD_BUG_ON(sizeof(sts22_entry_t) != 64);
7841 BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64);
7842 BUILD_BUG_ON(sizeof(sts_entry_t) != 64);
7843 BUILD_BUG_ON(sizeof(sw_info_t) != 32);
7844 BUILD_BUG_ON(sizeof(target_id_t) != 2);
7845
7846 /* Allocate cache for SRBs. */
7847 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
7848 SLAB_HWCACHE_ALIGN, NULL);
7849 if (srb_cachep == NULL) {
7850 ql_log(ql_log_fatal, NULL, 0x0001,
7851 "Unable to allocate SRB cache...Failing load!.\n");
7852 return -ENOMEM;
7853 }
7854
7855 /* Initialize target kmem_cache and mem_pools */
7856 ret = qlt_init();
7857 if (ret < 0) {
7858 goto destroy_cache;
7859 } else if (ret > 0) {
7860 /*
7861 * If initiator mode is explictly disabled by qlt_init(),
7862 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
7863 * performing scsi_scan_target() during LOOP UP event.
7864 */
7865 qla2xxx_transport_functions.disable_target_scan = 1;
7866 qla2xxx_transport_vport_functions.disable_target_scan = 1;
7867 }
7868
7869 /* Derive version string. */
7870 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
7871 if (ql2xextended_error_logging)
7872 strcat(qla2x00_version_str, "-debug");
7873 if (ql2xextended_error_logging == 1)
7874 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
7875
7876 if (ql2x_ini_mode == QLA2XXX_INI_MODE_DUAL)
7877 qla_insert_tgt_attrs();
7878
7879 qla2xxx_transport_template =
7880 fc_attach_transport(&qla2xxx_transport_functions);
7881 if (!qla2xxx_transport_template) {
7882 ql_log(ql_log_fatal, NULL, 0x0002,
7883 "fc_attach_transport failed...Failing load!.\n");
7884 ret = -ENODEV;
7885 goto qlt_exit;
7886 }
7887
7888 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
7889 if (apidev_major < 0) {
7890 ql_log(ql_log_fatal, NULL, 0x0003,
7891 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
7892 }
7893
7894 qla2xxx_transport_vport_template =
7895 fc_attach_transport(&qla2xxx_transport_vport_functions);
7896 if (!qla2xxx_transport_vport_template) {
7897 ql_log(ql_log_fatal, NULL, 0x0004,
7898 "fc_attach_transport vport failed...Failing load!.\n");
7899 ret = -ENODEV;
7900 goto unreg_chrdev;
7901 }
7902 ql_log(ql_log_info, NULL, 0x0005,
7903 "QLogic Fibre Channel HBA Driver: %s.\n",
7904 qla2x00_version_str);
7905 ret = pci_register_driver(&qla2xxx_pci_driver);
7906 if (ret) {
7907 ql_log(ql_log_fatal, NULL, 0x0006,
7908 "pci_register_driver failed...ret=%d Failing load!.\n",
7909 ret);
7910 goto release_vport_transport;
7911 }
7912 return ret;
7913
7914 release_vport_transport:
7915 fc_release_transport(qla2xxx_transport_vport_template);
7916
7917 unreg_chrdev:
7918 if (apidev_major >= 0)
7919 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7920 fc_release_transport(qla2xxx_transport_template);
7921
7922 qlt_exit:
7923 qlt_exit();
7924
7925 destroy_cache:
7926 kmem_cache_destroy(srb_cachep);
7927 return ret;
7928 }
7929
7930 /**
7931 * qla2x00_module_exit - Module cleanup.
7932 **/
7933 static void __exit
qla2x00_module_exit(void)7934 qla2x00_module_exit(void)
7935 {
7936 pci_unregister_driver(&qla2xxx_pci_driver);
7937 qla2x00_release_firmware();
7938 kmem_cache_destroy(ctx_cachep);
7939 fc_release_transport(qla2xxx_transport_vport_template);
7940 if (apidev_major >= 0)
7941 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7942 fc_release_transport(qla2xxx_transport_template);
7943 qlt_exit();
7944 kmem_cache_destroy(srb_cachep);
7945 }
7946
7947 module_init(qla2x00_module_init);
7948 module_exit(qla2x00_module_exit);
7949
7950 MODULE_AUTHOR("QLogic Corporation");
7951 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
7952 MODULE_LICENSE("GPL");
7953 MODULE_FIRMWARE(FW_FILE_ISP21XX);
7954 MODULE_FIRMWARE(FW_FILE_ISP22XX);
7955 MODULE_FIRMWARE(FW_FILE_ISP2300);
7956 MODULE_FIRMWARE(FW_FILE_ISP2322);
7957 MODULE_FIRMWARE(FW_FILE_ISP24XX);
7958 MODULE_FIRMWARE(FW_FILE_ISP25XX);
7959