1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 *
4 * hda_intel.c - Implementation of primary alsa driver code base
5 * for Intel HD Audio.
6 *
7 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 *
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
11 *
12 * CONTACTS:
13 *
14 * Matt Jared matt.jared@intel.com
15 * Andy Kopp andy.kopp@intel.com
16 * Dan Kogan dan.d.kogan@intel.com
17 *
18 * CHANGES:
19 *
20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
21 */
22
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/moduleparam.h>
29 #include <linux/init.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/mutex.h>
33 #include <linux/io.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/clocksource.h>
36 #include <linux/time.h>
37 #include <linux/completion.h>
38 #include <linux/acpi.h>
39 #include <linux/pgtable.h>
40
41 #ifdef CONFIG_X86
42 /* for snoop control */
43 #include <asm/set_memory.h>
44 #include <asm/cpufeature.h>
45 #endif
46 #include <sound/core.h>
47 #include <sound/initval.h>
48 #include <sound/hdaudio.h>
49 #include <sound/hda_i915.h>
50 #include <sound/intel-dsp-config.h>
51 #include <linux/vgaarb.h>
52 #include <linux/vga_switcheroo.h>
53 #include <linux/firmware.h>
54 #include <sound/hda_codec.h>
55 #include "hda_controller.h"
56 #include "hda_intel.h"
57
58 #define CREATE_TRACE_POINTS
59 #include "hda_intel_trace.h"
60
61 /* position fix mode */
62 enum {
63 POS_FIX_AUTO,
64 POS_FIX_LPIB,
65 POS_FIX_POSBUF,
66 POS_FIX_VIACOMBO,
67 POS_FIX_COMBO,
68 POS_FIX_SKL,
69 POS_FIX_FIFO,
70 };
71
72 /* Defines for ATI HD Audio support in SB450 south bridge */
73 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
74 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
75
76 /* Defines for Nvidia HDA support */
77 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
78 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
79 #define NVIDIA_HDA_ISTRM_COH 0x4d
80 #define NVIDIA_HDA_OSTRM_COH 0x4c
81 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
82
83 /* Defines for Intel SCH HDA snoop control */
84 #define INTEL_HDA_CGCTL 0x48
85 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
86 #define INTEL_SCH_HDA_DEVC 0x78
87 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
88
89 /* Define VIA HD Audio Device ID*/
90 #define VIA_HDAC_DEVICE_ID 0x3288
91
92 /* max number of SDs */
93 /* ICH, ATI and VIA have 4 playback and 4 capture */
94 #define ICH6_NUM_CAPTURE 4
95 #define ICH6_NUM_PLAYBACK 4
96
97 /* ULI has 6 playback and 5 capture */
98 #define ULI_NUM_CAPTURE 5
99 #define ULI_NUM_PLAYBACK 6
100
101 /* ATI HDMI may have up to 8 playbacks and 0 capture */
102 #define ATIHDMI_NUM_CAPTURE 0
103 #define ATIHDMI_NUM_PLAYBACK 8
104
105 /* TERA has 4 playback and 3 capture */
106 #define TERA_NUM_CAPTURE 3
107 #define TERA_NUM_PLAYBACK 4
108
109
110 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
111 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
112 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
113 static char *model[SNDRV_CARDS];
114 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
115 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
116 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
117 static int probe_only[SNDRV_CARDS];
118 static int jackpoll_ms[SNDRV_CARDS];
119 static int single_cmd = -1;
120 static int enable_msi = -1;
121 #ifdef CONFIG_SND_HDA_PATCH_LOADER
122 static char *patch[SNDRV_CARDS];
123 #endif
124 #ifdef CONFIG_SND_HDA_INPUT_BEEP
125 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
126 CONFIG_SND_HDA_INPUT_BEEP_MODE};
127 #endif
128 static bool dmic_detect = 1;
129
130 module_param_array(index, int, NULL, 0444);
131 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
132 module_param_array(id, charp, NULL, 0444);
133 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
134 module_param_array(enable, bool, NULL, 0444);
135 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
136 module_param_array(model, charp, NULL, 0444);
137 MODULE_PARM_DESC(model, "Use the given board model.");
138 module_param_array(position_fix, int, NULL, 0444);
139 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
140 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
141 module_param_array(bdl_pos_adj, int, NULL, 0644);
142 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
143 module_param_array(probe_mask, int, NULL, 0444);
144 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
145 module_param_array(probe_only, int, NULL, 0444);
146 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
147 module_param_array(jackpoll_ms, int, NULL, 0444);
148 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
149 module_param(single_cmd, bint, 0444);
150 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
151 "(for debugging only).");
152 module_param(enable_msi, bint, 0444);
153 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
154 #ifdef CONFIG_SND_HDA_PATCH_LOADER
155 module_param_array(patch, charp, NULL, 0444);
156 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
157 #endif
158 #ifdef CONFIG_SND_HDA_INPUT_BEEP
159 module_param_array(beep_mode, bool, NULL, 0444);
160 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
161 "(0=off, 1=on) (default=1).");
162 #endif
163 module_param(dmic_detect, bool, 0444);
164 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
165 "(0=off, 1=on) (default=1); "
166 "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
167
168 #ifdef CONFIG_PM
169 static int param_set_xint(const char *val, const struct kernel_param *kp);
170 static const struct kernel_param_ops param_ops_xint = {
171 .set = param_set_xint,
172 .get = param_get_int,
173 };
174 #define param_check_xint param_check_int
175
176 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
177 module_param(power_save, xint, 0644);
178 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
179 "(in second, 0 = disable).");
180
181 static bool pm_blacklist = true;
182 module_param(pm_blacklist, bool, 0644);
183 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist");
184
185 /* reset the HD-audio controller in power save mode.
186 * this may give more power-saving, but will take longer time to
187 * wake up.
188 */
189 static bool power_save_controller = 1;
190 module_param(power_save_controller, bool, 0644);
191 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
192 #else
193 #define power_save 0
194 #endif /* CONFIG_PM */
195
196 static int align_buffer_size = -1;
197 module_param(align_buffer_size, bint, 0644);
198 MODULE_PARM_DESC(align_buffer_size,
199 "Force buffer and period sizes to be multiple of 128 bytes.");
200
201 #ifdef CONFIG_X86
202 static int hda_snoop = -1;
203 module_param_named(snoop, hda_snoop, bint, 0444);
204 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
205 #else
206 #define hda_snoop true
207 #endif
208
209
210 MODULE_LICENSE("GPL");
211 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
212 "{Intel, ICH6M},"
213 "{Intel, ICH7},"
214 "{Intel, ESB2},"
215 "{Intel, ICH8},"
216 "{Intel, ICH9},"
217 "{Intel, ICH10},"
218 "{Intel, PCH},"
219 "{Intel, CPT},"
220 "{Intel, PPT},"
221 "{Intel, LPT},"
222 "{Intel, LPT_LP},"
223 "{Intel, WPT_LP},"
224 "{Intel, SPT},"
225 "{Intel, SPT_LP},"
226 "{Intel, HPT},"
227 "{Intel, PBG},"
228 "{Intel, SCH},"
229 "{ATI, SB450},"
230 "{ATI, SB600},"
231 "{ATI, RS600},"
232 "{ATI, RS690},"
233 "{ATI, RS780},"
234 "{ATI, R600},"
235 "{ATI, RV630},"
236 "{ATI, RV610},"
237 "{ATI, RV670},"
238 "{ATI, RV635},"
239 "{ATI, RV620},"
240 "{ATI, RV770},"
241 "{VIA, VT8251},"
242 "{VIA, VT8237A},"
243 "{SiS, SIS966},"
244 "{ULI, M5461}}");
245 MODULE_DESCRIPTION("Intel HDA driver");
246
247 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
248 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
249 #define SUPPORT_VGA_SWITCHEROO
250 #endif
251 #endif
252
253
254 /*
255 */
256
257 /* driver types */
258 enum {
259 AZX_DRIVER_ICH,
260 AZX_DRIVER_PCH,
261 AZX_DRIVER_SCH,
262 AZX_DRIVER_SKL,
263 AZX_DRIVER_HDMI,
264 AZX_DRIVER_ATI,
265 AZX_DRIVER_ATIHDMI,
266 AZX_DRIVER_ATIHDMI_NS,
267 AZX_DRIVER_VIA,
268 AZX_DRIVER_SIS,
269 AZX_DRIVER_ULI,
270 AZX_DRIVER_NVIDIA,
271 AZX_DRIVER_TERA,
272 AZX_DRIVER_CTX,
273 AZX_DRIVER_CTHDA,
274 AZX_DRIVER_CMEDIA,
275 AZX_DRIVER_ZHAOXIN,
276 AZX_DRIVER_GENERIC,
277 AZX_NUM_DRIVERS, /* keep this as last entry */
278 };
279
280 #define azx_get_snoop_type(chip) \
281 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
282 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
283
284 /* quirks for old Intel chipsets */
285 #define AZX_DCAPS_INTEL_ICH \
286 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
287
288 /* quirks for Intel PCH */
289 #define AZX_DCAPS_INTEL_PCH_BASE \
290 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
291 AZX_DCAPS_SNOOP_TYPE(SCH))
292
293 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
294 #define AZX_DCAPS_INTEL_PCH_NOPM \
295 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
296
297 /* PCH for HSW/BDW; with runtime PM */
298 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
299 #define AZX_DCAPS_INTEL_PCH \
300 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
301
302 /* HSW HDMI */
303 #define AZX_DCAPS_INTEL_HASWELL \
304 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
305 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
306 AZX_DCAPS_SNOOP_TYPE(SCH))
307
308 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
309 #define AZX_DCAPS_INTEL_BROADWELL \
310 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
311 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
312 AZX_DCAPS_SNOOP_TYPE(SCH))
313
314 #define AZX_DCAPS_INTEL_BAYTRAIL \
315 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
316
317 #define AZX_DCAPS_INTEL_BRASWELL \
318 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
319 AZX_DCAPS_I915_COMPONENT)
320
321 #define AZX_DCAPS_INTEL_SKYLAKE \
322 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
323 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
324
325 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE
326
327 /* quirks for ATI SB / AMD Hudson */
328 #define AZX_DCAPS_PRESET_ATI_SB \
329 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\
330 AZX_DCAPS_SNOOP_TYPE(ATI))
331
332 /* quirks for ATI/AMD HDMI */
333 #define AZX_DCAPS_PRESET_ATI_HDMI \
334 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\
335 AZX_DCAPS_NO_MSI64)
336
337 /* quirks for ATI HDMI with snoop off */
338 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
339 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
340
341 /* quirks for AMD SB */
342 #define AZX_DCAPS_PRESET_AMD_SB \
343 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\
344 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\
345 AZX_DCAPS_RETRY_PROBE)
346
347 /* quirks for Nvidia */
348 #define AZX_DCAPS_PRESET_NVIDIA \
349 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
350 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
351
352 #define AZX_DCAPS_PRESET_CTHDA \
353 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
354 AZX_DCAPS_NO_64BIT |\
355 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
356
357 /*
358 * vga_switcheroo support
359 */
360 #ifdef SUPPORT_VGA_SWITCHEROO
361 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
362 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power)
363 #else
364 #define use_vga_switcheroo(chip) 0
365 #define needs_eld_notify_link(chip) false
366 #endif
367
368 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
369 ((pci)->device == 0x0c0c) || \
370 ((pci)->device == 0x0d0c) || \
371 ((pci)->device == 0x160c) || \
372 ((pci)->device == 0x490d))
373
374 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
375
376 static const char * const driver_short_names[] = {
377 [AZX_DRIVER_ICH] = "HDA Intel",
378 [AZX_DRIVER_PCH] = "HDA Intel PCH",
379 [AZX_DRIVER_SCH] = "HDA Intel MID",
380 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
381 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
382 [AZX_DRIVER_ATI] = "HDA ATI SB",
383 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
384 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
385 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
386 [AZX_DRIVER_SIS] = "HDA SIS966",
387 [AZX_DRIVER_ULI] = "HDA ULI M5461",
388 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
389 [AZX_DRIVER_TERA] = "HDA Teradici",
390 [AZX_DRIVER_CTX] = "HDA Creative",
391 [AZX_DRIVER_CTHDA] = "HDA Creative",
392 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
393 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
394 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
395 };
396
397 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
398 static void set_default_power_save(struct azx *chip);
399
400 /*
401 * initialize the PCI registers
402 */
403 /* update bits in a PCI register byte */
update_pci_byte(struct pci_dev * pci,unsigned int reg,unsigned char mask,unsigned char val)404 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
405 unsigned char mask, unsigned char val)
406 {
407 unsigned char data;
408
409 pci_read_config_byte(pci, reg, &data);
410 data &= ~mask;
411 data |= (val & mask);
412 pci_write_config_byte(pci, reg, data);
413 }
414
azx_init_pci(struct azx * chip)415 static void azx_init_pci(struct azx *chip)
416 {
417 int snoop_type = azx_get_snoop_type(chip);
418
419 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
420 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
421 * Ensuring these bits are 0 clears playback static on some HD Audio
422 * codecs.
423 * The PCI register TCSEL is defined in the Intel manuals.
424 */
425 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
426 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
427 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
428 }
429
430 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
431 * we need to enable snoop.
432 */
433 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
434 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
435 azx_snoop(chip));
436 update_pci_byte(chip->pci,
437 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
438 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
439 }
440
441 /* For NVIDIA HDA, enable snoop */
442 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
443 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
444 azx_snoop(chip));
445 update_pci_byte(chip->pci,
446 NVIDIA_HDA_TRANSREG_ADDR,
447 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
448 update_pci_byte(chip->pci,
449 NVIDIA_HDA_ISTRM_COH,
450 0x01, NVIDIA_HDA_ENABLE_COHBIT);
451 update_pci_byte(chip->pci,
452 NVIDIA_HDA_OSTRM_COH,
453 0x01, NVIDIA_HDA_ENABLE_COHBIT);
454 }
455
456 /* Enable SCH/PCH snoop if needed */
457 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
458 unsigned short snoop;
459 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
460 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
461 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
462 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
463 if (!azx_snoop(chip))
464 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
465 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
466 pci_read_config_word(chip->pci,
467 INTEL_SCH_HDA_DEVC, &snoop);
468 }
469 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
470 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
471 "Disabled" : "Enabled");
472 }
473 }
474
475 /*
476 * In BXT-P A0, HD-Audio DMA requests is later than expected,
477 * and makes an audio stream sensitive to system latencies when
478 * 24/32 bits are playing.
479 * Adjusting threshold of DMA fifo to force the DMA request
480 * sooner to improve latency tolerance at the expense of power.
481 */
bxt_reduce_dma_latency(struct azx * chip)482 static void bxt_reduce_dma_latency(struct azx *chip)
483 {
484 u32 val;
485
486 val = azx_readl(chip, VS_EM4L);
487 val &= (0x3 << 20);
488 azx_writel(chip, VS_EM4L, val);
489 }
490
491 /*
492 * ML_LCAP bits:
493 * bit 0: 6 MHz Supported
494 * bit 1: 12 MHz Supported
495 * bit 2: 24 MHz Supported
496 * bit 3: 48 MHz Supported
497 * bit 4: 96 MHz Supported
498 * bit 5: 192 MHz Supported
499 */
intel_get_lctl_scf(struct azx * chip)500 static int intel_get_lctl_scf(struct azx *chip)
501 {
502 struct hdac_bus *bus = azx_bus(chip);
503 static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
504 u32 val, t;
505 int i;
506
507 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
508
509 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
510 t = preferred_bits[i];
511 if (val & (1 << t))
512 return t;
513 }
514
515 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
516 return 0;
517 }
518
intel_ml_lctl_set_power(struct azx * chip,int state)519 static int intel_ml_lctl_set_power(struct azx *chip, int state)
520 {
521 struct hdac_bus *bus = azx_bus(chip);
522 u32 val;
523 int timeout;
524
525 /*
526 * the codecs are sharing the first link setting by default
527 * If other links are enabled for stream, they need similar fix
528 */
529 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
530 val &= ~AZX_MLCTL_SPA;
531 val |= state << AZX_MLCTL_SPA_SHIFT;
532 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
533 /* wait for CPA */
534 timeout = 50;
535 while (timeout) {
536 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
537 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
538 return 0;
539 timeout--;
540 udelay(10);
541 }
542
543 return -1;
544 }
545
intel_init_lctl(struct azx * chip)546 static void intel_init_lctl(struct azx *chip)
547 {
548 struct hdac_bus *bus = azx_bus(chip);
549 u32 val;
550 int ret;
551
552 /* 0. check lctl register value is correct or not */
553 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
554 /* if SCF is already set, let's use it */
555 if ((val & ML_LCTL_SCF_MASK) != 0)
556 return;
557
558 /*
559 * Before operating on SPA, CPA must match SPA.
560 * Any deviation may result in undefined behavior.
561 */
562 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
563 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
564 return;
565
566 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
567 ret = intel_ml_lctl_set_power(chip, 0);
568 udelay(100);
569 if (ret)
570 goto set_spa;
571
572 /* 2. update SCF to select a properly audio clock*/
573 val &= ~ML_LCTL_SCF_MASK;
574 val |= intel_get_lctl_scf(chip);
575 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
576
577 set_spa:
578 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
579 intel_ml_lctl_set_power(chip, 1);
580 udelay(100);
581 }
582
hda_intel_init_chip(struct azx * chip,bool full_reset)583 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
584 {
585 struct hdac_bus *bus = azx_bus(chip);
586 struct pci_dev *pci = chip->pci;
587 u32 val;
588
589 snd_hdac_set_codec_wakeup(bus, true);
590 if (chip->driver_type == AZX_DRIVER_SKL) {
591 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
592 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
593 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
594 }
595 azx_init_chip(chip, full_reset);
596 if (chip->driver_type == AZX_DRIVER_SKL) {
597 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
598 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
599 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
600 }
601
602 snd_hdac_set_codec_wakeup(bus, false);
603
604 /* reduce dma latency to avoid noise */
605 if (IS_BXT(pci))
606 bxt_reduce_dma_latency(chip);
607
608 if (bus->mlcap != NULL)
609 intel_init_lctl(chip);
610 }
611
612 /* calculate runtime delay from LPIB */
azx_get_delay_from_lpib(struct azx * chip,struct azx_dev * azx_dev,unsigned int pos)613 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
614 unsigned int pos)
615 {
616 struct snd_pcm_substream *substream = azx_dev->core.substream;
617 int stream = substream->stream;
618 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
619 int delay;
620
621 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
622 delay = pos - lpib_pos;
623 else
624 delay = lpib_pos - pos;
625 if (delay < 0) {
626 if (delay >= azx_dev->core.delay_negative_threshold)
627 delay = 0;
628 else
629 delay += azx_dev->core.bufsize;
630 }
631
632 if (delay >= azx_dev->core.period_bytes) {
633 dev_info(chip->card->dev,
634 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
635 delay, azx_dev->core.period_bytes);
636 delay = 0;
637 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
638 chip->get_delay[stream] = NULL;
639 }
640
641 return bytes_to_frames(substream->runtime, delay);
642 }
643
644 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
645
646 /* called from IRQ */
azx_position_check(struct azx * chip,struct azx_dev * azx_dev)647 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
648 {
649 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
650 int ok;
651
652 ok = azx_position_ok(chip, azx_dev);
653 if (ok == 1) {
654 azx_dev->irq_pending = 0;
655 return ok;
656 } else if (ok == 0) {
657 /* bogus IRQ, process it later */
658 azx_dev->irq_pending = 1;
659 schedule_work(&hda->irq_pending_work);
660 }
661 return 0;
662 }
663
664 #define display_power(chip, enable) \
665 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
666
667 /*
668 * Check whether the current DMA position is acceptable for updating
669 * periods. Returns non-zero if it's OK.
670 *
671 * Many HD-audio controllers appear pretty inaccurate about
672 * the update-IRQ timing. The IRQ is issued before actually the
673 * data is processed. So, we need to process it afterwords in a
674 * workqueue.
675 */
azx_position_ok(struct azx * chip,struct azx_dev * azx_dev)676 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
677 {
678 struct snd_pcm_substream *substream = azx_dev->core.substream;
679 int stream = substream->stream;
680 u32 wallclk;
681 unsigned int pos;
682
683 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
684 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
685 return -1; /* bogus (too early) interrupt */
686
687 if (chip->get_position[stream])
688 pos = chip->get_position[stream](chip, azx_dev);
689 else { /* use the position buffer as default */
690 pos = azx_get_pos_posbuf(chip, azx_dev);
691 if (!pos || pos == (u32)-1) {
692 dev_info(chip->card->dev,
693 "Invalid position buffer, using LPIB read method instead.\n");
694 chip->get_position[stream] = azx_get_pos_lpib;
695 if (chip->get_position[0] == azx_get_pos_lpib &&
696 chip->get_position[1] == azx_get_pos_lpib)
697 azx_bus(chip)->use_posbuf = false;
698 pos = azx_get_pos_lpib(chip, azx_dev);
699 chip->get_delay[stream] = NULL;
700 } else {
701 chip->get_position[stream] = azx_get_pos_posbuf;
702 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
703 chip->get_delay[stream] = azx_get_delay_from_lpib;
704 }
705 }
706
707 if (pos >= azx_dev->core.bufsize)
708 pos = 0;
709
710 if (WARN_ONCE(!azx_dev->core.period_bytes,
711 "hda-intel: zero azx_dev->period_bytes"))
712 return -1; /* this shouldn't happen! */
713 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
714 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
715 /* NG - it's below the first next period boundary */
716 return chip->bdl_pos_adj ? 0 : -1;
717 azx_dev->core.start_wallclk += wallclk;
718 return 1; /* OK, it's fine */
719 }
720
721 /*
722 * The work for pending PCM period updates.
723 */
azx_irq_pending_work(struct work_struct * work)724 static void azx_irq_pending_work(struct work_struct *work)
725 {
726 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
727 struct azx *chip = &hda->chip;
728 struct hdac_bus *bus = azx_bus(chip);
729 struct hdac_stream *s;
730 int pending, ok;
731
732 if (!hda->irq_pending_warned) {
733 dev_info(chip->card->dev,
734 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
735 chip->card->number);
736 hda->irq_pending_warned = 1;
737 }
738
739 for (;;) {
740 pending = 0;
741 spin_lock_irq(&bus->reg_lock);
742 list_for_each_entry(s, &bus->stream_list, list) {
743 struct azx_dev *azx_dev = stream_to_azx_dev(s);
744 if (!azx_dev->irq_pending ||
745 !s->substream ||
746 !s->running)
747 continue;
748 ok = azx_position_ok(chip, azx_dev);
749 if (ok > 0) {
750 azx_dev->irq_pending = 0;
751 spin_unlock(&bus->reg_lock);
752 snd_pcm_period_elapsed(s->substream);
753 spin_lock(&bus->reg_lock);
754 } else if (ok < 0) {
755 pending = 0; /* too early */
756 } else
757 pending++;
758 }
759 spin_unlock_irq(&bus->reg_lock);
760 if (!pending)
761 return;
762 msleep(1);
763 }
764 }
765
766 /* clear irq_pending flags and assure no on-going workq */
azx_clear_irq_pending(struct azx * chip)767 static void azx_clear_irq_pending(struct azx *chip)
768 {
769 struct hdac_bus *bus = azx_bus(chip);
770 struct hdac_stream *s;
771
772 spin_lock_irq(&bus->reg_lock);
773 list_for_each_entry(s, &bus->stream_list, list) {
774 struct azx_dev *azx_dev = stream_to_azx_dev(s);
775 azx_dev->irq_pending = 0;
776 }
777 spin_unlock_irq(&bus->reg_lock);
778 }
779
azx_acquire_irq(struct azx * chip,int do_disconnect)780 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
781 {
782 struct hdac_bus *bus = azx_bus(chip);
783
784 if (request_irq(chip->pci->irq, azx_interrupt,
785 chip->msi ? 0 : IRQF_SHARED,
786 chip->card->irq_descr, chip)) {
787 dev_err(chip->card->dev,
788 "unable to grab IRQ %d, disabling device\n",
789 chip->pci->irq);
790 if (do_disconnect)
791 snd_card_disconnect(chip->card);
792 return -1;
793 }
794 bus->irq = chip->pci->irq;
795 chip->card->sync_irq = bus->irq;
796 pci_intx(chip->pci, !chip->msi);
797 return 0;
798 }
799
800 /* get the current DMA position with correction on VIA chips */
azx_via_get_position(struct azx * chip,struct azx_dev * azx_dev)801 static unsigned int azx_via_get_position(struct azx *chip,
802 struct azx_dev *azx_dev)
803 {
804 unsigned int link_pos, mini_pos, bound_pos;
805 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
806 unsigned int fifo_size;
807
808 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
809 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
810 /* Playback, no problem using link position */
811 return link_pos;
812 }
813
814 /* Capture */
815 /* For new chipset,
816 * use mod to get the DMA position just like old chipset
817 */
818 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
819 mod_dma_pos %= azx_dev->core.period_bytes;
820
821 fifo_size = azx_stream(azx_dev)->fifo_size - 1;
822
823 if (azx_dev->insufficient) {
824 /* Link position never gather than FIFO size */
825 if (link_pos <= fifo_size)
826 return 0;
827
828 azx_dev->insufficient = 0;
829 }
830
831 if (link_pos <= fifo_size)
832 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
833 else
834 mini_pos = link_pos - fifo_size;
835
836 /* Find nearest previous boudary */
837 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
838 mod_link_pos = link_pos % azx_dev->core.period_bytes;
839 if (mod_link_pos >= fifo_size)
840 bound_pos = link_pos - mod_link_pos;
841 else if (mod_dma_pos >= mod_mini_pos)
842 bound_pos = mini_pos - mod_mini_pos;
843 else {
844 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
845 if (bound_pos >= azx_dev->core.bufsize)
846 bound_pos = 0;
847 }
848
849 /* Calculate real DMA position we want */
850 return bound_pos + mod_dma_pos;
851 }
852
853 #define AMD_FIFO_SIZE 32
854
855 /* get the current DMA position with FIFO size correction */
azx_get_pos_fifo(struct azx * chip,struct azx_dev * azx_dev)856 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
857 {
858 struct snd_pcm_substream *substream = azx_dev->core.substream;
859 struct snd_pcm_runtime *runtime = substream->runtime;
860 unsigned int pos, delay;
861
862 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
863 if (!runtime)
864 return pos;
865
866 runtime->delay = AMD_FIFO_SIZE;
867 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
868 if (azx_dev->insufficient) {
869 if (pos < delay) {
870 delay = pos;
871 runtime->delay = bytes_to_frames(runtime, pos);
872 } else {
873 azx_dev->insufficient = 0;
874 }
875 }
876
877 /* correct the DMA position for capture stream */
878 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
879 if (pos < delay)
880 pos += azx_dev->core.bufsize;
881 pos -= delay;
882 }
883
884 return pos;
885 }
886
azx_get_delay_from_fifo(struct azx * chip,struct azx_dev * azx_dev,unsigned int pos)887 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
888 unsigned int pos)
889 {
890 struct snd_pcm_substream *substream = azx_dev->core.substream;
891
892 /* just read back the calculated value in the above */
893 return substream->runtime->delay;
894 }
895
azx_skl_get_dpib_pos(struct azx * chip,struct azx_dev * azx_dev)896 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
897 struct azx_dev *azx_dev)
898 {
899 return _snd_hdac_chip_readl(azx_bus(chip),
900 AZX_REG_VS_SDXDPIB_XBASE +
901 (AZX_REG_VS_SDXDPIB_XINTERVAL *
902 azx_dev->core.index));
903 }
904
905 /* get the current DMA position with correction on SKL+ chips */
azx_get_pos_skl(struct azx * chip,struct azx_dev * azx_dev)906 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
907 {
908 /* DPIB register gives a more accurate position for playback */
909 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
910 return azx_skl_get_dpib_pos(chip, azx_dev);
911
912 /* For capture, we need to read posbuf, but it requires a delay
913 * for the possible boundary overlap; the read of DPIB fetches the
914 * actual posbuf
915 */
916 udelay(20);
917 azx_skl_get_dpib_pos(chip, azx_dev);
918 return azx_get_pos_posbuf(chip, azx_dev);
919 }
920
921 #ifdef CONFIG_PM
922 static DEFINE_MUTEX(card_list_lock);
923 static LIST_HEAD(card_list);
924
azx_add_card_list(struct azx * chip)925 static void azx_add_card_list(struct azx *chip)
926 {
927 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
928 mutex_lock(&card_list_lock);
929 list_add(&hda->list, &card_list);
930 mutex_unlock(&card_list_lock);
931 }
932
azx_del_card_list(struct azx * chip)933 static void azx_del_card_list(struct azx *chip)
934 {
935 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
936 mutex_lock(&card_list_lock);
937 list_del_init(&hda->list);
938 mutex_unlock(&card_list_lock);
939 }
940
941 /* trigger power-save check at writing parameter */
param_set_xint(const char * val,const struct kernel_param * kp)942 static int param_set_xint(const char *val, const struct kernel_param *kp)
943 {
944 struct hda_intel *hda;
945 struct azx *chip;
946 int prev = power_save;
947 int ret = param_set_int(val, kp);
948
949 if (ret || prev == power_save)
950 return ret;
951
952 mutex_lock(&card_list_lock);
953 list_for_each_entry(hda, &card_list, list) {
954 chip = &hda->chip;
955 if (!hda->probe_continued || chip->disabled)
956 continue;
957 snd_hda_set_power_save(&chip->bus, power_save * 1000);
958 }
959 mutex_unlock(&card_list_lock);
960 return 0;
961 }
962
963 /*
964 * power management
965 */
azx_is_pm_ready(struct snd_card * card)966 static bool azx_is_pm_ready(struct snd_card *card)
967 {
968 struct azx *chip;
969 struct hda_intel *hda;
970
971 if (!card)
972 return false;
973 chip = card->private_data;
974 hda = container_of(chip, struct hda_intel, chip);
975 if (chip->disabled || hda->init_failed || !chip->running)
976 return false;
977 return true;
978 }
979
__azx_runtime_suspend(struct azx * chip)980 static void __azx_runtime_suspend(struct azx *chip)
981 {
982 azx_stop_chip(chip);
983 azx_enter_link_reset(chip);
984 azx_clear_irq_pending(chip);
985 display_power(chip, false);
986 }
987
__azx_runtime_resume(struct azx * chip)988 static void __azx_runtime_resume(struct azx *chip)
989 {
990 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
991 struct hdac_bus *bus = azx_bus(chip);
992 struct hda_codec *codec;
993 int status;
994
995 display_power(chip, true);
996 if (hda->need_i915_power)
997 snd_hdac_i915_set_bclk(bus);
998
999 /* Read STATESTS before controller reset */
1000 status = azx_readw(chip, STATESTS);
1001
1002 azx_init_pci(chip);
1003 hda_intel_init_chip(chip, true);
1004
1005 /* Avoid codec resume if runtime resume is for system suspend */
1006 if (!chip->pm_prepared) {
1007 list_for_each_codec(codec, &chip->bus) {
1008 if (codec->relaxed_resume)
1009 continue;
1010
1011 if (codec->forced_resume || (status & (1 << codec->addr)))
1012 pm_request_resume(hda_codec_dev(codec));
1013 }
1014 }
1015
1016 /* power down again for link-controlled chips */
1017 if (!hda->need_i915_power)
1018 display_power(chip, false);
1019 }
1020
1021 #ifdef CONFIG_PM_SLEEP
azx_prepare(struct device * dev)1022 static int azx_prepare(struct device *dev)
1023 {
1024 struct snd_card *card = dev_get_drvdata(dev);
1025 struct azx *chip;
1026
1027 if (!azx_is_pm_ready(card))
1028 return 0;
1029
1030 chip = card->private_data;
1031 chip->pm_prepared = 1;
1032 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1033
1034 flush_work(&azx_bus(chip)->unsol_work);
1035
1036 /* HDA controller always requires different WAKEEN for runtime suspend
1037 * and system suspend, so don't use direct-complete here.
1038 */
1039 return 0;
1040 }
1041
azx_complete(struct device * dev)1042 static void azx_complete(struct device *dev)
1043 {
1044 struct snd_card *card = dev_get_drvdata(dev);
1045 struct azx *chip;
1046
1047 if (!azx_is_pm_ready(card))
1048 return;
1049
1050 chip = card->private_data;
1051 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1052 chip->pm_prepared = 0;
1053 }
1054
azx_suspend(struct device * dev)1055 static int azx_suspend(struct device *dev)
1056 {
1057 struct snd_card *card = dev_get_drvdata(dev);
1058 struct azx *chip;
1059 struct hdac_bus *bus;
1060
1061 if (!azx_is_pm_ready(card))
1062 return 0;
1063
1064 chip = card->private_data;
1065 bus = azx_bus(chip);
1066 __azx_runtime_suspend(chip);
1067 if (bus->irq >= 0) {
1068 free_irq(bus->irq, chip);
1069 bus->irq = -1;
1070 chip->card->sync_irq = -1;
1071 }
1072
1073 if (chip->msi)
1074 pci_disable_msi(chip->pci);
1075
1076 trace_azx_suspend(chip);
1077 return 0;
1078 }
1079
azx_resume(struct device * dev)1080 static int azx_resume(struct device *dev)
1081 {
1082 struct snd_card *card = dev_get_drvdata(dev);
1083 struct azx *chip;
1084
1085 if (!azx_is_pm_ready(card))
1086 return 0;
1087
1088 chip = card->private_data;
1089 if (chip->msi)
1090 if (pci_enable_msi(chip->pci) < 0)
1091 chip->msi = 0;
1092 if (azx_acquire_irq(chip, 1) < 0)
1093 return -EIO;
1094
1095 __azx_runtime_resume(chip);
1096
1097 trace_azx_resume(chip);
1098 return 0;
1099 }
1100
1101 /* put codec down to D3 at hibernation for Intel SKL+;
1102 * otherwise BIOS may still access the codec and screw up the driver
1103 */
azx_freeze_noirq(struct device * dev)1104 static int azx_freeze_noirq(struct device *dev)
1105 {
1106 struct snd_card *card = dev_get_drvdata(dev);
1107 struct azx *chip = card->private_data;
1108 struct pci_dev *pci = to_pci_dev(dev);
1109
1110 if (!azx_is_pm_ready(card))
1111 return 0;
1112 if (chip->driver_type == AZX_DRIVER_SKL)
1113 pci_set_power_state(pci, PCI_D3hot);
1114
1115 return 0;
1116 }
1117
azx_thaw_noirq(struct device * dev)1118 static int azx_thaw_noirq(struct device *dev)
1119 {
1120 struct snd_card *card = dev_get_drvdata(dev);
1121 struct azx *chip = card->private_data;
1122 struct pci_dev *pci = to_pci_dev(dev);
1123
1124 if (!azx_is_pm_ready(card))
1125 return 0;
1126 if (chip->driver_type == AZX_DRIVER_SKL)
1127 pci_set_power_state(pci, PCI_D0);
1128
1129 return 0;
1130 }
1131 #endif /* CONFIG_PM_SLEEP */
1132
azx_runtime_suspend(struct device * dev)1133 static int azx_runtime_suspend(struct device *dev)
1134 {
1135 struct snd_card *card = dev_get_drvdata(dev);
1136 struct azx *chip;
1137
1138 if (!azx_is_pm_ready(card))
1139 return 0;
1140 chip = card->private_data;
1141
1142 /* enable controller wake up event */
1143 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK);
1144
1145 __azx_runtime_suspend(chip);
1146 trace_azx_runtime_suspend(chip);
1147 return 0;
1148 }
1149
azx_runtime_resume(struct device * dev)1150 static int azx_runtime_resume(struct device *dev)
1151 {
1152 struct snd_card *card = dev_get_drvdata(dev);
1153 struct azx *chip;
1154
1155 if (!azx_is_pm_ready(card))
1156 return 0;
1157 chip = card->private_data;
1158 __azx_runtime_resume(chip);
1159
1160 /* disable controller Wake Up event*/
1161 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK);
1162
1163 trace_azx_runtime_resume(chip);
1164 return 0;
1165 }
1166
azx_runtime_idle(struct device * dev)1167 static int azx_runtime_idle(struct device *dev)
1168 {
1169 struct snd_card *card = dev_get_drvdata(dev);
1170 struct azx *chip;
1171 struct hda_intel *hda;
1172
1173 if (!card)
1174 return 0;
1175
1176 chip = card->private_data;
1177 hda = container_of(chip, struct hda_intel, chip);
1178 if (chip->disabled || hda->init_failed)
1179 return 0;
1180
1181 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1182 azx_bus(chip)->codec_powered || !chip->running)
1183 return -EBUSY;
1184
1185 /* ELD notification gets broken when HD-audio bus is off */
1186 if (needs_eld_notify_link(chip))
1187 return -EBUSY;
1188
1189 return 0;
1190 }
1191
1192 static const struct dev_pm_ops azx_pm = {
1193 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1194 #ifdef CONFIG_PM_SLEEP
1195 .prepare = azx_prepare,
1196 .complete = azx_complete,
1197 .freeze_noirq = azx_freeze_noirq,
1198 .thaw_noirq = azx_thaw_noirq,
1199 #endif
1200 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1201 };
1202
1203 #define AZX_PM_OPS &azx_pm
1204 #else
1205 #define azx_add_card_list(chip) /* NOP */
1206 #define azx_del_card_list(chip) /* NOP */
1207 #define AZX_PM_OPS NULL
1208 #endif /* CONFIG_PM */
1209
1210
1211 static int azx_probe_continue(struct azx *chip);
1212
1213 #ifdef SUPPORT_VGA_SWITCHEROO
1214 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1215
azx_vs_set_state(struct pci_dev * pci,enum vga_switcheroo_state state)1216 static void azx_vs_set_state(struct pci_dev *pci,
1217 enum vga_switcheroo_state state)
1218 {
1219 struct snd_card *card = pci_get_drvdata(pci);
1220 struct azx *chip = card->private_data;
1221 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1222 struct hda_codec *codec;
1223 bool disabled;
1224
1225 wait_for_completion(&hda->probe_wait);
1226 if (hda->init_failed)
1227 return;
1228
1229 disabled = (state == VGA_SWITCHEROO_OFF);
1230 if (chip->disabled == disabled)
1231 return;
1232
1233 if (!hda->probe_continued) {
1234 chip->disabled = disabled;
1235 if (!disabled) {
1236 dev_info(chip->card->dev,
1237 "Start delayed initialization\n");
1238 if (azx_probe_continue(chip) < 0)
1239 dev_err(chip->card->dev, "initialization error\n");
1240 }
1241 } else {
1242 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1243 disabled ? "Disabling" : "Enabling");
1244 if (disabled) {
1245 list_for_each_codec(codec, &chip->bus) {
1246 pm_runtime_suspend(hda_codec_dev(codec));
1247 pm_runtime_disable(hda_codec_dev(codec));
1248 }
1249 pm_runtime_suspend(card->dev);
1250 pm_runtime_disable(card->dev);
1251 /* when we get suspended by vga_switcheroo we end up in D3cold,
1252 * however we have no ACPI handle, so pci/acpi can't put us there,
1253 * put ourselves there */
1254 pci->current_state = PCI_D3cold;
1255 chip->disabled = true;
1256 if (snd_hda_lock_devices(&chip->bus))
1257 dev_warn(chip->card->dev,
1258 "Cannot lock devices!\n");
1259 } else {
1260 snd_hda_unlock_devices(&chip->bus);
1261 chip->disabled = false;
1262 pm_runtime_enable(card->dev);
1263 list_for_each_codec(codec, &chip->bus) {
1264 pm_runtime_enable(hda_codec_dev(codec));
1265 pm_runtime_resume(hda_codec_dev(codec));
1266 }
1267 }
1268 }
1269 }
1270
azx_vs_can_switch(struct pci_dev * pci)1271 static bool azx_vs_can_switch(struct pci_dev *pci)
1272 {
1273 struct snd_card *card = pci_get_drvdata(pci);
1274 struct azx *chip = card->private_data;
1275 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1276
1277 wait_for_completion(&hda->probe_wait);
1278 if (hda->init_failed)
1279 return false;
1280 if (chip->disabled || !hda->probe_continued)
1281 return true;
1282 if (snd_hda_lock_devices(&chip->bus))
1283 return false;
1284 snd_hda_unlock_devices(&chip->bus);
1285 return true;
1286 }
1287
1288 /*
1289 * The discrete GPU cannot power down unless the HDA controller runtime
1290 * suspends, so activate runtime PM on codecs even if power_save == 0.
1291 */
setup_vga_switcheroo_runtime_pm(struct azx * chip)1292 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1293 {
1294 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1295 struct hda_codec *codec;
1296
1297 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
1298 list_for_each_codec(codec, &chip->bus)
1299 codec->auto_runtime_pm = 1;
1300 /* reset the power save setup */
1301 if (chip->running)
1302 set_default_power_save(chip);
1303 }
1304 }
1305
azx_vs_gpu_bound(struct pci_dev * pci,enum vga_switcheroo_client_id client_id)1306 static void azx_vs_gpu_bound(struct pci_dev *pci,
1307 enum vga_switcheroo_client_id client_id)
1308 {
1309 struct snd_card *card = pci_get_drvdata(pci);
1310 struct azx *chip = card->private_data;
1311
1312 if (client_id == VGA_SWITCHEROO_DIS)
1313 chip->bus.keep_power = 0;
1314 setup_vga_switcheroo_runtime_pm(chip);
1315 }
1316
init_vga_switcheroo(struct azx * chip)1317 static void init_vga_switcheroo(struct azx *chip)
1318 {
1319 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1320 struct pci_dev *p = get_bound_vga(chip->pci);
1321 struct pci_dev *parent;
1322 if (p) {
1323 dev_info(chip->card->dev,
1324 "Handle vga_switcheroo audio client\n");
1325 hda->use_vga_switcheroo = 1;
1326
1327 /* cleared in either gpu_bound op or codec probe, or when its
1328 * upstream port has _PR3 (i.e. dGPU).
1329 */
1330 parent = pci_upstream_bridge(p);
1331 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
1332 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1333 pci_dev_put(p);
1334 }
1335 }
1336
1337 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1338 .set_gpu_state = azx_vs_set_state,
1339 .can_switch = azx_vs_can_switch,
1340 .gpu_bound = azx_vs_gpu_bound,
1341 };
1342
register_vga_switcheroo(struct azx * chip)1343 static int register_vga_switcheroo(struct azx *chip)
1344 {
1345 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1346 struct pci_dev *p;
1347 int err;
1348
1349 if (!hda->use_vga_switcheroo)
1350 return 0;
1351
1352 p = get_bound_vga(chip->pci);
1353 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1354 pci_dev_put(p);
1355
1356 if (err < 0)
1357 return err;
1358 hda->vga_switcheroo_registered = 1;
1359
1360 return 0;
1361 }
1362 #else
1363 #define init_vga_switcheroo(chip) /* NOP */
1364 #define register_vga_switcheroo(chip) 0
1365 #define check_hdmi_disabled(pci) false
1366 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
1367 #endif /* SUPPORT_VGA_SWITCHER */
1368
1369 /*
1370 * destructor
1371 */
azx_free(struct azx * chip)1372 static void azx_free(struct azx *chip)
1373 {
1374 struct pci_dev *pci = chip->pci;
1375 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1376 struct hdac_bus *bus = azx_bus(chip);
1377
1378 if (hda->freed)
1379 return;
1380
1381 if (azx_has_pm_runtime(chip) && chip->running)
1382 pm_runtime_get_noresume(&pci->dev);
1383 chip->running = 0;
1384
1385 azx_del_card_list(chip);
1386
1387 hda->init_failed = 1; /* to be sure */
1388 complete_all(&hda->probe_wait);
1389
1390 if (use_vga_switcheroo(hda)) {
1391 if (chip->disabled && hda->probe_continued)
1392 snd_hda_unlock_devices(&chip->bus);
1393 if (hda->vga_switcheroo_registered)
1394 vga_switcheroo_unregister_client(chip->pci);
1395 }
1396
1397 if (bus->chip_init) {
1398 azx_clear_irq_pending(chip);
1399 azx_stop_all_streams(chip);
1400 azx_stop_chip(chip);
1401 }
1402
1403 if (bus->irq >= 0)
1404 free_irq(bus->irq, (void*)chip);
1405 if (chip->msi)
1406 pci_disable_msi(chip->pci);
1407 iounmap(bus->remap_addr);
1408
1409 azx_free_stream_pages(chip);
1410 azx_free_streams(chip);
1411 snd_hdac_bus_exit(bus);
1412
1413 if (chip->region_requested)
1414 pci_release_regions(chip->pci);
1415
1416 pci_disable_device(chip->pci);
1417 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1418 release_firmware(chip->fw);
1419 #endif
1420 display_power(chip, false);
1421
1422 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1423 snd_hdac_i915_exit(bus);
1424
1425 hda->freed = 1;
1426 }
1427
azx_dev_disconnect(struct snd_device * device)1428 static int azx_dev_disconnect(struct snd_device *device)
1429 {
1430 struct azx *chip = device->device_data;
1431 struct hdac_bus *bus = azx_bus(chip);
1432
1433 chip->bus.shutdown = 1;
1434 cancel_work_sync(&bus->unsol_work);
1435
1436 return 0;
1437 }
1438
azx_dev_free(struct snd_device * device)1439 static int azx_dev_free(struct snd_device *device)
1440 {
1441 azx_free(device->device_data);
1442 return 0;
1443 }
1444
1445 #ifdef SUPPORT_VGA_SWITCHEROO
1446 #ifdef CONFIG_ACPI
1447 /* ATPX is in the integrated GPU's namespace */
atpx_present(void)1448 static bool atpx_present(void)
1449 {
1450 struct pci_dev *pdev = NULL;
1451 acpi_handle dhandle, atpx_handle;
1452 acpi_status status;
1453
1454 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
1455 dhandle = ACPI_HANDLE(&pdev->dev);
1456 if (dhandle) {
1457 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1458 if (!ACPI_FAILURE(status)) {
1459 pci_dev_put(pdev);
1460 return true;
1461 }
1462 }
1463 }
1464 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
1465 dhandle = ACPI_HANDLE(&pdev->dev);
1466 if (dhandle) {
1467 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1468 if (!ACPI_FAILURE(status)) {
1469 pci_dev_put(pdev);
1470 return true;
1471 }
1472 }
1473 }
1474 return false;
1475 }
1476 #else
atpx_present(void)1477 static bool atpx_present(void)
1478 {
1479 return false;
1480 }
1481 #endif
1482
1483 /*
1484 * Check of disabled HDMI controller by vga_switcheroo
1485 */
get_bound_vga(struct pci_dev * pci)1486 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1487 {
1488 struct pci_dev *p;
1489
1490 /* check only discrete GPU */
1491 switch (pci->vendor) {
1492 case PCI_VENDOR_ID_ATI:
1493 case PCI_VENDOR_ID_AMD:
1494 if (pci->devfn == 1) {
1495 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1496 pci->bus->number, 0);
1497 if (p) {
1498 /* ATPX is in the integrated GPU's ACPI namespace
1499 * rather than the dGPU's namespace. However,
1500 * the dGPU is the one who is involved in
1501 * vgaswitcheroo.
1502 */
1503 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
1504 atpx_present())
1505 return p;
1506 pci_dev_put(p);
1507 }
1508 }
1509 break;
1510 case PCI_VENDOR_ID_NVIDIA:
1511 if (pci->devfn == 1) {
1512 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1513 pci->bus->number, 0);
1514 if (p) {
1515 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1516 return p;
1517 pci_dev_put(p);
1518 }
1519 }
1520 break;
1521 }
1522 return NULL;
1523 }
1524
check_hdmi_disabled(struct pci_dev * pci)1525 static bool check_hdmi_disabled(struct pci_dev *pci)
1526 {
1527 bool vga_inactive = false;
1528 struct pci_dev *p = get_bound_vga(pci);
1529
1530 if (p) {
1531 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1532 vga_inactive = true;
1533 pci_dev_put(p);
1534 }
1535 return vga_inactive;
1536 }
1537 #endif /* SUPPORT_VGA_SWITCHEROO */
1538
1539 /*
1540 * allow/deny-listing for position_fix
1541 */
1542 static const struct snd_pci_quirk position_fix_list[] = {
1543 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1544 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1545 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1546 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1547 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1548 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1549 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1550 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1551 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1552 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1553 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1554 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1555 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1556 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1557 {}
1558 };
1559
check_position_fix(struct azx * chip,int fix)1560 static int check_position_fix(struct azx *chip, int fix)
1561 {
1562 const struct snd_pci_quirk *q;
1563
1564 switch (fix) {
1565 case POS_FIX_AUTO:
1566 case POS_FIX_LPIB:
1567 case POS_FIX_POSBUF:
1568 case POS_FIX_VIACOMBO:
1569 case POS_FIX_COMBO:
1570 case POS_FIX_SKL:
1571 case POS_FIX_FIFO:
1572 return fix;
1573 }
1574
1575 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1576 if (q) {
1577 dev_info(chip->card->dev,
1578 "position_fix set to %d for device %04x:%04x\n",
1579 q->value, q->subvendor, q->subdevice);
1580 return q->value;
1581 }
1582
1583 /* Check VIA/ATI HD Audio Controller exist */
1584 if (chip->driver_type == AZX_DRIVER_VIA) {
1585 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1586 return POS_FIX_VIACOMBO;
1587 }
1588 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1589 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1590 return POS_FIX_FIFO;
1591 }
1592 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1593 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1594 return POS_FIX_LPIB;
1595 }
1596 if (chip->driver_type == AZX_DRIVER_SKL) {
1597 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1598 return POS_FIX_SKL;
1599 }
1600 return POS_FIX_AUTO;
1601 }
1602
assign_position_fix(struct azx * chip,int fix)1603 static void assign_position_fix(struct azx *chip, int fix)
1604 {
1605 static const azx_get_pos_callback_t callbacks[] = {
1606 [POS_FIX_AUTO] = NULL,
1607 [POS_FIX_LPIB] = azx_get_pos_lpib,
1608 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1609 [POS_FIX_VIACOMBO] = azx_via_get_position,
1610 [POS_FIX_COMBO] = azx_get_pos_lpib,
1611 [POS_FIX_SKL] = azx_get_pos_skl,
1612 [POS_FIX_FIFO] = azx_get_pos_fifo,
1613 };
1614
1615 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1616
1617 /* combo mode uses LPIB only for playback */
1618 if (fix == POS_FIX_COMBO)
1619 chip->get_position[1] = NULL;
1620
1621 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1622 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1623 chip->get_delay[0] = chip->get_delay[1] =
1624 azx_get_delay_from_lpib;
1625 }
1626
1627 if (fix == POS_FIX_FIFO)
1628 chip->get_delay[0] = chip->get_delay[1] =
1629 azx_get_delay_from_fifo;
1630 }
1631
1632 /*
1633 * deny-lists for probe_mask
1634 */
1635 static const struct snd_pci_quirk probe_mask_list[] = {
1636 /* Thinkpad often breaks the controller communication when accessing
1637 * to the non-working (or non-existing) modem codec slot.
1638 */
1639 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1640 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1641 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1642 /* broken BIOS */
1643 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1644 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1645 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1646 /* forced codec slots */
1647 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1648 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1649 /* WinFast VP200 H (Teradici) user reported broken communication */
1650 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1651 {}
1652 };
1653
1654 #define AZX_FORCE_CODEC_MASK 0x100
1655
check_probe_mask(struct azx * chip,int dev)1656 static void check_probe_mask(struct azx *chip, int dev)
1657 {
1658 const struct snd_pci_quirk *q;
1659
1660 chip->codec_probe_mask = probe_mask[dev];
1661 if (chip->codec_probe_mask == -1) {
1662 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1663 if (q) {
1664 dev_info(chip->card->dev,
1665 "probe_mask set to 0x%x for device %04x:%04x\n",
1666 q->value, q->subvendor, q->subdevice);
1667 chip->codec_probe_mask = q->value;
1668 }
1669 }
1670
1671 /* check forced option */
1672 if (chip->codec_probe_mask != -1 &&
1673 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1674 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1675 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1676 (int)azx_bus(chip)->codec_mask);
1677 }
1678 }
1679
1680 /*
1681 * allow/deny-list for enable_msi
1682 */
1683 static const struct snd_pci_quirk msi_deny_list[] = {
1684 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1685 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1686 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1687 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1688 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1689 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1690 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1691 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1692 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1693 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1694 {}
1695 };
1696
check_msi(struct azx * chip)1697 static void check_msi(struct azx *chip)
1698 {
1699 const struct snd_pci_quirk *q;
1700
1701 if (enable_msi >= 0) {
1702 chip->msi = !!enable_msi;
1703 return;
1704 }
1705 chip->msi = 1; /* enable MSI as default */
1706 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list);
1707 if (q) {
1708 dev_info(chip->card->dev,
1709 "msi for device %04x:%04x set to %d\n",
1710 q->subvendor, q->subdevice, q->value);
1711 chip->msi = q->value;
1712 return;
1713 }
1714
1715 /* NVidia chipsets seem to cause troubles with MSI */
1716 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1717 dev_info(chip->card->dev, "Disabling MSI\n");
1718 chip->msi = 0;
1719 }
1720 }
1721
1722 /* check the snoop mode availability */
azx_check_snoop_available(struct azx * chip)1723 static void azx_check_snoop_available(struct azx *chip)
1724 {
1725 int snoop = hda_snoop;
1726
1727 if (snoop >= 0) {
1728 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1729 snoop ? "snoop" : "non-snoop");
1730 chip->snoop = snoop;
1731 chip->uc_buffer = !snoop;
1732 return;
1733 }
1734
1735 snoop = true;
1736 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1737 chip->driver_type == AZX_DRIVER_VIA) {
1738 /* force to non-snoop mode for a new VIA controller
1739 * when BIOS is set
1740 */
1741 u8 val;
1742 pci_read_config_byte(chip->pci, 0x42, &val);
1743 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1744 chip->pci->revision == 0x20))
1745 snoop = false;
1746 }
1747
1748 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1749 snoop = false;
1750
1751 chip->snoop = snoop;
1752 if (!snoop) {
1753 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1754 /* C-Media requires non-cached pages only for CORB/RIRB */
1755 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1756 chip->uc_buffer = true;
1757 }
1758 }
1759
azx_probe_work(struct work_struct * work)1760 static void azx_probe_work(struct work_struct *work)
1761 {
1762 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work);
1763 azx_probe_continue(&hda->chip);
1764 }
1765
default_bdl_pos_adj(struct azx * chip)1766 static int default_bdl_pos_adj(struct azx *chip)
1767 {
1768 /* some exceptions: Atoms seem problematic with value 1 */
1769 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1770 switch (chip->pci->device) {
1771 case 0x0f04: /* Baytrail */
1772 case 0x2284: /* Braswell */
1773 return 32;
1774 }
1775 }
1776
1777 switch (chip->driver_type) {
1778 case AZX_DRIVER_ICH:
1779 case AZX_DRIVER_PCH:
1780 return 1;
1781 default:
1782 return 32;
1783 }
1784 }
1785
1786 /*
1787 * constructor
1788 */
1789 static const struct hda_controller_ops pci_hda_ops;
1790
azx_create(struct snd_card * card,struct pci_dev * pci,int dev,unsigned int driver_caps,struct azx ** rchip)1791 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1792 int dev, unsigned int driver_caps,
1793 struct azx **rchip)
1794 {
1795 static const struct snd_device_ops ops = {
1796 .dev_disconnect = azx_dev_disconnect,
1797 .dev_free = azx_dev_free,
1798 };
1799 struct hda_intel *hda;
1800 struct azx *chip;
1801 int err;
1802
1803 *rchip = NULL;
1804
1805 err = pci_enable_device(pci);
1806 if (err < 0)
1807 return err;
1808
1809 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
1810 if (!hda) {
1811 pci_disable_device(pci);
1812 return -ENOMEM;
1813 }
1814
1815 chip = &hda->chip;
1816 mutex_init(&chip->open_mutex);
1817 chip->card = card;
1818 chip->pci = pci;
1819 chip->ops = &pci_hda_ops;
1820 chip->driver_caps = driver_caps;
1821 chip->driver_type = driver_caps & 0xff;
1822 check_msi(chip);
1823 chip->dev_index = dev;
1824 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1825 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1826 INIT_LIST_HEAD(&chip->pcm_list);
1827 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1828 INIT_LIST_HEAD(&hda->list);
1829 init_vga_switcheroo(chip);
1830 init_completion(&hda->probe_wait);
1831
1832 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1833
1834 check_probe_mask(chip, dev);
1835
1836 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1837 chip->fallback_to_single_cmd = 1;
1838 else /* explicitly set to single_cmd or not */
1839 chip->single_cmd = single_cmd;
1840
1841 azx_check_snoop_available(chip);
1842
1843 if (bdl_pos_adj[dev] < 0)
1844 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1845 else
1846 chip->bdl_pos_adj = bdl_pos_adj[dev];
1847
1848 err = azx_bus_init(chip, model[dev]);
1849 if (err < 0) {
1850 pci_disable_device(pci);
1851 return err;
1852 }
1853
1854 /* use the non-cached pages in non-snoop mode */
1855 if (!azx_snoop(chip))
1856 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC;
1857
1858 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1859 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1860 chip->bus.core.needs_damn_long_delay = 1;
1861 }
1862
1863 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1864 if (err < 0) {
1865 dev_err(card->dev, "Error creating device [card]!\n");
1866 azx_free(chip);
1867 return err;
1868 }
1869
1870 /* continue probing in work context as may trigger request module */
1871 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work);
1872
1873 *rchip = chip;
1874
1875 return 0;
1876 }
1877
azx_first_init(struct azx * chip)1878 static int azx_first_init(struct azx *chip)
1879 {
1880 int dev = chip->dev_index;
1881 struct pci_dev *pci = chip->pci;
1882 struct snd_card *card = chip->card;
1883 struct hdac_bus *bus = azx_bus(chip);
1884 int err;
1885 unsigned short gcap;
1886 unsigned int dma_bits = 64;
1887
1888 #if BITS_PER_LONG != 64
1889 /* Fix up base address on ULI M5461 */
1890 if (chip->driver_type == AZX_DRIVER_ULI) {
1891 u16 tmp3;
1892 pci_read_config_word(pci, 0x40, &tmp3);
1893 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1894 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1895 }
1896 #endif
1897
1898 err = pci_request_regions(pci, "ICH HD audio");
1899 if (err < 0)
1900 return err;
1901 chip->region_requested = 1;
1902
1903 bus->addr = pci_resource_start(pci, 0);
1904 bus->remap_addr = pci_ioremap_bar(pci, 0);
1905 if (bus->remap_addr == NULL) {
1906 dev_err(card->dev, "ioremap error\n");
1907 return -ENXIO;
1908 }
1909
1910 if (chip->driver_type == AZX_DRIVER_SKL)
1911 snd_hdac_bus_parse_capabilities(bus);
1912
1913 /*
1914 * Some Intel CPUs has always running timer (ART) feature and
1915 * controller may have Global time sync reporting capability, so
1916 * check both of these before declaring synchronized time reporting
1917 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1918 */
1919 chip->gts_present = false;
1920
1921 #ifdef CONFIG_X86
1922 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1923 chip->gts_present = true;
1924 #endif
1925
1926 if (chip->msi) {
1927 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1928 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1929 pci->no_64bit_msi = true;
1930 }
1931 if (pci_enable_msi(pci) < 0)
1932 chip->msi = 0;
1933 }
1934
1935 pci_set_master(pci);
1936
1937 gcap = azx_readw(chip, GCAP);
1938 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1939
1940 /* AMD devices support 40 or 48bit DMA, take the safe one */
1941 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1942 dma_bits = 40;
1943
1944 /* disable SB600 64bit support for safety */
1945 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1946 struct pci_dev *p_smbus;
1947 dma_bits = 40;
1948 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1949 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1950 NULL);
1951 if (p_smbus) {
1952 if (p_smbus->revision < 0x30)
1953 gcap &= ~AZX_GCAP_64OK;
1954 pci_dev_put(p_smbus);
1955 }
1956 }
1957
1958 /* NVidia hardware normally only supports up to 40 bits of DMA */
1959 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1960 dma_bits = 40;
1961
1962 /* disable 64bit DMA address on some devices */
1963 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1964 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1965 gcap &= ~AZX_GCAP_64OK;
1966 }
1967
1968 /* disable buffer size rounding to 128-byte multiples if supported */
1969 if (align_buffer_size >= 0)
1970 chip->align_buffer_size = !!align_buffer_size;
1971 else {
1972 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1973 chip->align_buffer_size = 0;
1974 else
1975 chip->align_buffer_size = 1;
1976 }
1977
1978 /* allow 64bit DMA address if supported by H/W */
1979 if (!(gcap & AZX_GCAP_64OK))
1980 dma_bits = 32;
1981 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1982 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1983 } else {
1984 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1985 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1986 }
1987
1988 /* read number of streams from GCAP register instead of using
1989 * hardcoded value
1990 */
1991 chip->capture_streams = (gcap >> 8) & 0x0f;
1992 chip->playback_streams = (gcap >> 12) & 0x0f;
1993 if (!chip->playback_streams && !chip->capture_streams) {
1994 /* gcap didn't give any info, switching to old method */
1995
1996 switch (chip->driver_type) {
1997 case AZX_DRIVER_ULI:
1998 chip->playback_streams = ULI_NUM_PLAYBACK;
1999 chip->capture_streams = ULI_NUM_CAPTURE;
2000 break;
2001 case AZX_DRIVER_ATIHDMI:
2002 case AZX_DRIVER_ATIHDMI_NS:
2003 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2004 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2005 break;
2006 case AZX_DRIVER_GENERIC:
2007 default:
2008 chip->playback_streams = ICH6_NUM_PLAYBACK;
2009 chip->capture_streams = ICH6_NUM_CAPTURE;
2010 break;
2011 }
2012 }
2013 chip->capture_index_offset = 0;
2014 chip->playback_index_offset = chip->capture_streams;
2015 chip->num_streams = chip->playback_streams + chip->capture_streams;
2016
2017 /* sanity check for the SDxCTL.STRM field overflow */
2018 if (chip->num_streams > 15 &&
2019 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
2020 dev_warn(chip->card->dev, "number of I/O streams is %d, "
2021 "forcing separate stream tags", chip->num_streams);
2022 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
2023 }
2024
2025 /* initialize streams */
2026 err = azx_init_streams(chip);
2027 if (err < 0)
2028 return err;
2029
2030 err = azx_alloc_stream_pages(chip);
2031 if (err < 0)
2032 return err;
2033
2034 /* initialize chip */
2035 azx_init_pci(chip);
2036
2037 snd_hdac_i915_set_bclk(bus);
2038
2039 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
2040
2041 /* codec detection */
2042 if (!azx_bus(chip)->codec_mask) {
2043 dev_err(card->dev, "no codecs found!\n");
2044 /* keep running the rest for the runtime PM */
2045 }
2046
2047 if (azx_acquire_irq(chip, 0) < 0)
2048 return -EBUSY;
2049
2050 strcpy(card->driver, "HDA-Intel");
2051 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2052 sizeof(card->shortname));
2053 snprintf(card->longname, sizeof(card->longname),
2054 "%s at 0x%lx irq %i",
2055 card->shortname, bus->addr, bus->irq);
2056
2057 return 0;
2058 }
2059
2060 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2061 /* callback from request_firmware_nowait() */
azx_firmware_cb(const struct firmware * fw,void * context)2062 static void azx_firmware_cb(const struct firmware *fw, void *context)
2063 {
2064 struct snd_card *card = context;
2065 struct azx *chip = card->private_data;
2066
2067 if (fw)
2068 chip->fw = fw;
2069 else
2070 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
2071 if (!chip->disabled) {
2072 /* continue probing */
2073 azx_probe_continue(chip);
2074 }
2075 }
2076 #endif
2077
disable_msi_reset_irq(struct azx * chip)2078 static int disable_msi_reset_irq(struct azx *chip)
2079 {
2080 struct hdac_bus *bus = azx_bus(chip);
2081 int err;
2082
2083 free_irq(bus->irq, chip);
2084 bus->irq = -1;
2085 chip->card->sync_irq = -1;
2086 pci_disable_msi(chip->pci);
2087 chip->msi = 0;
2088 err = azx_acquire_irq(chip, 1);
2089 if (err < 0)
2090 return err;
2091
2092 return 0;
2093 }
2094
pcm_mmap_prepare(struct snd_pcm_substream * substream,struct vm_area_struct * area)2095 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2096 struct vm_area_struct *area)
2097 {
2098 #ifdef CONFIG_X86
2099 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2100 struct azx *chip = apcm->chip;
2101 if (chip->uc_buffer)
2102 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2103 #endif
2104 }
2105
2106 /* Denylist for skipping the whole probe:
2107 * some HD-audio PCI entries are exposed without any codecs, and such devices
2108 * should be ignored from the beginning.
2109 */
2110 static const struct pci_device_id driver_denylist[] = {
2111 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2112 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2113 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
2114 {}
2115 };
2116
2117 static const struct hda_controller_ops pci_hda_ops = {
2118 .disable_msi_reset_irq = disable_msi_reset_irq,
2119 .pcm_mmap_prepare = pcm_mmap_prepare,
2120 .position_check = azx_position_check,
2121 };
2122
azx_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)2123 static int azx_probe(struct pci_dev *pci,
2124 const struct pci_device_id *pci_id)
2125 {
2126 static int dev;
2127 struct snd_card *card;
2128 struct hda_intel *hda;
2129 struct azx *chip;
2130 bool schedule_probe;
2131 int err;
2132
2133 if (pci_match_id(driver_denylist, pci)) {
2134 dev_info(&pci->dev, "Skipping the device on the denylist\n");
2135 return -ENODEV;
2136 }
2137
2138 if (dev >= SNDRV_CARDS)
2139 return -ENODEV;
2140 if (!enable[dev]) {
2141 dev++;
2142 return -ENOENT;
2143 }
2144
2145 /*
2146 * stop probe if another Intel's DSP driver should be activated
2147 */
2148 if (dmic_detect) {
2149 err = snd_intel_dsp_driver_probe(pci);
2150 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) {
2151 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n");
2152 return -ENODEV;
2153 }
2154 } else {
2155 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
2156 }
2157
2158 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2159 0, &card);
2160 if (err < 0) {
2161 dev_err(&pci->dev, "Error creating card!\n");
2162 return err;
2163 }
2164
2165 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2166 if (err < 0)
2167 goto out_free;
2168 card->private_data = chip;
2169 hda = container_of(chip, struct hda_intel, chip);
2170
2171 pci_set_drvdata(pci, card);
2172
2173 err = register_vga_switcheroo(chip);
2174 if (err < 0) {
2175 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2176 goto out_free;
2177 }
2178
2179 if (check_hdmi_disabled(pci)) {
2180 dev_info(card->dev, "VGA controller is disabled\n");
2181 dev_info(card->dev, "Delaying initialization\n");
2182 chip->disabled = true;
2183 }
2184
2185 schedule_probe = !chip->disabled;
2186
2187 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2188 if (patch[dev] && *patch[dev]) {
2189 dev_info(card->dev, "Applying patch firmware '%s'\n",
2190 patch[dev]);
2191 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2192 &pci->dev, GFP_KERNEL, card,
2193 azx_firmware_cb);
2194 if (err < 0)
2195 goto out_free;
2196 schedule_probe = false; /* continued in azx_firmware_cb() */
2197 }
2198 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2199
2200 #ifndef CONFIG_SND_HDA_I915
2201 if (CONTROLLER_IN_GPU(pci))
2202 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2203 #endif
2204
2205 if (schedule_probe)
2206 schedule_delayed_work(&hda->probe_work, 0);
2207
2208 dev++;
2209 if (chip->disabled)
2210 complete_all(&hda->probe_wait);
2211 return 0;
2212
2213 out_free:
2214 snd_card_free(card);
2215 return err;
2216 }
2217
2218 #ifdef CONFIG_PM
2219 /* On some boards setting power_save to a non 0 value leads to clicking /
2220 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2221 * figure out how to avoid these sounds, but that is not always feasible.
2222 * So we keep a list of devices where we disable powersaving as its known
2223 * to causes problems on these devices.
2224 */
2225 static const struct snd_pci_quirk power_save_denylist[] = {
2226 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2227 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2228 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2229 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2230 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2231 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2232 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2233 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2234 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2235 SND_PCI_QUIRK(0x1558, 0x6504, "Clevo W65_67SB", 0),
2236 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2237 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2238 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2239 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2240 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2241 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2242 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2243 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2244 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2245 /* https://bugs.launchpad.net/bugs/1821663 */
2246 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2247 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2248 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2249 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2250 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2251 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2252 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2253 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2254 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2255 /* https://bugs.launchpad.net/bugs/1821663 */
2256 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2257 {}
2258 };
2259 #endif /* CONFIG_PM */
2260
set_default_power_save(struct azx * chip)2261 static void set_default_power_save(struct azx *chip)
2262 {
2263 int val = power_save;
2264
2265 #ifdef CONFIG_PM
2266 if (pm_blacklist) {
2267 const struct snd_pci_quirk *q;
2268
2269 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist);
2270 if (q && val) {
2271 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n",
2272 q->subvendor, q->subdevice);
2273 val = 0;
2274 }
2275 }
2276 #endif /* CONFIG_PM */
2277 snd_hda_set_power_save(&chip->bus, val * 1000);
2278 }
2279
2280 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2281 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2282 [AZX_DRIVER_NVIDIA] = 8,
2283 [AZX_DRIVER_TERA] = 1,
2284 };
2285
azx_probe_continue(struct azx * chip)2286 static int azx_probe_continue(struct azx *chip)
2287 {
2288 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2289 struct hdac_bus *bus = azx_bus(chip);
2290 struct pci_dev *pci = chip->pci;
2291 int dev = chip->dev_index;
2292 int err;
2293
2294 if (chip->disabled || hda->init_failed)
2295 return -EIO;
2296 if (hda->probe_retry)
2297 goto probe_retry;
2298
2299 to_hda_bus(bus)->bus_probing = 1;
2300 hda->probe_continued = 1;
2301
2302 /* bind with i915 if needed */
2303 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2304 err = snd_hdac_i915_init(bus);
2305 if (err < 0) {
2306 /* if the controller is bound only with HDMI/DP
2307 * (for HSW and BDW), we need to abort the probe;
2308 * for other chips, still continue probing as other
2309 * codecs can be on the same link.
2310 */
2311 if (CONTROLLER_IN_GPU(pci)) {
2312 dev_err(chip->card->dev,
2313 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2314 goto out_free;
2315 } else {
2316 /* don't bother any longer */
2317 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2318 }
2319 }
2320
2321 /* HSW/BDW controllers need this power */
2322 if (CONTROLLER_IN_GPU(pci))
2323 hda->need_i915_power = 1;
2324 }
2325
2326 /* Request display power well for the HDA controller or codec. For
2327 * Haswell/Broadwell, both the display HDA controller and codec need
2328 * this power. For other platforms, like Baytrail/Braswell, only the
2329 * display codec needs the power and it can be released after probe.
2330 */
2331 display_power(chip, true);
2332
2333 err = azx_first_init(chip);
2334 if (err < 0)
2335 goto out_free;
2336
2337 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2338 chip->beep_mode = beep_mode[dev];
2339 #endif
2340
2341 /* create codec instances */
2342 if (bus->codec_mask) {
2343 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2344 if (err < 0)
2345 goto out_free;
2346 }
2347
2348 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2349 if (chip->fw) {
2350 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2351 chip->fw->data);
2352 if (err < 0)
2353 goto out_free;
2354 #ifndef CONFIG_PM
2355 release_firmware(chip->fw); /* no longer needed */
2356 chip->fw = NULL;
2357 #endif
2358 }
2359 #endif
2360
2361 probe_retry:
2362 if (bus->codec_mask && !(probe_only[dev] & 1)) {
2363 err = azx_codec_configure(chip);
2364 if (err) {
2365 if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) &&
2366 ++hda->probe_retry < 60) {
2367 schedule_delayed_work(&hda->probe_work,
2368 msecs_to_jiffies(1000));
2369 return 0; /* keep things up */
2370 }
2371 dev_err(chip->card->dev, "Cannot probe codecs, giving up\n");
2372 goto out_free;
2373 }
2374 }
2375
2376 err = snd_card_register(chip->card);
2377 if (err < 0)
2378 goto out_free;
2379
2380 setup_vga_switcheroo_runtime_pm(chip);
2381
2382 chip->running = 1;
2383 azx_add_card_list(chip);
2384
2385 set_default_power_save(chip);
2386
2387 if (azx_has_pm_runtime(chip)) {
2388 pm_runtime_use_autosuspend(&pci->dev);
2389 pm_runtime_allow(&pci->dev);
2390 pm_runtime_put_autosuspend(&pci->dev);
2391 }
2392
2393 out_free:
2394 if (err < 0) {
2395 azx_free(chip);
2396 return err;
2397 }
2398
2399 if (!hda->need_i915_power)
2400 display_power(chip, false);
2401 complete_all(&hda->probe_wait);
2402 to_hda_bus(bus)->bus_probing = 0;
2403 hda->probe_retry = 0;
2404 return 0;
2405 }
2406
azx_remove(struct pci_dev * pci)2407 static void azx_remove(struct pci_dev *pci)
2408 {
2409 struct snd_card *card = pci_get_drvdata(pci);
2410 struct azx *chip;
2411 struct hda_intel *hda;
2412
2413 if (card) {
2414 /* cancel the pending probing work */
2415 chip = card->private_data;
2416 hda = container_of(chip, struct hda_intel, chip);
2417 /* FIXME: below is an ugly workaround.
2418 * Both device_release_driver() and driver_probe_device()
2419 * take *both* the device's and its parent's lock before
2420 * calling the remove() and probe() callbacks. The codec
2421 * probe takes the locks of both the codec itself and its
2422 * parent, i.e. the PCI controller dev. Meanwhile, when
2423 * the PCI controller is unbound, it takes its lock, too
2424 * ==> ouch, a deadlock!
2425 * As a workaround, we unlock temporarily here the controller
2426 * device during cancel_work_sync() call.
2427 */
2428 device_unlock(&pci->dev);
2429 cancel_delayed_work_sync(&hda->probe_work);
2430 device_lock(&pci->dev);
2431
2432 snd_card_free(card);
2433 }
2434 }
2435
azx_shutdown(struct pci_dev * pci)2436 static void azx_shutdown(struct pci_dev *pci)
2437 {
2438 struct snd_card *card = pci_get_drvdata(pci);
2439 struct azx *chip;
2440
2441 if (!card)
2442 return;
2443 chip = card->private_data;
2444 if (chip && chip->running)
2445 azx_stop_chip(chip);
2446 }
2447
2448 /* PCI IDs */
2449 static const struct pci_device_id azx_ids[] = {
2450 /* CPT */
2451 { PCI_DEVICE(0x8086, 0x1c20),
2452 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2453 /* PBG */
2454 { PCI_DEVICE(0x8086, 0x1d20),
2455 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2456 /* Panther Point */
2457 { PCI_DEVICE(0x8086, 0x1e20),
2458 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2459 /* Lynx Point */
2460 { PCI_DEVICE(0x8086, 0x8c20),
2461 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2462 /* 9 Series */
2463 { PCI_DEVICE(0x8086, 0x8ca0),
2464 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2465 /* Wellsburg */
2466 { PCI_DEVICE(0x8086, 0x8d20),
2467 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2468 { PCI_DEVICE(0x8086, 0x8d21),
2469 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2470 /* Lewisburg */
2471 { PCI_DEVICE(0x8086, 0xa1f0),
2472 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2473 { PCI_DEVICE(0x8086, 0xa270),
2474 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2475 /* Lynx Point-LP */
2476 { PCI_DEVICE(0x8086, 0x9c20),
2477 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2478 /* Lynx Point-LP */
2479 { PCI_DEVICE(0x8086, 0x9c21),
2480 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2481 /* Wildcat Point-LP */
2482 { PCI_DEVICE(0x8086, 0x9ca0),
2483 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2484 /* Sunrise Point */
2485 { PCI_DEVICE(0x8086, 0xa170),
2486 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2487 /* Sunrise Point-LP */
2488 { PCI_DEVICE(0x8086, 0x9d70),
2489 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2490 /* Kabylake */
2491 { PCI_DEVICE(0x8086, 0xa171),
2492 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2493 /* Kabylake-LP */
2494 { PCI_DEVICE(0x8086, 0x9d71),
2495 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2496 /* Kabylake-H */
2497 { PCI_DEVICE(0x8086, 0xa2f0),
2498 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2499 /* Coffelake */
2500 { PCI_DEVICE(0x8086, 0xa348),
2501 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2502 /* Cannonlake */
2503 { PCI_DEVICE(0x8086, 0x9dc8),
2504 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2505 /* CometLake-LP */
2506 { PCI_DEVICE(0x8086, 0x02C8),
2507 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2508 /* CometLake-H */
2509 { PCI_DEVICE(0x8086, 0x06C8),
2510 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2511 { PCI_DEVICE(0x8086, 0xf1c8),
2512 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2513 /* CometLake-S */
2514 { PCI_DEVICE(0x8086, 0xa3f0),
2515 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2516 /* CometLake-R */
2517 { PCI_DEVICE(0x8086, 0xf0c8),
2518 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2519 /* Icelake */
2520 { PCI_DEVICE(0x8086, 0x34c8),
2521 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2522 /* Icelake-H */
2523 { PCI_DEVICE(0x8086, 0x3dc8),
2524 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2525 /* Jasperlake */
2526 { PCI_DEVICE(0x8086, 0x38c8),
2527 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2528 { PCI_DEVICE(0x8086, 0x4dc8),
2529 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2530 /* Tigerlake */
2531 { PCI_DEVICE(0x8086, 0xa0c8),
2532 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2533 /* Tigerlake-H */
2534 { PCI_DEVICE(0x8086, 0x43c8),
2535 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2536 /* DG1 */
2537 { PCI_DEVICE(0x8086, 0x490d),
2538 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2539 /* Alderlake-S */
2540 { PCI_DEVICE(0x8086, 0x7ad0),
2541 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2542 /* Alderlake-P */
2543 { PCI_DEVICE(0x8086, 0x51c8),
2544 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2545 /* Elkhart Lake */
2546 { PCI_DEVICE(0x8086, 0x4b55),
2547 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2548 { PCI_DEVICE(0x8086, 0x4b58),
2549 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2550 /* Broxton-P(Apollolake) */
2551 { PCI_DEVICE(0x8086, 0x5a98),
2552 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2553 /* Broxton-T */
2554 { PCI_DEVICE(0x8086, 0x1a98),
2555 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2556 /* Gemini-Lake */
2557 { PCI_DEVICE(0x8086, 0x3198),
2558 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2559 /* Haswell */
2560 { PCI_DEVICE(0x8086, 0x0a0c),
2561 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2562 { PCI_DEVICE(0x8086, 0x0c0c),
2563 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2564 { PCI_DEVICE(0x8086, 0x0d0c),
2565 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2566 /* Broadwell */
2567 { PCI_DEVICE(0x8086, 0x160c),
2568 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2569 /* 5 Series/3400 */
2570 { PCI_DEVICE(0x8086, 0x3b56),
2571 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2572 /* Poulsbo */
2573 { PCI_DEVICE(0x8086, 0x811b),
2574 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2575 /* Oaktrail */
2576 { PCI_DEVICE(0x8086, 0x080a),
2577 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2578 /* BayTrail */
2579 { PCI_DEVICE(0x8086, 0x0f04),
2580 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2581 /* Braswell */
2582 { PCI_DEVICE(0x8086, 0x2284),
2583 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2584 /* ICH6 */
2585 { PCI_DEVICE(0x8086, 0x2668),
2586 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2587 /* ICH7 */
2588 { PCI_DEVICE(0x8086, 0x27d8),
2589 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2590 /* ESB2 */
2591 { PCI_DEVICE(0x8086, 0x269a),
2592 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2593 /* ICH8 */
2594 { PCI_DEVICE(0x8086, 0x284b),
2595 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2596 /* ICH9 */
2597 { PCI_DEVICE(0x8086, 0x293e),
2598 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2599 /* ICH9 */
2600 { PCI_DEVICE(0x8086, 0x293f),
2601 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2602 /* ICH10 */
2603 { PCI_DEVICE(0x8086, 0x3a3e),
2604 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2605 /* ICH10 */
2606 { PCI_DEVICE(0x8086, 0x3a6e),
2607 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2608 /* Generic Intel */
2609 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2610 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2611 .class_mask = 0xffffff,
2612 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2613 /* ATI SB 450/600/700/800/900 */
2614 { PCI_DEVICE(0x1002, 0x437b),
2615 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2616 { PCI_DEVICE(0x1002, 0x4383),
2617 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2618 /* AMD Hudson */
2619 { PCI_DEVICE(0x1022, 0x780d),
2620 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2621 /* AMD, X370 & co */
2622 { PCI_DEVICE(0x1022, 0x1457),
2623 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2624 /* AMD, X570 & co */
2625 { PCI_DEVICE(0x1022, 0x1487),
2626 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2627 /* AMD Stoney */
2628 { PCI_DEVICE(0x1022, 0x157a),
2629 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2630 AZX_DCAPS_PM_RUNTIME },
2631 /* AMD Raven */
2632 { PCI_DEVICE(0x1022, 0x15e3),
2633 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2634 /* ATI HDMI */
2635 { PCI_DEVICE(0x1002, 0x0002),
2636 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2637 { PCI_DEVICE(0x1002, 0x1308),
2638 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2639 { PCI_DEVICE(0x1002, 0x157a),
2640 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2641 { PCI_DEVICE(0x1002, 0x15b3),
2642 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2643 { PCI_DEVICE(0x1002, 0x793b),
2644 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2645 { PCI_DEVICE(0x1002, 0x7919),
2646 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2647 { PCI_DEVICE(0x1002, 0x960f),
2648 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2649 { PCI_DEVICE(0x1002, 0x970f),
2650 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2651 { PCI_DEVICE(0x1002, 0x9840),
2652 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2653 { PCI_DEVICE(0x1002, 0xaa00),
2654 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2655 { PCI_DEVICE(0x1002, 0xaa08),
2656 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2657 { PCI_DEVICE(0x1002, 0xaa10),
2658 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2659 { PCI_DEVICE(0x1002, 0xaa18),
2660 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2661 { PCI_DEVICE(0x1002, 0xaa20),
2662 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2663 { PCI_DEVICE(0x1002, 0xaa28),
2664 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2665 { PCI_DEVICE(0x1002, 0xaa30),
2666 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2667 { PCI_DEVICE(0x1002, 0xaa38),
2668 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2669 { PCI_DEVICE(0x1002, 0xaa40),
2670 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2671 { PCI_DEVICE(0x1002, 0xaa48),
2672 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2673 { PCI_DEVICE(0x1002, 0xaa50),
2674 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2675 { PCI_DEVICE(0x1002, 0xaa58),
2676 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2677 { PCI_DEVICE(0x1002, 0xaa60),
2678 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2679 { PCI_DEVICE(0x1002, 0xaa68),
2680 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2681 { PCI_DEVICE(0x1002, 0xaa80),
2682 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2683 { PCI_DEVICE(0x1002, 0xaa88),
2684 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2685 { PCI_DEVICE(0x1002, 0xaa90),
2686 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2687 { PCI_DEVICE(0x1002, 0xaa98),
2688 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2689 { PCI_DEVICE(0x1002, 0x9902),
2690 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2691 { PCI_DEVICE(0x1002, 0xaaa0),
2692 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2693 { PCI_DEVICE(0x1002, 0xaaa8),
2694 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2695 { PCI_DEVICE(0x1002, 0xaab0),
2696 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2697 { PCI_DEVICE(0x1002, 0xaac0),
2698 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2699 { PCI_DEVICE(0x1002, 0xaac8),
2700 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2701 { PCI_DEVICE(0x1002, 0xaad8),
2702 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2703 AZX_DCAPS_PM_RUNTIME },
2704 { PCI_DEVICE(0x1002, 0xaae0),
2705 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2706 AZX_DCAPS_PM_RUNTIME },
2707 { PCI_DEVICE(0x1002, 0xaae8),
2708 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2709 AZX_DCAPS_PM_RUNTIME },
2710 { PCI_DEVICE(0x1002, 0xaaf0),
2711 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2712 AZX_DCAPS_PM_RUNTIME },
2713 { PCI_DEVICE(0x1002, 0xaaf8),
2714 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2715 AZX_DCAPS_PM_RUNTIME },
2716 { PCI_DEVICE(0x1002, 0xab00),
2717 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2718 AZX_DCAPS_PM_RUNTIME },
2719 { PCI_DEVICE(0x1002, 0xab08),
2720 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2721 AZX_DCAPS_PM_RUNTIME },
2722 { PCI_DEVICE(0x1002, 0xab10),
2723 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2724 AZX_DCAPS_PM_RUNTIME },
2725 { PCI_DEVICE(0x1002, 0xab18),
2726 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2727 AZX_DCAPS_PM_RUNTIME },
2728 { PCI_DEVICE(0x1002, 0xab20),
2729 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2730 AZX_DCAPS_PM_RUNTIME },
2731 { PCI_DEVICE(0x1002, 0xab28),
2732 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2733 AZX_DCAPS_PM_RUNTIME },
2734 { PCI_DEVICE(0x1002, 0xab38),
2735 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2736 AZX_DCAPS_PM_RUNTIME },
2737 /* VIA VT8251/VT8237A */
2738 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2739 /* VIA GFX VT7122/VX900 */
2740 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2741 /* VIA GFX VT6122/VX11 */
2742 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2743 /* SIS966 */
2744 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2745 /* ULI M5461 */
2746 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2747 /* NVIDIA MCP */
2748 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2749 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2750 .class_mask = 0xffffff,
2751 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2752 /* Teradici */
2753 { PCI_DEVICE(0x6549, 0x1200),
2754 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2755 { PCI_DEVICE(0x6549, 0x2200),
2756 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2757 /* Creative X-Fi (CA0110-IBG) */
2758 /* CTHDA chips */
2759 { PCI_DEVICE(0x1102, 0x0010),
2760 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2761 { PCI_DEVICE(0x1102, 0x0012),
2762 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2763 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2764 /* the following entry conflicts with snd-ctxfi driver,
2765 * as ctxfi driver mutates from HD-audio to native mode with
2766 * a special command sequence.
2767 */
2768 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2769 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2770 .class_mask = 0xffffff,
2771 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2772 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2773 #else
2774 /* this entry seems still valid -- i.e. without emu20kx chip */
2775 { PCI_DEVICE(0x1102, 0x0009),
2776 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2777 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2778 #endif
2779 /* CM8888 */
2780 { PCI_DEVICE(0x13f6, 0x5011),
2781 .driver_data = AZX_DRIVER_CMEDIA |
2782 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2783 /* Vortex86MX */
2784 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2785 /* VMware HDAudio */
2786 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2787 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2788 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2789 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2790 .class_mask = 0xffffff,
2791 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2792 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2793 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2794 .class_mask = 0xffffff,
2795 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2796 /* Zhaoxin */
2797 { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2798 { 0, }
2799 };
2800 MODULE_DEVICE_TABLE(pci, azx_ids);
2801
2802 /* pci_driver definition */
2803 static struct pci_driver azx_driver = {
2804 .name = KBUILD_MODNAME,
2805 .id_table = azx_ids,
2806 .probe = azx_probe,
2807 .remove = azx_remove,
2808 .shutdown = azx_shutdown,
2809 .driver = {
2810 .pm = AZX_PM_OPS,
2811 },
2812 };
2813
2814 module_pci_driver(azx_driver);
2815