1 /* 2 * This header was generated from the Linux kernel headers by update_headers.py, 3 * to provide necessary information from kernel to userspace, such as constants, 4 * structures, and macros, and thus, contains no copyrightable information. 5 */ 6 #ifndef _UAPI_SYNCLINK_H_ 7 #define _UAPI_SYNCLINK_H_ 8 #define SYNCLINK_H_VERSION 3.6 9 #include <linux/types.h> 10 #define BIT0 0x0001 11 #define BIT1 0x0002 12 #define BIT2 0x0004 13 #define BIT3 0x0008 14 #define BIT4 0x0010 15 #define BIT5 0x0020 16 #define BIT6 0x0040 17 #define BIT7 0x0080 18 #define BIT8 0x0100 19 #define BIT9 0x0200 20 #define BIT10 0x0400 21 #define BIT11 0x0800 22 #define BIT12 0x1000 23 #define BIT13 0x2000 24 #define BIT14 0x4000 25 #define BIT15 0x8000 26 #define BIT16 0x00010000 27 #define BIT17 0x00020000 28 #define BIT18 0x00040000 29 #define BIT19 0x00080000 30 #define BIT20 0x00100000 31 #define BIT21 0x00200000 32 #define BIT22 0x00400000 33 #define BIT23 0x00800000 34 #define BIT24 0x01000000 35 #define BIT25 0x02000000 36 #define BIT26 0x04000000 37 #define BIT27 0x08000000 38 #define BIT28 0x10000000 39 #define BIT29 0x20000000 40 #define BIT30 0x40000000 41 #define BIT31 0x80000000 42 #define HDLC_MAX_FRAME_SIZE 65535 43 #define MAX_ASYNC_TRANSMIT 4096 44 #define MAX_ASYNC_BUFFER_SIZE 4096 45 #define ASYNC_PARITY_NONE 0 46 #define ASYNC_PARITY_EVEN 1 47 #define ASYNC_PARITY_ODD 2 48 #define ASYNC_PARITY_SPACE 3 49 #define HDLC_FLAG_UNDERRUN_ABORT7 0x0000 50 #define HDLC_FLAG_UNDERRUN_ABORT15 0x0001 51 #define HDLC_FLAG_UNDERRUN_FLAG 0x0002 52 #define HDLC_FLAG_UNDERRUN_CRC 0x0004 53 #define HDLC_FLAG_SHARE_ZERO 0x0010 54 #define HDLC_FLAG_AUTO_CTS 0x0020 55 #define HDLC_FLAG_AUTO_DCD 0x0040 56 #define HDLC_FLAG_AUTO_RTS 0x0080 57 #define HDLC_FLAG_RXC_DPLL 0x0100 58 #define HDLC_FLAG_RXC_BRG 0x0200 59 #define HDLC_FLAG_RXC_TXCPIN 0x8000 60 #define HDLC_FLAG_RXC_RXCPIN 0x0000 61 #define HDLC_FLAG_TXC_DPLL 0x0400 62 #define HDLC_FLAG_TXC_BRG 0x0800 63 #define HDLC_FLAG_TXC_TXCPIN 0x0000 64 #define HDLC_FLAG_TXC_RXCPIN 0x0008 65 #define HDLC_FLAG_DPLL_DIV8 0x1000 66 #define HDLC_FLAG_DPLL_DIV16 0x2000 67 #define HDLC_FLAG_DPLL_DIV32 0x0000 68 #define HDLC_FLAG_HDLC_LOOPMODE 0x4000 69 #define HDLC_CRC_NONE 0 70 #define HDLC_CRC_16_CCITT 1 71 #define HDLC_CRC_32_CCITT 2 72 #define HDLC_CRC_MASK 0x00ff 73 #define HDLC_CRC_RETURN_EX 0x8000 74 #define RX_OK 0 75 #define RX_CRC_ERROR 1 76 #define HDLC_TXIDLE_FLAGS 0 77 #define HDLC_TXIDLE_ALT_ZEROS_ONES 1 78 #define HDLC_TXIDLE_ZEROS 2 79 #define HDLC_TXIDLE_ONES 3 80 #define HDLC_TXIDLE_ALT_MARK_SPACE 4 81 #define HDLC_TXIDLE_SPACE 5 82 #define HDLC_TXIDLE_MARK 6 83 #define HDLC_TXIDLE_CUSTOM_8 0x10000000 84 #define HDLC_TXIDLE_CUSTOM_16 0x20000000 85 #define HDLC_ENCODING_NRZ 0 86 #define HDLC_ENCODING_NRZB 1 87 #define HDLC_ENCODING_NRZI_MARK 2 88 #define HDLC_ENCODING_NRZI_SPACE 3 89 #define HDLC_ENCODING_NRZI HDLC_ENCODING_NRZI_SPACE 90 #define HDLC_ENCODING_BIPHASE_MARK 4 91 #define HDLC_ENCODING_BIPHASE_SPACE 5 92 #define HDLC_ENCODING_BIPHASE_LEVEL 6 93 #define HDLC_ENCODING_DIFF_BIPHASE_LEVEL 7 94 #define HDLC_PREAMBLE_LENGTH_8BITS 0 95 #define HDLC_PREAMBLE_LENGTH_16BITS 1 96 #define HDLC_PREAMBLE_LENGTH_32BITS 2 97 #define HDLC_PREAMBLE_LENGTH_64BITS 3 98 #define HDLC_PREAMBLE_PATTERN_NONE 0 99 #define HDLC_PREAMBLE_PATTERN_ZEROS 1 100 #define HDLC_PREAMBLE_PATTERN_FLAGS 2 101 #define HDLC_PREAMBLE_PATTERN_10 3 102 #define HDLC_PREAMBLE_PATTERN_01 4 103 #define HDLC_PREAMBLE_PATTERN_ONES 5 104 #define MGSL_MODE_ASYNC 1 105 #define MGSL_MODE_HDLC 2 106 #define MGSL_MODE_MONOSYNC 3 107 #define MGSL_MODE_BISYNC 4 108 #define MGSL_MODE_RAW 6 109 #define MGSL_MODE_BASE_CLOCK 7 110 #define MGSL_MODE_XSYNC 8 111 #define MGSL_BUS_TYPE_ISA 1 112 #define MGSL_BUS_TYPE_EISA 2 113 #define MGSL_BUS_TYPE_PCI 5 114 #define MGSL_INTERFACE_MASK 0xf 115 #define MGSL_INTERFACE_DISABLE 0 116 #define MGSL_INTERFACE_RS232 1 117 #define MGSL_INTERFACE_V35 2 118 #define MGSL_INTERFACE_RS422 3 119 #define MGSL_INTERFACE_RTS_EN 0x10 120 #define MGSL_INTERFACE_LL 0x20 121 #define MGSL_INTERFACE_RL 0x40 122 #define MGSL_INTERFACE_MSB_FIRST 0x80 123 typedef struct _MGSL_PARAMS 124 { 125 126 unsigned long mode; 127 unsigned char loopback; 128 129 unsigned short flags; 130 unsigned char encoding; 131 unsigned long clock_speed; 132 unsigned char addr_filter; 133 unsigned short crc_type; 134 unsigned char preamble_length; 135 unsigned char preamble; 136 137 unsigned long data_rate; 138 unsigned char data_bits; 139 unsigned char stop_bits; 140 unsigned char parity; 141 } MGSL_PARAMS, *PMGSL_PARAMS; 142 #define MICROGATE_VENDOR_ID 0x13c0 143 #define SYNCLINK_DEVICE_ID 0x0010 144 #define MGSCC_DEVICE_ID 0x0020 145 #define SYNCLINK_SCA_DEVICE_ID 0x0030 146 #define SYNCLINK_GT_DEVICE_ID 0x0070 147 #define SYNCLINK_GT4_DEVICE_ID 0x0080 148 #define SYNCLINK_AC_DEVICE_ID 0x0090 149 #define SYNCLINK_GT2_DEVICE_ID 0x00A0 150 #define MGSL_MAX_SERIAL_NUMBER 30 151 #define DiagStatus_OK 0 152 #define DiagStatus_AddressFailure 1 153 #define DiagStatus_AddressConflict 2 154 #define DiagStatus_IrqFailure 3 155 #define DiagStatus_IrqConflict 4 156 #define DiagStatus_DmaFailure 5 157 #define DiagStatus_DmaConflict 6 158 #define DiagStatus_PciAdapterNotFound 7 159 #define DiagStatus_CantAssignPciResources 8 160 #define DiagStatus_CantAssignPciMemAddr 9 161 #define DiagStatus_CantAssignPciIoAddr 10 162 #define DiagStatus_CantAssignPciIrq 11 163 #define DiagStatus_MemoryError 12 164 #define SerialSignal_DCD 0x01 165 #define SerialSignal_TXD 0x02 166 #define SerialSignal_RI 0x04 167 #define SerialSignal_RXD 0x08 168 #define SerialSignal_CTS 0x10 169 #define SerialSignal_RTS 0x20 170 #define SerialSignal_DSR 0x40 171 #define SerialSignal_DTR 0x80 172 struct mgsl_icount { 173 __u32 cts, dsr, rng, dcd, tx, rx; 174 __u32 frame, parity, overrun, brk; 175 __u32 buf_overrun; 176 __u32 txok; 177 __u32 txunder; 178 __u32 txabort; 179 __u32 txtimeout; 180 __u32 rxshort; 181 __u32 rxlong; 182 __u32 rxabort; 183 __u32 rxover; 184 __u32 rxcrc; 185 __u32 rxok; 186 __u32 exithunt; 187 __u32 rxidle; 188 }; 189 struct gpio_desc { 190 __u32 state; 191 __u32 smask; 192 __u32 dir; 193 __u32 dmask; 194 }; 195 #define DEBUG_LEVEL_DATA 1 196 #define DEBUG_LEVEL_ERROR 2 197 #define DEBUG_LEVEL_INFO 3 198 #define DEBUG_LEVEL_BH 4 199 #define DEBUG_LEVEL_ISR 5 200 #define MgslEvent_DsrActive 0x0001 201 #define MgslEvent_DsrInactive 0x0002 202 #define MgslEvent_Dsr 0x0003 203 #define MgslEvent_CtsActive 0x0004 204 #define MgslEvent_CtsInactive 0x0008 205 #define MgslEvent_Cts 0x000c 206 #define MgslEvent_DcdActive 0x0010 207 #define MgslEvent_DcdInactive 0x0020 208 #define MgslEvent_Dcd 0x0030 209 #define MgslEvent_RiActive 0x0040 210 #define MgslEvent_RiInactive 0x0080 211 #define MgslEvent_Ri 0x00c0 212 #define MgslEvent_ExitHuntMode 0x0100 213 #define MgslEvent_IdleReceived 0x0200 214 #define MGSL_MAGIC_IOC 'm' 215 #define MGSL_IOCSPARAMS _IOW(MGSL_MAGIC_IOC,0,struct _MGSL_PARAMS) 216 #define MGSL_IOCGPARAMS _IOR(MGSL_MAGIC_IOC,1,struct _MGSL_PARAMS) 217 #define MGSL_IOCSTXIDLE _IO(MGSL_MAGIC_IOC,2) 218 #define MGSL_IOCGTXIDLE _IO(MGSL_MAGIC_IOC,3) 219 #define MGSL_IOCTXENABLE _IO(MGSL_MAGIC_IOC,4) 220 #define MGSL_IOCRXENABLE _IO(MGSL_MAGIC_IOC,5) 221 #define MGSL_IOCTXABORT _IO(MGSL_MAGIC_IOC,6) 222 #define MGSL_IOCGSTATS _IO(MGSL_MAGIC_IOC,7) 223 #define MGSL_IOCWAITEVENT _IOWR(MGSL_MAGIC_IOC,8,int) 224 #define MGSL_IOCCLRMODCOUNT _IO(MGSL_MAGIC_IOC,15) 225 #define MGSL_IOCLOOPTXDONE _IO(MGSL_MAGIC_IOC,9) 226 #define MGSL_IOCSIF _IO(MGSL_MAGIC_IOC,10) 227 #define MGSL_IOCGIF _IO(MGSL_MAGIC_IOC,11) 228 #define MGSL_IOCSGPIO _IOW(MGSL_MAGIC_IOC,16,struct gpio_desc) 229 #define MGSL_IOCGGPIO _IOR(MGSL_MAGIC_IOC,17,struct gpio_desc) 230 #define MGSL_IOCWAITGPIO _IOWR(MGSL_MAGIC_IOC,18,struct gpio_desc) 231 #define MGSL_IOCSXSYNC _IO(MGSL_MAGIC_IOC, 19) 232 #define MGSL_IOCGXSYNC _IO(MGSL_MAGIC_IOC, 20) 233 #define MGSL_IOCSXCTRL _IO(MGSL_MAGIC_IOC, 21) 234 #define MGSL_IOCGXCTRL _IO(MGSL_MAGIC_IOC, 22) 235 #endif 236