1 /*
2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this list of
9 * conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list
12 * of conditions and the following disclaimer in the documentation and/or other materials
13 * provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its contributors may be used
16 * to endorse or promote products derived from this software without specific prior written
17 * permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include "los_timer.h"
33 #include "los_config.h"
34 #include "los_tick.h"
35 #include "los_arch_interrupt.h"
36 #include "los_debug.h"
37
38 typedef struct {
39 UINT32 CTRL;
40 UINT32 LOAD;
41 UINT32 VAL;
42 UINT32 CALIB;
43 } CORE_TIM_TYPE;
44
45 #define CORE_TIM_BASE (0xE000E010UL)
46 #define SysTick ((CORE_TIM_TYPE *)CORE_TIM_BASE)
47
48 #define CORETIM_ENABLE (1UL << 0)
49 #define CORETIM_INTMASK (1UL << 1)
50 #define CORETIM_SOURCE (1UL << 2)
51 #define CORETIM_MODE (1UL << 16)
52
53 #define TIM_INT_NUM 1
54
55 STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
56 STATIC UINT64 SysTickReload(UINT64 nextResponseTime);
57 STATIC UINT64 SysTickCycleGet(UINT32 *period);
58 STATIC VOID SysTickLock(VOID);
59 STATIC VOID SysTickUnlock(VOID);
60
61 STATIC ArchTickTimer g_archTickTimer = {
62 .freq = 0,
63 .irqNum = TIM_INT_NUM,
64 .periodMax = LOSCFG_BASE_CORE_TICK_RESPONSE_MAX,
65 .init = SysTickStart,
66 .getCycle = SysTickCycleGet,
67 .reload = SysTickReload,
68 .lock = SysTickLock,
69 .unlock = SysTickUnlock,
70 .tickHandler = NULL,
71 };
72
73 /* ****************************************************************************
74 Function : HalTickStart
75 Description : Configure Tick Interrupt Start
76 Input : none
77 output : none
78 return : LOS_OK - Success , or LOS_ERRNO_TICK_CFG_INVALID - failed
79 **************************************************************************** */
SysTickStart(HWI_PROC_FUNC handler)80 STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
81 {
82 ArchTickTimer *tick = &g_archTickTimer;
83
84 tick->freq = OS_SYS_CLOCK;
85
86 SysTick->LOAD = (OS_CYCLE_PER_TICK - 1);
87 SysTick->VAL = 0;
88 SysTick->CTRL |= (CORETIM_SOURCE | CORETIM_ENABLE | CORETIM_INTMASK);
89
90 VIC_REG->IWER[0] = 0x1 << TIM_INT_NUM;
91
92 #if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
93 #if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
94 OsSetVector(tick->irqNum, handler, NULL);
95 #else
96 OsSetVector(tick->irqNum, handler);
97 #endif
98 #endif
99 return LOS_OK;
100 }
101
SysTickReload(UINT64 nextResponseTime)102 STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
103 {
104 if (nextResponseTime > g_archTickTimer.periodMax) {
105 nextResponseTime = g_archTickTimer.periodMax;
106 }
107 SysTick->CTRL &= ~CORETIM_ENABLE;
108 SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
109 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
110 SysTick->CTRL |= CORETIM_ENABLE;
111 return nextResponseTime;
112 }
113
SysTickCycleGet(UINT32 * period)114 STATIC UINT64 SysTickCycleGet(UINT32 *period)
115 {
116 UINT32 hwCycle;
117 UINT32 intSave = LOS_IntLock();
118 *period = SysTick->LOAD;
119 hwCycle = *period - SysTick->VAL;
120 LOS_IntRestore(intSave);
121 return (UINT64)hwCycle;
122 }
123
SysTickLock(VOID)124 STATIC VOID SysTickLock(VOID)
125 {
126 SysTick->CTRL &= ~CORETIM_ENABLE;
127 }
128
SysTickUnlock(VOID)129 STATIC VOID SysTickUnlock(VOID)
130 {
131 SysTick->CTRL |= CORETIM_ENABLE;
132 }
133
ArchSysTickTimerGet(VOID)134 ArchTickTimer *ArchSysTickTimerGet(VOID)
135 {
136 return &g_archTickTimer;
137 }
138
Wfi(VOID)139 VOID Wfi(VOID)
140 {
141 __asm__ volatile("wait");
142 }
143
Dsb(VOID)144 VOID Dsb(VOID)
145 {
146 __asm__ volatile("sync" : : : "memory");
147 }
148
ArchEnterSleep(VOID)149 UINT32 ArchEnterSleep(VOID)
150 {
151 Dsb();
152 Wfi();
153 return LOS_OK;
154 }
155