1 /**************************************************************************//**
2 * @file core_cm35p.h
3 * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File
4 * @version V1.1.0
5 * @date 27. March 2020
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2018-2020 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29 #elif defined ( __GNUC__ )
30 #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
31 #endif
32
33 #ifndef __CORE_CM35P_H_GENERIC
34 #define __CORE_CM35P_H_GENERIC
35
36 #include <stdint.h>
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
42 /**
43 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
44 CMSIS violates the following MISRA-C:2004 rules:
45
46 \li Required Rule 8.5, object/function definition in header file.<br>
47 Function definitions in header files are used to allow 'inlining'.
48
49 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
50 Unions are used for effective representation of core registers.
51
52 \li Advisory Rule 19.7, Function-like macro defined.<br>
53 Function-like macros are used to allow more efficient code.
54 */
55
56
57 /*******************************************************************************
58 * CMSIS definitions
59 ******************************************************************************/
60 /**
61 \ingroup Cortex_M35P
62 @{
63 */
64
65 #include "cmsis_version.h"
66
67 /* CMSIS CM35P definitions */
68 #define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
69 #define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
70 #define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \
71 __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
72
73 #define __CORTEX_M (35U) /*!< Cortex-M Core */
74
75 /** __FPU_USED indicates whether an FPU is used or not.
76 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
77 */
78 #if defined ( __CC_ARM )
79 #if defined (__TARGET_FPU_VFP)
80 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
81 #define __FPU_USED 1U
82 #else
83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
84 #define __FPU_USED 0U
85 #endif
86 #else
87 #define __FPU_USED 0U
88 #endif
89
90 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
91 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
92 #define __DSP_USED 1U
93 #else
94 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
95 #define __DSP_USED 0U
96 #endif
97 #else
98 #define __DSP_USED 0U
99 #endif
100
101 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
102 #if defined (__ARM_FP)
103 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
104 #define __FPU_USED 1U
105 #else
106 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
107 #define __FPU_USED 0U
108 #endif
109 #else
110 #define __FPU_USED 0U
111 #endif
112
113 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
114 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
115 #define __DSP_USED 1U
116 #else
117 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
118 #define __DSP_USED 0U
119 #endif
120 #else
121 #define __DSP_USED 0U
122 #endif
123
124 #elif defined ( __GNUC__ )
125 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
126 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
127 #define __FPU_USED 1U
128 #else
129 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
130 #define __FPU_USED 0U
131 #endif
132 #else
133 #define __FPU_USED 0U
134 #endif
135
136 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
137 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
138 #define __DSP_USED 1U
139 #else
140 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
141 #define __DSP_USED 0U
142 #endif
143 #else
144 #define __DSP_USED 0U
145 #endif
146
147 #elif defined ( __ICCARM__ )
148 #if defined (__ARMVFP__)
149 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
150 #define __FPU_USED 1U
151 #else
152 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
153 #define __FPU_USED 0U
154 #endif
155 #else
156 #define __FPU_USED 0U
157 #endif
158
159 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
160 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
161 #define __DSP_USED 1U
162 #else
163 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
164 #define __DSP_USED 0U
165 #endif
166 #else
167 #define __DSP_USED 0U
168 #endif
169
170 #elif defined ( __TI_ARM__ )
171 #if defined (__TI_VFP_SUPPORT__)
172 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
173 #define __FPU_USED 1U
174 #else
175 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
176 #define __FPU_USED 0U
177 #endif
178 #else
179 #define __FPU_USED 0U
180 #endif
181
182 #elif defined ( __TASKING__ )
183 #if defined (__FPU_VFP__)
184 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
185 #define __FPU_USED 1U
186 #else
187 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
188 #define __FPU_USED 0U
189 #endif
190 #else
191 #define __FPU_USED 0U
192 #endif
193
194 #elif defined ( __CSMC__ )
195 #if ( __CSMC__ & 0x400U)
196 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
197 #define __FPU_USED 1U
198 #else
199 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
200 #define __FPU_USED 0U
201 #endif
202 #else
203 #define __FPU_USED 0U
204 #endif
205
206 #endif
207
208 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
209
210
211 #ifdef __cplusplus
212 }
213 #endif
214
215 #endif /* __CORE_CM35P_H_GENERIC */
216
217 #ifndef __CMSIS_GENERIC
218
219 #ifndef __CORE_CM35P_H_DEPENDANT
220 #define __CORE_CM35P_H_DEPENDANT
221
222 #ifdef __cplusplus
223 extern "C" {
224 #endif
225
226 /* check device defines and use defaults */
227 #if defined __CHECK_DEVICE_DEFINES
228 #ifndef __CM35P_REV
229 #define __CM35P_REV 0x0000U
230 #warning "__CM35P_REV not defined in device header file; using default!"
231 #endif
232
233 #ifndef __FPU_PRESENT
234 #define __FPU_PRESENT 0U
235 #warning "__FPU_PRESENT not defined in device header file; using default!"
236 #endif
237
238 #ifndef __MPU_PRESENT
239 #define __MPU_PRESENT 0U
240 #warning "__MPU_PRESENT not defined in device header file; using default!"
241 #endif
242
243 #ifndef __SAUREGION_PRESENT
244 #define __SAUREGION_PRESENT 0U
245 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
246 #endif
247
248 #ifndef __DSP_PRESENT
249 #define __DSP_PRESENT 0U
250 #warning "__DSP_PRESENT not defined in device header file; using default!"
251 #endif
252
253 #ifndef __VTOR_PRESENT
254 #define __VTOR_PRESENT 1U
255 #warning "__VTOR_PRESENT not defined in device header file; using default!"
256 #endif
257
258 #ifndef __NVIC_PRIO_BITS
259 #define __NVIC_PRIO_BITS 3U
260 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
261 #endif
262
263 #ifndef __Vendor_SysTickConfig
264 #define __Vendor_SysTickConfig 0U
265 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
266 #endif
267 #endif
268
269 /* IO definitions (access restrictions to peripheral registers) */
270 /**
271 \defgroup CMSIS_glob_defs CMSIS Global Defines
272
273 <strong>IO Type Qualifiers</strong> are used
274 \li to specify the access to peripheral variables.
275 \li for automatic generation of peripheral register debug information.
276 */
277 #ifdef __cplusplus
278 #define __I volatile /*!< Defines 'read only' permissions */
279 #else
280 #define __I volatile const /*!< Defines 'read only' permissions */
281 #endif
282 #define __O volatile /*!< Defines 'write only' permissions */
283 #define __IO volatile /*!< Defines 'read / write' permissions */
284
285 /* following defines should be used for structure members */
286 #define __IM volatile const /*! Defines 'read only' structure member permissions */
287 #define __OM volatile /*! Defines 'write only' structure member permissions */
288 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
289
290 /*@} end of group Cortex_M35P */
291
292
293
294 /*******************************************************************************
295 * Register Abstraction
296 Core Register contain:
297 - Core Register
298 - Core NVIC Register
299 - Core SCB Register
300 - Core SysTick Register
301 - Core Debug Register
302 - Core MPU Register
303 - Core SAU Register
304 - Core FPU Register
305 ******************************************************************************/
306 /**
307 \defgroup CMSIS_core_register Defines and Type Definitions
308 \brief Type definitions and defines for Cortex-M processor based devices.
309 */
310
311 /**
312 \ingroup CMSIS_core_register
313 \defgroup CMSIS_CORE Status and Control Registers
314 \brief Core Register type definitions.
315 @{
316 */
317
318 /**
319 \brief Union type to access the Application Program Status Register (APSR).
320 */
321 typedef union
322 {
323 struct
324 {
325 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
326 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
327 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
328 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
329 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
330 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
331 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
332 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
333 } b; /*!< Structure used for bit access */
334 uint32_t w; /*!< Type used for word access */
335 } APSR_Type;
336
337 /* APSR Register Definitions */
338 #define APSR_N_Pos 31U /*!< APSR: N Position */
339 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
340
341 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
342 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
343
344 #define APSR_C_Pos 29U /*!< APSR: C Position */
345 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
346
347 #define APSR_V_Pos 28U /*!< APSR: V Position */
348 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
349
350 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
351 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
352
353 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
354 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
355
356
357 /**
358 \brief Union type to access the Interrupt Program Status Register (IPSR).
359 */
360 typedef union
361 {
362 struct
363 {
364 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
365 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
366 } b; /*!< Structure used for bit access */
367 uint32_t w; /*!< Type used for word access */
368 } IPSR_Type;
369
370 /* IPSR Register Definitions */
371 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
372 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
373
374
375 /**
376 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
377 */
378 typedef union
379 {
380 struct
381 {
382 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
383 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
384 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
385 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
386 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
387 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
388 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
389 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
390 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
391 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
392 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
393 } b; /*!< Structure used for bit access */
394 uint32_t w; /*!< Type used for word access */
395 } xPSR_Type;
396
397 /* xPSR Register Definitions */
398 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
399 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
400
401 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
402 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
403
404 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
405 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
406
407 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
408 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
409
410 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
411 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
412
413 #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
414 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
415
416 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
417 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
418
419 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
420 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
421
422 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
423 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
424
425
426 /**
427 \brief Union type to access the Control Registers (CONTROL).
428 */
429 typedef union
430 {
431 struct
432 {
433 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
434 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
435 uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
436 uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
437 uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
438 } b; /*!< Structure used for bit access */
439 uint32_t w; /*!< Type used for word access */
440 } CONTROL_Type;
441
442 /* CONTROL Register Definitions */
443 #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
444 #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
445
446 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
447 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
448
449 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
450 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
451
452 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
453 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
454
455 /*@} end of group CMSIS_CORE */
456
457
458 /**
459 \ingroup CMSIS_core_register
460 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
461 \brief Type definitions for the NVIC Registers
462 @{
463 */
464
465 /**
466 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
467 */
468 typedef struct
469 {
470 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
471 uint32_t RESERVED0[16U];
472 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
473 uint32_t RSERVED1[16U];
474 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
475 uint32_t RESERVED2[16U];
476 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
477 uint32_t RESERVED3[16U];
478 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
479 uint32_t RESERVED4[16U];
480 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
481 uint32_t RESERVED5[16U];
482 __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
483 uint32_t RESERVED6[580U];
484 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
485 } NVIC_Type;
486
487 /* Software Triggered Interrupt Register Definitions */
488 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
489 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
490
491 /*@} end of group CMSIS_NVIC */
492
493
494 /**
495 \ingroup CMSIS_core_register
496 \defgroup CMSIS_SCB System Control Block (SCB)
497 \brief Type definitions for the System Control Block Registers
498 @{
499 */
500
501 /**
502 \brief Structure type to access the System Control Block (SCB).
503 */
504 typedef struct
505 {
506 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
507 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
508 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
509 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
510 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
511 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
512 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
513 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
514 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
515 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
516 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
517 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
518 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
519 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
520 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
521 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
522 __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
523 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
524 __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
525 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
526 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
527 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
528 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
529 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
530 __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
531 uint32_t RESERVED3[92U];
532 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
533 uint32_t RESERVED4[15U];
534 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
535 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
536 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
537 uint32_t RESERVED5[1U];
538 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
539 uint32_t RESERVED6[1U];
540 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
541 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
542 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
543 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
544 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
545 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
546 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
547 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
548 } SCB_Type;
549
550 /* SCB CPUID Register Definitions */
551 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
552 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
553
554 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
555 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
556
557 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
558 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
559
560 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
561 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
562
563 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
564 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
565
566 /* SCB Interrupt Control State Register Definitions */
567 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
568 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
569
570 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
571 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
572
573 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
574 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
575
576 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
577 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
578
579 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
580 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
581
582 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
583 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
584
585 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
586 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
587
588 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
589 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
590
591 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
592 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
593
594 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
595 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
596
597 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
598 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
599
600 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
601 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
602
603 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
604 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
605
606 /* SCB Vector Table Offset Register Definitions */
607 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
608 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
609
610 /* SCB Application Interrupt and Reset Control Register Definitions */
611 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
612 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
613
614 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
615 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
616
617 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
618 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
619
620 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
621 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
622
623 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
624 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
625
626 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
627 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
628
629 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
630 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
631
632 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
633 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
634
635 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
636 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
637
638 /* SCB System Control Register Definitions */
639 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
640 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
641
642 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
643 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
644
645 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
646 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
647
648 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
649 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
650
651 /* SCB Configuration Control Register Definitions */
652 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
653 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
654
655 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
656 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
657
658 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
659 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
660
661 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
662 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
663
664 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
665 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
666
667 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
668 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
669
670 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
671 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
672
673 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
674 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
675
676 /* SCB System Handler Control and State Register Definitions */
677 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
678 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
679
680 #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
681 #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
682
683 #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
684 #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
685
686 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
687 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
688
689 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
690 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
691
692 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
693 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
694
695 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
696 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
697
698 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
699 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
700
701 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
702 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
703
704 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
705 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
706
707 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
708 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
709
710 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
711 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
712
713 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
714 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
715
716 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
717 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
718
719 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
720 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
721
722 #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
723 #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
724
725 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
726 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
727
728 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
729 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
730
731 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
732 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
733
734 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
735 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
736
737 /* SCB Configurable Fault Status Register Definitions */
738 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
739 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
740
741 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
742 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
743
744 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
745 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
746
747 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
748 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
749 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
750
751 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
752 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
753
754 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
755 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
756
757 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
758 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
759
760 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
761 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
762
763 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
764 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
765
766 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
767 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
768 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
769
770 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
771 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
772
773 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
774 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
775
776 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
777 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
778
779 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
780 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
781
782 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
783 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
784
785 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
786 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
787
788 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
789 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
790 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
791
792 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
793 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
794
795 #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
796 #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
797
798 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
799 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
800
801 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
802 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
803
804 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
805 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
806
807 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
808 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
809
810 /* SCB Hard Fault Status Register Definitions */
811 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
812 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
813
814 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
815 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
816
817 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
818 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
819
820 /* SCB Debug Fault Status Register Definitions */
821 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
822 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
823
824 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
825 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
826
827 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
828 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
829
830 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
831 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
832
833 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
834 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
835
836 /* SCB Non-Secure Access Control Register Definitions */
837 #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
838 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
839
840 #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
841 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
842
843 #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
844 #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
845
846 /* SCB Cache Level ID Register Definitions */
847 #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
848 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
849
850 #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
851 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
852
853 /* SCB Cache Type Register Definitions */
854 #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
855 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
856
857 #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
858 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
859
860 #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
861 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
862
863 #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
864 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
865
866 #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
867 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
868
869 /* SCB Cache Size ID Register Definitions */
870 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
871 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
872
873 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
874 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
875
876 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
877 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
878
879 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
880 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
881
882 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
883 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
884
885 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
886 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
887
888 #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
889 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
890
891 /* SCB Cache Size Selection Register Definitions */
892 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
893 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
894
895 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
896 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
897
898 /* SCB Software Triggered Interrupt Register Definitions */
899 #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
900 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
901
902 /* SCB D-Cache Invalidate by Set-way Register Definitions */
903 #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
904 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
905
906 #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
907 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
908
909 /* SCB D-Cache Clean by Set-way Register Definitions */
910 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
911 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
912
913 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
914 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
915
916 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
917 #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
918 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
919
920 #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
921 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
922
923 /*@} end of group CMSIS_SCB */
924
925
926 /**
927 \ingroup CMSIS_core_register
928 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
929 \brief Type definitions for the System Control and ID Register not in the SCB
930 @{
931 */
932
933 /**
934 \brief Structure type to access the System Control and ID Register not in the SCB.
935 */
936 typedef struct
937 {
938 uint32_t RESERVED0[1U];
939 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
940 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
941 __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
942 } SCnSCB_Type;
943
944 /* Interrupt Controller Type Register Definitions */
945 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
946 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
947
948 /*@} end of group CMSIS_SCnotSCB */
949
950
951 /**
952 \ingroup CMSIS_core_register
953 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
954 \brief Type definitions for the System Timer Registers.
955 @{
956 */
957
958 /**
959 \brief Structure type to access the System Timer (SysTick).
960 */
961 typedef struct
962 {
963 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
964 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
965 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
966 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
967 } SysTick_Type;
968
969 /* SysTick Control / Status Register Definitions */
970 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
971 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
972
973 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
974 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
975
976 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
977 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
978
979 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
980 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
981
982 /* SysTick Reload Register Definitions */
983 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
984 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
985
986 /* SysTick Current Register Definitions */
987 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
988 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
989
990 /* SysTick Calibration Register Definitions */
991 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
992 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
993
994 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
995 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
996
997 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
998 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
999
1000 /*@} end of group CMSIS_SysTick */
1001
1002
1003 /**
1004 \ingroup CMSIS_core_register
1005 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
1006 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
1007 @{
1008 */
1009
1010 /**
1011 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
1012 */
1013 typedef struct
1014 {
1015 __OM union
1016 {
1017 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
1018 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
1019 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
1020 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
1021 uint32_t RESERVED0[864U];
1022 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
1023 uint32_t RESERVED1[15U];
1024 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
1025 uint32_t RESERVED2[15U];
1026 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
1027 uint32_t RESERVED3[32U];
1028 uint32_t RESERVED4[43U];
1029 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
1030 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
1031 uint32_t RESERVED5[1U];
1032 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
1033 uint32_t RESERVED6[4U];
1034 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
1035 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
1036 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
1037 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
1038 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
1039 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
1040 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
1041 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
1042 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
1043 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
1044 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
1045 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
1046 } ITM_Type;
1047
1048 /* ITM Stimulus Port Register Definitions */
1049 #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
1050 #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
1051
1052 #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
1053 #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
1054
1055 /* ITM Trace Privilege Register Definitions */
1056 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
1057 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
1058
1059 /* ITM Trace Control Register Definitions */
1060 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
1061 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
1062
1063 #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
1064 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
1065
1066 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
1067 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
1068
1069 #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
1070 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
1071
1072 #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
1073 #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
1074
1075 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
1076 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
1077
1078 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
1079 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
1080
1081 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
1082 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
1083
1084 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
1085 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
1086
1087 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
1088 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
1089
1090 /* ITM Lock Status Register Definitions */
1091 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
1092 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
1093
1094 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
1095 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
1096
1097 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
1098 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
1099
1100 /*@}*/ /* end of group CMSIS_ITM */
1101
1102
1103 /**
1104 \ingroup CMSIS_core_register
1105 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
1106 \brief Type definitions for the Data Watchpoint and Trace (DWT)
1107 @{
1108 */
1109
1110 /**
1111 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
1112 */
1113 typedef struct
1114 {
1115 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
1116 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
1117 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
1118 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
1119 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
1120 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
1121 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
1122 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
1123 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
1124 uint32_t RESERVED1[1U];
1125 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
1126 uint32_t RESERVED2[1U];
1127 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
1128 uint32_t RESERVED3[1U];
1129 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
1130 uint32_t RESERVED4[1U];
1131 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
1132 uint32_t RESERVED5[1U];
1133 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
1134 uint32_t RESERVED6[1U];
1135 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
1136 uint32_t RESERVED7[1U];
1137 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
1138 uint32_t RESERVED8[1U];
1139 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
1140 uint32_t RESERVED9[1U];
1141 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
1142 uint32_t RESERVED10[1U];
1143 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
1144 uint32_t RESERVED11[1U];
1145 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
1146 uint32_t RESERVED12[1U];
1147 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
1148 uint32_t RESERVED13[1U];
1149 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
1150 uint32_t RESERVED14[1U];
1151 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
1152 uint32_t RESERVED15[1U];
1153 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
1154 uint32_t RESERVED16[1U];
1155 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
1156 uint32_t RESERVED17[1U];
1157 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
1158 uint32_t RESERVED18[1U];
1159 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
1160 uint32_t RESERVED19[1U];
1161 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
1162 uint32_t RESERVED20[1U];
1163 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
1164 uint32_t RESERVED21[1U];
1165 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
1166 uint32_t RESERVED22[1U];
1167 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
1168 uint32_t RESERVED23[1U];
1169 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
1170 uint32_t RESERVED24[1U];
1171 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
1172 uint32_t RESERVED25[1U];
1173 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
1174 uint32_t RESERVED26[1U];
1175 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
1176 uint32_t RESERVED27[1U];
1177 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
1178 uint32_t RESERVED28[1U];
1179 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
1180 uint32_t RESERVED29[1U];
1181 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
1182 uint32_t RESERVED30[1U];
1183 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
1184 uint32_t RESERVED31[1U];
1185 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
1186 uint32_t RESERVED32[934U];
1187 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
1188 uint32_t RESERVED33[1U];
1189 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
1190 } DWT_Type;
1191
1192 /* DWT Control Register Definitions */
1193 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
1194 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
1195
1196 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
1197 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
1198
1199 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
1200 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
1201
1202 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
1203 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
1204
1205 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
1206 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
1207
1208 #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
1209 #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
1210
1211 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
1212 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
1213
1214 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
1215 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
1216
1217 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
1218 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
1219
1220 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
1221 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
1222
1223 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
1224 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
1225
1226 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
1227 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
1228
1229 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
1230 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
1231
1232 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
1233 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
1234
1235 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
1236 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
1237
1238 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
1239 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
1240
1241 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
1242 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
1243
1244 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
1245 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
1246
1247 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
1248 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
1249
1250 /* DWT CPI Count Register Definitions */
1251 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
1252 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
1253
1254 /* DWT Exception Overhead Count Register Definitions */
1255 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
1256 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
1257
1258 /* DWT Sleep Count Register Definitions */
1259 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
1260 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
1261
1262 /* DWT LSU Count Register Definitions */
1263 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
1264 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
1265
1266 /* DWT Folded-instruction Count Register Definitions */
1267 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
1268 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
1269
1270 /* DWT Comparator Function Register Definitions */
1271 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
1272 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
1273
1274 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
1275 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
1276
1277 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
1278 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
1279
1280 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
1281 #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
1282
1283 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
1284 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
1285
1286 /*@}*/ /* end of group CMSIS_DWT */
1287
1288
1289 /**
1290 \ingroup CMSIS_core_register
1291 \defgroup CMSIS_TPI Trace Port Interface (TPI)
1292 \brief Type definitions for the Trace Port Interface (TPI)
1293 @{
1294 */
1295
1296 /**
1297 \brief Structure type to access the Trace Port Interface Register (TPI).
1298 */
1299 typedef struct
1300 {
1301 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
1302 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
1303 uint32_t RESERVED0[2U];
1304 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
1305 uint32_t RESERVED1[55U];
1306 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
1307 uint32_t RESERVED2[131U];
1308 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
1309 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
1310 __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
1311 uint32_t RESERVED3[759U];
1312 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1313 __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
1314 __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
1315 uint32_t RESERVED4[1U];
1316 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
1317 __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
1318 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
1319 uint32_t RESERVED5[39U];
1320 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1321 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
1322 uint32_t RESERVED7[8U];
1323 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
1324 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
1325 } TPI_Type;
1326
1327 /* TPI Asynchronous Clock Prescaler Register Definitions */
1328 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
1329 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
1330
1331 /* TPI Selected Pin Protocol Register Definitions */
1332 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
1333 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
1334
1335 /* TPI Formatter and Flush Status Register Definitions */
1336 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
1337 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
1338
1339 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
1340 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
1341
1342 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
1343 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
1344
1345 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
1346 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
1347
1348 /* TPI Formatter and Flush Control Register Definitions */
1349 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
1350 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
1351
1352 #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
1353 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
1354
1355 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
1356 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
1357
1358 /* TPI TRIGGER Register Definitions */
1359 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
1360 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
1361
1362 /* TPI Integration Test FIFO Test Data 0 Register Definitions */
1363 #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
1364 #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
1365
1366 #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
1367 #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
1368
1369 #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
1370 #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
1371
1372 #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
1373 #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
1374
1375 #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
1376 #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
1377
1378 #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
1379 #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
1380
1381 #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
1382 #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
1383
1384 /* TPI Integration Test ATB Control Register 2 Register Definitions */
1385 #define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
1386 #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
1387
1388 #define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
1389 #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
1390
1391 #define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
1392 #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
1393
1394 #define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
1395 #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
1396
1397 /* TPI Integration Test FIFO Test Data 1 Register Definitions */
1398 #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
1399 #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
1400
1401 #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
1402 #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
1403
1404 #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
1405 #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
1406
1407 #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
1408 #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
1409
1410 #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
1411 #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
1412
1413 #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
1414 #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
1415
1416 #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
1417 #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
1418
1419 /* TPI Integration Test ATB Control Register 0 Definitions */
1420 #define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
1421 #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
1422
1423 #define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
1424 #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
1425
1426 #define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
1427 #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
1428
1429 #define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
1430 #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
1431
1432 /* TPI Integration Mode Control Register Definitions */
1433 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
1434 #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
1435
1436 /* TPI DEVID Register Definitions */
1437 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
1438 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1439
1440 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
1441 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1442
1443 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
1444 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1445
1446 #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
1447 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
1448
1449 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
1450 #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
1451
1452 /* TPI DEVTYPE Register Definitions */
1453 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
1454 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
1455
1456 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
1457 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1458
1459 /*@}*/ /* end of group CMSIS_TPI */
1460
1461
1462 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1463 /**
1464 \ingroup CMSIS_core_register
1465 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1466 \brief Type definitions for the Memory Protection Unit (MPU)
1467 @{
1468 */
1469
1470 /**
1471 \brief Structure type to access the Memory Protection Unit (MPU).
1472 */
1473 typedef struct
1474 {
1475 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1476 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1477 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
1478 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1479 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
1480 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
1481 __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
1482 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
1483 __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
1484 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
1485 __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
1486 uint32_t RESERVED0[1];
1487 union {
1488 __IOM uint32_t MAIR[2];
1489 struct {
1490 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
1491 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
1492 };
1493 };
1494 } MPU_Type;
1495
1496 #define MPU_TYPE_RALIASES 4U
1497
1498 /* MPU Type Register Definitions */
1499 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
1500 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1501
1502 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
1503 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1504
1505 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
1506 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1507
1508 /* MPU Control Register Definitions */
1509 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
1510 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1511
1512 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
1513 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1514
1515 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
1516 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1517
1518 /* MPU Region Number Register Definitions */
1519 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1520 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1521
1522 /* MPU Region Base Address Register Definitions */
1523 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
1524 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
1525
1526 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
1527 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
1528
1529 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
1530 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
1531
1532 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
1533 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
1534
1535 /* MPU Region Limit Address Register Definitions */
1536 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
1537 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
1538
1539 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
1540 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
1541
1542 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
1543 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
1544
1545 /* MPU Memory Attribute Indirection Register 0 Definitions */
1546 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
1547 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
1548
1549 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
1550 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
1551
1552 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
1553 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
1554
1555 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
1556 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
1557
1558 /* MPU Memory Attribute Indirection Register 1 Definitions */
1559 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
1560 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
1561
1562 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
1563 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
1564
1565 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
1566 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
1567
1568 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
1569 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
1570
1571 /*@} end of group CMSIS_MPU */
1572 #endif
1573
1574
1575 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1576 /**
1577 \ingroup CMSIS_core_register
1578 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
1579 \brief Type definitions for the Security Attribution Unit (SAU)
1580 @{
1581 */
1582
1583 /**
1584 \brief Structure type to access the Security Attribution Unit (SAU).
1585 */
1586 typedef struct
1587 {
1588 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
1589 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
1590 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1591 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
1592 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
1593 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
1594 #else
1595 uint32_t RESERVED0[3];
1596 #endif
1597 __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
1598 __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
1599 } SAU_Type;
1600
1601 /* SAU Control Register Definitions */
1602 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
1603 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
1604
1605 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
1606 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
1607
1608 /* SAU Type Register Definitions */
1609 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
1610 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
1611
1612 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1613 /* SAU Region Number Register Definitions */
1614 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
1615 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
1616
1617 /* SAU Region Base Address Register Definitions */
1618 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
1619 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
1620
1621 /* SAU Region Limit Address Register Definitions */
1622 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
1623 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
1624
1625 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
1626 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
1627
1628 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
1629 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
1630
1631 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1632
1633 /* Secure Fault Status Register Definitions */
1634 #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
1635 #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
1636
1637 #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
1638 #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
1639
1640 #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
1641 #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
1642
1643 #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
1644 #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
1645
1646 #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
1647 #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
1648
1649 #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
1650 #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
1651
1652 #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
1653 #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
1654
1655 #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
1656 #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
1657
1658 /*@} end of group CMSIS_SAU */
1659 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1660
1661
1662 /**
1663 \ingroup CMSIS_core_register
1664 \defgroup CMSIS_FPU Floating Point Unit (FPU)
1665 \brief Type definitions for the Floating Point Unit (FPU)
1666 @{
1667 */
1668
1669 /**
1670 \brief Structure type to access the Floating Point Unit (FPU).
1671 */
1672 typedef struct
1673 {
1674 uint32_t RESERVED0[1U];
1675 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
1676 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
1677 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
1678 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
1679 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
1680 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
1681 } FPU_Type;
1682
1683 /* Floating-Point Context Control Register Definitions */
1684 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
1685 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
1686
1687 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
1688 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
1689
1690 #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
1691 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
1692
1693 #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
1694 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
1695
1696 #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
1697 #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
1698
1699 #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
1700 #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
1701
1702 #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
1703 #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
1704
1705 #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
1706 #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
1707
1708 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
1709 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
1710
1711 #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
1712 #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
1713
1714 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
1715 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
1716
1717 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
1718 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
1719
1720 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
1721 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
1722
1723 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
1724 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
1725
1726 #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
1727 #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
1728
1729 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
1730 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
1731
1732 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
1733 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
1734
1735 /* Floating-Point Context Address Register Definitions */
1736 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
1737 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
1738
1739 /* Floating-Point Default Status Control Register Definitions */
1740 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
1741 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
1742
1743 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
1744 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
1745
1746 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
1747 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
1748
1749 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
1750 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
1751
1752 /* Media and VFP Feature Register 0 Definitions */
1753 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
1754 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
1755
1756 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
1757 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
1758
1759 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
1760 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
1761
1762 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
1763 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
1764
1765 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
1766 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
1767
1768 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
1769 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
1770
1771 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
1772 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
1773
1774 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
1775 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
1776
1777 /* Media and VFP Feature Register 1 Definitions */
1778 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
1779 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
1780
1781 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
1782 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
1783
1784 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
1785 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
1786
1787 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
1788 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
1789
1790 /* Media and VFP Feature Register 2 Definitions */
1791 #define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */
1792 #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */
1793
1794 /*@} end of group CMSIS_FPU */
1795
1796 /* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
1797 /**
1798 \ingroup CMSIS_core_register
1799 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1800 \brief Type definitions for the Core Debug Registers
1801 @{
1802 */
1803
1804 /**
1805 \brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
1806 */
1807 typedef struct
1808 {
1809 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1810 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1811 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1812 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1813 uint32_t RESERVED0[1U];
1814 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
1815 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
1816 } CoreDebug_Type;
1817
1818 /* Debug Halting Control and Status Register Definitions */
1819 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
1820 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
1821
1822 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
1823 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
1824
1825 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
1826 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
1827
1828 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
1829 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
1830
1831 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
1832 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
1833
1834 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
1835 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
1836
1837 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
1838 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
1839
1840 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
1841 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
1842
1843 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */
1844 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */
1845
1846 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
1847 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
1848
1849 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
1850 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
1851
1852 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
1853 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
1854
1855 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
1856 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
1857
1858 /* Debug Core Register Selector Register Definitions */
1859 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
1860 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
1861
1862 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
1863 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
1864
1865 /* Debug Exception and Monitor Control Register Definitions */
1866 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */
1867 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */
1868
1869 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */
1870 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */
1871
1872 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */
1873 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */
1874
1875 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */
1876 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */
1877
1878 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */
1879 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */
1880
1881 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
1882 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
1883
1884 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */
1885 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */
1886
1887 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */
1888 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */
1889
1890 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */
1891 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */
1892
1893 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */
1894 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */
1895
1896 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */
1897 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */
1898
1899 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */
1900 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */
1901
1902 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
1903 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
1904
1905 /* Debug Authentication Control Register Definitions */
1906 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
1907 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
1908
1909 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
1910 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
1911
1912 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
1913 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
1914
1915 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
1916 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
1917
1918 /* Debug Security Control and Status Register Definitions */
1919 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
1920 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
1921
1922 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
1923 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
1924
1925 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
1926 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
1927
1928 /*@} end of group CMSIS_CoreDebug */
1929
1930
1931 /**
1932 \ingroup CMSIS_core_register
1933 \defgroup CMSIS_DCB Debug Control Block
1934 \brief Type definitions for the Debug Control Block Registers
1935 @{
1936 */
1937
1938 /**
1939 \brief Structure type to access the Debug Control Block Registers (DCB).
1940 */
1941 typedef struct
1942 {
1943 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1944 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1945 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1946 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1947 uint32_t RESERVED0[1U];
1948 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
1949 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
1950 } DCB_Type;
1951
1952 /* DHCSR, Debug Halting Control and Status Register Definitions */
1953 #define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
1954 #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
1955
1956 #define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
1957 #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
1958
1959 #define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
1960 #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
1961
1962 #define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
1963 #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
1964
1965 #define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
1966 #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
1967
1968 #define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
1969 #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
1970
1971 #define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
1972 #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
1973
1974 #define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
1975 #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
1976
1977 #define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
1978 #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
1979
1980 #define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
1981 #define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
1982
1983 #define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
1984 #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
1985
1986 #define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
1987 #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
1988
1989 #define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
1990 #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
1991
1992 #define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
1993 #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
1994
1995 /* DCRSR, Debug Core Register Select Register Definitions */
1996 #define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
1997 #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
1998
1999 #define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
2000 #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
2001
2002 /* DCRDR, Debug Core Register Data Register Definitions */
2003 #define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
2004 #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
2005
2006 /* DEMCR, Debug Exception and Monitor Control Register Definitions */
2007 #define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
2008 #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
2009
2010 #define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
2011 #define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
2012
2013 #define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
2014 #define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
2015
2016 #define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
2017 #define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
2018
2019 #define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
2020 #define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
2021
2022 #define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
2023 #define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
2024
2025 #define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
2026 #define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
2027
2028 #define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
2029 #define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
2030
2031 #define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
2032 #define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
2033
2034 #define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
2035 #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
2036
2037 #define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
2038 #define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
2039
2040 #define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
2041 #define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
2042
2043 #define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
2044 #define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
2045
2046 #define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
2047 #define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
2048
2049 #define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
2050 #define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
2051
2052 #define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
2053 #define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
2054
2055 #define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
2056 #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
2057
2058 /* DAUTHCTRL, Debug Authentication Control Register Definitions */
2059 #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
2060 #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
2061
2062 #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
2063 #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
2064
2065 #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
2066 #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
2067
2068 #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
2069 #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
2070
2071 /* DSCSR, Debug Security Control and Status Register Definitions */
2072 #define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
2073 #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
2074
2075 #define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
2076 #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
2077
2078 #define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
2079 #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
2080
2081 #define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
2082 #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
2083
2084 /*@} end of group CMSIS_DCB */
2085
2086
2087
2088 /**
2089 \ingroup CMSIS_core_register
2090 \defgroup CMSIS_DIB Debug Identification Block
2091 \brief Type definitions for the Debug Identification Block Registers
2092 @{
2093 */
2094
2095 /**
2096 \brief Structure type to access the Debug Identification Block Registers (DIB).
2097 */
2098 typedef struct
2099 {
2100 __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
2101 __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
2102 __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
2103 __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
2104 __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
2105 } DIB_Type;
2106
2107 /* DLAR, SCS Software Lock Access Register Definitions */
2108 #define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
2109 #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
2110
2111 /* DLSR, SCS Software Lock Status Register Definitions */
2112 #define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
2113 #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
2114
2115 #define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
2116 #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
2117
2118 #define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
2119 #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
2120
2121 /* DAUTHSTATUS, Debug Authentication Status Register Definitions */
2122 #define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
2123 #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
2124
2125 #define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
2126 #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
2127
2128 #define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
2129 #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
2130
2131 #define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
2132 #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
2133
2134 /* DDEVARCH, SCS Device Architecture Register Definitions */
2135 #define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
2136 #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
2137
2138 #define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
2139 #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
2140
2141 #define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
2142 #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
2143
2144 #define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
2145 #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
2146
2147 #define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
2148 #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
2149
2150 /* DDEVTYPE, SCS Device Type Register Definitions */
2151 #define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
2152 #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
2153
2154 #define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
2155 #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
2156
2157
2158 /*@} end of group CMSIS_DIB */
2159
2160
2161 /**
2162 \ingroup CMSIS_core_register
2163 \defgroup CMSIS_core_bitfield Core register bit field macros
2164 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
2165 @{
2166 */
2167
2168 /**
2169 \brief Mask and shift a bit field value for use in a register bit range.
2170 \param[in] field Name of the register bit field.
2171 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
2172 \return Masked and shifted value.
2173 */
2174 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
2175
2176 /**
2177 \brief Mask and shift a register value to extract a bit filed value.
2178 \param[in] field Name of the register bit field.
2179 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
2180 \return Masked and shifted bit field value.
2181 */
2182 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
2183
2184 /*@} end of group CMSIS_core_bitfield */
2185
2186
2187 /**
2188 \ingroup CMSIS_core_register
2189 \defgroup CMSIS_core_base Core Definitions
2190 \brief Definitions for base addresses, unions, and structures.
2191 @{
2192 */
2193
2194 /* Memory mapping of Core Hardware */
2195 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
2196 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
2197 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
2198 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
2199 #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
2200 #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
2201 #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
2202 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
2203 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
2204 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
2205
2206 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
2207 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
2208 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
2209 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
2210 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
2211 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
2212 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
2213 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
2214 #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
2215 #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
2216
2217 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2218 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
2219 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
2220 #endif
2221
2222 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2223 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
2224 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
2225 #endif
2226
2227 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
2228 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
2229
2230 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2231 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
2232 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
2233 #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
2234 #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
2235 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
2236 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
2237 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
2238
2239 #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
2240 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
2241 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
2242 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
2243 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
2244 #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
2245 #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
2246
2247 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2248 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
2249 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
2250 #endif
2251
2252 #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
2253 #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
2254
2255 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2256 /*@} */
2257
2258
2259
2260 /*******************************************************************************
2261 * Hardware Abstraction Layer
2262 Core Function Interface contains:
2263 - Core NVIC Functions
2264 - Core SysTick Functions
2265 - Core Debug Functions
2266 - Core Register Access Functions
2267 ******************************************************************************/
2268 /**
2269 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
2270 */
2271
2272
2273
2274 /* ########################## NVIC functions #################################### */
2275 /**
2276 \ingroup CMSIS_Core_FunctionInterface
2277 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
2278 \brief Functions that manage interrupts and exceptions via the NVIC.
2279 @{
2280 */
2281
2282 #ifdef CMSIS_NVIC_VIRTUAL
2283 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
2284 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
2285 #endif
2286 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
2287 #else
2288 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
2289 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
2290 #define NVIC_EnableIRQ __NVIC_EnableIRQ
2291 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
2292 #define NVIC_DisableIRQ __NVIC_DisableIRQ
2293 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
2294 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
2295 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
2296 #define NVIC_GetActive __NVIC_GetActive
2297 #define NVIC_SetPriority __NVIC_SetPriority
2298 #define NVIC_GetPriority __NVIC_GetPriority
2299 #define NVIC_SystemReset __NVIC_SystemReset
2300 #endif /* CMSIS_NVIC_VIRTUAL */
2301
2302 #ifdef CMSIS_VECTAB_VIRTUAL
2303 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2304 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
2305 #endif
2306 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2307 #else
2308 #define NVIC_SetVector __NVIC_SetVector
2309 #define NVIC_GetVector __NVIC_GetVector
2310 #endif /* (CMSIS_VECTAB_VIRTUAL) */
2311
2312 #define NVIC_USER_IRQ_OFFSET 16
2313
2314
2315 /* Special LR values for Secure/Non-Secure call handling and exception handling */
2316
2317 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
2318 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
2319
2320 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
2321 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
2322 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
2323 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
2324 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
2325 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
2326 #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
2327 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
2328
2329 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
2330 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
2331 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
2332 #else
2333 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
2334 #endif
2335
2336
2337 /**
2338 \brief Set Priority Grouping
2339 \details Sets the priority grouping field using the required unlock sequence.
2340 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
2341 Only values from 0..7 are used.
2342 In case of a conflict between priority grouping and available
2343 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2344 \param [in] PriorityGroup Priority grouping field.
2345 */
__NVIC_SetPriorityGrouping(uint32_t PriorityGroup)2346 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
2347 {
2348 uint32_t reg_value;
2349 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2350
2351 reg_value = SCB->AIRCR; /* read old register configuration */
2352 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2353 reg_value = (reg_value |
2354 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2355 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
2356 SCB->AIRCR = reg_value;
2357 }
2358
2359
2360 /**
2361 \brief Get Priority Grouping
2362 \details Reads the priority grouping field from the NVIC Interrupt Controller.
2363 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
2364 */
__NVIC_GetPriorityGrouping(void)2365 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
2366 {
2367 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2368 }
2369
2370
2371 /**
2372 \brief Enable Interrupt
2373 \details Enables a device specific interrupt in the NVIC interrupt controller.
2374 \param [in] IRQn Device specific interrupt number.
2375 \note IRQn must not be negative.
2376 */
__NVIC_EnableIRQ(IRQn_Type IRQn)2377 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
2378 {
2379 if ((int32_t)(IRQn) >= 0)
2380 {
2381 __COMPILER_BARRIER();
2382 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2383 __COMPILER_BARRIER();
2384 }
2385 }
2386
2387
2388 /**
2389 \brief Get Interrupt Enable status
2390 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
2391 \param [in] IRQn Device specific interrupt number.
2392 \return 0 Interrupt is not enabled.
2393 \return 1 Interrupt is enabled.
2394 \note IRQn must not be negative.
2395 */
__NVIC_GetEnableIRQ(IRQn_Type IRQn)2396 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
2397 {
2398 if ((int32_t)(IRQn) >= 0)
2399 {
2400 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2401 }
2402 else
2403 {
2404 return(0U);
2405 }
2406 }
2407
2408
2409 /**
2410 \brief Disable Interrupt
2411 \details Disables a device specific interrupt in the NVIC interrupt controller.
2412 \param [in] IRQn Device specific interrupt number.
2413 \note IRQn must not be negative.
2414 */
__NVIC_DisableIRQ(IRQn_Type IRQn)2415 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
2416 {
2417 if ((int32_t)(IRQn) >= 0)
2418 {
2419 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2420 __DSB();
2421 __ISB();
2422 }
2423 }
2424
2425
2426 /**
2427 \brief Get Pending Interrupt
2428 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
2429 \param [in] IRQn Device specific interrupt number.
2430 \return 0 Interrupt status is not pending.
2431 \return 1 Interrupt status is pending.
2432 \note IRQn must not be negative.
2433 */
__NVIC_GetPendingIRQ(IRQn_Type IRQn)2434 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
2435 {
2436 if ((int32_t)(IRQn) >= 0)
2437 {
2438 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2439 }
2440 else
2441 {
2442 return(0U);
2443 }
2444 }
2445
2446
2447 /**
2448 \brief Set Pending Interrupt
2449 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
2450 \param [in] IRQn Device specific interrupt number.
2451 \note IRQn must not be negative.
2452 */
__NVIC_SetPendingIRQ(IRQn_Type IRQn)2453 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
2454 {
2455 if ((int32_t)(IRQn) >= 0)
2456 {
2457 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2458 }
2459 }
2460
2461
2462 /**
2463 \brief Clear Pending Interrupt
2464 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
2465 \param [in] IRQn Device specific interrupt number.
2466 \note IRQn must not be negative.
2467 */
__NVIC_ClearPendingIRQ(IRQn_Type IRQn)2468 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
2469 {
2470 if ((int32_t)(IRQn) >= 0)
2471 {
2472 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2473 }
2474 }
2475
2476
2477 /**
2478 \brief Get Active Interrupt
2479 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
2480 \param [in] IRQn Device specific interrupt number.
2481 \return 0 Interrupt status is not active.
2482 \return 1 Interrupt status is active.
2483 \note IRQn must not be negative.
2484 */
__NVIC_GetActive(IRQn_Type IRQn)2485 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
2486 {
2487 if ((int32_t)(IRQn) >= 0)
2488 {
2489 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2490 }
2491 else
2492 {
2493 return(0U);
2494 }
2495 }
2496
2497
2498 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2499 /**
2500 \brief Get Interrupt Target State
2501 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2502 \param [in] IRQn Device specific interrupt number.
2503 \return 0 if interrupt is assigned to Secure
2504 \return 1 if interrupt is assigned to Non Secure
2505 \note IRQn must not be negative.
2506 */
NVIC_GetTargetState(IRQn_Type IRQn)2507 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
2508 {
2509 if ((int32_t)(IRQn) >= 0)
2510 {
2511 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2512 }
2513 else
2514 {
2515 return(0U);
2516 }
2517 }
2518
2519
2520 /**
2521 \brief Set Interrupt Target State
2522 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2523 \param [in] IRQn Device specific interrupt number.
2524 \return 0 if interrupt is assigned to Secure
2525 1 if interrupt is assigned to Non Secure
2526 \note IRQn must not be negative.
2527 */
NVIC_SetTargetState(IRQn_Type IRQn)2528 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
2529 {
2530 if ((int32_t)(IRQn) >= 0)
2531 {
2532 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2533 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2534 }
2535 else
2536 {
2537 return(0U);
2538 }
2539 }
2540
2541
2542 /**
2543 \brief Clear Interrupt Target State
2544 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2545 \param [in] IRQn Device specific interrupt number.
2546 \return 0 if interrupt is assigned to Secure
2547 1 if interrupt is assigned to Non Secure
2548 \note IRQn must not be negative.
2549 */
NVIC_ClearTargetState(IRQn_Type IRQn)2550 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
2551 {
2552 if ((int32_t)(IRQn) >= 0)
2553 {
2554 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2555 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2556 }
2557 else
2558 {
2559 return(0U);
2560 }
2561 }
2562 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2563
2564
2565 /**
2566 \brief Set Interrupt Priority
2567 \details Sets the priority of a device specific interrupt or a processor exception.
2568 The interrupt number can be positive to specify a device specific interrupt,
2569 or negative to specify a processor exception.
2570 \param [in] IRQn Interrupt number.
2571 \param [in] priority Priority to set.
2572 \note The priority cannot be set for every processor exception.
2573 */
__NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)2574 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
2575 {
2576 if ((int32_t)(IRQn) >= 0)
2577 {
2578 NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2579 }
2580 else
2581 {
2582 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2583 }
2584 }
2585
2586
2587 /**
2588 \brief Get Interrupt Priority
2589 \details Reads the priority of a device specific interrupt or a processor exception.
2590 The interrupt number can be positive to specify a device specific interrupt,
2591 or negative to specify a processor exception.
2592 \param [in] IRQn Interrupt number.
2593 \return Interrupt Priority.
2594 Value is aligned automatically to the implemented priority bits of the microcontroller.
2595 */
__NVIC_GetPriority(IRQn_Type IRQn)2596 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
2597 {
2598
2599 if ((int32_t)(IRQn) >= 0)
2600 {
2601 return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2602 }
2603 else
2604 {
2605 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2606 }
2607 }
2608
2609
2610 /**
2611 \brief Encode Priority
2612 \details Encodes the priority for an interrupt with the given priority group,
2613 preemptive priority value, and subpriority value.
2614 In case of a conflict between priority grouping and available
2615 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2616 \param [in] PriorityGroup Used priority group.
2617 \param [in] PreemptPriority Preemptive priority value (starting from 0).
2618 \param [in] SubPriority Subpriority value (starting from 0).
2619 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
2620 */
NVIC_EncodePriority(uint32_t PriorityGroup,uint32_t PreemptPriority,uint32_t SubPriority)2621 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
2622 {
2623 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2624 uint32_t PreemptPriorityBits;
2625 uint32_t SubPriorityBits;
2626
2627 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2628 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2629
2630 return (
2631 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
2632 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
2633 );
2634 }
2635
2636
2637 /**
2638 \brief Decode Priority
2639 \details Decodes an interrupt priority value with a given priority group to
2640 preemptive priority value and subpriority value.
2641 In case of a conflict between priority grouping and available
2642 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
2643 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
2644 \param [in] PriorityGroup Used priority group.
2645 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
2646 \param [out] pSubPriority Subpriority value (starting from 0).
2647 */
NVIC_DecodePriority(uint32_t Priority,uint32_t PriorityGroup,uint32_t * const pPreemptPriority,uint32_t * const pSubPriority)2648 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
2649 {
2650 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2651 uint32_t PreemptPriorityBits;
2652 uint32_t SubPriorityBits;
2653
2654 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2655 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2656
2657 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
2658 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
2659 }
2660
2661
2662 /**
2663 \brief Set Interrupt Vector
2664 \details Sets an interrupt vector in SRAM based interrupt vector table.
2665 The interrupt number can be positive to specify a device specific interrupt,
2666 or negative to specify a processor exception.
2667 VTOR must been relocated to SRAM before.
2668 \param [in] IRQn Interrupt number
2669 \param [in] vector Address of interrupt handler function
2670 */
__NVIC_SetVector(IRQn_Type IRQn,uint32_t vector)2671 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
2672 {
2673 uint32_t *vectors = (uint32_t *)SCB->VTOR;
2674 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
2675 __DSB();
2676 }
2677
2678
2679 /**
2680 \brief Get Interrupt Vector
2681 \details Reads an interrupt vector from interrupt vector table.
2682 The interrupt number can be positive to specify a device specific interrupt,
2683 or negative to specify a processor exception.
2684 \param [in] IRQn Interrupt number.
2685 \return Address of interrupt handler function
2686 */
__NVIC_GetVector(IRQn_Type IRQn)2687 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
2688 {
2689 uint32_t *vectors = (uint32_t *)SCB->VTOR;
2690 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
2691 }
2692
2693
2694 /**
2695 \brief System Reset
2696 \details Initiates a system reset request to reset the MCU.
2697 */
__NVIC_SystemReset(void)2698 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
2699 {
2700 __DSB(); /* Ensure all outstanding memory accesses included
2701 buffered write are completed before reset */
2702 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2703 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2704 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
2705 __DSB(); /* Ensure completion of memory access */
2706
2707 for(;;) /* wait until reset */
2708 {
2709 __NOP();
2710 }
2711 }
2712
2713 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2714 /**
2715 \brief Set Priority Grouping (non-secure)
2716 \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
2717 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
2718 Only values from 0..7 are used.
2719 In case of a conflict between priority grouping and available
2720 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2721 \param [in] PriorityGroup Priority grouping field.
2722 */
TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)2723 __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
2724 {
2725 uint32_t reg_value;
2726 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2727
2728 reg_value = SCB_NS->AIRCR; /* read old register configuration */
2729 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2730 reg_value = (reg_value |
2731 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2732 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
2733 SCB_NS->AIRCR = reg_value;
2734 }
2735
2736
2737 /**
2738 \brief Get Priority Grouping (non-secure)
2739 \details Reads the priority grouping field from the non-secure NVIC when in secure state.
2740 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
2741 */
TZ_NVIC_GetPriorityGrouping_NS(void)2742 __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
2743 {
2744 return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2745 }
2746
2747
2748 /**
2749 \brief Enable Interrupt (non-secure)
2750 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
2751 \param [in] IRQn Device specific interrupt number.
2752 \note IRQn must not be negative.
2753 */
TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)2754 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
2755 {
2756 if ((int32_t)(IRQn) >= 0)
2757 {
2758 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2759 }
2760 }
2761
2762
2763 /**
2764 \brief Get Interrupt Enable status (non-secure)
2765 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
2766 \param [in] IRQn Device specific interrupt number.
2767 \return 0 Interrupt is not enabled.
2768 \return 1 Interrupt is enabled.
2769 \note IRQn must not be negative.
2770 */
TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)2771 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
2772 {
2773 if ((int32_t)(IRQn) >= 0)
2774 {
2775 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2776 }
2777 else
2778 {
2779 return(0U);
2780 }
2781 }
2782
2783
2784 /**
2785 \brief Disable Interrupt (non-secure)
2786 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
2787 \param [in] IRQn Device specific interrupt number.
2788 \note IRQn must not be negative.
2789 */
TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)2790 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
2791 {
2792 if ((int32_t)(IRQn) >= 0)
2793 {
2794 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2795 }
2796 }
2797
2798
2799 /**
2800 \brief Get Pending Interrupt (non-secure)
2801 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
2802 \param [in] IRQn Device specific interrupt number.
2803 \return 0 Interrupt status is not pending.
2804 \return 1 Interrupt status is pending.
2805 \note IRQn must not be negative.
2806 */
TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)2807 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
2808 {
2809 if ((int32_t)(IRQn) >= 0)
2810 {
2811 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2812 }
2813 else
2814 {
2815 return(0U);
2816 }
2817 }
2818
2819
2820 /**
2821 \brief Set Pending Interrupt (non-secure)
2822 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
2823 \param [in] IRQn Device specific interrupt number.
2824 \note IRQn must not be negative.
2825 */
TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)2826 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
2827 {
2828 if ((int32_t)(IRQn) >= 0)
2829 {
2830 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2831 }
2832 }
2833
2834
2835 /**
2836 \brief Clear Pending Interrupt (non-secure)
2837 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
2838 \param [in] IRQn Device specific interrupt number.
2839 \note IRQn must not be negative.
2840 */
TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)2841 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
2842 {
2843 if ((int32_t)(IRQn) >= 0)
2844 {
2845 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2846 }
2847 }
2848
2849
2850 /**
2851 \brief Get Active Interrupt (non-secure)
2852 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
2853 \param [in] IRQn Device specific interrupt number.
2854 \return 0 Interrupt status is not active.
2855 \return 1 Interrupt status is active.
2856 \note IRQn must not be negative.
2857 */
TZ_NVIC_GetActive_NS(IRQn_Type IRQn)2858 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
2859 {
2860 if ((int32_t)(IRQn) >= 0)
2861 {
2862 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2863 }
2864 else
2865 {
2866 return(0U);
2867 }
2868 }
2869
2870
2871 /**
2872 \brief Set Interrupt Priority (non-secure)
2873 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
2874 The interrupt number can be positive to specify a device specific interrupt,
2875 or negative to specify a processor exception.
2876 \param [in] IRQn Interrupt number.
2877 \param [in] priority Priority to set.
2878 \note The priority cannot be set for every non-secure processor exception.
2879 */
TZ_NVIC_SetPriority_NS(IRQn_Type IRQn,uint32_t priority)2880 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
2881 {
2882 if ((int32_t)(IRQn) >= 0)
2883 {
2884 NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2885 }
2886 else
2887 {
2888 SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2889 }
2890 }
2891
2892
2893 /**
2894 \brief Get Interrupt Priority (non-secure)
2895 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
2896 The interrupt number can be positive to specify a device specific interrupt,
2897 or negative to specify a processor exception.
2898 \param [in] IRQn Interrupt number.
2899 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
2900 */
TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)2901 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
2902 {
2903
2904 if ((int32_t)(IRQn) >= 0)
2905 {
2906 return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2907 }
2908 else
2909 {
2910 return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2911 }
2912 }
2913 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
2914
2915 /*@} end of CMSIS_Core_NVICFunctions */
2916
2917 /* ########################## MPU functions #################################### */
2918
2919 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2920
2921 #include "mpu_armv8.h"
2922
2923 #endif
2924
2925 /* ########################## FPU functions #################################### */
2926 /**
2927 \ingroup CMSIS_Core_FunctionInterface
2928 \defgroup CMSIS_Core_FpuFunctions FPU Functions
2929 \brief Function that provides FPU type.
2930 @{
2931 */
2932
2933 /**
2934 \brief get FPU type
2935 \details returns the FPU type
2936 \returns
2937 - \b 0: No FPU
2938 - \b 1: Single precision FPU
2939 - \b 2: Double + Single precision FPU
2940 */
SCB_GetFPUType(void)2941 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
2942 {
2943 uint32_t mvfr0;
2944
2945 mvfr0 = FPU->MVFR0;
2946 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
2947 {
2948 return 2U; /* Double + Single precision FPU */
2949 }
2950 else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
2951 {
2952 return 1U; /* Single precision FPU */
2953 }
2954 else
2955 {
2956 return 0U; /* No FPU */
2957 }
2958 }
2959
2960
2961 /*@} end of CMSIS_Core_FpuFunctions */
2962
2963
2964
2965 /* ########################## SAU functions #################################### */
2966 /**
2967 \ingroup CMSIS_Core_FunctionInterface
2968 \defgroup CMSIS_Core_SAUFunctions SAU Functions
2969 \brief Functions that configure the SAU.
2970 @{
2971 */
2972
2973 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2974
2975 /**
2976 \brief Enable SAU
2977 \details Enables the Security Attribution Unit (SAU).
2978 */
TZ_SAU_Enable(void)2979 __STATIC_INLINE void TZ_SAU_Enable(void)
2980 {
2981 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
2982 }
2983
2984
2985
2986 /**
2987 \brief Disable SAU
2988 \details Disables the Security Attribution Unit (SAU).
2989 */
TZ_SAU_Disable(void)2990 __STATIC_INLINE void TZ_SAU_Disable(void)
2991 {
2992 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
2993 }
2994
2995 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2996
2997 /*@} end of CMSIS_Core_SAUFunctions */
2998
2999
3000
3001
3002 /* ################################## Debug Control function ############################################ */
3003 /**
3004 \ingroup CMSIS_Core_FunctionInterface
3005 \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
3006 \brief Functions that access the Debug Control Block.
3007 @{
3008 */
3009
3010
3011 /**
3012 \brief Set Debug Authentication Control Register
3013 \details writes to Debug Authentication Control register.
3014 \param [in] value value to be writen.
3015 */
DCB_SetAuthCtrl(uint32_t value)3016 __STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
3017 {
3018 __DSB();
3019 __ISB();
3020 DCB->DAUTHCTRL = value;
3021 __DSB();
3022 __ISB();
3023 }
3024
3025
3026 /**
3027 \brief Get Debug Authentication Control Register
3028 \details Reads Debug Authentication Control register.
3029 \return Debug Authentication Control Register.
3030 */
DCB_GetAuthCtrl(void)3031 __STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
3032 {
3033 return (DCB->DAUTHCTRL);
3034 }
3035
3036
3037 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3038 /**
3039 \brief Set Debug Authentication Control Register (non-secure)
3040 \details writes to non-secure Debug Authentication Control register when in secure state.
3041 \param [in] value value to be writen
3042 */
TZ_DCB_SetAuthCtrl_NS(uint32_t value)3043 __STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
3044 {
3045 __DSB();
3046 __ISB();
3047 DCB_NS->DAUTHCTRL = value;
3048 __DSB();
3049 __ISB();
3050 }
3051
3052
3053 /**
3054 \brief Get Debug Authentication Control Register (non-secure)
3055 \details Reads non-secure Debug Authentication Control register when in secure state.
3056 \return Debug Authentication Control Register.
3057 */
TZ_DCB_GetAuthCtrl_NS(void)3058 __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
3059 {
3060 return (DCB_NS->DAUTHCTRL);
3061 }
3062 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3063
3064 /*@} end of CMSIS_Core_DCBFunctions */
3065
3066
3067
3068
3069 /* ################################## Debug Identification function ############################################ */
3070 /**
3071 \ingroup CMSIS_Core_FunctionInterface
3072 \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
3073 \brief Functions that access the Debug Identification Block.
3074 @{
3075 */
3076
3077
3078 /**
3079 \brief Get Debug Authentication Status Register
3080 \details Reads Debug Authentication Status register.
3081 \return Debug Authentication Status Register.
3082 */
DIB_GetAuthStatus(void)3083 __STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
3084 {
3085 return (DIB->DAUTHSTATUS);
3086 }
3087
3088
3089 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3090 /**
3091 \brief Get Debug Authentication Status Register (non-secure)
3092 \details Reads non-secure Debug Authentication Status register when in secure state.
3093 \return Debug Authentication Status Register.
3094 */
TZ_DIB_GetAuthStatus_NS(void)3095 __STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
3096 {
3097 return (DIB_NS->DAUTHSTATUS);
3098 }
3099 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3100
3101 /*@} end of CMSIS_Core_DCBFunctions */
3102
3103
3104
3105
3106 /* ################################## SysTick function ############################################ */
3107 /**
3108 \ingroup CMSIS_Core_FunctionInterface
3109 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
3110 \brief Functions that configure the System.
3111 @{
3112 */
3113
3114 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
3115
3116 /**
3117 \brief System Tick Configuration
3118 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
3119 Counter is in free running mode to generate periodic interrupts.
3120 \param [in] ticks Number of ticks between two interrupts.
3121 \return 0 Function succeeded.
3122 \return 1 Function failed.
3123 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
3124 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
3125 must contain a vendor-specific implementation of this function.
3126 */
SysTick_Config(uint32_t ticks)3127 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
3128 {
3129 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
3130 {
3131 return (1UL); /* Reload value impossible */
3132 }
3133
3134 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
3135 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
3136 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
3137 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
3138 SysTick_CTRL_TICKINT_Msk |
3139 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
3140 return (0UL); /* Function successful */
3141 }
3142
3143 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3144 /**
3145 \brief System Tick Configuration (non-secure)
3146 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
3147 Counter is in free running mode to generate periodic interrupts.
3148 \param [in] ticks Number of ticks between two interrupts.
3149 \return 0 Function succeeded.
3150 \return 1 Function failed.
3151 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
3152 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
3153 must contain a vendor-specific implementation of this function.
3154
3155 */
TZ_SysTick_Config_NS(uint32_t ticks)3156 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
3157 {
3158 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
3159 {
3160 return (1UL); /* Reload value impossible */
3161 }
3162
3163 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
3164 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
3165 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
3166 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
3167 SysTick_CTRL_TICKINT_Msk |
3168 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
3169 return (0UL); /* Function successful */
3170 }
3171 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3172
3173 #endif
3174
3175 /*@} end of CMSIS_Core_SysTickFunctions */
3176
3177
3178
3179 /* ##################################### Debug In/Output function ########################################### */
3180 /**
3181 \ingroup CMSIS_Core_FunctionInterface
3182 \defgroup CMSIS_core_DebugFunctions ITM Functions
3183 \brief Functions that access the ITM debug interface.
3184 @{
3185 */
3186
3187 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
3188 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
3189
3190
3191 /**
3192 \brief ITM Send Character
3193 \details Transmits a character via the ITM channel 0, and
3194 \li Just returns when no debugger is connected that has booked the output.
3195 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
3196 \param [in] ch Character to transmit.
3197 \returns Character to transmit.
3198 */
ITM_SendChar(uint32_t ch)3199 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
3200 {
3201 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
3202 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
3203 {
3204 while (ITM->PORT[0U].u32 == 0UL)
3205 {
3206 __NOP();
3207 }
3208 ITM->PORT[0U].u8 = (uint8_t)ch;
3209 }
3210 return (ch);
3211 }
3212
3213
3214 /**
3215 \brief ITM Receive Character
3216 \details Inputs a character via the external variable \ref ITM_RxBuffer.
3217 \return Received character.
3218 \return -1 No character pending.
3219 */
ITM_ReceiveChar(void)3220 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
3221 {
3222 int32_t ch = -1; /* no character available */
3223
3224 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
3225 {
3226 ch = ITM_RxBuffer;
3227 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
3228 }
3229
3230 return (ch);
3231 }
3232
3233
3234 /**
3235 \brief ITM Check Character
3236 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
3237 \return 0 No character available.
3238 \return 1 Character available.
3239 */
ITM_CheckChar(void)3240 __STATIC_INLINE int32_t ITM_CheckChar (void)
3241 {
3242
3243 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
3244 {
3245 return (0); /* no character available */
3246 }
3247 else
3248 {
3249 return (1); /* character available */
3250 }
3251 }
3252
3253 /*@} end of CMSIS_core_DebugFunctions */
3254
3255
3256
3257
3258 #ifdef __cplusplus
3259 }
3260 #endif
3261
3262 #endif /* __CORE_CM35P_H_DEPENDANT */
3263
3264 #endif /* __CMSIS_GENERIC */
3265