1#! /usr/bin/env perl 2# Copyright 2009-2020 The OpenSSL Project Authors. All Rights Reserved. 3# 4# Licensed under the OpenSSL license (the "License"). You may not use 5# this file except in compliance with the License. You can obtain a copy 6# in the file LICENSE in the source distribution or at 7# https://www.openssl.org/source/license.html 8 9 10# ==================================================================== 11# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL 12# project. The module is, however, dual licensed under OpenSSL and 13# CRYPTOGAMS licenses depending on where you obtain it. For further 14# details see http://www.openssl.org/~appro/cryptogams/. 15# ==================================================================== 16 17# January 2009 18# 19# Provided that UltraSPARC VIS instructions are pipe-lined(*) and 20# pairable(*) with IALU ones, offloading of Xupdate to the UltraSPARC 21# Graphic Unit would make it possible to achieve higher instruction- 22# level parallelism, ILP, and thus higher performance. It should be 23# explicitly noted that ILP is the keyword, and it means that this 24# code would be unsuitable for cores like UltraSPARC-Tx. The idea is 25# not really novel, Sun had VIS-powered implementation for a while. 26# Unlike Sun's implementation this one can process multiple unaligned 27# input blocks, and as such works as drop-in replacement for OpenSSL 28# sha1_block_data_order. Performance improvement was measured to be 29# 40% over pure IALU sha1-sparcv9.pl on UltraSPARC-IIi, but 12% on 30# UltraSPARC-III. See below for discussion... 31# 32# The module does not present direct interest for OpenSSL, because 33# it doesn't provide better performance on contemporary SPARCv9 CPUs, 34# UltraSPARC-Tx and SPARC64-V[II] to be specific. Those who feel they 35# absolutely must score on UltraSPARC-I-IV can simply replace 36# crypto/sha/asm/sha1-sparcv9.pl with this module. 37# 38# (*) "Pipe-lined" means that even if it takes several cycles to 39# complete, next instruction using same functional unit [but not 40# depending on the result of the current instruction] can start 41# execution without having to wait for the unit. "Pairable" 42# means that two [or more] independent instructions can be 43# issued at the very same time. 44 45$bits=32; 46for (@ARGV) { $bits=64 if (/\-m64/ || /\-xarch\=v9/); } 47if ($bits==64) { $bias=2047; $frame=192; } 48else { $bias=0; $frame=112; } 49 50$output=shift; 51open STDOUT,">$output"; 52 53$ctx="%i0"; 54$inp="%i1"; 55$len="%i2"; 56$tmp0="%i3"; 57$tmp1="%i4"; 58$tmp2="%i5"; 59$tmp3="%g5"; 60 61$base="%g1"; 62$align="%g4"; 63$Xfer="%o5"; 64$nXfer=$tmp3; 65$Xi="%o7"; 66 67$A="%l0"; 68$B="%l1"; 69$C="%l2"; 70$D="%l3"; 71$E="%l4"; 72@V=($A,$B,$C,$D,$E); 73 74$Actx="%o0"; 75$Bctx="%o1"; 76$Cctx="%o2"; 77$Dctx="%o3"; 78$Ectx="%o4"; 79 80$fmul="%f32"; 81$VK_00_19="%f34"; 82$VK_20_39="%f36"; 83$VK_40_59="%f38"; 84$VK_60_79="%f40"; 85@VK=($VK_00_19,$VK_20_39,$VK_40_59,$VK_60_79); 86@X=("%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", 87 "%f8", "%f9","%f10","%f11","%f12","%f13","%f14","%f15","%f16"); 88 89# This is reference 2x-parallelized VIS-powered Xupdate procedure. It 90# covers even K_NN_MM addition... 91sub Xupdate { 92my ($i)=@_; 93my $K=@VK[($i+16)/20]; 94my $j=($i+16)%16; 95 96# [ provided that GSR.alignaddr_offset is 5, $mul contains 97# 0x100ULL<<32|0x100 value and K_NN_MM are pre-loaded to 98# chosen registers... ] 99$code.=<<___; 100 fxors @X[($j+13)%16],@X[$j],@X[$j] !-1/-1/-1:X[0]^=X[13] 101 fxors @X[($j+14)%16],@X[$j+1],@X[$j+1]! 0/ 0/ 0:X[1]^=X[14] 102 fxor @X[($j+2)%16],@X[($j+8)%16],%f18! 1/ 1/ 1:Tmp=X[2,3]^X[8,9] 103 fxor %f18,@X[$j],@X[$j] ! 2/ 4/ 3:X[0,1]^=X[2,3]^X[8,9] 104 faligndata @X[$j],@X[$j],%f18 ! 3/ 7/ 5:Tmp=X[0,1]>>>24 105 fpadd32 @X[$j],@X[$j],@X[$j] ! 4/ 8/ 6:X[0,1]<<=1 106 fmul8ulx16 %f18,$fmul,%f18 ! 5/10/ 7:Tmp>>=7, Tmp&=1 107 ![fxors %f15,%f2,%f2] 108 for %f18,@X[$j],@X[$j] ! 8/14/10:X[0,1]|=Tmp 109 ![fxors %f0,%f3,%f3] !10/17/12:X[0] dependency 110 fpadd32 $K,@X[$j],%f20 111 std %f20,[$Xfer+`4*$j`] 112___ 113# The numbers delimited with slash are the earliest possible dispatch 114# cycles for given instruction assuming 1 cycle latency for simple VIS 115# instructions, such as on UltraSPARC-I&II, 3 cycles latency, such as 116# on UltraSPARC-III&IV, and 2 cycles latency(*), respectively. Being 117# 2x-parallelized the procedure is "worth" 5, 8.5 or 6 ticks per SHA1 118# round. As [long as] FPU/VIS instructions are perfectly pairable with 119# IALU ones, the round timing is defined by the maximum between VIS 120# and IALU timings. The latter varies from round to round and averages 121# out at 6.25 ticks. This means that USI&II should operate at IALU 122# rate, while USIII&IV - at VIS rate. This explains why performance 123# improvement varies among processors. Well, given that pure IALU 124# sha1-sparcv9.pl module exhibits virtually uniform performance of 125# ~9.3 cycles per SHA1 round. Timings mentioned above are theoretical 126# lower limits. Real-life performance was measured to be 6.6 cycles 127# per SHA1 round on USIIi and 8.3 on USIII. The latter is lower than 128# half-round VIS timing, because there are 16 Xupdate-free rounds, 129# which "push down" average theoretical timing to 8 cycles... 130 131# (*) SPARC64-V[II] was originally believed to have 2 cycles VIS 132# latency. Well, it might have, but it doesn't have dedicated 133# VIS-unit. Instead, VIS instructions are executed by other 134# functional units, ones used here - by IALU. This doesn't 135# improve effective ILP... 136} 137 138# The reference Xupdate procedure is then "strained" over *pairs* of 139# BODY_NN_MM and kind of modulo-scheduled in respect to X[n]^=X[n+13] 140# and K_NN_MM addition. It's "running" 15 rounds ahead, which leaves 141# plenty of room to amortize for read-after-write hazard, as well as 142# to fetch and align input for the next spin. The VIS instructions are 143# scheduled for latency of 2 cycles, because there are not enough IALU 144# instructions to schedule for latency of 3, while scheduling for 1 145# would give no gain on USI&II anyway. 146 147sub BODY_00_19 { 148my ($i,$a,$b,$c,$d,$e)=@_; 149my $j=$i&~1; 150my $k=($j+16+2)%16; # ahead reference 151my $l=($j+16-2)%16; # behind reference 152my $K=@VK[($j+16-2)/20]; 153 154$j=($j+16)%16; 155 156$code.=<<___ if (!($i&1)); 157 sll $a,5,$tmp0 !! $i 158 and $c,$b,$tmp3 159 ld [$Xfer+`4*($i%16)`],$Xi 160 fxors @X[($j+14)%16],@X[$j+1],@X[$j+1]! 0/ 0/ 0:X[1]^=X[14] 161 srl $a,27,$tmp1 162 add $tmp0,$e,$e 163 fxor @X[($j+2)%16],@X[($j+8)%16],%f18! 1/ 1/ 1:Tmp=X[2,3]^X[8,9] 164 sll $b,30,$tmp2 165 add $tmp1,$e,$e 166 andn $d,$b,$tmp1 167 add $Xi,$e,$e 168 fxor %f18,@X[$j],@X[$j] ! 2/ 4/ 3:X[0,1]^=X[2,3]^X[8,9] 169 srl $b,2,$b 170 or $tmp1,$tmp3,$tmp1 171 or $tmp2,$b,$b 172 add $tmp1,$e,$e 173 faligndata @X[$j],@X[$j],%f18 ! 3/ 7/ 5:Tmp=X[0,1]>>>24 174___ 175$code.=<<___ if ($i&1); 176 sll $a,5,$tmp0 !! $i 177 and $c,$b,$tmp3 178 ld [$Xfer+`4*($i%16)`],$Xi 179 fpadd32 @X[$j],@X[$j],@X[$j] ! 4/ 8/ 6:X[0,1]<<=1 180 srl $a,27,$tmp1 181 add $tmp0,$e,$e 182 fmul8ulx16 %f18,$fmul,%f18 ! 5/10/ 7:Tmp>>=7, Tmp&=1 183 sll $b,30,$tmp2 184 add $tmp1,$e,$e 185 fpadd32 $K,@X[$l],%f20 ! 186 andn $d,$b,$tmp1 187 add $Xi,$e,$e 188 fxors @X[($k+13)%16],@X[$k],@X[$k] !-1/-1/-1:X[0]^=X[13] 189 srl $b,2,$b 190 or $tmp1,$tmp3,$tmp1 191 fxor %f18,@X[$j],@X[$j] ! 8/14/10:X[0,1]|=Tmp 192 or $tmp2,$b,$b 193 add $tmp1,$e,$e 194___ 195$code.=<<___ if ($i&1 && $i>=2); 196 std %f20,[$Xfer+`4*$l`] ! 197___ 198} 199 200sub BODY_20_39 { 201my ($i,$a,$b,$c,$d,$e)=@_; 202my $j=$i&~1; 203my $k=($j+16+2)%16; # ahead reference 204my $l=($j+16-2)%16; # behind reference 205my $K=@VK[($j+16-2)/20]; 206 207$j=($j+16)%16; 208 209$code.=<<___ if (!($i&1) && $i<64); 210 sll $a,5,$tmp0 !! $i 211 ld [$Xfer+`4*($i%16)`],$Xi 212 fxors @X[($j+14)%16],@X[$j+1],@X[$j+1]! 0/ 0/ 0:X[1]^=X[14] 213 srl $a,27,$tmp1 214 add $tmp0,$e,$e 215 fxor @X[($j+2)%16],@X[($j+8)%16],%f18! 1/ 1/ 1:Tmp=X[2,3]^X[8,9] 216 xor $c,$b,$tmp0 217 add $tmp1,$e,$e 218 sll $b,30,$tmp2 219 xor $d,$tmp0,$tmp1 220 fxor %f18,@X[$j],@X[$j] ! 2/ 4/ 3:X[0,1]^=X[2,3]^X[8,9] 221 srl $b,2,$b 222 add $tmp1,$e,$e 223 or $tmp2,$b,$b 224 add $Xi,$e,$e 225 faligndata @X[$j],@X[$j],%f18 ! 3/ 7/ 5:Tmp=X[0,1]>>>24 226___ 227$code.=<<___ if ($i&1 && $i<64); 228 sll $a,5,$tmp0 !! $i 229 ld [$Xfer+`4*($i%16)`],$Xi 230 fpadd32 @X[$j],@X[$j],@X[$j] ! 4/ 8/ 6:X[0,1]<<=1 231 srl $a,27,$tmp1 232 add $tmp0,$e,$e 233 fmul8ulx16 %f18,$fmul,%f18 ! 5/10/ 7:Tmp>>=7, Tmp&=1 234 xor $c,$b,$tmp0 235 add $tmp1,$e,$e 236 fpadd32 $K,@X[$l],%f20 ! 237 sll $b,30,$tmp2 238 xor $d,$tmp0,$tmp1 239 fxors @X[($k+13)%16],@X[$k],@X[$k] !-1/-1/-1:X[0]^=X[13] 240 srl $b,2,$b 241 add $tmp1,$e,$e 242 fxor %f18,@X[$j],@X[$j] ! 8/14/10:X[0,1]|=Tmp 243 or $tmp2,$b,$b 244 add $Xi,$e,$e 245 std %f20,[$Xfer+`4*$l`] ! 246___ 247$code.=<<___ if ($i==64); 248 sll $a,5,$tmp0 !! $i 249 ld [$Xfer+`4*($i%16)`],$Xi 250 fpadd32 $K,@X[$l],%f20 251 srl $a,27,$tmp1 252 add $tmp0,$e,$e 253 xor $c,$b,$tmp0 254 add $tmp1,$e,$e 255 sll $b,30,$tmp2 256 xor $d,$tmp0,$tmp1 257 std %f20,[$Xfer+`4*$l`] 258 srl $b,2,$b 259 add $tmp1,$e,$e 260 or $tmp2,$b,$b 261 add $Xi,$e,$e 262___ 263$code.=<<___ if ($i>64); 264 sll $a,5,$tmp0 !! $i 265 ld [$Xfer+`4*($i%16)`],$Xi 266 srl $a,27,$tmp1 267 add $tmp0,$e,$e 268 xor $c,$b,$tmp0 269 add $tmp1,$e,$e 270 sll $b,30,$tmp2 271 xor $d,$tmp0,$tmp1 272 srl $b,2,$b 273 add $tmp1,$e,$e 274 or $tmp2,$b,$b 275 add $Xi,$e,$e 276___ 277} 278 279sub BODY_40_59 { 280my ($i,$a,$b,$c,$d,$e)=@_; 281my $j=$i&~1; 282my $k=($j+16+2)%16; # ahead reference 283my $l=($j+16-2)%16; # behind reference 284my $K=@VK[($j+16-2)/20]; 285 286$j=($j+16)%16; 287 288$code.=<<___ if (!($i&1)); 289 sll $a,5,$tmp0 !! $i 290 ld [$Xfer+`4*($i%16)`],$Xi 291 fxors @X[($j+14)%16],@X[$j+1],@X[$j+1]! 0/ 0/ 0:X[1]^=X[14] 292 srl $a,27,$tmp1 293 add $tmp0,$e,$e 294 fxor @X[($j+2)%16],@X[($j+8)%16],%f18! 1/ 1/ 1:Tmp=X[2,3]^X[8,9] 295 and $c,$b,$tmp0 296 add $tmp1,$e,$e 297 sll $b,30,$tmp2 298 or $c,$b,$tmp1 299 fxor %f18,@X[$j],@X[$j] ! 2/ 4/ 3:X[0,1]^=X[2,3]^X[8,9] 300 srl $b,2,$b 301 and $d,$tmp1,$tmp1 302 add $Xi,$e,$e 303 or $tmp1,$tmp0,$tmp1 304 faligndata @X[$j],@X[$j],%f18 ! 3/ 7/ 5:Tmp=X[0,1]>>>24 305 or $tmp2,$b,$b 306 add $tmp1,$e,$e 307 fpadd32 @X[$j],@X[$j],@X[$j] ! 4/ 8/ 6:X[0,1]<<=1 308___ 309$code.=<<___ if ($i&1); 310 sll $a,5,$tmp0 !! $i 311 ld [$Xfer+`4*($i%16)`],$Xi 312 srl $a,27,$tmp1 313 add $tmp0,$e,$e 314 fmul8ulx16 %f18,$fmul,%f18 ! 5/10/ 7:Tmp>>=7, Tmp&=1 315 and $c,$b,$tmp0 316 add $tmp1,$e,$e 317 fpadd32 $K,@X[$l],%f20 ! 318 sll $b,30,$tmp2 319 or $c,$b,$tmp1 320 fxors @X[($k+13)%16],@X[$k],@X[$k] !-1/-1/-1:X[0]^=X[13] 321 srl $b,2,$b 322 and $d,$tmp1,$tmp1 323 fxor %f18,@X[$j],@X[$j] ! 8/14/10:X[0,1]|=Tmp 324 add $Xi,$e,$e 325 or $tmp1,$tmp0,$tmp1 326 or $tmp2,$b,$b 327 add $tmp1,$e,$e 328 std %f20,[$Xfer+`4*$l`] ! 329___ 330} 331 332# If there is more data to process, then we pre-fetch the data for 333# next iteration in last ten rounds... 334sub BODY_70_79 { 335my ($i,$a,$b,$c,$d,$e)=@_; 336my $j=$i&~1; 337my $m=($i%8)*2; 338 339$j=($j+16)%16; 340 341$code.=<<___ if ($i==70); 342 sll $a,5,$tmp0 !! $i 343 ld [$Xfer+`4*($i%16)`],$Xi 344 srl $a,27,$tmp1 345 add $tmp0,$e,$e 346 ldd [$inp+64],@X[0] 347 xor $c,$b,$tmp0 348 add $tmp1,$e,$e 349 sll $b,30,$tmp2 350 xor $d,$tmp0,$tmp1 351 srl $b,2,$b 352 add $tmp1,$e,$e 353 or $tmp2,$b,$b 354 add $Xi,$e,$e 355 356 and $inp,-64,$nXfer 357 inc 64,$inp 358 and $nXfer,255,$nXfer 359 alignaddr %g0,$align,%g0 360 add $base,$nXfer,$nXfer 361___ 362$code.=<<___ if ($i==71); 363 sll $a,5,$tmp0 !! $i 364 ld [$Xfer+`4*($i%16)`],$Xi 365 srl $a,27,$tmp1 366 add $tmp0,$e,$e 367 xor $c,$b,$tmp0 368 add $tmp1,$e,$e 369 sll $b,30,$tmp2 370 xor $d,$tmp0,$tmp1 371 srl $b,2,$b 372 add $tmp1,$e,$e 373 or $tmp2,$b,$b 374 add $Xi,$e,$e 375___ 376$code.=<<___ if ($i>=72); 377 faligndata @X[$m],@X[$m+2],@X[$m] 378 sll $a,5,$tmp0 !! $i 379 ld [$Xfer+`4*($i%16)`],$Xi 380 srl $a,27,$tmp1 381 add $tmp0,$e,$e 382 xor $c,$b,$tmp0 383 add $tmp1,$e,$e 384 fpadd32 $VK_00_19,@X[$m],%f20 385 sll $b,30,$tmp2 386 xor $d,$tmp0,$tmp1 387 srl $b,2,$b 388 add $tmp1,$e,$e 389 or $tmp2,$b,$b 390 add $Xi,$e,$e 391___ 392$code.=<<___ if ($i<77); 393 ldd [$inp+`8*($i+1-70)`],@X[2*($i+1-70)] 394___ 395$code.=<<___ if ($i==77); # redundant if $inp was aligned 396 add $align,63,$tmp0 397 and $tmp0,-8,$tmp0 398 ldd [$inp+$tmp0],@X[16] 399___ 400$code.=<<___ if ($i>=72); 401 std %f20,[$nXfer+`4*$m`] 402___ 403} 404 405$code.=<<___; 406.section ".text",#alloc,#execinstr 407 408.align 64 409vis_const: 410.long 0x5a827999,0x5a827999 ! K_00_19 411.long 0x6ed9eba1,0x6ed9eba1 ! K_20_39 412.long 0x8f1bbcdc,0x8f1bbcdc ! K_40_59 413.long 0xca62c1d6,0xca62c1d6 ! K_60_79 414.long 0x00000100,0x00000100 415.align 64 416.type vis_const,#object 417.size vis_const,(.-vis_const) 418 419.globl sha1_block_data_order 420sha1_block_data_order: 421 save %sp,-$frame,%sp 422 add %fp,$bias-256,$base 423 4241: call .+8 425 add %o7,vis_const-1b,$tmp0 426 427 ldd [$tmp0+0],$VK_00_19 428 ldd [$tmp0+8],$VK_20_39 429 ldd [$tmp0+16],$VK_40_59 430 ldd [$tmp0+24],$VK_60_79 431 ldd [$tmp0+32],$fmul 432 433 ld [$ctx+0],$Actx 434 and $base,-256,$base 435 ld [$ctx+4],$Bctx 436 sub $base,$bias+$frame,%sp 437 ld [$ctx+8],$Cctx 438 and $inp,7,$align 439 ld [$ctx+12],$Dctx 440 and $inp,-8,$inp 441 ld [$ctx+16],$Ectx 442 443 ! X[16] is maintained in FP register bank 444 alignaddr %g0,$align,%g0 445 ldd [$inp+0],@X[0] 446 sub $inp,-64,$Xfer 447 ldd [$inp+8],@X[2] 448 and $Xfer,-64,$Xfer 449 ldd [$inp+16],@X[4] 450 and $Xfer,255,$Xfer 451 ldd [$inp+24],@X[6] 452 add $base,$Xfer,$Xfer 453 ldd [$inp+32],@X[8] 454 ldd [$inp+40],@X[10] 455 ldd [$inp+48],@X[12] 456 brz,pt $align,.Laligned 457 ldd [$inp+56],@X[14] 458 459 ldd [$inp+64],@X[16] 460 faligndata @X[0],@X[2],@X[0] 461 faligndata @X[2],@X[4],@X[2] 462 faligndata @X[4],@X[6],@X[4] 463 faligndata @X[6],@X[8],@X[6] 464 faligndata @X[8],@X[10],@X[8] 465 faligndata @X[10],@X[12],@X[10] 466 faligndata @X[12],@X[14],@X[12] 467 faligndata @X[14],@X[16],@X[14] 468 469.Laligned: 470 mov 5,$tmp0 471 dec 1,$len 472 alignaddr %g0,$tmp0,%g0 473 fpadd32 $VK_00_19,@X[0],%f16 474 fpadd32 $VK_00_19,@X[2],%f18 475 fpadd32 $VK_00_19,@X[4],%f20 476 fpadd32 $VK_00_19,@X[6],%f22 477 fpadd32 $VK_00_19,@X[8],%f24 478 fpadd32 $VK_00_19,@X[10],%f26 479 fpadd32 $VK_00_19,@X[12],%f28 480 fpadd32 $VK_00_19,@X[14],%f30 481 std %f16,[$Xfer+0] 482 mov $Actx,$A 483 std %f18,[$Xfer+8] 484 mov $Bctx,$B 485 std %f20,[$Xfer+16] 486 mov $Cctx,$C 487 std %f22,[$Xfer+24] 488 mov $Dctx,$D 489 std %f24,[$Xfer+32] 490 mov $Ectx,$E 491 std %f26,[$Xfer+40] 492 fxors @X[13],@X[0],@X[0] 493 std %f28,[$Xfer+48] 494 ba .Loop 495 std %f30,[$Xfer+56] 496.align 32 497.Loop: 498___ 499for ($i=0;$i<20;$i++) { &BODY_00_19($i,@V); unshift(@V,pop(@V)); } 500for (;$i<40;$i++) { &BODY_20_39($i,@V); unshift(@V,pop(@V)); } 501for (;$i<60;$i++) { &BODY_40_59($i,@V); unshift(@V,pop(@V)); } 502for (;$i<70;$i++) { &BODY_20_39($i,@V); unshift(@V,pop(@V)); } 503$code.=<<___; 504 tst $len 505 bz,pn `$bits==32?"%icc":"%xcc"`,.Ltail 506 nop 507___ 508for (;$i<80;$i++) { &BODY_70_79($i,@V); unshift(@V,pop(@V)); } 509$code.=<<___; 510 add $A,$Actx,$Actx 511 add $B,$Bctx,$Bctx 512 add $C,$Cctx,$Cctx 513 add $D,$Dctx,$Dctx 514 add $E,$Ectx,$Ectx 515 mov 5,$tmp0 516 fxors @X[13],@X[0],@X[0] 517 mov $Actx,$A 518 mov $Bctx,$B 519 mov $Cctx,$C 520 mov $Dctx,$D 521 mov $Ectx,$E 522 alignaddr %g0,$tmp0,%g0 523 dec 1,$len 524 ba .Loop 525 mov $nXfer,$Xfer 526 527.align 32 528.Ltail: 529___ 530for($i=70;$i<80;$i++) { &BODY_20_39($i,@V); unshift(@V,pop(@V)); } 531$code.=<<___; 532 add $A,$Actx,$Actx 533 add $B,$Bctx,$Bctx 534 add $C,$Cctx,$Cctx 535 add $D,$Dctx,$Dctx 536 add $E,$Ectx,$Ectx 537 538 st $Actx,[$ctx+0] 539 st $Bctx,[$ctx+4] 540 st $Cctx,[$ctx+8] 541 st $Dctx,[$ctx+12] 542 st $Ectx,[$ctx+16] 543 544 ret 545 restore 546.type sha1_block_data_order,#function 547.size sha1_block_data_order,(.-sha1_block_data_order) 548.asciz "SHA1 block transform for SPARCv9a, CRYPTOGAMS by <appro\@openssl.org>" 549.align 4 550___ 551 552# Purpose of these subroutines is to explicitly encode VIS instructions, 553# so that one can compile the module without having to specify VIS 554# extensions on compiler command line, e.g. -xarch=v9 vs. -xarch=v9a. 555# Idea is to reserve for option to produce "universal" binary and let 556# programmer detect if current CPU is VIS capable at run-time. 557sub unvis { 558my ($mnemonic,$rs1,$rs2,$rd)=@_; 559my ($ref,$opf); 560my %visopf = ( "fmul8ulx16" => 0x037, 561 "faligndata" => 0x048, 562 "fpadd32" => 0x052, 563 "fxor" => 0x06c, 564 "fxors" => 0x06d ); 565 566 $ref = "$mnemonic\t$rs1,$rs2,$rd"; 567 568 if ($opf=$visopf{$mnemonic}) { 569 foreach ($rs1,$rs2,$rd) { 570 return $ref if (!/%f([0-9]{1,2})/); 571 $_=$1; 572 if ($1>=32) { 573 return $ref if ($1&1); 574 # re-encode for upper double register addressing 575 $_=($1|$1>>5)&31; 576 } 577 } 578 579 return sprintf ".word\t0x%08x !%s", 580 0x81b00000|$rd<<25|$rs1<<14|$opf<<5|$rs2, 581 $ref; 582 } else { 583 return $ref; 584 } 585} 586sub unalignaddr { 587my ($mnemonic,$rs1,$rs2,$rd)=@_; 588my %bias = ( "g" => 0, "o" => 8, "l" => 16, "i" => 24 ); 589my $ref="$mnemonic\t$rs1,$rs2,$rd"; 590 591 foreach ($rs1,$rs2,$rd) { 592 if (/%([goli])([0-7])/) { $_=$bias{$1}+$2; } 593 else { return $ref; } 594 } 595 return sprintf ".word\t0x%08x !%s", 596 0x81b00300|$rd<<25|$rs1<<14|$rs2, 597 $ref; 598} 599 600$code =~ s/\`([^\`]*)\`/eval $1/gem; 601$code =~ s/\b(f[^\s]*)\s+(%f[0-9]{1,2}),(%f[0-9]{1,2}),(%f[0-9]{1,2})/ 602 &unvis($1,$2,$3,$4) 603 /gem; 604$code =~ s/\b(alignaddr)\s+(%[goli][0-7]),(%[goli][0-7]),(%[goli][0-7])/ 605 &unalignaddr($1,$2,$3,$4) 606 /gem; 607print $code; 608close STDOUT or die "error closing STDOUT: $!"; 609