1 /*
2 * pll_trainning.c
3 *
4 * The pll trainning Device Driver for hisilicon.
5 *
6 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 *
21 */
22 #include <asm/arch/platform.h>
23 #include <config.h>
24 #include <asm/io.h>
25 #include <asm/string.h>
26
27 #ifdef CONFIG_EDMA_PLL_TRAINNING
28
29 #define __24MHZ 24000000
30
31 #define LOOP_COUNT 5
32
33 #define THE_CRG_BASE 0x12010000
34 #define PERI_CRG_PLL1 0x04
35 #define PERI_CRG32 0x80
36 #define PERI_CRG101 0x194
37 #define PERI_CRG110 0x1b8
38
39 #define MISC_REG_BASE 0x12028000
40 #define SVB_CTRL_BASE 0x12080000
41 #define SVB_SYS_VOLTAGE_OFFSET 0x04
42 #define SVB_SYS_VOLTAGE_UPDATE_OFFSET 0x0C
43 #define SVB_PWM_SEL 0x1202009c
44
45 #define UART0_REG_PHYS 0x12040000
46 #define UART1_REG_PHYS 0x12041000
47 #define UART2_REG_PHYS 0x12042000
48
49 #define UART_DR 0x0
50 #define UART_CR 0x30
51
52 #define HIEDMA0_REG_BASE 0x100b0000
53 #define INT_TC1 0x4
54 #define INT_TC1_RAW 0x600
55
56 #define DMA_RXCHNL_CONFIG 0x47700005
57 #define DMA_TXCHNL_CONFIG 0x87700005
58 #define DMA_REG_CHNL0 0X830
59 #define DMA_REG_CHNL1 0X870
60
61 #define DMA_CHNL0_DONE (1<<0)
62 #define DMA_CHNL1_DONE (1<<1)
63
64 #define DDR_DATA_BASE 0x42000000
65
66 #define ioremap(physaddr, size) ((void *)(physaddr))
67 #define iounmap(physassr) ((void)0)
68
69 #define array_size(x) (sizeof(x) / sizeof((x)[0]))
70
71 #define pll_trainning_debug(s)
72 #define pll_trainning_debug_hex(s)
73 void uart_early_puts(const char *ss);
74 void uart_early_put_hex(int hex);
75
udelay(unsigned int num)76 static inline void udelay(unsigned int num)
77 {
78 volatile unsigned int i;
79
80 for (i = 0; i < (100 * num); i++) /* 100: Cycle */
81 __asm__ __volatile__("nop");
82 }
83
84 static unsigned long dma_phys;
85
86 static void *crg_base;
87 static void *misc_base;
88 static void *edma0_reg_base;
89
90 struct pin_info {
91 unsigned long pinmx_reg_base;
92 unsigned long pinmx_reg_offset;
93 unsigned int pinmx_func_num;
94 unsigned int restored_val;
95 unsigned int pinmx_func_changed;
96 };
97
98 static struct pin_info pmx_list[] = {
99 {
100 .pinmx_reg_base = 0x100c0000,
101 .pinmx_reg_offset = 0x0c,
102 .pinmx_func_num = 0x2,
103 .restored_val = 0x0,
104 .pinmx_func_changed = 0
105 },
106 {
107 .pinmx_reg_base = 0x100c0000,
108 .pinmx_reg_offset = 0x10,
109 .pinmx_func_num = 0x2,
110 .restored_val = 0x0,
111 .pinmx_func_changed = 0
112 },
113 {
114 .pinmx_reg_base = 0x112c0000,
115 .pinmx_reg_offset = 0x70,
116 .pinmx_func_num = 0x2,
117 .restored_val = 0x0,
118 .pinmx_func_changed = 0
119 },
120 {
121 .pinmx_reg_base = 0x112c0000,
122 .pinmx_reg_offset = 0x74,
123 .pinmx_func_num = 0x2,
124 .restored_val = 0x0,
125 .pinmx_func_changed = 0
126 },
127 {
128 .pinmx_reg_base = 0x0120c0000,
129 .pinmx_reg_offset = 0x10,
130 .pinmx_func_num = 0x4,
131 .restored_val = 0x0,
132 .pinmx_func_changed = 0
133 },
134 {
135 .pinmx_reg_base = 0x120c0000,
136 .pinmx_reg_offset = 0x14,
137 .pinmx_func_num = 0x4,
138 .restored_val = 0x0,
139 .pinmx_func_changed = 0
140 },
141 {
142 .pinmx_reg_base = 0x120c0000,
143 .pinmx_reg_offset = 0x18,
144 .pinmx_func_num = 0x4,
145 .restored_val = 0x0,
146 .pinmx_func_changed = 0
147 },
148 {
149 .pinmx_reg_base = 0x120c0000,
150 .pinmx_reg_offset = 0x1c,
151 .pinmx_func_num = 0x4,
152 .restored_val = 0x0,
153 .pinmx_func_changed = 0
154 },
155 };
156
save_one_pin(struct pin_info * pin)157 static void save_one_pin(struct pin_info *pin)
158 {
159 unsigned int val;
160 void *pmx_reg_virt = ioremap(pin->pinmx_reg_base, 0x1000);
161 pmx_reg_virt += pin->pinmx_reg_offset;
162 val = readl(pmx_reg_virt);
163 if ((val & 0xf) == pin->pinmx_func_num) {
164 pin->restored_val = val;
165 val &= 0xfffffff0;
166 writel(val, pmx_reg_virt);
167 pin->pinmx_func_changed = 1;
168 } else {
169 pin->pinmx_func_changed = 0;
170 }
171 iounmap(pmx_reg_virt);
172 }
173
ptdev_pinmux_save(void)174 static void ptdev_pinmux_save(void)
175 {
176 unsigned pmx_nr = array_size(pmx_list);
177 struct pin_info *pmx_info = NULL;
178 int i;
179
180 for (i = 0; i < pmx_nr; i++) {
181 pmx_info = &pmx_list[i];
182 save_one_pin(pmx_info);
183 }
184 }
185
restore_one_pin(struct pin_info * pin)186 static void restore_one_pin(struct pin_info *pin)
187 {
188 void *pmx_reg_virt = ioremap(pin->pinmx_reg_base, 0x1000);
189 pmx_reg_virt += pin->pinmx_reg_offset;
190
191 if (pin->pinmx_func_changed)
192 writel(pin->restored_val, pmx_reg_virt);
193
194 iounmap(pmx_reg_virt);
195 }
196
ptdev_pinmux_restore(void)197 static void ptdev_pinmux_restore(void)
198 {
199 unsigned pmx_nr = array_size(pmx_list);
200 struct pin_info *pmx_info = NULL;
201 int i;
202
203 for (i = 0; i < pmx_nr; i++) {
204 pmx_info = &pmx_list[i];
205 restore_one_pin(pmx_info);
206 }
207 }
208
209 struct pll_trainning_dev {
210 char *name;
211 unsigned long ctrlreg_phys;
212 void *ctrlreg_base;
213 unsigned int tx_dma_reqline_val;
214 unsigned int rx_dma_reqline_val;
215 unsigned int reset_bit;
216 unsigned int clock_gate_bit;
217
218 void (*dev_clock_enable)(struct pll_trainning_dev *dev);
219 void (*dev_rx_dma_init)(struct pll_trainning_dev *dev);
220 void (*dev_dma_exit)(struct pll_trainning_dev *dev);
221 int (*rx_trans_test)(struct pll_trainning_dev *dev);
222 };
223
224 struct voltage_regulator {
225 unsigned int curr;
226 unsigned int max;
227 unsigned int min;
228 unsigned int reg_base;
229 void *reg_virt;
230 unsigned int pwm_sel;
231 void *pwm_sel_reg_virt;
232 unsigned int steps[NUM_7];
233 void (*init)(struct voltage_regulator *regulator);
234 int (*adjust)(struct voltage_regulator *regulator, int step);
235 void (*restore)(struct voltage_regulator *regulator);
236 void (*exit)(struct voltage_regulator *regulator);
237 };
238
edma_apb_axi_clock_enable(void)239 static void edma_apb_axi_clock_enable(void)
240 {
241 void *addr = crg_base + PERI_CRG101;
242 unsigned int val = readl(addr);
243
244 /* set bit1: dmac_apb_cken and bit2: dmac_cken Enable */
245 val |= ((1 << 1) | (1 << 2));
246 writel(val, addr);
247 /* set bit0: dmac_srst_req Enable */
248 val |= (1 << 0);
249 writel(val, addr);
250 /* set bit0: dmac_srst_req disable */
251 val &= ~(1 << 0);
252 writel(val, addr);
253 }
254
pt_dev_clock_enable(struct pll_trainning_dev * dev)255 static void pt_dev_clock_enable(struct pll_trainning_dev *dev)
256 {
257 void *addr = crg_base + PERI_CRG110;
258 unsigned int val = readl(addr);
259
260 val |= (1 << dev->clock_gate_bit);
261 writel(val, addr);
262
263 val |= (1 << dev->reset_bit);
264 writel(val, addr);
265
266 val &= ~(1 << dev->reset_bit);
267 writel(val, addr);
268 }
269
uart_rx_dma_init(struct pll_trainning_dev * dev)270 static void uart_rx_dma_init(struct pll_trainning_dev *dev)
271 {
272 edma_apb_axi_clock_enable();
273 if (dev->dev_clock_enable)
274 dev->dev_clock_enable(dev);
275
276 /* dma cfg */
277 writel(0x0, edma0_reg_base + 0x688);
278 writel(0xff, edma0_reg_base + 0x600);
279 writel(0xff, edma0_reg_base + 0x608);
280 writel(0xff, edma0_reg_base + 0x610);
281 writel(0xff, edma0_reg_base + 0x618);
282 writel(0xff, edma0_reg_base + 0x620);
283 writel(0x0, edma0_reg_base + 0x18);
284 writel(0x0, edma0_reg_base + 0x1c);
285 writel(0x0, edma0_reg_base + 0x20);
286 writel(0x0, edma0_reg_base + 0x24);
287 writel(0x0, edma0_reg_base + 0x28);
288 writel(0x0, edma0_reg_base + 0x830);
289 writel(dev->ctrlreg_phys, edma0_reg_base + 0x820); /* dma src address */
290 writel(0, edma0_reg_base + 0x824);
291 writel(dma_phys + 0x800, edma0_reg_base + 0x828); /* dma dest address */
292 writel(0, edma0_reg_base + 0x82c);
293 writel(0x400, edma0_reg_base + 0x81c); /* len */
294
295 writel(0x0, edma0_reg_base + 0x870);
296 writel(dma_phys, edma0_reg_base + 0x860); /* dma src address */
297 writel(0, edma0_reg_base + 0x864);
298 writel(dev->ctrlreg_phys, edma0_reg_base + 0x868); /* dma dest address */
299 writel(0, edma0_reg_base + 0x86c);
300 writel(0x400, edma0_reg_base + 0x85c); /* len */
301
302 /* uart cfg */
303 writel(0x7ff, dev->ctrlreg_base + 0x44);
304 writel(0x1, dev->ctrlreg_base + 0x24);
305 writel(0x0, dev->ctrlreg_base + 0x28);
306 writel(0x70, dev->ctrlreg_base + 0x2c);
307 writel(0x0, dev->ctrlreg_base + 0x34);
308 writel(0x40, dev->ctrlreg_base + 0x38);
309 writel(0x3, dev->ctrlreg_base + 0x48);
310 udelay(1);
311 writel(0x381, dev->ctrlreg_base + 0x30);
312 udelay(1);
313 }
314
uart_dma_exit(struct pll_trainning_dev * dev)315 static void uart_dma_exit(struct pll_trainning_dev *dev)
316 {
317 edma_apb_axi_clock_enable();
318 if (dev->dev_clock_enable)
319 dev->dev_clock_enable(dev);
320 }
321
322
323 /*
324 * return: on -1, dma timeout;
325 * on -2, data err;
326 */
do_uart_dma_rx_tst(struct pll_trainning_dev * dev)327 static int do_uart_dma_rx_tst(struct pll_trainning_dev *dev)
328 {
329 int j;
330 unsigned int val;
331 int ret = -1;
332
333 writel(DMA_RXCHNL_CONFIG + (dev->rx_dma_reqline_val << NUM_4),
334 edma0_reg_base + DMA_REG_CHNL0);
335 writel(DMA_TXCHNL_CONFIG + (dev->tx_dma_reqline_val << NUM_4),
336 edma0_reg_base + DMA_REG_CHNL1);
337
338 for (j = 0; j < 0x1000; j++) {
339 val = readl(edma0_reg_base + INT_TC1_RAW);
340 if ((val & DMA_CHNL0_DONE) && (val & DMA_CHNL1_DONE)) {
341 ret = 0;
342 writel(0x3, edma0_reg_base + INT_TC1_RAW);
343 break;
344 }
345 udelay(1); /* delay 1 us */
346 }
347
348 if (ret)
349 pll_trainning_debug("DMA time out!\r\n");
350
351 return ret;
352 }
353
uart_rx_trans_test(struct pll_trainning_dev * dev)354 static int uart_rx_trans_test(struct pll_trainning_dev *dev)
355 {
356 int ret;
357
358 if (dev->dev_rx_dma_init)
359 dev->dev_rx_dma_init(dev);
360
361 ret = do_uart_dma_rx_tst(dev);
362
363 dev->dev_dma_exit(dev);
364 return ret;
365 }
366
start_training(struct pll_trainning_dev * devs,unsigned int dev_nr)367 static int start_training(struct pll_trainning_dev *devs, unsigned int dev_nr)
368 {
369 int i, ret;
370 int pass = 1;
371
372 for (i = 0; i < dev_nr; i++) {
373 struct pll_trainning_dev *pt_dev = &devs[i];
374 if (pt_dev->rx_trans_test) {
375 ret = pt_dev->rx_trans_test(pt_dev);
376 if (ret) {
377 pass = 0;
378 pll_trainning_debug(pt_dev->name);
379 pll_trainning_debug(":rx trainning failed!\r\n");
380 return pass;
381 }
382 }
383 }
384
385 return pass;
386 }
387
388 struct pll_trainning_dev train_devs[] = {
389 {
390 .name = "uart1",
391 .ctrlreg_phys = UART1_REG_PHYS,
392 .tx_dma_reqline_val = 0x13,
393 .rx_dma_reqline_val = 0x12,
394 .clock_gate_bit = 1, /* bit1: clock gate bit */
395 .reset_bit = 6, /* bit6 :Soft reset */
396 .dev_clock_enable = pt_dev_clock_enable,
397 .dev_rx_dma_init = uart_rx_dma_init,
398 .dev_dma_exit = uart_dma_exit,
399 .rx_trans_test = uart_rx_trans_test
400 },
401
402 {
403 .name = "uart2",
404 .ctrlreg_phys = UART2_REG_PHYS,
405 .tx_dma_reqline_val = 0x15,
406 .rx_dma_reqline_val = 0x14,
407 .clock_gate_bit = 2, /* bit2: clock gate bit */
408 .reset_bit = 7, /* bit7 :Soft reset */
409 .dev_clock_enable = pt_dev_clock_enable,
410 .dev_rx_dma_init = uart_rx_dma_init,
411 .dev_dma_exit = uart_dma_exit,
412 .rx_trans_test = uart_rx_trans_test
413 },
414 };
415
svb_voltage_regulator_init(struct voltage_regulator * regulator)416 static void svb_voltage_regulator_init(struct voltage_regulator *regulator)
417 {
418 unsigned int i, val;
419 unsigned int step_25 = 10;
420 unsigned int step_50 = 20;
421 unsigned int step_80 = 30;
422 unsigned int step_100 = 50;
423
424 regulator->pwm_sel_reg_virt = ioremap(SVB_PWM_SEL, 0x1000);
425 val = readl(regulator->pwm_sel_reg_virt);
426 regulator->pwm_sel = (val) & 0xf;
427
428 regulator->reg_virt = ioremap(regulator->reg_base, 0x1000);
429 val = readl(regulator->reg_virt + SVB_SYS_VOLTAGE_OFFSET + 0x20 *
430 regulator->pwm_sel);
431 regulator->curr = (val) & 0xff;
432
433 if (regulator->curr + step_50 < regulator->max)
434 regulator->steps[NUM_0] = regulator->curr + step_50;
435 else
436 regulator->steps[NUM_0] = regulator->max;
437
438 if (regulator->curr + step_25 < regulator->max)
439 regulator->steps[NUM_1] = regulator->curr + step_25;
440 else
441 regulator->steps[NUM_1] = regulator->max;
442
443 regulator->steps[NUM_2] = regulator->curr;
444
445 if (regulator->curr > regulator->min + step_25)
446 regulator->steps[NUM_3] = regulator->curr - step_25;
447 else
448 regulator->steps[NUM_3] = regulator->min;
449
450 if (regulator->curr > regulator->min + step_50)
451 regulator->steps[NUM_4] = regulator->curr - step_50;
452 else
453 regulator->steps[NUM_4] = regulator->min;
454
455 if (regulator->curr > regulator->min + step_80)
456 regulator->steps[NUM_5] = regulator->curr - step_80;
457 else
458 regulator->steps[NUM_5] = regulator->min;
459
460 if (regulator->curr > regulator->min + step_100)
461 regulator->steps[NUM_6] = regulator->curr - step_100;
462 else
463 regulator->steps[NUM_6] = regulator->min;
464
465 if (regulator->steps[NUM_5] <= regulator->steps[NUM_6])
466 regulator->steps[NUM_6] = 0xffffffff;
467
468 if (regulator->steps[NUM_4] <= regulator->steps[NUM_5])
469 regulator->steps[NUM_5] = 0xffffffff;
470
471 if (regulator->steps[NUM_3] <= regulator->steps[NUM_4])
472 regulator->steps[NUM_4] = 0xffffffff;
473
474 if (regulator->steps[NUM_2] <= regulator->steps[NUM_3])
475 regulator->steps[NUM_3] = 0xffffffff;
476
477 if (regulator->steps[NUM_0] <= regulator->steps[NUM_1])
478 regulator->steps[NUM_0] = 0xffffffff;
479
480 if (regulator->steps[NUM_1] <= regulator->steps[NUM_2])
481 regulator->steps[NUM_1] = 0xffffffff;
482
483 regulator->max = ((regulator->curr + step_50) < regulator->max) ?
484 (regulator->curr + step_50) : regulator->max;
485 regulator->min = ((regulator->curr - step_100) > regulator->min) ?
486 (regulator->curr - step_100) : regulator->min;
487
488 pll_trainning_debug("svb voltage min/max[0x");
489 pll_trainning_debug_hex(regulator->min);
490 pll_trainning_debug("/0x");
491 pll_trainning_debug_hex(regulator->max);
492 pll_trainning_debug("] steps: \r\n");
493 for (i = 0; i < NUM_7; i++) {
494 pll_trainning_debug_hex(regulator->steps[i]);
495 pll_trainning_debug("\r\n");
496 }
497 }
498
svb_voltage_adjust(struct voltage_regulator * regulator,int step)499 static int svb_voltage_adjust(struct voltage_regulator *regulator, int step)
500 {
501 unsigned int val;
502
503 if (regulator->steps[step] == 0xffffffff)
504 return -1;
505
506 val = readl(regulator->reg_virt + SVB_SYS_VOLTAGE_OFFSET + 0x20 *
507 regulator->pwm_sel);
508 val &= 0xffffff00;
509 val |= regulator->steps[step];
510 writel(val, regulator->reg_virt + SVB_SYS_VOLTAGE_OFFSET + 0x20 *
511 regulator->pwm_sel);
512 writel(NUM_5, regulator->reg_virt + SVB_SYS_VOLTAGE_UPDATE_OFFSET + 0x20 *
513 regulator->pwm_sel);
514 return 0;
515 }
516
svb_voltage_restore(struct voltage_regulator * regulator)517 static void svb_voltage_restore(struct voltage_regulator *regulator)
518 {
519 unsigned int val = readl(regulator->reg_virt + SVB_SYS_VOLTAGE_OFFSET + 0x20 *
520 regulator->pwm_sel);
521 val &= 0xffffff00;
522 val |= regulator->curr;
523 writel(val, regulator->reg_virt + SVB_SYS_VOLTAGE_OFFSET + 0x20 *
524 regulator->pwm_sel);
525 writel(NUM_5, regulator->reg_virt + SVB_SYS_VOLTAGE_UPDATE_OFFSET + 0x20 *
526 regulator->pwm_sel);
527 }
528
svb_voltage_regulator_exit(struct voltage_regulator * regulator)529 static void svb_voltage_regulator_exit(struct voltage_regulator *regulator)
530 {
531 iounmap(regulator->reg_virt);
532 iounmap(regulator->pwm_sel_reg_virt);
533 }
534
535
536 struct voltage_regulator volt_regulator = {
537 .min = 0,
538 .max = 0xc7,
539 .reg_base = SVB_CTRL_BASE,
540 .steps = {0},
541 .init = svb_voltage_regulator_init,
542 .adjust = svb_voltage_adjust,
543 .restore = svb_voltage_restore,
544 .exit = svb_voltage_regulator_exit
545 };
546
pll_trainning_init(void)547 int pll_trainning_init(void)
548 {
549 int ret = -1;
550 int i;
551 int j;
552 unsigned int dev_nr;
553 int trainning_pass = 1;
554 static int pll_rst_cnt = 0xffffffff;
555
556 dev_nr = array_size(train_devs);
557 crg_base = ioremap(THE_CRG_BASE, 0x1000);
558 if (!crg_base)
559 return ret;
560 misc_base = ioremap(MISC_REG_BASE, 0x1000);
561 if (!misc_base) {
562 iounmap(crg_base);
563 return ret;
564 }
565 edma0_reg_base = ioremap(HIEDMA0_REG_BASE, 0x1000);
566 if (!edma0_reg_base) {
567 iounmap(misc_base);
568 iounmap(crg_base);
569 return ret;
570 }
571
572 ptdev_pinmux_save();
573 dma_phys = DDR_DATA_BASE;
574
575 for (i = 0; i < dev_nr; i++) {
576 struct pll_trainning_dev *pt_dev = &train_devs[i];
577 pt_dev->ctrlreg_base = ioremap(pt_dev->ctrlreg_phys, 0x1000);
578 }
579
580 if (volt_regulator.init)
581 volt_regulator.init(&volt_regulator);
582
583 pll_trainning_debug("### UART pll reset count 0x");
584 pll_trainning_debug_hex(pll_rst_cnt);
585 pll_trainning_debug("\r\n");
586
587 for (j = 0; (j < LOOP_COUNT) && (trainning_pass == 1); j++) {
588 for (i = 0; (i < array_size(volt_regulator.steps)) &&
589 (trainning_pass == 1); i++) {
590 pll_trainning_debug("svb_just step=");
591 pll_trainning_debug_hex(i);
592 pll_trainning_debug("\r\n");
593
594 if (volt_regulator.adjust(&volt_regulator, i)) {
595 /*
596 * invalid voltage range, no need to do the trainning.
597 */
598 continue;
599 }
600
601 trainning_pass = start_training(train_devs, dev_nr);
602 }
603 }
604
605 if (trainning_pass != 1) {
606 pll_trainning_debug("### PLL trainning failed!!\r\n");
607 pll_trainning_debug("### LOOP_COUNT: 0x");
608 pll_trainning_debug_hex(j);
609 pll_trainning_debug("\r\n");
610
611 pll_rst_cnt--;
612 ret = -1;
613 } else {
614 uart_early_puts("\r\n EDMA PLL TRAINNING ALL PASS!\r\n");
615 ret = 0;
616 }
617
618 volt_regulator.restore(&volt_regulator);
619 volt_regulator.exit(&volt_regulator);
620
621 ptdev_pinmux_restore();
622
623 iounmap(edma0_reg_base);
624 iounmap(misc_base);
625 iounmap(crg_base);
626
627 return ret;
628 }
629
630 #endif
631
632