1 /*
2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 *
17 */
18
19 #include <asm/arch/platform.h>
20 #include <config.h>
21 #include <compiler.h>
22 #include "ddr_training_impl.h"
23
24 #define HI_SYS_CTL_REG SYS_CTRL_REG_BASE
25
26 #define OK 0
27 #define ERROR -1
28 #define DDR_CA0_OFST 0x24
29 #define DDR_CA1_OFST 0x28
30 #define DDR_CA2_OFST 0x2c
31 #define REG_BASE_DDRC 0x11130000
32
33 #define DDRC_CTRL_SREF_OFST 0x8000 + 0x0
34 #define DDRC_CFG_DDRMODE_OFST 0x8000 + 0X50
35 #define DDRC_CURR_FUNC_OFST 0x8000 + 0x294
36
37 #define DDRC1_CTRL_SREF_OFST 0x9000 + 0x0
38 #define DDRC1_CFG_DDRMODE_OFST 0x9000 + 0X50
39 #define DDRC1_CURR_FUNC_OFST 0x9000 + 0x294
40
41 #define DDRC2_CTRL_SREF_OFST 0xa000 + 0x0
42 #define DDRC2_CFG_DDRMODE_OFST 0xa000 + 0X50
43 #define DDRC2_CURR_FUNC_OFST 0xa000 + 0x294
44
45 #define DDRC3_CTRL_SREF_OFST 0xb000 + 0x0
46 #define DDRC3_CFG_DDRMODE_OFST 0xb000 + 0X50
47 #define DDRC3_CURR_FUNC_OFST 0xb000 + 0x294
48
49 #define DDRC_SELF_REFURBISH_MASK (0x1)
50
delay(unsigned int num)51 static inline void delay(unsigned int num)
52 {
53 volatile unsigned int i;
54
55 for (i = 0; i < (100 * num); i++) {
56 __asm__ __volatile__("nop");
57 }
58 }
59
60 extern void reset_cpu(unsigned long addr);
61
DWB(void)62 static inline void DWB(void) /* drain write buffer */
63 {
64 }
65
readl(unsigned addr)66 static inline unsigned int readl(unsigned addr)
67 {
68 unsigned int val;
69
70 val = (*(volatile unsigned int *)(uintptr_t)(addr));
71 return val;
72 }
73
writel(unsigned val,unsigned addr)74 static inline void writel(unsigned val, unsigned addr)
75 {
76 DWB();
77 (*(volatile unsigned *)(uintptr_t)(addr)) = (uintptr_t)(val);
78 DWB();
79 }
80
81 #define REG_BASE_MISC 0x11024000
82
83 #ifdef DDR_SCRAMB_ENABLE
84
85 #undef reg_get
86 #define reg_get(addr) (*(volatile unsigned int *)((long)addr))
87
88 #undef reg_set
89 #define reg_set(addr, val) (*(volatile unsigned int *)((long)addr) = (val))
ddr_scramb_start(unsigned int random1,unsigned int random2)90 void ddr_scramb_start(unsigned int random1, unsigned int random2)
91 {
92
93 reg_set((unsigned int *)(REG_BASE_MISC + DDR_CA0_OFST), random1);
94 reg_set((unsigned int *)(REG_BASE_MISC + DDR_CA1_OFST), random2);
95 reg_set((unsigned int *)(REG_BASE_MISC + DDR_CA2_OFST), 0);
96 reg_set((unsigned int *)(REG_BASE_MISC + DDR_CA2_OFST), 0x10);
97 delay(0x100);
98 reg_set((unsigned int *)(REG_BASE_MISC + DDR_CA0_OFST), 0);
99 reg_set((unsigned int *)(REG_BASE_MISC + DDR_CA1_OFST), 0);
100 }
101
102 #define REG_BASE_RNG_GEN 0x10130000
103 #define TRNG_DSTA_FIFO_DATA_OFST 0x204
104 #define TRNG_DATA_ST_OFST 0x208
105 #define HISEC_COM_TRNG_CTRL_OFST 0x200
106
107 #define BIT_TRNG_FIFO_DATA_CNT 0x8
108 #define TRNG_FIFO_DATA_CNT_MASK 0xff
109 #define TRNG_CTRL_DEF_VAL 0xa
110
111 #define REG_PERI_CRG_TRNG 0x2d80
112 #define TRNG_CLK_ENABLE (0x1 << 4)
113 #define TRNG_DO_SRST (0x1 << 0)
114 #define TRNG_CLK_DISABLE ~(0x1 << 4)
115 #define TRNG_UNDO_SRST ~(0x1 << 0)
116
117
118 /* get random number */
get_random_num(void)119 int get_random_num(void)
120 {
121 unsigned int reg_val = 0;
122
123 do {
124 reg_val = reg_get(REG_BASE_RNG_GEN + TRNG_DATA_ST_OFST);
125
126 } while (!((reg_val >> BIT_TRNG_FIFO_DATA_CNT)
127 & TRNG_FIFO_DATA_CNT_MASK));
128
129 reg_val = reg_get(REG_BASE_RNG_GEN + TRNG_DSTA_FIFO_DATA_OFST);
130
131 return reg_val;
132 }
133
trng_init(void)134 void trng_init(void)
135 {
136 unsigned int reg_val = 0;
137
138 /* open trng clock */
139 reg_val = reg_get(CRG_REG_BASE + REG_PERI_CRG_TRNG);
140 reg_val |= TRNG_CLK_ENABLE;
141 reg_val &= TRNG_UNDO_SRST;
142 reg_set(CRG_REG_BASE + REG_PERI_CRG_TRNG, reg_val);
143
144 /* set trng ctrl register */
145 reg_set(REG_BASE_RNG_GEN + HISEC_COM_TRNG_CTRL_OFST,
146 TRNG_CTRL_DEF_VAL);
147 }
148
trng_deinit(void)149 void trng_deinit(void)
150 {
151 unsigned int reg_val = 0;
152
153 /* close trng clock */
154 reg_val = reg_get(CRG_REG_BASE + REG_PERI_CRG_TRNG);
155 reg_val &= TRNG_CLK_DISABLE;
156 reg_set(CRG_REG_BASE + REG_PERI_CRG_TRNG, reg_val);
157 }
158
ddr_scramb(void)159 int ddr_scramb(void)
160 {
161 unsigned int random_num1 = 0;
162 unsigned int random_num2 = 0;
163 unsigned int reg_val[4] = {0, 0, 0, 0};
164 unsigned int ddrc_isvalid[4] = {0, 0, 0, 0};
165
166 /* read ddrc_cfg_ddrmode register,
167 * if value[3:0] is not 0x0 ,the channel is valid.
168 */
169 ddrc_isvalid[0] = (reg_get(REG_BASE_DDRC + DDRC_CFG_DDRMODE_OFST) & 0xf)?1:0;
170 ddrc_isvalid[1] = (reg_get(REG_BASE_DDRC + DDRC1_CFG_DDRMODE_OFST) & 0xf)?1:0;
171 ddrc_isvalid[2] = (reg_get(REG_BASE_DDRC + DDRC2_CFG_DDRMODE_OFST) & 0xf)?1:0;
172 ddrc_isvalid[3] = (reg_get(REG_BASE_DDRC + DDRC3_CFG_DDRMODE_OFST) & 0xf)?1:0;
173
174 /* set ddrc to do self-refurbish */
175 if (ddrc_isvalid[0])
176 reg_set(REG_BASE_DDRC + DDRC_CTRL_SREF_OFST, 0x1);
177 if (ddrc_isvalid[1])
178 reg_set(REG_BASE_DDRC + DDRC1_CTRL_SREF_OFST, 0x1);
179 if (ddrc_isvalid[2])
180 reg_set(REG_BASE_DDRC + DDRC2_CTRL_SREF_OFST, 0x1);
181 if (ddrc_isvalid[3])
182 reg_set(REG_BASE_DDRC + DDRC3_CTRL_SREF_OFST, 0x1);
183
184 /* wait the status of ddrc to be sef-refurbish */
185 do {
186 reg_val[0] = ddrc_isvalid[0]?(reg_get(REG_BASE_DDRC + DDRC_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK):1;
187 reg_val[1] = ddrc_isvalid[1]?(reg_get(REG_BASE_DDRC + DDRC1_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK):1;
188 reg_val[2] = ddrc_isvalid[2]?(reg_get(REG_BASE_DDRC + DDRC2_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK):1;
189 reg_val[3] = ddrc_isvalid[3]?(reg_get(REG_BASE_DDRC + DDRC3_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK):1;
190
191 } while (!(reg_val[0] & reg_val[1] & reg_val[2] & reg_val[3]));
192
193 trng_init();
194
195 /* get random number */
196 random_num1 = get_random_num();
197 random_num2 = get_random_num();
198
199 /* start ddr scrambling */
200 ddr_scramb_start(random_num1, random_num2);
201
202 /* clear random number */
203 random_num1 = get_random_num();
204 random_num2 = get_random_num();
205 random_num1 = get_random_num();
206 random_num2 = get_random_num();
207
208 /* set ddrc to exit self-refurbish */
209 if (ddrc_isvalid[0])
210 reg_set(REG_BASE_DDRC + DDRC_CTRL_SREF_OFST, (0x1<<1));
211 if (ddrc_isvalid[1])
212 reg_set(REG_BASE_DDRC + DDRC1_CTRL_SREF_OFST, (0x1<<1));
213 if (ddrc_isvalid[2])
214 reg_set(REG_BASE_DDRC + DDRC2_CTRL_SREF_OFST, (0x1<<1));
215 if (ddrc_isvalid[3])
216 reg_set(REG_BASE_DDRC + DDRC3_CTRL_SREF_OFST, (0x1<<1));
217
218 /* wait the status of ddrc to be normal */
219 do {
220 reg_val[0] = ddrc_isvalid[0]?(reg_get(REG_BASE_DDRC + DDRC_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK):0;
221 reg_val[1] = ddrc_isvalid[1]?(reg_get(REG_BASE_DDRC + DDRC1_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK):0;
222 reg_val[2] = ddrc_isvalid[2]?(reg_get(REG_BASE_DDRC + DDRC2_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK):0;
223 reg_val[3] = ddrc_isvalid[3]?(reg_get(REG_BASE_DDRC + DDRC3_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK):0;
224
225 } while (reg_val[0] | reg_val[1] | reg_val[2] | reg_val[3]);
226
227 return OK;
228 }
229
230
231 #endif /* DDR_SCRAMB_ENABLE */
232
233 #define CORE_SVB_PWM_CTRL 0x11029000
234
235 #define HPM_CLK_REG 0x11014A80
236 #define CORE_HPM_CTRL0_REG 0x1102B010
237 #define HPM_CORE_REG0 0x1102B018
238 #define HPM_CORE_REG1 0x1102B01c
239 #define CYCLE_NUM 32
240 #define HPM_RECORD_REG0 0x11020340
241 #define HPM_RECORD_REG1 0x11020344
242 #define VOLTAGE_RECOED_REG 0x1102015C
243
244 #define SVB_VERSION_REG 0x11020168
245 #define SVB_VERSION_21DV200 0x0003
246 #define OTP_HPM_CORE_REG 0x11021504
247 #define OTP_VOLTAGE_DELTA_CORE_REG 0x1102150C
248 #define OTP_VOLTAGE_DELTA_CORE_FOR_TRAINING_REG 0x11021518
249
250 #define TSENSOR_STATUS0 0X1102A008
251
252 #define USE_ATE_HPM 0
253
hpm_value_avg(const unsigned int val[],unsigned int size)254 static unsigned hpm_value_avg(const unsigned int val[], unsigned int size)
255 {
256 unsigned int i;
257 unsigned tmp = 0;
258
259 for (i = 0; i < size; i++)
260 tmp += val[i] >> 2; //2
261
262 return tmp >> 5;//5
263 }
264
get_hpm_value(unsigned int * hpm_core)265 static void get_hpm_value(unsigned int *hpm_core)
266 {
267 int i;
268 unsigned int temp;
269 unsigned int core_value[4] = {0, 0, 0, 0};//4
270
271 for (i = 0; i < CYCLE_NUM; i++) {
272 delay(18);//18
273
274 /* core */
275 temp = readl(HPM_CORE_REG0);
276 core_value[1] += (temp >> 16) & 0x3ff;//16
277 core_value[0] += temp & 0x3ff;
278 temp = readl(HPM_CORE_REG1);
279 core_value[3] += (temp >> 16) & 0x3ff;//3 16
280 core_value[2] += temp & 0x3ff;//2
281 }
282
283 *hpm_core = hpm_value_avg(core_value, 4);
284 }
285
286
start_hpm(unsigned int * hpm_core)287 static void start_hpm(unsigned int *hpm_core)
288 {
289 /* core */
290 writel(0x60080001, CORE_HPM_CTRL0_REG);
291
292 delay(180); /*180 10ms*/
293
294 get_hpm_value(hpm_core);
295 }
296
297 union union_hpm_reg0 {
298 struct {
299 unsigned int sys_hpm_core : 9; /* [8..0]*/
300 unsigned int reserved_0 : 7; /* [15..9]*/
301 unsigned int sys_hpm_cpu : 9; /* [24..16]*/
302 unsigned int reserved_1 : 7; /* [31..25]*/
303 } bits;
304 unsigned int u32;
305 };
306
307 union union_hpm_reg1 {
308 struct {
309 unsigned int temperature : 8; /* [7..0]*/
310 unsigned int reserved_0 : 20; /* [27..8]*/
311 unsigned int temperature_err : 1; /* [28]*/
312 unsigned int hpm_cpu_err : 1; /* [29]*/
313 unsigned int hpm_core_err : 1; /* [30]*/
314 unsigned int from_otp : 1; /* [31]*/
315 }bits;
316 unsigned int u32;
317 };
318
hpm_check(unsigned int * hpm_core,int * temperature,unsigned int hpm_from_otp_flag)319 static void hpm_check(unsigned int *hpm_core, int *temperature, unsigned int hpm_from_otp_flag)
320 {
321 union union_hpm_reg0 hpm_reg0; /*SVB_RECORD_REG0 0x11020340*/
322 union union_hpm_reg1 hpm_reg1; /*SVB_RECORD_REG1 0x11020344*/
323
324 hpm_reg0.u32 = 0;
325 hpm_reg1.u32 = 0;
326
327 if (*hpm_core < 220) { //220
328 *hpm_core = 220;
329 hpm_reg1.bits.hpm_core_err = 1;
330 }
331
332 if (*hpm_core > 350) { //350
333 *hpm_core = 350;
334 hpm_reg1.bits.hpm_core_err = 1;
335 }
336
337 if (*temperature < -40) { //-40
338 *temperature = -40;
339 hpm_reg1.bits.temperature_err = 1;
340 }
341
342 if (*temperature > 120) { //120
343 *temperature = 120;
344 hpm_reg1.bits.temperature_err = 1;
345 }
346
347 hpm_reg0.bits.sys_hpm_core = *hpm_core;
348 hpm_reg1.bits.temperature = (unsigned int)*temperature;
349 hpm_reg1.bits.from_otp = hpm_from_otp_flag;
350 writel(hpm_reg0.u32, HPM_RECORD_REG0);
351 writel(hpm_reg1.u32, HPM_RECORD_REG1);
352 }
353
hpm_adjust(unsigned int * hpm_core,const int * temperature,unsigned int hpm_from_otp_flag)354 static void hpm_adjust(unsigned int *hpm_core, const int *temperature, unsigned int hpm_from_otp_flag)
355 {
356 unsigned int hpm_core_tmp;
357 unsigned int hpm_core_bese_line;
358
359 if (hpm_from_otp_flag == 1)
360 return;
361
362 if (*temperature < 90)//90
363 return;
364
365 hpm_core_tmp = *hpm_core;
366 hpm_core_bese_line = 326 - ((((unsigned int) *temperature) * 102 + 256) >> 9);//326 102 256 9
367 if (hpm_core_tmp > hpm_core_bese_line)
368 *hpm_core = hpm_core_tmp + 10;//10
369 }
370
voltage_adjust(unsigned int * core_volt)371 static void voltage_adjust(unsigned int *core_volt)
372 {
373 unsigned int core_volt_tmp;
374 short otp_voltage_delta_core;
375
376 union {
377 struct {
378 unsigned int voltage_core : 12; /* [11..0]*/
379 unsigned int voltage_cpu : 12; /* [23..12]*/
380 unsigned int reserved: 8; /* [31..24]*/
381 } bits;
382 unsigned int u32;
383 } voltage_reg;
384
385 core_volt_tmp = *core_volt;
386 otp_voltage_delta_core = (short)(readl(OTP_VOLTAGE_DELTA_CORE_REG) & 0xffff);
387 *core_volt = (unsigned int)((int)core_volt_tmp + otp_voltage_delta_core);
388
389 voltage_reg.u32 = 0;
390 voltage_reg.bits.voltage_core = *core_volt;
391
392 writel(voltage_reg.u32, VOLTAGE_RECOED_REG);
393 }
394
set_core_volt(unsigned int mv)395 static void set_core_volt(unsigned int mv)
396 {
397 unsigned int svb_value;
398
399 svb_value = (((((1078595 - mv * 1000) * 1337) >> 4)-0x10000) & 0xffff0000) + 0x19f5;//1078595 1000 1337 4 0x19f5
400
401 writel(svb_value, CORE_SVB_PWM_CTRL);
402 }
403
404
convert_hpm_to_volt_core(unsigned int hpm_core,unsigned int * mv)405 static void convert_hpm_to_volt_core(unsigned int hpm_core, unsigned int *mv)
406 {
407 unsigned int volt;
408
409 volt = 1490 - (hpm_core * 2);//1490 2
410
411 if (volt > 990)//990
412 *mv = 990;
413 else if (volt < 850)//850
414 *mv = 850;
415 else
416 *mv = volt;
417 }
418
get_temperature(int * temperature)419 static void get_temperature(int *temperature)
420 {
421 unsigned int value;
422
423 value = (unsigned int)(readl(TSENSOR_STATUS0) & 0x3ff);
424 *temperature = (int)((((int)value - 127) * 431) >> 11) - 40;//127 431 11 40
425 }
426
get_ate_hpm(unsigned int * pate_hpm_core)427 static void get_ate_hpm(unsigned int *pate_hpm_core)
428 {
429 *pate_hpm_core = (unsigned int)(readl(OTP_HPM_CORE_REG) & 0xffff);
430 }
431
get_volt_delta_for_training(short * otp_volt_delta_core_for_training)432 static void get_volt_delta_for_training(short *otp_volt_delta_core_for_training)
433 {
434 short volt_delta_tmp;
435
436 volt_delta_tmp = (short)(readl(OTP_VOLTAGE_DELTA_CORE_FOR_TRAINING_REG) & 0xffff);
437 if (volt_delta_tmp >= 40)//40
438 *otp_volt_delta_core_for_training = 40;
439 else if (volt_delta_tmp <= -40)//-40
440 *otp_volt_delta_core_for_training = -40;
441 else
442 *otp_volt_delta_core_for_training = volt_delta_tmp;
443 }
444
start_svb(void)445 static void start_svb(void)
446 {
447 unsigned int ate_hpm_core;
448 unsigned int hpm_core;
449 unsigned int core_volt;
450 unsigned int core_volt_for_training;
451 short otp_volt_delta_core_for_training;
452 int temperature;
453 unsigned int hpm_from_otp;
454 unsigned int version;
455
456 version = readl(SVB_VERSION_REG);
457 version = (version & 0x0000FFFF) | (SVB_VERSION_21DV200 << 16);//16
458 writel(version, SVB_VERSION_REG);
459
460 /* open hmp clock */
461 writel(0x10, HPM_CLK_REG);//0x10
462 delay(18);//18
463 get_temperature(&temperature);
464
465 if (!USE_ATE_HPM) {
466 set_core_volt(990);//990
467 start_hpm(&hpm_core);
468 hpm_from_otp = 0;
469 } else {
470 get_ate_hpm(&ate_hpm_core);
471 /*ATE SVB transfer to board SVB*/
472 hpm_core = ate_hpm_core;
473 hpm_from_otp = 1;
474 }
475
476 hpm_adjust(&hpm_core, &temperature, hpm_from_otp);
477
478 hpm_check(&hpm_core, &temperature, hpm_from_otp);
479
480 convert_hpm_to_volt_core(hpm_core, &core_volt);
481
482 voltage_adjust(&core_volt);
483
484 get_volt_delta_for_training(&otp_volt_delta_core_for_training);
485 core_volt_for_training = (unsigned int)((int)core_volt + otp_volt_delta_core_for_training - 20);//20
486
487 set_core_volt(core_volt_for_training);
488
489 /* delay 10ms do not delete */
490 delay(180);//180 10ms
491 }
492
end_svb(void)493 static void end_svb(void)
494 {
495 unsigned int core_volt;
496
497 union {
498 struct {
499 unsigned int voltage_core : 12; /* [11..0]*/
500 unsigned int voltage_cpu : 12; /* [23..12]*/
501 unsigned int reserved: 8; /* [31..24]*/
502 } bits;
503 unsigned int u32;
504 } voltage_reg;
505
506 voltage_reg.u32 = 0;
507 voltage_reg.u32 = readl(VOLTAGE_RECOED_REG);
508 core_volt = voltage_reg.bits.voltage_core;
509
510 set_core_volt(core_volt);
511
512 /* delay 10ms do not delete */
513 delay(90); //90 5ms
514 }
515
start_ddr_training(unsigned int base)516 void start_ddr_training(unsigned int base)
517 {
518 start_svb();
519
520 /* ddr hw training */
521 ddr_hw_training_if();
522
523 /* ddr sw training */
524 ddr_sw_training_if();
525
526 /* the value should config after trainning, or
527 it will cause chip compatibility problems */
528 if ((readl(DDR_REG_BASE_PHY0 + DDR_PHY_DRAMCFG)
529 & PHY_DRAMCFG_TYPE_MASK) == PHY_DRAMCFG_TYPE_LPDDR4) {
530 writel(0x401, DDR_REG_BASE_DMC0 + 0x28);
531 writel(0x401, DDR_REG_BASE_DMC1 + 0x28);
532 } else {
533 writel(0x401, DDR_REG_BASE_DMC0 + 0x28);
534 }
535 #ifdef DDR_REG_BASE_PHY1
536 if ((readl(DDR_REG_BASE_PHY1 + DDR_PHY_DRAMCFG)
537 & PHY_DRAMCFG_TYPE_MASK) == PHY_DRAMCFG_TYPE_LPDDR4) {
538 writel(0x401, DDR_REG_BASE_DMC2 + 0x28);
539 writel(0x401, DDR_REG_BASE_DMC3 + 0x28);
540 } else {
541 writel(0x401, DDR_REG_BASE_DMC1 + 0x28);
542 }
543 #endif
544 #ifdef DDR_SCRAMB_ENABLE
545 /* enable ddr scramb */
546 ddr_scramb();
547 #endif
548
549 end_svb();
550 }
551