1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core 4 * 5 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 6 * 7 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 8 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 9 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 10 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 11 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 12 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com> 13 */ 14 15#include <asm-offsets.h> 16#include <config.h> 17#include <asm/system.h> 18#include <linux/linkage.h> 19#include <asm/armv7.h> 20 21/************************************************************************* 22 * 23 * Startup Code (reset vector) 24 * 25 * Do important init only if we don't start from memory! 26 * Setup memory and board specific bits prior to relocation. 27 * Relocate armboot to ram. Setup stack. 28 * 29 *************************************************************************/ 30 31 .globl reset 32 .globl save_boot_params_ret 33 .type save_boot_params_ret,%function 34#ifdef CONFIG_ARMV7_LPAE 35 .global switch_to_hypervisor_ret 36#endif 37 38reset: 39#ifndef CONFIG_MINI_BOOT 40 /* Allow the board to save important registers */ 41 b save_boot_params 42save_boot_params_ret: 43#ifdef CONFIG_ARMV7_LPAE 44/* 45 * check for Hypervisor support 46 */ 47 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 48 and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits 49 cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT) 50 beq switch_to_hypervisor 51switch_to_hypervisor_ret: 52#endif 53 /* 54 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode, 55 * except if in HYP mode already 56 */ 57 mrs r0, cpsr 58 and r1, r0, #0x1f @ mask mode bits 59 teq r1, #0x1a @ test for HYP mode 60 bicne r0, r0, #0x1f @ clear all mode bits 61 orrne r0, r0, #0x13 @ set SVC mode 62 orr r0, r0, #0xc0 @ disable FIQ and IRQ 63 msr cpsr,r0 64 65/* 66 * Setup vector: 67 * (OMAP4 spl TEXT_BASE is not 32 byte aligned. 68 * Continue to use ROM code vector only in OMAP4 spl) 69 */ 70#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) 71 /* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */ 72 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register 73 bic r0, #CR_V @ V = 0 74 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register 75 76#ifdef CONFIG_HAS_VBAR 77 /* Set vector address in CP15 VBAR register */ 78 ldr r0, =_start 79 mcr p15, 0, r0, c12, c0, 0 @Set VBAR 80#endif 81#endif 82 83 /* the mask ROM code should have PLL and others stable */ 84#ifndef CONFIG_SKIP_LOWLEVEL_INIT 85#ifdef CONFIG_CPU_V7A 86 bl cpu_init_cp15 87#endif 88#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY 89 bl cpu_init_crit 90#endif 91#endif 92#endif /* CONFIG_MINI_BOOT */ 93 bl _main 94 95/*------------------------------------------------------------------------------*/ 96 97ENTRY(c_runtime_cpu_setup) 98/* 99 * If I-cache is enabled invalidate it 100 */ 101#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) 102 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 103 mcr p15, 0, r0, c7, c10, 4 @ DSB 104 mcr p15, 0, r0, c7, c5, 4 @ ISB 105#endif 106 107 bx lr 108 109ENDPROC(c_runtime_cpu_setup) 110 111#ifndef CONFIG_MINI_BOOT 112/************************************************************************* 113 * 114 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) 115 * __attribute__((weak)); 116 * 117 * Stack pointer is not yet initialized at this moment 118 * Don't save anything to stack even if compiled with -O0 119 * 120 *************************************************************************/ 121ENTRY(save_boot_params) 122 b save_boot_params_ret @ back to my caller 123ENDPROC(save_boot_params) 124 .weak save_boot_params 125#endif /* CONFIG_MINI_BOOT */ 126 127#ifdef CONFIG_ARMV7_LPAE 128ENTRY(switch_to_hypervisor) 129 b switch_to_hypervisor_ret 130ENDPROC(switch_to_hypervisor) 131 .weak switch_to_hypervisor 132#endif 133 134/************************************************************************* 135 * 136 * cpu_init_cp15 137 * 138 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless 139 * CONFIG_SYS_ICACHE_OFF is defined. 140 * 141 *************************************************************************/ 142ENTRY(cpu_init_cp15) 143 /* 144 * Invalidate L1 I/D 145 */ 146 mov r0, #0 @ set up for MCR 147 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs 148 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 149 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array 150 mcr p15, 0, r0, c7, c10, 4 @ DSB 151 mcr p15, 0, r0, c7, c5, 4 @ ISB 152 153 /* 154 * disable MMU stuff and caches 155 */ 156 mrc p15, 0, r0, c1, c0, 0 157 bic r0, r0, #0x00002000 @ clear bits 13 (--V-) 158 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) 159 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align 160 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB 161#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF) 162 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache 163#else 164 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache 165#endif 166 mcr p15, 0, r0, c1, c0, 0 167 168#ifdef CONFIG_ARM_ERRATA_716044 169 mrc p15, 0, r0, c1, c0, 0 @ read system control register 170 orr r0, r0, #1 << 11 @ set bit #11 171 mcr p15, 0, r0, c1, c0, 0 @ write system control register 172#endif 173 174#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072)) 175 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 176 orr r0, r0, #1 << 4 @ set bit #4 177 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 178#endif 179 180#ifdef CONFIG_ARM_ERRATA_743622 181 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 182 orr r0, r0, #1 << 6 @ set bit #6 183 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 184#endif 185 186#ifdef CONFIG_ARM_ERRATA_751472 187 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 188 orr r0, r0, #1 << 11 @ set bit #11 189 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 190#endif 191#ifdef CONFIG_ARM_ERRATA_761320 192 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 193 orr r0, r0, #1 << 21 @ set bit #21 194 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 195#endif 196 197#ifdef CONFIG_ARM_ERRATA_845369 198 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 199 orr r0, r0, #1 << 22 @ set bit #22 200 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 201#endif 202 203 mov r5, lr @ Store my Caller 204 mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR) 205 mov r3, r1, lsr #20 @ get variant field 206 and r3, r3, #0xf @ r3 has CPU variant 207 and r4, r1, #0xf @ r4 has CPU revision 208 mov r2, r3, lsl #4 @ shift variant field for combined value 209 orr r2, r4, r2 @ r2 has combined CPU variant + revision 210 211/* Early stack for ERRATA that needs into call C code */ 212#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) 213 ldr r0, =(CONFIG_SPL_STACK) 214#else 215 ldr r0, =(CONFIG_SYS_INIT_SP_ADDR) 216#endif 217 bic r0, r0, #7 /* 8-byte alignment for ABI compliance */ 218 mov sp, r0 219 220#ifdef CONFIG_ARM_ERRATA_798870 221 cmp r2, #0x30 @ Applies to lower than R3p0 222 bge skip_errata_798870 @ skip if not affected rev 223 cmp r2, #0x20 @ Applies to including and above R2p0 224 blt skip_errata_798870 @ skip if not affected rev 225 226 mrc p15, 1, r0, c15, c0, 0 @ read l2 aux ctrl reg 227 orr r0, r0, #1 << 7 @ Enable hazard-detect timeout 228 push {r1-r5} @ Save the cpu info registers 229 bl v7_arch_cp15_set_l2aux_ctrl 230 isb @ Recommended ISB after l2actlr update 231 pop {r1-r5} @ Restore the cpu info - fall through 232skip_errata_798870: 233#endif 234 235#ifdef CONFIG_ARM_ERRATA_801819 236 cmp r2, #0x24 @ Applies to lt including R2p4 237 bgt skip_errata_801819 @ skip if not affected rev 238 cmp r2, #0x20 @ Applies to including and above R2p0 239 blt skip_errata_801819 @ skip if not affected rev 240 mrc p15, 0, r0, c0, c0, 6 @ pick up REVIDR reg 241 and r0, r0, #1 << 3 @ check REVIDR[3] 242 cmp r0, #1 << 3 243 beq skip_errata_801819 @ skip erratum if REVIDR[3] is set 244 245 mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register 246 orr r0, r0, #3 << 27 @ Disables streaming. All write-allocate 247 @ lines allocate in the L1 or L2 cache. 248 orr r0, r0, #3 << 25 @ Disables streaming. All write-allocate 249 @ lines allocate in the L1 cache. 250 push {r1-r5} @ Save the cpu info registers 251 bl v7_arch_cp15_set_acr 252 pop {r1-r5} @ Restore the cpu info - fall through 253skip_errata_801819: 254#endif 255 256#ifdef CONFIG_ARM_CORTEX_A15_CVE_2017_5715 257 mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register 258 orr r0, r0, #1 << 0 @ Enable invalidates of BTB 259 push {r1-r5} @ Save the cpu info registers 260 bl v7_arch_cp15_set_acr 261 pop {r1-r5} @ Restore the cpu info - fall through 262#endif 263 264#ifdef CONFIG_ARM_ERRATA_454179 265 mrc p15, 0, r0, c1, c0, 1 @ Read ACR 266 267 cmp r2, #0x21 @ Only on < r2p1 268 orrlt r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits 269 270 push {r1-r5} @ Save the cpu info registers 271 bl v7_arch_cp15_set_acr 272 pop {r1-r5} @ Restore the cpu info - fall through 273#endif 274 275#if defined(CONFIG_ARM_ERRATA_430973) || defined (CONFIG_ARM_CORTEX_A8_CVE_2017_5715) 276 mrc p15, 0, r0, c1, c0, 1 @ Read ACR 277 278#ifdef CONFIG_ARM_CORTEX_A8_CVE_2017_5715 279 orr r0, r0, #(0x1 << 6) @ Set IBE bit always to enable OS WA 280#else 281 cmp r2, #0x21 @ Only on < r2p1 282 orrlt r0, r0, #(0x1 << 6) @ Set IBE bit 283#endif 284 push {r1-r5} @ Save the cpu info registers 285 bl v7_arch_cp15_set_acr 286 pop {r1-r5} @ Restore the cpu info - fall through 287#endif 288 289#ifdef CONFIG_ARM_ERRATA_621766 290 mrc p15, 0, r0, c1, c0, 1 @ Read ACR 291 292 cmp r2, #0x21 @ Only on < r2p1 293 orrlt r0, r0, #(0x1 << 5) @ Set L1NEON bit 294 295 push {r1-r5} @ Save the cpu info registers 296 bl v7_arch_cp15_set_acr 297 pop {r1-r5} @ Restore the cpu info - fall through 298#endif 299 300#ifdef CONFIG_ARM_ERRATA_725233 301 mrc p15, 1, r0, c9, c0, 2 @ Read L2ACR 302 303 cmp r2, #0x21 @ Only on < r2p1 (Cortex A8) 304 orrlt r0, r0, #(0x1 << 27) @ L2 PLD data forwarding disable 305 306 push {r1-r5} @ Save the cpu info registers 307 bl v7_arch_cp15_set_l2aux_ctrl 308 pop {r1-r5} @ Restore the cpu info - fall through 309#endif 310 311#ifdef CONFIG_ARM_ERRATA_852421 312 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 313 orr r0, r0, #1 << 24 @ set bit #24 314 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 315#endif 316 317#ifdef CONFIG_ARM_ERRATA_852423 318 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 319 orr r0, r0, #1 << 12 @ set bit #12 320 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 321#endif 322 323 mov pc, r5 @ back to my caller 324ENDPROC(cpu_init_cp15) 325 326#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ 327 !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) 328/************************************************************************* 329 * 330 * CPU_init_critical registers 331 * 332 * setup important registers 333 * setup memory timing 334 * 335 *************************************************************************/ 336ENTRY(cpu_init_crit) 337 /* 338 * Jump to board specific initialization... 339 * The Mask ROM will have already initialized 340 * basic memory. Go here to bump up clock rate and handle 341 * wake up conditions. 342 */ 343 b lowlevel_init @ go setup pll,mux,memory 344ENDPROC(cpu_init_crit) 345#endif 346