1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2014-2015, Freescale Semiconductor, Inc.
4 * Copyright 2019 NXP Semiconductors
5 *
6 * Derived from arch/power/cpu/mpc85xx/speed.c
7 */
8
9 #include <common.h>
10 #include <cpu_func.h>
11 #include <linux/compiler.h>
12 #include <fsl_ifc.h>
13 #include <asm/processor.h>
14 #include <asm/io.h>
15 #include <asm/arch-fsl-layerscape/immap_lsch3.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/soc.h>
18 #include "cpu.h"
19
20 DECLARE_GLOBAL_DATA_PTR;
21
22 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
23 #define CONFIG_SYS_FSL_NUM_CC_PLLS 6
24 #endif
25
26
get_sys_info(struct sys_info * sys_info)27 void get_sys_info(struct sys_info *sys_info)
28 {
29 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
30 struct ccsr_clk_cluster_group __iomem *clk_grp[2] = {
31 (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR),
32 (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR)
33 };
34 struct ccsr_clk_ctrl __iomem *clk_ctrl =
35 (void *)(CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR);
36 unsigned int cpu;
37 const u8 core_cplx_pll[16] = {
38 [0] = 0, /* CC1 PPL / 1 */
39 [1] = 0, /* CC1 PPL / 2 */
40 [2] = 0, /* CC1 PPL / 4 */
41 [4] = 1, /* CC2 PPL / 1 */
42 [5] = 1, /* CC2 PPL / 2 */
43 [6] = 1, /* CC2 PPL / 4 */
44 [8] = 2, /* CC3 PPL / 1 */
45 [9] = 2, /* CC3 PPL / 2 */
46 [10] = 2, /* CC3 PPL / 4 */
47 [12] = 3, /* CC4 PPL / 1 */
48 [13] = 3, /* CC4 PPL / 2 */
49 [14] = 3, /* CC4 PPL / 4 */
50 };
51
52 const u8 core_cplx_pll_div[16] = {
53 [0] = 1, /* CC1 PPL / 1 */
54 [1] = 2, /* CC1 PPL / 2 */
55 [2] = 4, /* CC1 PPL / 4 */
56 [4] = 1, /* CC2 PPL / 1 */
57 [5] = 2, /* CC2 PPL / 2 */
58 [6] = 4, /* CC2 PPL / 4 */
59 [8] = 1, /* CC3 PPL / 1 */
60 [9] = 2, /* CC3 PPL / 2 */
61 [10] = 4, /* CC3 PPL / 4 */
62 [12] = 1, /* CC4 PPL / 1 */
63 [13] = 2, /* CC4 PPL / 2 */
64 [14] = 4, /* CC4 PPL / 4 */
65 };
66
67 uint i, cluster;
68 #if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
69 uint rcw_tmp;
70 #endif
71 uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
72 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
73 unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
74 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
75 u32 c_pll_sel, cplx_pll;
76 void *offset;
77
78 sys_info->freq_systembus = sysclk;
79 #ifdef CONFIG_DDR_CLK_FREQ
80 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
81 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
82 sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ;
83 #endif
84 #else
85 sys_info->freq_ddrbus = sysclk;
86 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
87 sys_info->freq_ddrbus2 = sysclk;
88 #endif
89 #endif
90
91 /* The freq_systembus is used to record frequency of platform PLL */
92 sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
93 FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
94 FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
95 sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
96 FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
97 FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
98 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
99 if (soc_has_dp_ddr()) {
100 sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
101 FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
102 FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
103 } else {
104 sys_info->freq_ddrbus2 = 0;
105 }
106 #endif
107
108 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
109 /*
110 * fixme: prefer to combine the following into one line, but
111 * cannot pass compiling without warning about in_le32.
112 */
113 offset = (void *)((size_t)clk_grp[i/3] +
114 offsetof(struct ccsr_clk_cluster_group,
115 pllngsr[i%3].gsr));
116 ratio[i] = (in_le32(offset) >> 1) & 0x3f;
117 freq_c_pll[i] = sysclk * ratio[i];
118 }
119
120 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
121 cluster = fsl_qoriq_core_to_cluster(cpu);
122 c_pll_sel = (in_le32(&clk_ctrl->clkcncsr[cluster].csr) >> 27)
123 & 0xf;
124 cplx_pll = core_cplx_pll[c_pll_sel];
125 cplx_pll += cc_group[cluster] - 1;
126 sys_info->freq_processor[cpu] =
127 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
128 }
129
130 #if defined(CONFIG_FSL_IFC)
131 sys_info->freq_localbus = sys_info->freq_systembus /
132 CONFIG_SYS_FSL_IFC_CLK_DIV;
133 #endif
134
135 #if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
136 #define HWA_CGA_M2_CLK_SEL 0x00380000
137 #define HWA_CGA_M2_CLK_SHIFT 19
138 rcw_tmp = in_le32(&gur->rcwsr[5]);
139 switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
140 case 1:
141 sys_info->freq_cga_m2 = freq_c_pll[1];
142 break;
143 case 2:
144 sys_info->freq_cga_m2 = freq_c_pll[1] / 2;
145 break;
146 case 3:
147 sys_info->freq_cga_m2 = freq_c_pll[1] / 3;
148 break;
149 case 4:
150 sys_info->freq_cga_m2 = freq_c_pll[1] / 4;
151 break;
152 case 6:
153 sys_info->freq_cga_m2 = freq_c_pll[0] / 2;
154 break;
155 case 7:
156 sys_info->freq_cga_m2 = freq_c_pll[0] / 3;
157 break;
158 default:
159 printf("Error: Unknown peripheral clock select!\n");
160 break;
161 }
162 #endif
163 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A)
164 sys_info->freq_cga_m2 = sys_info->freq_systembus;
165 #endif
166 }
167
get_clocks(void)168 int get_clocks(void)
169 {
170 struct sys_info sys_info;
171 get_sys_info(&sys_info);
172 gd->cpu_clk = sys_info.freq_processor[0];
173 gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
174 gd->mem_clk = sys_info.freq_ddrbus;
175 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
176 gd->arch.mem2_clk = sys_info.freq_ddrbus2;
177 #endif
178 #if defined(CONFIG_FSL_ESDHC)
179 #if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
180 #if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A)
181 gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2;
182 #endif
183 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
184 gd->arch.sdhc_clk = sys_info.freq_cga_m2;
185 #endif
186 #else
187 gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV;
188 #endif
189 #endif /* defined(CONFIG_FSL_ESDHC) */
190
191 if (gd->cpu_clk != 0)
192 return 0;
193 else
194 return 1;
195 }
196
197 /********************************************
198 * get_bus_freq
199 * return platform clock in Hz
200 *********************************************/
get_bus_freq(ulong dummy)201 ulong get_bus_freq(ulong dummy)
202 {
203 if (!gd->bus_clk)
204 get_clocks();
205
206 return gd->bus_clk;
207 }
208
209 /********************************************
210 * get_ddr_freq
211 * return ddr bus freq in Hz
212 *********************************************/
get_ddr_freq(ulong ctrl_num)213 ulong get_ddr_freq(ulong ctrl_num)
214 {
215 if (!gd->mem_clk)
216 get_clocks();
217
218 /*
219 * DDR controller 0 & 1 are on memory complex 0
220 * DDR controller 2 is on memory complext 1
221 */
222 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
223 if (ctrl_num >= 2)
224 return gd->arch.mem2_clk;
225 #endif
226
227 return gd->mem_clk;
228 }
229
get_i2c_freq(ulong dummy)230 int get_i2c_freq(ulong dummy)
231 {
232 return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV;
233 }
234
get_dspi_freq(ulong dummy)235 int get_dspi_freq(ulong dummy)
236 {
237 return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV;
238 }
239
get_serial_clock(void)240 int get_serial_clock(void)
241 {
242 return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV;
243 }
244
mxc_get_clock(enum mxc_clock clk)245 unsigned int mxc_get_clock(enum mxc_clock clk)
246 {
247 switch (clk) {
248 case MXC_I2C_CLK:
249 return get_i2c_freq(0);
250 case MXC_DSPI_CLK:
251 return get_dspi_freq(0);
252 default:
253 printf("Unsupported clock\n");
254 }
255 return 0;
256 }
257