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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2013
4  * David Feng <fenghua@phytium.com.cn>
5  */
6 
7 #include <common.h>
8 #include <command.h>
9 #include <time.h>
10 #include <asm/system.h>
11 
12 DECLARE_GLOBAL_DATA_PTR;
13 
14 /*
15  * Generic timer implementation of get_tbclk()
16  */
get_tbclk(void)17 __weak unsigned long get_tbclk(void)
18 {
19 	unsigned long cntfrq;
20 	asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq));
21 	return cntfrq;
22 }
23 
24 #ifdef CONFIG_SYS_FSL_ERRATUM_A008585
25 /*
26  * FSL erratum A-008585 says that the ARM generic timer counter "has the
27  * potential to contain an erroneous value for a small number of core
28  * clock cycles every time the timer value changes".
29  * This sometimes leads to a consecutive counter read returning a lower
30  * value than the previous one, thus reporting the time to go backwards.
31  * The workaround is to read the counter twice and only return when the value
32  * was the same in both reads.
33  * Assumes that the CPU runs in much higher frequency than the timer.
34  */
timer_read_counter(void)35 __weak unsigned long timer_read_counter(void)
36 {
37 	unsigned long cntpct;
38 	unsigned long temp;
39 
40 	isb();
41 	asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
42 	asm volatile("mrs %0, cntpct_el0" : "=r" (temp));
43 	while (temp != cntpct) {
44 		asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
45 		asm volatile("mrs %0, cntpct_el0" : "=r" (temp));
46 	}
47 
48 	return cntpct;
49 }
50 #elif CONFIG_SUNXI_A64_TIMER_ERRATUM
51 /*
52  * This erratum sometimes flips the lower 11 bits of the counter value
53  * to all 0's or all 1's, leading to jumps forwards or backwards.
54  * Backwards jumps might be interpreted all roll-overs and be treated as
55  * huge jumps forward.
56  * The workaround is to check whether the lower 11 bits of the counter are
57  * all 0 or all 1, then discard this value and read again.
58  * This occasionally discards valid values, but will catch all erroneous
59  * reads and fixes the problem reliably. Also this mostly requires only a
60  * single read, so does not have any significant overhead.
61  * The algorithm was conceived by Samuel Holland.
62  */
timer_read_counter(void)63 unsigned long timer_read_counter(void)
64 {
65 	unsigned long cntpct;
66 
67 	isb();
68 	do {
69 		asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
70 	} while (((cntpct + 1) & GENMASK(10, 0)) <= 1);
71 
72 	return cntpct;
73 }
74 #else
75 /*
76  * timer_read_counter() using the Arm Generic Timer (aka arch timer).
77  */
timer_read_counter(void)78 unsigned long timer_read_counter(void)
79 {
80 	unsigned long cntpct;
81 
82 	isb();
83 	asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
84 
85 	return cntpct;
86 }
87 #endif
88 
get_ticks(void)89 __weak uint64_t get_ticks(void)
90 {
91 	unsigned long ticks = timer_read_counter();
92 
93 	gd->arch.tbl = ticks;
94 
95     /* increment tbu if tbl has rolled over */
96     if (ticks < gd->timebase_l) {
97         gd->timebase_h++;
98     }
99 
100     gd->timebase_l = ticks;
101     return ((uint64_t)gd->timebase_h << 32) | gd->timebase_l;
102 }
103 
usec2ticks(unsigned long usec)104 unsigned long usec2ticks(unsigned long usec)
105 {
106 	ulong ticks;
107 	if (usec < 1000)
108 		ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
109 	else
110 		ticks = ((usec / 10) * (get_tbclk() / 100000));
111 
112 	return ticks;
113 }
114 
timer_get_boot_us(void)115 ulong timer_get_boot_us(void)
116 {
117 	u64 val = get_ticks() * 1000000;
118 
119 	return val / get_tbclk();
120 }
121