1 /*
2 * lowlevel_init_v300.c
3 *
4 * The file is Hardware initialization.
5 *
6 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 *
21 */
22
23 #include <asm/arch/platform.h>
24 #include <config.h>
25 #include "ddr_interface.h"
26
27 #define HI_SYS_CTL_REG SYS_CTRL_REG_BASE
28
29 #define OK 0
30 #define ERROR (-1)
31 #define DDR_CA0_OFST 0x88
32 #define DDR_CA1_OFST 0x8c
33 #define DDR_CA2_OFST 0x90
34 #define REG_BASE_DDRC 0x12060000
35
36 #define DDRC_CTRL_SREF_OFST (0x8000 + 0x0)
37 #define DDRC_CFG_DDRMODE_OFST (0x8000 + 0X50)
38 #define DDRC_CURR_FUNC_OFST (0x8000 + 0x294)
39
40 #define DDRC1_CTRL_SREF_OFST (0x9000 + 0x0)
41 #define DDRC1_CFG_DDRMODE_OFST (0x9000 + 0X50)
42 #define DDRC1_CURR_FUNC_OFST (0x9000 + 0x294)
43
44 #define DDRC2_CTRL_SREF_OFST (0xa000 + 0x0)
45 #define DDRC2_CFG_DDRMODE_OFST (0xa000 + 0X50)
46 #define DDRC2_CURR_FUNC_OFST (0xa000 + 0x294)
47
48 #define DDRC3_CTRL_SREF_OFST (0xb000 + 0x0)
49 #define DDRC3_CFG_DDRMODE_OFST (0xb000 + 0X50)
50 #define DDRC3_CURR_FUNC_OFST (0xb000 + 0x294)
51
52 #define DDRC_SELF_REFURBISH_MASK 0x1
53
54 /* [CUSTOM] DDR DMC0-DMC3 base register */
55 #define DDR_REG_BASE_DMC0 0x12068000
56 #define DDR_REG_BASE_DMC1 0x12069000
57 #define DDR_REG_BASE_DMC2 0x1206a000
58 #define DDR_REG_BASE_DMC3 0x1206b000
59 /* [CUSTOM] DDR PHY0-PHY1 base register */
60 #define DDR_REG_BASE_PHY0 0x1206c000
61 #define DDR_REG_BASE_PHY1 0x1206e000
62
63 #define DDR_PHY_DRAMCFG 0x2c /* DRAM config register */
64 #define PHY_DRAMCFG_TYPE_MASK 0xf /* [3:0] */
65 #define PHY_DRAMCFG_TYPE_LPDDR4 0x6 /* [2:0] 110 LPDDR4 */
delay(unsigned int num)66 static inline void delay(unsigned int num)
67 {
68 volatile unsigned int i;
69
70 for (i = 0; i < (100 * num); i++) /* 100: Cycle */
71 __asm__ __volatile__("nop");
72 }
73
dwb(void)74 static inline void dwb(void) /* drain write buffer */
75 {
76 }
77
readl(unsigned addr)78 static inline unsigned int readl(unsigned addr)
79 {
80 unsigned int val;
81
82 val = (*(volatile unsigned int *)(long)(addr));
83 return val;
84 }
85
writel(unsigned val,unsigned addr)86 static inline void writel(unsigned val, unsigned addr)
87 {
88 dwb();
89 (*(volatile unsigned *)(long)(addr)) = (val);
90 dwb();
91 }
92
93 #define REG_BASE_MISC 0x12030000
94 #ifdef DDR_SCRAMB_ENABLE
95
96 #define MISC_CTRL104_OFST 0x104
97 #define MISC_CTRL108_OFST 0x108
98 #define MISC_CTRL10C_OFST 0x10c
99
100 #define DDRC_0_CTRL_SREF_OFST (0x8000 + 0x0)
101 #define DDRC_0_CURR_FUNC_OFST (0x8000 + 0x294)
102 #define DDRC_1_CTRL_SREF_OFST (0x9000 + 0x0)
103 #define DDRC_1_CURR_FUNC_OFST (0x9000 + 0x294)
104 #undef reg_get
105 #define reg_get(addr) (*(volatile unsigned int *)((long)addr))
106
107 #undef reg_set
108 #define reg_set(addr, val) (*(volatile unsigned int *)((long)addr) = (val))
ddr_scramb_start(unsigned int random1,unsigned int random2)109 void ddr_scramb_start(unsigned int random1, unsigned int random2)
110 {
111 reg_set((unsigned int *)(REG_BASE_MISC + DDR_CA0_OFST), random1);
112 reg_set((unsigned int *)(REG_BASE_MISC + DDR_CA1_OFST), random2);
113 reg_set((unsigned int *)(REG_BASE_MISC + DDR_CA2_OFST), 0);
114 reg_set((unsigned int *)(REG_BASE_MISC + DDR_CA2_OFST), 0x10);
115 delay(0x100); /* delay 0x100 Cycle */
116 reg_set((unsigned int *)(REG_BASE_MISC + DDR_CA0_OFST), 0);
117 reg_set((unsigned int *)(REG_BASE_MISC + DDR_CA1_OFST), 0);
118 }
119
120 #define REG_BASE_RNG_GEN 0x10230000
121 #define TRNG_DSTA_FIFO_DATA_OFST 0x204
122 #define TRNG_DATA_ST_OFST 0x208
123 #define HISEC_COM_TRNG_CTRL_OFST 0x200
124 #define REG_PERI_CRG101 0x0194
125
126 #define BIT_TRNG_FIFO_DATA_CNT 0x8
127 #define TRNG_FIFO_DATA_CNT_MASK 0xff
128 #define TRNG_CTRL_DEF_VAL 0xa
129
130 #define TRNG_CLK_ENABLE (0x1 << 13)
131 #define TRNG_DO_SRST (0x1 << 12)
132 #define TRNG_CLK_DISABLE ~(0x1 << 13)
133 #define TRNG_UNDO_SRST ~(0x1 << 12)
134
135
136 /* get random number */
get_random_num(void)137 int get_random_num(void)
138 {
139 unsigned int reg_val;
140
141 do {
142 reg_val = reg_get(REG_BASE_RNG_GEN + TRNG_DATA_ST_OFST);
143 } while (!((reg_val >> BIT_TRNG_FIFO_DATA_CNT) &
144 TRNG_FIFO_DATA_CNT_MASK));
145
146 reg_val = reg_get(REG_BASE_RNG_GEN + TRNG_DSTA_FIFO_DATA_OFST);
147
148 return reg_val;
149 }
150
trng_init(void)151 void trng_init(void)
152 {
153 unsigned int reg_val;
154 /* open rsa and trng clock */
155 reg_val = reg_get(CRG_REG_BASE + REG_PERI_CRG101);
156 reg_val |= TRNG_CLK_ENABLE;
157 reg_set(CRG_REG_BASE + REG_PERI_CRG101, reg_val);
158
159 /* set trng ctrl register */
160 reg_set(REG_BASE_RNG_GEN + HISEC_COM_TRNG_CTRL_OFST,
161 TRNG_CTRL_DEF_VAL);
162 }
163
trng_deinit(void)164 void trng_deinit(void)
165 {
166 unsigned int reg_val;
167
168 /* close rsa and trng clock */
169 reg_val = reg_get(CRG_REG_BASE + REG_PERI_CRG101);
170 reg_val &= TRNG_CLK_DISABLE;
171 reg_set(CRG_REG_BASE + REG_PERI_CRG101, reg_val);
172 }
173
ddr_scramb(void)174 int ddr_scramb(void)
175 {
176 unsigned int random_num1;
177 unsigned int random_num2;
178 unsigned int reg_val[NUM_4] = {0, 0, 0, 0};
179 unsigned int ddrc_isvalid[NUM_4] = {0, 0, 0, 0};
180
181 /* read ddrc_cfg_ddrmode register,
182 * if value[3:0] is not 0x0 ,the channel is valid.
183 */
184 ddrc_isvalid[NUM_0] =
185 (reg_get(REG_BASE_DDRC + DDRC_CFG_DDRMODE_OFST) & 0xf) ? 1 : 0;
186 ddrc_isvalid[NUM_1] =
187 (reg_get(REG_BASE_DDRC + DDRC1_CFG_DDRMODE_OFST) & 0xf) ? 1 : 0;
188 ddrc_isvalid[NUM_2] =
189 (reg_get(REG_BASE_DDRC + DDRC2_CFG_DDRMODE_OFST) & 0xf) ? 1 : 0;
190 ddrc_isvalid[NUM_3] =
191 (reg_get(REG_BASE_DDRC + DDRC3_CFG_DDRMODE_OFST) & 0xf) ? 1 : 0;
192
193 /* set ddrc to do self-refurbish */
194 if (ddrc_isvalid[NUM_0])
195 reg_set(REG_BASE_DDRC + DDRC_CTRL_SREF_OFST, 0x1);
196
197 if (ddrc_isvalid[NUM_1])
198 reg_set(REG_BASE_DDRC + DDRC1_CTRL_SREF_OFST, 0x1);
199
200 if (ddrc_isvalid[NUM_2])
201 reg_set(REG_BASE_DDRC + DDRC2_CTRL_SREF_OFST, 0x1);
202
203 if (ddrc_isvalid[NUM_3])
204 reg_set(REG_BASE_DDRC + DDRC3_CTRL_SREF_OFST, 0x1);
205
206 /* wait the status of ddrc to be sef-refurbish */
207 do {
208 reg_val[NUM_0] = ddrc_isvalid[NUM_0] ? (reg_get(REG_BASE_DDRC +
209 DDRC_CURR_FUNC_OFST) & 0x1) : 1;
210 reg_val[NUM_1] = ddrc_isvalid[NUM_1] ? (reg_get(REG_BASE_DDRC +
211 DDRC1_CURR_FUNC_OFST) & 0x1) : 1;
212 reg_val[NUM_2] = ddrc_isvalid[NUM_2] ? (reg_get(REG_BASE_DDRC +
213 DDRC2_CURR_FUNC_OFST) & 0x1) : 1;
214 reg_val[NUM_3] = ddrc_isvalid[NUM_3] ? (reg_get(REG_BASE_DDRC +
215 DDRC3_CURR_FUNC_OFST) & 0x1) : 1;
216 } while (!(reg_val[NUM_0] & reg_val[NUM_1] & reg_val[NUM_2] & reg_val[NUM_3]));
217
218 trng_init();
219 /* get random number */
220 random_num1 = get_random_num();
221 random_num2 = get_random_num();
222
223 /* start ddr scrambling */
224 ddr_scramb_start(random_num1, random_num2);
225
226 /* clear random number */
227 (void)get_random_num();
228 (void)get_random_num();
229 (void)get_random_num();
230 (void)get_random_num();
231 trng_deinit();
232
233 /* set ddrc to exit self-refurbish */
234 if (ddrc_isvalid[NUM_0])
235 reg_set(REG_BASE_DDRC + DDRC_CTRL_SREF_OFST, (0x1 << 1));
236
237 if (ddrc_isvalid[NUM_1])
238 reg_set(REG_BASE_DDRC + DDRC1_CTRL_SREF_OFST, (0x1 << 1));
239
240 if (ddrc_isvalid[NUM_2])
241 reg_set(REG_BASE_DDRC + DDRC2_CTRL_SREF_OFST, (0x1 << 1));
242
243 if (ddrc_isvalid[NUM_3])
244 reg_set(REG_BASE_DDRC + DDRC3_CTRL_SREF_OFST, (0x1 << 1));
245
246 /* wait the status of ddrc to be normal */
247 do {
248 reg_val[NUM_0] = ddrc_isvalid[NUM_0] ? (reg_get(REG_BASE_DDRC +
249 DDRC_CURR_FUNC_OFST) & 0x1) : 0;
250 reg_val[NUM_1] = ddrc_isvalid[NUM_1] ? (reg_get(REG_BASE_DDRC +
251 DDRC1_CURR_FUNC_OFST) & 0x1) : 0;
252 reg_val[NUM_2] = ddrc_isvalid[NUM_2] ? (reg_get(REG_BASE_DDRC +
253 DDRC2_CURR_FUNC_OFST) & 0x1) : 0;
254 reg_val[NUM_3] = ddrc_isvalid[NUM_3] ? (reg_get(REG_BASE_DDRC +
255 DDRC3_CURR_FUNC_OFST) & 0x1) : 0;
256 } while (reg_val[NUM_0] | reg_val[NUM_1] | reg_val[NUM_2] | reg_val[NUM_3]);
257
258 return OK;
259 }
260
261 #endif /* DDR_SCRAMB_ENABLE */
262
263 #ifdef SVB_ENABLE
264
265 #define HI_PMC_CTL_REG 0x12030000
266 #define HPM_CORE_VOL_REG (HI_PMC_CTL_REG + 0x60)
267 #define HPM_GPU_VOL_REG (HI_PMC_CTL_REG + 0x64)
268 #define HPM_MDA_VOL_REG (HI_PMC_CTL_REG + 0x68)
269 #define HPM_CPU_VOL_REG (HI_PMC_CTL_REG + 0x6c)
270 #define CYCLE_NUM 8
271 #define HPM_CPU_REG0 0x1208
272 #define HPM_CPU_REG1 0x120c
273 #define HPM_MDA_REG0 0x1218
274 #define HPM_MDA_REG1 0x121c
275 #define HPM_GPU_REG0 0x1228
276 #define HPM_GPU_REG1 0x122C
277 #define HPM_CORE_REG0 0x1238
278 #define HPM_CORE_REG1 0x123c
279
280 #define HMP_CLK_REG 0x1201019c
281 #define CPU_ISO_REG 0x1d821104
282
283 #define TSENSOR_CTRL 0x70
284 #define TSENSOR_STATUS0 0X78
285
286 #define OTP_CPU_IF_REG 0x10250000
287 #define OTP_HPM_CORE_OFFSET 0x0028
288 #define OTP_HPM_MDA_OFFSET 0x002c
289 #define OTP_HPM_GPU_OFFSET 0x0030
290 #define OTP_HPM_CPU_OFFSET 0x0034
291 #define OTP_IDDQ_SENSORHUB_OFFSET 0x004c
292
293 #define SYSCTRL_BASE_REG 0x12020000
294 #define HPM_CORE_STORAGE_REG 0x300
295 #define HPM_MDA_STORAGE_REG 0x304
296 #define HPM_GPU_STORAGE_REG 0x308
297 #define HPM_CPU_STORAGE_REG 0x30c
298
299
300 /* physical max/min */
301 #define CORE_VOLT_MAX 943
302 #define CORE_VOLT_MIN 603
303
304 #define MDA_VOLT_MAX 935
305 #define MDA_VOLT_MIN 603
306
307 #define GPU_VOLT_MAX 943
308 #define GPU_VOLT_MIN 603
309
310 #define CPU_VOLT_MAX 1078
311 #define CPU_VOLT_MIN 597
312
313
314 /* curve max/min; voltage curve: v = (b - a * hpm)/10 */
315 #define CORE_CURVE_VLOT_MAX 900
316 #define CORE_CURVE_VLOT_MIN 840
317 #define CORE_CURVE_B 13200
318 #define CORE_CURVE_A 12
319
320 #define MEDIA_CURVE_VLOT_MAX 880
321 #define MEDIA_CURVE_VLOT_MIN 780
322 #define MEDIA_CURVE_B 12210
323 #define MEDIA_CURVE_A 11
324
325 #define GPU_CURVE_VLOT_MAX 950
326 #define GPU_CURVE_VLOT_MIN 858
327 #define GPU_CURVE_B 14180
328 #define GPU_CURVE_A 14
329
330 #define CPU_CURVE_VLOT_MAX 988
331 #define CPU_CURVE_VLOT_MIN 888
332 #define CPU_CURVE_B 15180
333 #define CPU_CURVE_A 14
334
335 #define temperature_formula(val) (((((val) - 116) * 165) / 806) - 40)
336 #define duty_formula(max, min, val) (((max - val) * 416 + \
337 (max - min + 1) / 2) / (max - min) - 1)
338 #define volt_regval_formula(val) (((val) << 16) + ((416 - 1) << 4) + 0x5)
339
hpm_value_avg(unsigned int * val,int num)340 static unsigned hpm_value_avg(unsigned int *val, int num)
341 {
342 unsigned int i;
343 unsigned tmp = 0;
344
345 for (i = 0; i < num; i++)
346 tmp += val[i];
347
348 return (tmp / CYCLE_NUM) >> NUM_2;
349 }
350
get_hpm_value(unsigned int * hpm_core,unsigned int * hpm_cpu,unsigned int * hpm_gpu,unsigned int * hpm_mda)351 static void get_hpm_value(unsigned int *hpm_core, unsigned int *hpm_cpu,
352 unsigned int *hpm_gpu, unsigned int *hpm_mda)
353 {
354 int i;
355 unsigned int temp;
356 unsigned int core_value[NUM_4] = {0, 0, 0, 0};
357 unsigned int mda_value[NUM_4] = {0, 0, 0, 0};
358 unsigned int cpu_value[NUM_4] = {0, 0, 0, 0};
359 unsigned int gpu_value[NUM_4] = {0, 0, 0, 0};
360
361 for (i = 0; i < CYCLE_NUM; i++) {
362 /* (at least 16us*4) */
363 delay(NUM_5);
364 /* cpu */
365 temp = readl(HI_PMC_CTL_REG + HPM_CPU_REG0);
366 cpu_value[NUM_1] += (temp >> 16) & 0x3ff; /* get hight 16 bits */
367 cpu_value[NUM_0] += temp & 0x3ff;
368 temp = readl(HI_PMC_CTL_REG + HPM_CPU_REG1);
369 cpu_value[NUM_3] += (temp >> 16) & 0x3ff; /* get hight 16 bits */
370 cpu_value[NUM_2] += temp & 0x3ff;
371
372 /* mda */
373 temp = readl(HI_PMC_CTL_REG + HPM_MDA_REG0);
374 mda_value[NUM_1] += (temp >> 16) & 0x3ff; /* get hight 16 bits */
375 mda_value[NUM_0] += temp & 0x3ff;
376 temp = readl(HI_PMC_CTL_REG + HPM_MDA_REG1);
377 mda_value[NUM_3] += (temp >> 16) & 0x3ff; /* get hight 16 bits */
378 mda_value[NUM_2] += temp & 0x3ff;
379
380 /* gpu */
381 temp = readl(HI_PMC_CTL_REG + HPM_GPU_REG0);
382 gpu_value[NUM_1] += (temp >> 16) & 0x3ff; /* get hight 16 bits */
383 gpu_value[NUM_0] += temp & 0x3ff;
384 temp = readl(HI_PMC_CTL_REG + HPM_GPU_REG1);
385 gpu_value[NUM_3] += (temp >> 16) & 0x3ff; /* get hight 16 bits */
386 gpu_value[NUM_2] += temp & 0x3ff;
387
388 /* core */
389 temp = readl(HI_PMC_CTL_REG + HPM_CORE_REG0);
390 core_value[NUM_1] += (temp >> 16) & 0x3ff; /* get hight 16 bits */
391 core_value[NUM_0] += temp & 0x3ff;
392 temp = readl(HI_PMC_CTL_REG + HPM_CORE_REG1);
393 core_value[NUM_3] += (temp >> 16) & 0x3ff; /* get hight 16 bits */
394 core_value[NUM_2] += temp & 0x3ff;
395 }
396
397 *hpm_core = hpm_value_avg(core_value,NUM_4);
398 *hpm_mda = hpm_value_avg(mda_value,NUM_4);
399 *hpm_cpu = hpm_value_avg(cpu_value,NUM_4);
400 *hpm_gpu = hpm_value_avg(gpu_value,NUM_4);
401 }
402
start_hpm(unsigned int * hpm_core,unsigned int * hpm_cpu,unsigned int * hpm_gpu,unsigned int * hpm_mda)403 static void start_hpm(unsigned int *hpm_core, unsigned int *hpm_cpu,
404 unsigned int *hpm_gpu, unsigned int *hpm_mda)
405 {
406 /* open hmp clock */
407 writel(0x7ff0000, HMP_CLK_REG);
408 /* cpu */
409 writel(0x60020001, HI_PMC_CTL_REG + 0x1200);
410 /* mda */
411 writel(0x60020001, HI_PMC_CTL_REG + 0x1210);
412 /* gpu */
413 writel(0x60020001, HI_PMC_CTL_REG + 0x1220);
414 /* core */
415 writel(0x60020001, HI_PMC_CTL_REG + 0x1230);
416
417 get_hpm_value(hpm_core, hpm_cpu, hpm_gpu, hpm_mda);
418
419 /* close hpm clock */
420 writel(0x0, HMP_CLK_REG);
421 }
422
adjust_hpm(unsigned int * hpm_core,unsigned int * hpm_cpu,unsigned int * hpm_gpu,unsigned int * hpm_mda,int temperature)423 static void adjust_hpm(unsigned int *hpm_core, unsigned int *hpm_cpu,
424 unsigned int *hpm_gpu, unsigned int *hpm_mda,
425 int temperature)
426 {
427 unsigned int otp_hpm_core = readl(OTP_CPU_IF_REG + OTP_HPM_CORE_OFFSET);
428 unsigned int otp_hpm_cpu = readl(OTP_CPU_IF_REG + OTP_HPM_CPU_OFFSET);
429 unsigned int otp_hpm_gpu = readl(OTP_CPU_IF_REG + OTP_HPM_GPU_OFFSET);
430 unsigned int otp_hpm_mda = readl(OTP_CPU_IF_REG + OTP_HPM_MDA_OFFSET);
431
432 if (temperature <= 0) { /* 0: the temperature min */
433 *hpm_cpu -= NUM_6;
434 *hpm_mda -= NUM_3;
435 *hpm_gpu -= NUM_6;
436 *hpm_core -= NUM_4;
437 } else if (temperature > 70) { /* 70: the temperature max */
438 *hpm_cpu += NUM_5;
439 *hpm_mda += NUM_3;
440 *hpm_gpu += NUM_2;
441 *hpm_core += NUM_2;
442 }
443
444 if (otp_hpm_core)
445 if (*hpm_core > (otp_hpm_core + 10)) /* 10: Increment */
446 *hpm_core = otp_hpm_core - NUM_5;
447
448 if (otp_hpm_cpu)
449 if (*hpm_cpu > (otp_hpm_cpu + 15)) /* 15: Increment */
450 *hpm_cpu = otp_hpm_cpu;
451
452 if (otp_hpm_gpu)
453 if (*hpm_gpu > (otp_hpm_gpu + 15)) /* 15: Increment */
454 *hpm_gpu = otp_hpm_gpu;
455
456 if (otp_hpm_mda)
457 if (*hpm_mda > (otp_hpm_mda + 15)) /* 15: Increment */
458 *hpm_mda = otp_hpm_mda;
459 }
460
461
save_hpm(unsigned int hpm_core,unsigned int hpm_cpu,unsigned int hpm_gpu,unsigned int hpm_mda)462 static void save_hpm(unsigned int hpm_core, unsigned int hpm_cpu,
463 unsigned int hpm_gpu, unsigned int hpm_mda)
464 {
465 writel(hpm_mda, SYSCTRL_BASE_REG + HPM_MDA_STORAGE_REG);
466 writel(hpm_gpu, SYSCTRL_BASE_REG + HPM_GPU_STORAGE_REG);
467 writel(hpm_cpu, SYSCTRL_BASE_REG + HPM_CPU_STORAGE_REG);
468 }
469
calc_volt_regval(unsigned int volt_val,unsigned int volt_max,unsigned int volt_min)470 static unsigned int calc_volt_regval(unsigned int volt_val,
471 unsigned int volt_max,
472 unsigned int volt_min)
473 {
474 unsigned int reg_val;
475 unsigned int duty;
476
477 if (volt_val >= volt_max)
478 volt_val = volt_max - 1;
479
480 if (volt_val <= volt_min)
481 volt_val = volt_min + 1 ;
482
483 duty = duty_formula(volt_max, volt_min, volt_val);
484 reg_val = volt_regval_formula(duty);
485
486 return reg_val;
487 }
488
set_hpm_core_volt(unsigned int hpm_core_value,int delta_v)489 static void set_hpm_core_volt(unsigned int hpm_core_value, int delta_v)
490 {
491 unsigned int volt_val;
492 unsigned int reg_val;
493
494 volt_val = (CORE_CURVE_B - CORE_CURVE_A * hpm_core_value) / NUM_10 + delta_v;
495 if (volt_val > CORE_CURVE_VLOT_MAX)
496 volt_val = CORE_CURVE_VLOT_MAX;
497 else if (volt_val < CORE_CURVE_VLOT_MIN)
498 volt_val = CORE_CURVE_VLOT_MIN;
499
500 reg_val = calc_volt_regval(volt_val, CORE_VOLT_MAX, CORE_VOLT_MIN);
501
502 writel(reg_val, HPM_CORE_VOL_REG);
503 }
504
set_hpm_mda_volt(unsigned int hpm_mda_value,int delta_v)505 static void set_hpm_mda_volt(unsigned int hpm_mda_value, int delta_v)
506 {
507 unsigned int volt_val;
508 unsigned int reg_val;
509
510 volt_val = (MEDIA_CURVE_B - MEDIA_CURVE_A * hpm_mda_value) / NUM_10 + delta_v;
511 if (volt_val > MEDIA_CURVE_VLOT_MAX)
512 volt_val = MEDIA_CURVE_VLOT_MAX;
513 else if (volt_val < MEDIA_CURVE_VLOT_MIN)
514 volt_val = MEDIA_CURVE_VLOT_MIN;
515
516 reg_val = calc_volt_regval(volt_val, MDA_VOLT_MAX, MDA_VOLT_MIN);
517
518 writel(reg_val, HPM_MDA_VOL_REG);
519 }
set_hpm_gpu_volt(unsigned int hpm_gpu_value,int delta_v)520 static void set_hpm_gpu_volt(unsigned int hpm_gpu_value, int delta_v)
521 {
522 unsigned int volt_val;
523 unsigned int reg_val;
524
525 volt_val = (GPU_CURVE_B - GPU_CURVE_A * hpm_gpu_value) / NUM_10 + delta_v;
526 if (volt_val > GPU_CURVE_VLOT_MAX)
527 volt_val = GPU_CURVE_VLOT_MAX;
528 else if (volt_val < GPU_CURVE_VLOT_MIN)
529 volt_val = GPU_CURVE_VLOT_MIN;
530
531 reg_val = calc_volt_regval(volt_val, GPU_VOLT_MAX, GPU_VOLT_MIN);
532
533 writel(reg_val, HPM_GPU_VOL_REG);
534 }
set_hpm_cpu_volt(unsigned int hpm_cpu_value,int delta_v)535 static void set_hpm_cpu_volt(unsigned int hpm_cpu_value, int delta_v)
536 {
537 unsigned int volt_val;
538 unsigned int reg_val;
539
540 volt_val = (CPU_CURVE_B - CPU_CURVE_A * hpm_cpu_value) / NUM_10 + delta_v;
541 if (volt_val > CPU_CURVE_VLOT_MAX)
542 volt_val = CPU_CURVE_VLOT_MAX;
543 else if (volt_val < CPU_CURVE_VLOT_MIN)
544 volt_val = CPU_CURVE_VLOT_MIN;
545
546 reg_val = calc_volt_regval(volt_val, CPU_VOLT_MAX, CPU_VOLT_MIN);
547
548 writel(reg_val, HPM_CPU_VOL_REG);
549 }
550
get_delta_v(int * core_delta_v,int * cpu_delta_v,int * gpu_delta_v,int * mda_delta_v)551 static void get_delta_v(int *core_delta_v, int *cpu_delta_v, int *gpu_delta_v,
552 int *mda_delta_v)
553 {
554 unsigned int value = readl(OTP_CPU_IF_REG + OTP_IDDQ_SENSORHUB_OFFSET);
555
556 /* core:bit 16-19,
557 bit19 equal to 1 means negative, equal to 0 means positive,
558 bit 16-18 is the absolute delta_v */
559 int flag = value & 0x00080000 ? -1 : 1;
560 *core_delta_v = flag * (int)((value >> BIT_16) & 0x7) * NUM_10; /* 0x7: Mask */
561
562 /* media:bit 20-23 */
563 flag = value & 0x00800000 ? -1 : 1;
564 *mda_delta_v = flag * (int)((value >> BIT_20) & 0x7) * NUM_10; /* 0x7: Mask */
565
566 /* gpu:bit 24-27 */
567 flag = value & 0x08000000 ? -1 : 1;
568 *gpu_delta_v = flag * (int)((value >> BIT_24) & 0x7) * NUM_10; /* 0x7: Mask */
569
570 /* cpu:bit 28-31 */
571 flag = value & 0x80000000 ? -1 : 1;
572 *cpu_delta_v = flag * (int)((value >> BIT_28) & 0x7) * NUM_10; /* 0x7: Mask */
573 }
574
575
set_volt(unsigned int hpm_core,unsigned int hpm_cpu,unsigned int hpm_gpu,unsigned int hpm_mda)576 static void set_volt(unsigned int hpm_core, unsigned int hpm_cpu,
577 unsigned int hpm_gpu, unsigned int hpm_mda)
578 {
579 int core_delta_v;
580 int cpu_delta_v;
581 int gpu_delta_v;
582 int mda_delta_v;
583 get_delta_v(&core_delta_v, &cpu_delta_v, &gpu_delta_v, &mda_delta_v);
584
585 set_hpm_core_volt(hpm_core, core_delta_v);
586 set_hpm_mda_volt(hpm_mda, mda_delta_v);
587 set_hpm_cpu_volt(hpm_cpu, cpu_delta_v);
588 set_hpm_gpu_volt(hpm_gpu, gpu_delta_v);
589
590 delay(280); /* delay 280ms */
591 }
592
power_on_avsp(void)593 static void power_on_avsp(void)
594 {
595 unsigned int tmp = readl(REG_BASE_MISC + 0xb0);
596 tmp |= (0x1 << 17); /* Move Left 17 bit */
597 writel(tmp, REG_BASE_MISC + 0xb0);
598 tmp &= (~(0x1 << 16)); /* Move Left 16 bit */
599 writel(tmp, REG_BASE_MISC + 0xb0);
600 }
601
602
power_down_avsp(void)603 static void power_down_avsp(void)
604 {
605 unsigned int tmp = readl(REG_BASE_MISC + 0xb0);
606 tmp |= (0x1 << 16); /* Move Left 16 bit */
607 writel(tmp, REG_BASE_MISC + 0xb0);
608 tmp &= (~(0x1 << 17)); /* Move Left 17 bit */
609 writel(tmp, REG_BASE_MISC + 0xb0);
610 }
611
612
disisolate_cpu(void)613 static void disisolate_cpu(void)
614 {
615 unsigned int tmp = readl(CPU_ISO_REG);
616 tmp &= (~(0x1 << NUM_3));
617 writel(tmp, CPU_ISO_REG);
618 }
619
isolate_cpu(void)620 static void isolate_cpu(void)
621 {
622 unsigned int tmp = readl(CPU_ISO_REG);
623 tmp |= (0x1 << NUM_3);
624 writel(tmp, CPU_ISO_REG);
625 }
626
get_temperature(int * temperature)627 static void get_temperature(int *temperature)
628 {
629 int value;
630
631 value = readl(REG_BASE_MISC + TSENSOR_STATUS0);
632 value = value & 0x3ff;
633
634 *temperature = temperature_formula(value);
635 }
636
start_svb(void)637 static void start_svb(void)
638 {
639 unsigned int hpm_core;
640 unsigned int hpm_cpu;
641 unsigned int hpm_gpu;
642 unsigned int hpm_mda;
643 int temperature;
644
645 /* avsp power on and disisolate cpu a73 */
646 disisolate_cpu();
647 power_on_avsp();
648
649 /* get hpm */
650 start_hpm(&hpm_core, &hpm_cpu, &hpm_gpu, &hpm_mda);
651
652 /* avsp power down and isolate cpu a73 */
653 power_down_avsp();
654 isolate_cpu();
655
656 get_temperature(&temperature);
657
658 adjust_hpm(&hpm_core, &hpm_cpu, &hpm_gpu, &hpm_mda, temperature);
659
660 set_volt(hpm_core, hpm_cpu, hpm_gpu, hpm_mda);
661
662 save_hpm(hpm_core, hpm_cpu, hpm_gpu, hpm_mda);
663
664 #define SVB_VER_REG 0x12020150
665 #define SVB_VER 0x30303030
666
667 /* add SVB VER */
668 writel(SVB_VER, SVB_VER_REG);
669 }
670 #endif
671
start_ddr_training(unsigned int base)672 void start_ddr_training(unsigned int base)
673 {
674 #ifdef SVB_ENABLE
675 start_svb();
676 #endif
677
678 /* ddr hw training */
679 ddr_hw_training_if();
680
681 ddr_cmd_site_save();
682 /* ddr sw training */
683 ddr_sw_training_if();
684 ddr_cmd_site_restore();
685
686 /* the value should config after trainning, or
687 it will cause chip compatibility problems */
688 if ((readl(DDR_REG_BASE_PHY0 + DDR_PHY_DRAMCFG) &
689 PHY_DRAMCFG_TYPE_MASK) == PHY_DRAMCFG_TYPE_LPDDR4) {
690 writel(0x401, DDR_REG_BASE_DMC0 + 0x28);
691 writel(0x401, DDR_REG_BASE_DMC1 + 0x28);
692 } else {
693 writel(0x401, DDR_REG_BASE_DMC0 + 0x28);
694 }
695 if ((readl(DDR_REG_BASE_PHY1 + DDR_PHY_DRAMCFG) &
696 PHY_DRAMCFG_TYPE_MASK) == PHY_DRAMCFG_TYPE_LPDDR4) {
697 writel(0x401, DDR_REG_BASE_DMC2 + 0x28);
698 writel(0x401, DDR_REG_BASE_DMC3 + 0x28);
699 } else {
700 writel(0x401, DDR_REG_BASE_DMC1 + 0x28);
701 }
702 #ifdef DDR_SCRAMB_ENABLE
703 /* enable ddr scramb */
704 ddr_scramb();
705 #endif
706 }
707