1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/px30-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/px30-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13 14/ { 15 compatible = "rockchip,px30"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &gmac; 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 serial0 = &uart0; 28 serial1 = &uart1; 29 serial2 = &uart2; 30 serial3 = &uart3; 31 serial4 = &uart4; 32 serial5 = &uart5; 33 spi0 = &spi0; 34 spi1 = &spi1; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 cpu0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a35"; 44 reg = <0x0 0x0>; 45 enable-method = "psci"; 46 clocks = <&cru ARMCLK>; 47 #cooling-cells = <2>; 48 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 49 dynamic-power-coefficient = <90>; 50 operating-points-v2 = <&cpu0_opp_table>; 51 }; 52 53 cpu1: cpu@1 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a35"; 56 reg = <0x0 0x1>; 57 enable-method = "psci"; 58 clocks = <&cru ARMCLK>; 59 #cooling-cells = <2>; 60 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 61 dynamic-power-coefficient = <90>; 62 operating-points-v2 = <&cpu0_opp_table>; 63 }; 64 65 cpu2: cpu@2 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a35"; 68 reg = <0x0 0x2>; 69 enable-method = "psci"; 70 clocks = <&cru ARMCLK>; 71 #cooling-cells = <2>; 72 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 73 dynamic-power-coefficient = <90>; 74 operating-points-v2 = <&cpu0_opp_table>; 75 }; 76 77 cpu3: cpu@3 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a35"; 80 reg = <0x0 0x3>; 81 enable-method = "psci"; 82 clocks = <&cru ARMCLK>; 83 #cooling-cells = <2>; 84 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 85 dynamic-power-coefficient = <90>; 86 operating-points-v2 = <&cpu0_opp_table>; 87 }; 88 89 idle-states { 90 entry-method = "psci"; 91 92 CPU_SLEEP: cpu-sleep { 93 compatible = "arm,idle-state"; 94 local-timer-stop; 95 arm,psci-suspend-param = <0x0010000>; 96 entry-latency-us = <120>; 97 exit-latency-us = <250>; 98 min-residency-us = <900>; 99 }; 100 101 CLUSTER_SLEEP: cluster-sleep { 102 compatible = "arm,idle-state"; 103 local-timer-stop; 104 arm,psci-suspend-param = <0x1010000>; 105 entry-latency-us = <400>; 106 exit-latency-us = <500>; 107 min-residency-us = <2000>; 108 }; 109 }; 110 }; 111 112 cpu0_opp_table: cpu0-opp-table { 113 compatible = "operating-points-v2"; 114 opp-shared; 115 116 opp-408000000 { 117 opp-hz = /bits/ 64 <408000000>; 118 opp-microvolt = <950000 950000 1350000>; 119 clock-latency-ns = <40000>; 120 opp-suspend; 121 }; 122 opp-600000000 { 123 opp-hz = /bits/ 64 <600000000>; 124 opp-microvolt = <950000 950000 1350000>; 125 clock-latency-ns = <40000>; 126 }; 127 opp-816000000 { 128 opp-hz = /bits/ 64 <816000000>; 129 opp-microvolt = <1050000 1050000 1350000>; 130 clock-latency-ns = <40000>; 131 }; 132 opp-1008000000 { 133 opp-hz = /bits/ 64 <1008000000>; 134 opp-microvolt = <1175000 1175000 1350000>; 135 clock-latency-ns = <40000>; 136 }; 137 opp-1200000000 { 138 opp-hz = /bits/ 64 <1200000000>; 139 opp-microvolt = <1300000 1300000 1350000>; 140 clock-latency-ns = <40000>; 141 }; 142 opp-1296000000 { 143 opp-hz = /bits/ 64 <1296000000>; 144 opp-microvolt = <1350000 1350000 1350000>; 145 clock-latency-ns = <40000>; 146 }; 147 }; 148 149 arm-pmu { 150 compatible = "arm,cortex-a53-pmu"; 151 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 155 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 156 }; 157 158 dmc: dmc { 159 compatible = "rockchip,px30-dmc", "syscon"; 160 reg = <0x0 0xff2a0000 0x0 0x1000>; 161 }; 162 163 display_subsystem: display-subsystem { 164 compatible = "rockchip,display-subsystem"; 165 ports = <&vopb_out>, <&vopl_out>; 166 status = "disabled"; 167 }; 168 169 gmac_clkin: external-gmac-clock { 170 compatible = "fixed-clock"; 171 clock-frequency = <50000000>; 172 clock-output-names = "gmac_clkin"; 173 #clock-cells = <0>; 174 }; 175 176 psci { 177 compatible = "arm,psci-1.0"; 178 method = "smc"; 179 }; 180 181 timer { 182 compatible = "arm,armv8-timer"; 183 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 184 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 185 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 186 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 187 }; 188 189 xin24m: xin24m { 190 compatible = "fixed-clock"; 191 #clock-cells = <0>; 192 clock-frequency = <24000000>; 193 clock-output-names = "xin24m"; 194 }; 195 196 pmu: power-management@ff000000 { 197 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; 198 reg = <0x0 0xff000000 0x0 0x1000>; 199 200 power: power-controller { 201 compatible = "rockchip,px30-power-controller"; 202 #power-domain-cells = <1>; 203 #address-cells = <1>; 204 #size-cells = <0>; 205 206 /* These power domains are grouped by VD_LOGIC */ 207 pd_usb@PX30_PD_USB { 208 reg = <PX30_PD_USB>; 209 clocks = <&cru HCLK_HOST>, 210 <&cru HCLK_OTG>, 211 <&cru SCLK_OTG_ADP>; 212 pm_qos = <&qos_usb_host>, <&qos_usb_otg>; 213 }; 214 pd_sdcard@PX30_PD_SDCARD { 215 reg = <PX30_PD_SDCARD>; 216 clocks = <&cru HCLK_SDMMC>, 217 <&cru SCLK_SDMMC>; 218 pm_qos = <&qos_sdmmc>; 219 }; 220 pd_gmac@PX30_PD_GMAC { 221 reg = <PX30_PD_GMAC>; 222 clocks = <&cru ACLK_GMAC>, 223 <&cru PCLK_GMAC>, 224 <&cru SCLK_MAC_REF>, 225 <&cru SCLK_GMAC_RX_TX>; 226 pm_qos = <&qos_gmac>; 227 }; 228 pd_mmc_nand@PX30_PD_MMC_NAND { 229 reg = <PX30_PD_MMC_NAND>; 230 clocks = <&cru HCLK_NANDC>, 231 <&cru HCLK_EMMC>, 232 <&cru HCLK_SDIO>, 233 <&cru HCLK_SFC>, 234 <&cru SCLK_EMMC>, 235 <&cru SCLK_NANDC>, 236 <&cru SCLK_SDIO>, 237 <&cru SCLK_SFC>; 238 pm_qos = <&qos_emmc>, <&qos_nand>, 239 <&qos_sdio>, <&qos_sfc>; 240 }; 241 pd_vpu@PX30_PD_VPU { 242 reg = <PX30_PD_VPU>; 243 clocks = <&cru ACLK_VPU>, 244 <&cru HCLK_VPU>, 245 <&cru SCLK_CORE_VPU>; 246 pm_qos = <&qos_vpu>, <&qos_vpu_r128>; 247 }; 248 pd_vo@PX30_PD_VO { 249 reg = <PX30_PD_VO>; 250 clocks = <&cru ACLK_RGA>, 251 <&cru ACLK_VOPB>, 252 <&cru ACLK_VOPL>, 253 <&cru DCLK_VOPB>, 254 <&cru DCLK_VOPL>, 255 <&cru HCLK_RGA>, 256 <&cru HCLK_VOPB>, 257 <&cru HCLK_VOPL>, 258 <&cru PCLK_MIPI_DSI>, 259 <&cru SCLK_RGA_CORE>, 260 <&cru SCLK_VOPB_PWM>; 261 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, 262 <&qos_vop_m0>, <&qos_vop_m1>; 263 }; 264 pd_vi@PX30_PD_VI { 265 reg = <PX30_PD_VI>; 266 clocks = <&cru ACLK_CIF>, 267 <&cru ACLK_ISP>, 268 <&cru HCLK_CIF>, 269 <&cru HCLK_ISP>, 270 <&cru SCLK_ISP>; 271 pm_qos = <&qos_isp_128>, <&qos_isp_rd>, 272 <&qos_isp_wr>, <&qos_isp_m1>, 273 <&qos_vip>; 274 }; 275 pd_gpu@PX30_PD_GPU { 276 reg = <PX30_PD_GPU>; 277 clocks = <&cru SCLK_GPU>; 278 pm_qos = <&qos_gpu>; 279 }; 280 }; 281 }; 282 283 pmugrf: syscon@ff010000 { 284 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; 285 reg = <0x0 0xff010000 0x0 0x1000>; 286 #address-cells = <1>; 287 #size-cells = <1>; 288 289 pmu_io_domains: io-domains { 290 compatible = "rockchip,px30-pmu-io-voltage-domain"; 291 status = "disabled"; 292 }; 293 294 reboot-mode { 295 compatible = "syscon-reboot-mode"; 296 offset = <0x200>; 297 mode-bootloader = <BOOT_BL_DOWNLOAD>; 298 mode-fastboot = <BOOT_FASTBOOT>; 299 mode-loader = <BOOT_BL_DOWNLOAD>; 300 mode-normal = <BOOT_NORMAL>; 301 mode-recovery = <BOOT_RECOVERY>; 302 }; 303 }; 304 305 uart0: serial@ff030000 { 306 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 307 reg = <0x0 0xff030000 0x0 0x100>; 308 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 309 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>; 310 clock-names = "baudclk", "apb_pclk"; 311 dmas = <&dmac 0>, <&dmac 1>; 312 dma-names = "tx", "rx"; 313 reg-shift = <2>; 314 reg-io-width = <4>; 315 pinctrl-names = "default"; 316 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 317 status = "disabled"; 318 }; 319 320 i2s1_2ch: i2s@ff070000 { 321 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 322 reg = <0x0 0xff070000 0x0 0x1000>; 323 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 325 clock-names = "i2s_clk", "i2s_hclk"; 326 dmas = <&dmac 18>, <&dmac 19>; 327 dma-names = "tx", "rx"; 328 pinctrl-names = "default"; 329 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck 330 &i2s1_2ch_sdi &i2s1_2ch_sdo>; 331 #sound-dai-cells = <0>; 332 status = "disabled"; 333 }; 334 335 i2s2_2ch: i2s@ff080000 { 336 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 337 reg = <0x0 0xff080000 0x0 0x1000>; 338 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 340 clock-names = "i2s_clk", "i2s_hclk"; 341 dmas = <&dmac 20>, <&dmac 21>; 342 dma-names = "tx", "rx"; 343 pinctrl-names = "default"; 344 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck 345 &i2s2_2ch_sdi &i2s2_2ch_sdo>; 346 #sound-dai-cells = <0>; 347 status = "disabled"; 348 }; 349 350 gic: interrupt-controller@ff131000 { 351 compatible = "arm,gic-400"; 352 #interrupt-cells = <3>; 353 #address-cells = <0>; 354 interrupt-controller; 355 reg = <0x0 0xff131000 0 0x1000>, 356 <0x0 0xff132000 0 0x2000>, 357 <0x0 0xff134000 0 0x2000>, 358 <0x0 0xff136000 0 0x2000>; 359 interrupts = <GIC_PPI 9 360 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 361 }; 362 363 grf: syscon@ff140000 { 364 compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; 365 reg = <0x0 0xff140000 0x0 0x1000>; 366 #address-cells = <1>; 367 #size-cells = <1>; 368 369 io_domains: io-domains { 370 compatible = "rockchip,px30-io-voltage-domain"; 371 status = "disabled"; 372 }; 373 }; 374 375 uart1: serial@ff158000 { 376 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 377 reg = <0x0 0xff158000 0x0 0x100>; 378 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 380 clock-names = "baudclk", "apb_pclk"; 381 dmas = <&dmac 2>, <&dmac 3>; 382 dma-names = "tx", "rx"; 383 reg-shift = <2>; 384 reg-io-width = <4>; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 387 status = "disabled"; 388 }; 389 390 uart2: serial@ff160000 { 391 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 392 reg = <0x0 0xff160000 0x0 0x100>; 393 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 395 clock-names = "baudclk", "apb_pclk"; 396 dmas = <&dmac 4>, <&dmac 5>; 397 dma-names = "tx", "rx"; 398 reg-shift = <2>; 399 reg-io-width = <4>; 400 pinctrl-names = "default"; 401 pinctrl-0 = <&uart2m0_xfer>; 402 status = "disabled"; 403 }; 404 405 uart3: serial@ff168000 { 406 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 407 reg = <0x0 0xff168000 0x0 0x100>; 408 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 410 clock-names = "baudclk", "apb_pclk"; 411 dmas = <&dmac 6>, <&dmac 7>; 412 dma-names = "tx", "rx"; 413 reg-shift = <2>; 414 reg-io-width = <4>; 415 pinctrl-names = "default"; 416 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; 417 status = "disabled"; 418 }; 419 420 uart4: serial@ff170000 { 421 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 422 reg = <0x0 0xff170000 0x0 0x100>; 423 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 424 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 425 clock-names = "baudclk", "apb_pclk"; 426 dmas = <&dmac 8>, <&dmac 9>; 427 dma-names = "tx", "rx"; 428 reg-shift = <2>; 429 reg-io-width = <4>; 430 pinctrl-names = "default"; 431 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 432 status = "disabled"; 433 }; 434 435 uart5: serial@ff178000 { 436 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 437 reg = <0x0 0xff178000 0x0 0x100>; 438 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 440 clock-names = "baudclk", "apb_pclk"; 441 dmas = <&dmac 10>, <&dmac 11>; 442 dma-names = "tx", "rx"; 443 reg-shift = <2>; 444 reg-io-width = <4>; 445 pinctrl-names = "default"; 446 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; 447 status = "disabled"; 448 }; 449 450 i2c0: i2c@ff180000 { 451 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 452 reg = <0x0 0xff180000 0x0 0x1000>; 453 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 454 clock-names = "i2c", "pclk"; 455 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 456 pinctrl-names = "default"; 457 pinctrl-0 = <&i2c0_xfer>; 458 #address-cells = <1>; 459 #size-cells = <0>; 460 status = "disabled"; 461 }; 462 463 i2c1: i2c@ff190000 { 464 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 465 reg = <0x0 0xff190000 0x0 0x1000>; 466 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 467 clock-names = "i2c", "pclk"; 468 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 469 pinctrl-names = "default"; 470 pinctrl-0 = <&i2c1_xfer>; 471 #address-cells = <1>; 472 #size-cells = <0>; 473 status = "disabled"; 474 }; 475 476 i2c2: i2c@ff1a0000 { 477 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 478 reg = <0x0 0xff1a0000 0x0 0x1000>; 479 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 480 clock-names = "i2c", "pclk"; 481 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 482 pinctrl-names = "default"; 483 pinctrl-0 = <&i2c2_xfer>; 484 #address-cells = <1>; 485 #size-cells = <0>; 486 status = "disabled"; 487 }; 488 489 i2c3: i2c@ff1b0000 { 490 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 491 reg = <0x0 0xff1b0000 0x0 0x1000>; 492 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 493 clock-names = "i2c", "pclk"; 494 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 495 pinctrl-names = "default"; 496 pinctrl-0 = <&i2c3_xfer>; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 status = "disabled"; 500 }; 501 502 spi0: spi@ff1d0000 { 503 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 504 reg = <0x0 0xff1d0000 0x0 0x1000>; 505 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 507 clock-names = "spiclk", "apb_pclk"; 508 dmas = <&dmac 12>, <&dmac 13>; 509 dma-names = "tx", "rx"; 510 pinctrl-names = "default"; 511 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 512 #address-cells = <1>; 513 #size-cells = <0>; 514 status = "disabled"; 515 }; 516 517 spi1: spi@ff1d8000 { 518 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 519 reg = <0x0 0xff1d8000 0x0 0x1000>; 520 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 522 clock-names = "spiclk", "apb_pclk"; 523 dmas = <&dmac 14>, <&dmac 15>; 524 dma-names = "tx", "rx"; 525 pinctrl-names = "default"; 526 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; 527 #address-cells = <1>; 528 #size-cells = <0>; 529 status = "disabled"; 530 }; 531 532 wdt: watchdog@ff1e0000 { 533 compatible = "snps,dw-wdt"; 534 reg = <0x0 0xff1e0000 0x0 0x100>; 535 clocks = <&cru PCLK_WDT_NS>; 536 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 537 status = "disabled"; 538 }; 539 540 pwm0: pwm@ff200000 { 541 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 542 reg = <0x0 0xff200000 0x0 0x10>; 543 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 544 clock-names = "pwm", "pclk"; 545 pinctrl-names = "default"; 546 pinctrl-0 = <&pwm0_pin>; 547 #pwm-cells = <3>; 548 status = "disabled"; 549 }; 550 551 pwm1: pwm@ff200010 { 552 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 553 reg = <0x0 0xff200010 0x0 0x10>; 554 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 555 clock-names = "pwm", "pclk"; 556 pinctrl-names = "default"; 557 pinctrl-0 = <&pwm1_pin>; 558 #pwm-cells = <3>; 559 status = "disabled"; 560 }; 561 562 pwm2: pwm@ff200020 { 563 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 564 reg = <0x0 0xff200020 0x0 0x10>; 565 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 566 clock-names = "pwm", "pclk"; 567 pinctrl-names = "default"; 568 pinctrl-0 = <&pwm2_pin>; 569 #pwm-cells = <3>; 570 status = "disabled"; 571 }; 572 573 pwm3: pwm@ff200030 { 574 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 575 reg = <0x0 0xff200030 0x0 0x10>; 576 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 577 clock-names = "pwm", "pclk"; 578 pinctrl-names = "default"; 579 pinctrl-0 = <&pwm3_pin>; 580 #pwm-cells = <3>; 581 status = "disabled"; 582 }; 583 584 pwm4: pwm@ff208000 { 585 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 586 reg = <0x0 0xff208000 0x0 0x10>; 587 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 588 clock-names = "pwm", "pclk"; 589 pinctrl-names = "default"; 590 pinctrl-0 = <&pwm4_pin>; 591 #pwm-cells = <3>; 592 status = "disabled"; 593 }; 594 595 pwm5: pwm@ff208010 { 596 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 597 reg = <0x0 0xff208010 0x0 0x10>; 598 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 599 clock-names = "pwm", "pclk"; 600 pinctrl-names = "default"; 601 pinctrl-0 = <&pwm5_pin>; 602 #pwm-cells = <3>; 603 status = "disabled"; 604 }; 605 606 pwm6: pwm@ff208020 { 607 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 608 reg = <0x0 0xff208020 0x0 0x10>; 609 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 610 clock-names = "pwm", "pclk"; 611 pinctrl-names = "default"; 612 pinctrl-0 = <&pwm6_pin>; 613 #pwm-cells = <3>; 614 status = "disabled"; 615 }; 616 617 pwm7: pwm@ff208030 { 618 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 619 reg = <0x0 0xff208030 0x0 0x10>; 620 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 621 clock-names = "pwm", "pclk"; 622 pinctrl-names = "default"; 623 pinctrl-0 = <&pwm7_pin>; 624 #pwm-cells = <3>; 625 status = "disabled"; 626 }; 627 628 rktimer: timer@ff210000 { 629 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer"; 630 reg = <0x0 0xff210000 0x0 0x1000>; 631 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 633 clock-names = "pclk", "timer"; 634 }; 635 636 amba { 637 compatible = "simple-bus"; 638 #address-cells = <2>; 639 #size-cells = <2>; 640 ranges; 641 642 dmac: dmac@ff240000 { 643 compatible = "arm,pl330", "arm,primecell"; 644 reg = <0x0 0xff240000 0x0 0x4000>; 645 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 647 clocks = <&cru ACLK_DMAC>; 648 clock-names = "apb_pclk"; 649 #dma-cells = <1>; 650 }; 651 }; 652 653 saradc: saradc@ff288000 { 654 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; 655 reg = <0x0 0xff288000 0x0 0x100>; 656 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 657 #io-channel-cells = <1>; 658 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 659 clock-names = "saradc", "apb_pclk"; 660 resets = <&cru SRST_SARADC_P>; 661 reset-names = "saradc-apb"; 662 status = "disabled"; 663 }; 664 665 otp: nvmem@ff290000 { 666 compatible = "rockchip,px30-otp"; 667 reg = <0x0 0xff290000 0x0 0x4000>; 668 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, 669 <&cru PCLK_OTP_PHY>; 670 clock-names = "otp", "apb_pclk", "phy"; 671 resets = <&cru SRST_OTP_PHY>; 672 reset-names = "phy"; 673 #address-cells = <1>; 674 #size-cells = <1>; 675 676 /* Data cells */ 677 cpu_id: id@7 { 678 reg = <0x07 0x10>; 679 }; 680 cpu_leakage: cpu-leakage@17 { 681 reg = <0x17 0x1>; 682 }; 683 performance: performance@1e { 684 reg = <0x1e 0x1>; 685 bits = <4 3>; 686 }; 687 }; 688 689 cru: clock-controller@ff2b0000 { 690 compatible = "rockchip,px30-cru"; 691 reg = <0x0 0xff2b0000 0x0 0x1000>; 692 clocks = <&xin24m>, <&pmucru PLL_GPLL>; 693 clock-names = "xin24m", "gpll"; 694 rockchip,grf = <&grf>; 695 #clock-cells = <1>; 696 #reset-cells = <1>; 697 }; 698 699 pmucru: clock-controller@ff2bc000 { 700 compatible = "rockchip,px30-pmucru"; 701 reg = <0x0 0xff2bc000 0x0 0x1000>; 702 clocks = <&xin24m>; 703 clock-names = "xin24m"; 704 rockchip,grf = <&grf>; 705 #clock-cells = <1>; 706 #reset-cells = <1>; 707 }; 708 709 dsi_dphy: phy@ff2e0000 { 710 compatible = "rockchip,px30-dsi-dphy"; 711 reg = <0x0 0xff2e0000 0x0 0x10000>; 712 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; 713 clock-names = "ref", "pclk"; 714 #clock-cells = <0>; 715 resets = <&cru SRST_MIPIDSIPHY_P>; 716 reset-names = "apb"; 717 #phy-cells = <0>; 718 power-domains = <&power PX30_PD_VO>; 719 status = "disabled"; 720 }; 721 722 usb20_otg: usb@ff300000 { 723 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", 724 "snps,dwc2"; 725 reg = <0x0 0xff300000 0x0 0x40000>; 726 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&cru HCLK_OTG>; 728 clock-names = "otg"; 729 dr_mode = "otg"; 730 g-np-tx-fifo-size = <16>; 731 g-rx-fifo-size = <280>; 732 g-tx-fifo-size = <256 128 128 64 32 16>; 733 g-use-dma; 734 power-domains = <&power PX30_PD_USB>; 735 status = "disabled"; 736 }; 737 738 usb_host0_ehci: usb@ff340000 { 739 compatible = "generic-ehci"; 740 reg = <0x0 0xff340000 0x0 0x10000>; 741 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 742 clocks = <&cru HCLK_HOST>; 743 clock-names = "usbhost"; 744 power-domains = <&power PX30_PD_USB>; 745 status = "disabled"; 746 }; 747 748 usb_host0_ohci: usb@ff350000 { 749 compatible = "generic-ohci"; 750 reg = <0x0 0xff350000 0x0 0x10000>; 751 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 752 clocks = <&cru HCLK_HOST>; 753 clock-names = "usbhost"; 754 power-domains = <&power PX30_PD_USB>; 755 status = "disabled"; 756 }; 757 758 gmac: ethernet@ff360000 { 759 compatible = "rockchip,px30-gmac"; 760 reg = <0x0 0xff360000 0x0 0x10000>; 761 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 762 interrupt-names = "macirq"; 763 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 764 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, 765 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 766 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; 767 clock-names = "stmmaceth", "mac_clk_rx", 768 "mac_clk_tx", "clk_mac_ref", 769 "clk_mac_refout", "aclk_mac", 770 "pclk_mac", "clk_mac_speed"; 771 rockchip,grf = <&grf>; 772 phy-mode = "rmii"; 773 pinctrl-names = "default"; 774 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 775 power-domains = <&power PX30_PD_GMAC>; 776 resets = <&cru SRST_GMAC_A>; 777 reset-names = "stmmaceth"; 778 status = "disabled"; 779 }; 780 781 sdmmc: dwmmc@ff370000 { 782 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 783 reg = <0x0 0xff370000 0x0 0x4000>; 784 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 785 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 786 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 787 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 788 fifo-depth = <0x100>; 789 max-frequency = <150000000>; 790 pinctrl-names = "default"; 791 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 792 power-domains = <&power PX30_PD_SDCARD>; 793 status = "disabled"; 794 }; 795 796 sdio: dwmmc@ff380000 { 797 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 798 reg = <0x0 0xff380000 0x0 0x4000>; 799 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 800 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 801 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 802 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 803 fifo-depth = <0x100>; 804 max-frequency = <150000000>; 805 pinctrl-names = "default"; 806 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 807 power-domains = <&power PX30_PD_MMC_NAND>; 808 status = "disabled"; 809 }; 810 811 emmc: dwmmc@ff390000 { 812 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 813 reg = <0x0 0xff390000 0x0 0x4000>; 814 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 815 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 816 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 817 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 818 fifo-depth = <0x100>; 819 max-frequency = <150000000>; 820 pinctrl-names = "default"; 821 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 822 power-domains = <&power PX30_PD_MMC_NAND>; 823 status = "disabled"; 824 }; 825 826 dsi: dsi@ff450000 { 827 compatible = "rockchip,px30-mipi-dsi"; 828 reg = <0x0 0xff450000 0x0 0x10000>; 829 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 830 clocks = <&cru PCLK_MIPI_DSI>, <&dsi_dphy>; 831 clock-names = "pclk", "pll"; 832 resets = <&cru SRST_MIPIDSI_HOST_P>; 833 reset-names = "apb"; 834 phys = <&dsi_dphy>; 835 phy-names = "dphy"; 836 power-domains = <&power PX30_PD_VO>; 837 rockchip,grf = <&grf>; 838 #address-cells = <1>; 839 #size-cells = <0>; 840 status = "disabled"; 841 842 ports { 843 #address-cells = <1>; 844 #size-cells = <0>; 845 846 port@0 { 847 reg = <0>; 848 #address-cells = <1>; 849 #size-cells = <0>; 850 851 dsi_in_vopb: endpoint@0 { 852 reg = <0>; 853 remote-endpoint = <&vopb_out_dsi>; 854 }; 855 856 dsi_in_vopl: endpoint@1 { 857 reg = <1>; 858 remote-endpoint = <&vopl_out_dsi>; 859 }; 860 }; 861 }; 862 }; 863 864 vopb: vop@ff460000 { 865 compatible = "rockchip,px30-vop-big"; 866 reg = <0x0 0xff460000 0x0 0xefc>; 867 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 868 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, 869 <&cru HCLK_VOPB>; 870 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 871 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>; 872 reset-names = "axi", "ahb", "dclk"; 873 iommus = <&vopb_mmu>; 874 power-domains = <&power PX30_PD_VO>; 875 rockchip,grf = <&grf>; 876 status = "disabled"; 877 878 vopb_out: port { 879 #address-cells = <1>; 880 #size-cells = <0>; 881 882 vopb_out_dsi: endpoint@0 { 883 reg = <0>; 884 remote-endpoint = <&dsi_in_vopb>; 885 }; 886 }; 887 }; 888 889 vopb_mmu: iommu@ff460f00 { 890 compatible = "rockchip,iommu"; 891 reg = <0x0 0xff460f00 0x0 0x100>; 892 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 893 interrupt-names = "vopb_mmu"; 894 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; 895 clock-names = "aclk", "iface"; 896 power-domains = <&power PX30_PD_VO>; 897 #iommu-cells = <0>; 898 status = "disabled"; 899 }; 900 901 vopl: vop@ff470000 { 902 compatible = "rockchip,px30-vop-lit"; 903 reg = <0x0 0xff470000 0x0 0xefc>; 904 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 905 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, 906 <&cru HCLK_VOPL>; 907 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 908 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>; 909 reset-names = "axi", "ahb", "dclk"; 910 iommus = <&vopl_mmu>; 911 power-domains = <&power PX30_PD_VO>; 912 rockchip,grf = <&grf>; 913 status = "disabled"; 914 915 vopl_out: port { 916 #address-cells = <1>; 917 #size-cells = <0>; 918 919 vopl_out_dsi: endpoint@0 { 920 reg = <0>; 921 remote-endpoint = <&dsi_in_vopl>; 922 }; 923 }; 924 }; 925 926 vopl_mmu: iommu@ff470f00 { 927 compatible = "rockchip,iommu"; 928 reg = <0x0 0xff470f00 0x0 0x100>; 929 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 930 interrupt-names = "vopl_mmu"; 931 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; 932 clock-names = "aclk", "iface"; 933 power-domains = <&power PX30_PD_VO>; 934 #iommu-cells = <0>; 935 status = "disabled"; 936 }; 937 938 qos_gmac: qos@ff518000 { 939 compatible = "syscon"; 940 reg = <0x0 0xff518000 0x0 0x20>; 941 }; 942 943 qos_gpu: qos@ff520000 { 944 compatible = "syscon"; 945 reg = <0x0 0xff520000 0x0 0x20>; 946 }; 947 948 qos_sdmmc: qos@ff52c000 { 949 compatible = "syscon"; 950 reg = <0x0 0xff52c000 0x0 0x20>; 951 }; 952 953 qos_emmc: qos@ff538000 { 954 compatible = "syscon"; 955 reg = <0x0 0xff538000 0x0 0x20>; 956 }; 957 958 qos_nand: qos@ff538080 { 959 compatible = "syscon"; 960 reg = <0x0 0xff538080 0x0 0x20>; 961 }; 962 963 qos_sdio: qos@ff538100 { 964 compatible = "syscon"; 965 reg = <0x0 0xff538100 0x0 0x20>; 966 }; 967 968 qos_sfc: qos@ff538180 { 969 compatible = "syscon"; 970 reg = <0x0 0xff538180 0x0 0x20>; 971 }; 972 973 qos_usb_host: qos@ff540000 { 974 compatible = "syscon"; 975 reg = <0x0 0xff540000 0x0 0x20>; 976 }; 977 978 qos_usb_otg: qos@ff540080 { 979 compatible = "syscon"; 980 reg = <0x0 0xff540080 0x0 0x20>; 981 }; 982 983 qos_isp_128: qos@ff548000 { 984 compatible = "syscon"; 985 reg = <0x0 0xff548000 0x0 0x20>; 986 }; 987 988 qos_isp_rd: qos@ff548080 { 989 compatible = "syscon"; 990 reg = <0x0 0xff548080 0x0 0x20>; 991 }; 992 993 qos_isp_wr: qos@ff548100 { 994 compatible = "syscon"; 995 reg = <0x0 0xff548100 0x0 0x20>; 996 }; 997 998 qos_isp_m1: qos@ff548180 { 999 compatible = "syscon"; 1000 reg = <0x0 0xff548180 0x0 0x20>; 1001 }; 1002 1003 qos_vip: qos@ff548200 { 1004 compatible = "syscon"; 1005 reg = <0x0 0xff548200 0x0 0x20>; 1006 }; 1007 1008 qos_rga_rd: qos@ff550000 { 1009 compatible = "syscon"; 1010 reg = <0x0 0xff550000 0x0 0x20>; 1011 }; 1012 1013 qos_rga_wr: qos@ff550080 { 1014 compatible = "syscon"; 1015 reg = <0x0 0xff550080 0x0 0x20>; 1016 }; 1017 1018 qos_vop_m0: qos@ff550100 { 1019 compatible = "syscon"; 1020 reg = <0x0 0xff550100 0x0 0x20>; 1021 }; 1022 1023 qos_vop_m1: qos@ff550180 { 1024 compatible = "syscon"; 1025 reg = <0x0 0xff550180 0x0 0x20>; 1026 }; 1027 1028 qos_vpu: qos@ff558000 { 1029 compatible = "syscon"; 1030 reg = <0x0 0xff558000 0x0 0x20>; 1031 }; 1032 1033 qos_vpu_r128: qos@ff558080 { 1034 compatible = "syscon"; 1035 reg = <0x0 0xff558080 0x0 0x20>; 1036 }; 1037 1038 pinctrl: pinctrl { 1039 compatible = "rockchip,px30-pinctrl"; 1040 rockchip,grf = <&grf>; 1041 rockchip,pmu = <&pmugrf>; 1042 #address-cells = <2>; 1043 #size-cells = <2>; 1044 ranges; 1045 1046 gpio0: gpio0@ff040000 { 1047 compatible = "rockchip,gpio-bank"; 1048 reg = <0x0 0xff040000 0x0 0x100>; 1049 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1050 clocks = <&pmucru PCLK_GPIO0_PMU>; 1051 gpio-controller; 1052 #gpio-cells = <2>; 1053 1054 interrupt-controller; 1055 #interrupt-cells = <2>; 1056 }; 1057 1058 gpio1: gpio1@ff250000 { 1059 compatible = "rockchip,gpio-bank"; 1060 reg = <0x0 0xff250000 0x0 0x100>; 1061 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1062 clocks = <&cru PCLK_GPIO1>; 1063 gpio-controller; 1064 #gpio-cells = <2>; 1065 1066 interrupt-controller; 1067 #interrupt-cells = <2>; 1068 }; 1069 1070 gpio2: gpio2@ff260000 { 1071 compatible = "rockchip,gpio-bank"; 1072 reg = <0x0 0xff260000 0x0 0x100>; 1073 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1074 clocks = <&cru PCLK_GPIO2>; 1075 gpio-controller; 1076 #gpio-cells = <2>; 1077 1078 interrupt-controller; 1079 #interrupt-cells = <2>; 1080 }; 1081 1082 gpio3: gpio3@ff270000 { 1083 compatible = "rockchip,gpio-bank"; 1084 reg = <0x0 0xff270000 0x0 0x100>; 1085 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1086 clocks = <&cru PCLK_GPIO3>; 1087 gpio-controller; 1088 #gpio-cells = <2>; 1089 1090 interrupt-controller; 1091 #interrupt-cells = <2>; 1092 }; 1093 1094 pcfg_pull_up: pcfg-pull-up { 1095 bias-pull-up; 1096 }; 1097 1098 pcfg_pull_down: pcfg-pull-down { 1099 bias-pull-down; 1100 }; 1101 1102 pcfg_pull_none: pcfg-pull-none { 1103 bias-disable; 1104 }; 1105 1106 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1107 bias-disable; 1108 drive-strength = <2>; 1109 }; 1110 1111 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1112 bias-pull-up; 1113 drive-strength = <2>; 1114 }; 1115 1116 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1117 bias-pull-up; 1118 drive-strength = <4>; 1119 }; 1120 1121 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1122 bias-disable; 1123 drive-strength = <4>; 1124 }; 1125 1126 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1127 bias-pull-down; 1128 drive-strength = <4>; 1129 }; 1130 1131 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1132 bias-disable; 1133 drive-strength = <8>; 1134 }; 1135 1136 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1137 bias-pull-up; 1138 drive-strength = <8>; 1139 }; 1140 1141 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1142 bias-disable; 1143 drive-strength = <12>; 1144 }; 1145 1146 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1147 bias-pull-up; 1148 drive-strength = <12>; 1149 }; 1150 1151 pcfg_pull_none_smt: pcfg-pull-none-smt { 1152 bias-disable; 1153 input-schmitt-enable; 1154 }; 1155 1156 pcfg_output_high: pcfg-output-high { 1157 output-high; 1158 }; 1159 1160 pcfg_output_low: pcfg-output-low { 1161 output-low; 1162 }; 1163 1164 pcfg_input_high: pcfg-input-high { 1165 bias-pull-up; 1166 input-enable; 1167 }; 1168 1169 pcfg_input: pcfg-input { 1170 input-enable; 1171 }; 1172 1173 i2c0 { 1174 i2c0_xfer: i2c0-xfer { 1175 rockchip,pins = 1176 <0 RK_PB0 1 &pcfg_pull_none_smt>, 1177 <0 RK_PB1 1 &pcfg_pull_none_smt>; 1178 }; 1179 }; 1180 1181 i2c1 { 1182 i2c1_xfer: i2c1-xfer { 1183 rockchip,pins = 1184 <0 RK_PC2 1 &pcfg_pull_none_smt>, 1185 <0 RK_PC3 1 &pcfg_pull_none_smt>; 1186 }; 1187 }; 1188 1189 i2c2 { 1190 i2c2_xfer: i2c2-xfer { 1191 rockchip,pins = 1192 <2 RK_PB7 2 &pcfg_pull_none_smt>, 1193 <2 RK_PC0 2 &pcfg_pull_none_smt>; 1194 }; 1195 }; 1196 1197 i2c3 { 1198 i2c3_xfer: i2c3-xfer { 1199 rockchip,pins = 1200 <1 RK_PB4 4 &pcfg_pull_none_smt>, 1201 <1 RK_PB5 4 &pcfg_pull_none_smt>; 1202 }; 1203 }; 1204 1205 tsadc { 1206 tsadc_otp_gpio: tsadc-otp-gpio { 1207 rockchip,pins = 1208 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1209 }; 1210 1211 tsadc_otp_out: tsadc-otp-out { 1212 rockchip,pins = 1213 <0 RK_PA6 1 &pcfg_pull_none>; 1214 }; 1215 }; 1216 1217 uart0 { 1218 uart0_xfer: uart0-xfer { 1219 rockchip,pins = 1220 <0 RK_PB2 1 &pcfg_pull_up>, 1221 <0 RK_PB3 1 &pcfg_pull_up>; 1222 }; 1223 1224 uart0_cts: uart0-cts { 1225 rockchip,pins = 1226 <0 RK_PB4 1 &pcfg_pull_none>; 1227 }; 1228 1229 uart0_rts: uart0-rts { 1230 rockchip,pins = 1231 <0 RK_PB5 1 &pcfg_pull_none>; 1232 }; 1233 }; 1234 1235 uart1 { 1236 uart1_xfer: uart1-xfer { 1237 rockchip,pins = 1238 <1 RK_PC1 1 &pcfg_pull_up>, 1239 <1 RK_PC0 1 &pcfg_pull_up>; 1240 }; 1241 1242 uart1_cts: uart1-cts { 1243 rockchip,pins = 1244 <1 RK_PC2 1 &pcfg_pull_none>; 1245 }; 1246 1247 uart1_rts: uart1-rts { 1248 rockchip,pins = 1249 <1 RK_PC3 1 &pcfg_pull_none>; 1250 }; 1251 }; 1252 1253 uart2-m0 { 1254 uart2m0_xfer: uart2m0-xfer { 1255 rockchip,pins = 1256 <1 RK_PD2 2 &pcfg_pull_up>, 1257 <1 RK_PD3 2 &pcfg_pull_up>; 1258 }; 1259 }; 1260 1261 uart2-m1 { 1262 uart2m1_xfer: uart2m1-xfer { 1263 rockchip,pins = 1264 <2 RK_PB4 2 &pcfg_pull_up>, 1265 <2 RK_PB6 2 &pcfg_pull_up>; 1266 }; 1267 }; 1268 1269 uart3-m0 { 1270 uart3m0_xfer: uart3m0-xfer { 1271 rockchip,pins = 1272 <0 RK_PC0 2 &pcfg_pull_up>, 1273 <0 RK_PC1 2 &pcfg_pull_up>; 1274 }; 1275 1276 uart3m0_cts: uart3m0-cts { 1277 rockchip,pins = 1278 <0 RK_PC2 2 &pcfg_pull_none>; 1279 }; 1280 1281 uart3m0_rts: uart3m0-rts { 1282 rockchip,pins = 1283 <0 RK_PC3 2 &pcfg_pull_none>; 1284 }; 1285 }; 1286 1287 uart3-m1 { 1288 uart3m1_xfer: uart3m1-xfer { 1289 rockchip,pins = 1290 <1 RK_PB6 2 &pcfg_pull_up>, 1291 <1 RK_PB7 2 &pcfg_pull_up>; 1292 }; 1293 1294 uart3m1_cts: uart3m1-cts { 1295 rockchip,pins = 1296 <1 RK_PB4 2 &pcfg_pull_none>; 1297 }; 1298 1299 uart3m1_rts: uart3m1-rts { 1300 rockchip,pins = 1301 <1 RK_PB5 2 &pcfg_pull_none>; 1302 }; 1303 }; 1304 1305 uart4 { 1306 uart4_xfer: uart4-xfer { 1307 rockchip,pins = 1308 <1 RK_PD4 2 &pcfg_pull_up>, 1309 <1 RK_PD5 2 &pcfg_pull_up>; 1310 }; 1311 1312 uart4_cts: uart4-cts { 1313 rockchip,pins = 1314 <1 RK_PD6 2 &pcfg_pull_none>; 1315 }; 1316 1317 uart4_rts: uart4-rts { 1318 rockchip,pins = 1319 <1 RK_PD7 2 &pcfg_pull_none>; 1320 }; 1321 }; 1322 1323 uart5 { 1324 uart5_xfer: uart5-xfer { 1325 rockchip,pins = 1326 <3 RK_PA2 4 &pcfg_pull_up>, 1327 <3 RK_PA1 4 &pcfg_pull_up>; 1328 }; 1329 1330 uart5_cts: uart5-cts { 1331 rockchip,pins = 1332 <3 RK_PA3 4 &pcfg_pull_none>; 1333 }; 1334 1335 uart5_rts: uart5-rts { 1336 rockchip,pins = 1337 <3 RK_PA5 4 &pcfg_pull_none>; 1338 }; 1339 }; 1340 1341 spi0 { 1342 spi0_clk: spi0-clk { 1343 rockchip,pins = 1344 <1 RK_PB7 3 &pcfg_pull_up_4ma>; 1345 }; 1346 1347 spi0_csn: spi0-csn { 1348 rockchip,pins = 1349 <1 RK_PB6 3 &pcfg_pull_up_4ma>; 1350 }; 1351 1352 spi0_miso: spi0-miso { 1353 rockchip,pins = 1354 <1 RK_PB5 3 &pcfg_pull_up_4ma>; 1355 }; 1356 1357 spi0_mosi: spi0-mosi { 1358 rockchip,pins = 1359 <1 RK_PB4 3 &pcfg_pull_up_4ma>; 1360 }; 1361 1362 spi0_clk_hs: spi0-clk-hs { 1363 rockchip,pins = 1364 <1 RK_PB7 3 &pcfg_pull_up_8ma>; 1365 }; 1366 1367 spi0_miso_hs: spi0-miso-hs { 1368 rockchip,pins = 1369 <1 RK_PB5 3 &pcfg_pull_up_8ma>; 1370 }; 1371 1372 spi0_mosi_hs: spi0-mosi-hs { 1373 rockchip,pins = 1374 <1 RK_PB4 3 &pcfg_pull_up_8ma>; 1375 }; 1376 }; 1377 1378 spi1 { 1379 spi1_clk: spi1-clk { 1380 rockchip,pins = 1381 <3 RK_PB7 4 &pcfg_pull_up_4ma>; 1382 }; 1383 1384 spi1_csn0: spi1-csn0 { 1385 rockchip,pins = 1386 <3 RK_PB1 4 &pcfg_pull_up_4ma>; 1387 }; 1388 1389 spi1_csn1: spi1-csn1 { 1390 rockchip,pins = 1391 <3 RK_PB2 2 &pcfg_pull_up_4ma>; 1392 }; 1393 1394 spi1_miso: spi1-miso { 1395 rockchip,pins = 1396 <3 RK_PB6 4 &pcfg_pull_up_4ma>; 1397 }; 1398 1399 spi1_mosi: spi1-mosi { 1400 rockchip,pins = 1401 <3 RK_PB4 4 &pcfg_pull_up_4ma>; 1402 }; 1403 1404 spi1_clk_hs: spi1-clk-hs { 1405 rockchip,pins = 1406 <3 RK_PB7 4 &pcfg_pull_up_8ma>; 1407 }; 1408 1409 spi1_miso_hs: spi1-miso-hs { 1410 rockchip,pins = 1411 <3 RK_PB6 4 &pcfg_pull_up_8ma>; 1412 }; 1413 1414 spi1_mosi_hs: spi1-mosi-hs { 1415 rockchip,pins = 1416 <3 RK_PB4 4 &pcfg_pull_up_8ma>; 1417 }; 1418 }; 1419 1420 pdm { 1421 pdm_clk0m0: pdm-clk0m0 { 1422 rockchip,pins = 1423 <3 RK_PC6 2 &pcfg_pull_none>; 1424 }; 1425 1426 pdm_clk0m1: pdm-clk0m1 { 1427 rockchip,pins = 1428 <2 RK_PC6 1 &pcfg_pull_none>; 1429 }; 1430 1431 pdm_clk1: pdm-clk1 { 1432 rockchip,pins = 1433 <3 RK_PC7 2 &pcfg_pull_none>; 1434 }; 1435 1436 pdm_sdi0m0: pdm-sdi0m0 { 1437 rockchip,pins = 1438 <3 RK_PD3 2 &pcfg_pull_none>; 1439 }; 1440 1441 pdm_sdi0m1: pdm-sdi0m1 { 1442 rockchip,pins = 1443 <2 RK_PC5 2 &pcfg_pull_none>; 1444 }; 1445 1446 pdm_sdi1: pdm-sdi1 { 1447 rockchip,pins = 1448 <3 RK_PD0 2 &pcfg_pull_none>; 1449 }; 1450 1451 pdm_sdi2: pdm-sdi2 { 1452 rockchip,pins = 1453 <3 RK_PD1 2 &pcfg_pull_none>; 1454 }; 1455 1456 pdm_sdi3: pdm-sdi3 { 1457 rockchip,pins = 1458 <3 RK_PD2 2 &pcfg_pull_none>; 1459 }; 1460 1461 pdm_clk0m0_sleep: pdm-clk0m0-sleep { 1462 rockchip,pins = 1463 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1464 }; 1465 1466 pdm_clk0m_sleep1: pdm-clk0m1-sleep { 1467 rockchip,pins = 1468 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1469 }; 1470 1471 pdm_clk1_sleep: pdm-clk1-sleep { 1472 rockchip,pins = 1473 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1474 }; 1475 1476 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { 1477 rockchip,pins = 1478 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; 1479 }; 1480 1481 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { 1482 rockchip,pins = 1483 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1484 }; 1485 1486 pdm_sdi1_sleep: pdm-sdi1-sleep { 1487 rockchip,pins = 1488 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; 1489 }; 1490 1491 pdm_sdi2_sleep: pdm-sdi2-sleep { 1492 rockchip,pins = 1493 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1494 }; 1495 1496 pdm_sdi3_sleep: pdm-sdi3-sleep { 1497 rockchip,pins = 1498 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; 1499 }; 1500 }; 1501 1502 i2s0 { 1503 i2s0_8ch_mclk: i2s0-8ch-mclk { 1504 rockchip,pins = 1505 <3 RK_PC1 2 &pcfg_pull_none>; 1506 }; 1507 1508 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 1509 rockchip,pins = 1510 <3 RK_PC3 2 &pcfg_pull_none>; 1511 }; 1512 1513 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 1514 rockchip,pins = 1515 <3 RK_PB4 2 &pcfg_pull_none>; 1516 }; 1517 1518 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 1519 rockchip,pins = 1520 <3 RK_PC2 2 &pcfg_pull_none>; 1521 }; 1522 1523 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 1524 rockchip,pins = 1525 <3 RK_PB5 2 &pcfg_pull_none>; 1526 }; 1527 1528 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 1529 rockchip,pins = 1530 <3 RK_PC4 2 &pcfg_pull_none>; 1531 }; 1532 1533 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 1534 rockchip,pins = 1535 <3 RK_PC0 2 &pcfg_pull_none>; 1536 }; 1537 1538 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 1539 rockchip,pins = 1540 <3 RK_PB7 2 &pcfg_pull_none>; 1541 }; 1542 1543 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 1544 rockchip,pins = 1545 <3 RK_PB6 2 &pcfg_pull_none>; 1546 }; 1547 1548 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 1549 rockchip,pins = 1550 <3 RK_PC5 2 &pcfg_pull_none>; 1551 }; 1552 1553 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 1554 rockchip,pins = 1555 <3 RK_PB3 2 &pcfg_pull_none>; 1556 }; 1557 1558 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 1559 rockchip,pins = 1560 <3 RK_PB1 2 &pcfg_pull_none>; 1561 }; 1562 1563 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 1564 rockchip,pins = 1565 <3 RK_PB0 2 &pcfg_pull_none>; 1566 }; 1567 }; 1568 1569 i2s1 { 1570 i2s1_2ch_mclk: i2s1-2ch-mclk { 1571 rockchip,pins = 1572 <2 RK_PC3 1 &pcfg_pull_none>; 1573 }; 1574 1575 i2s1_2ch_sclk: i2s1-2ch-sclk { 1576 rockchip,pins = 1577 <2 RK_PC2 1 &pcfg_pull_none>; 1578 }; 1579 1580 i2s1_2ch_lrck: i2s1-2ch-lrck { 1581 rockchip,pins = 1582 <2 RK_PC1 1 &pcfg_pull_none>; 1583 }; 1584 1585 i2s1_2ch_sdi: i2s1-2ch-sdi { 1586 rockchip,pins = 1587 <2 RK_PC5 1 &pcfg_pull_none>; 1588 }; 1589 1590 i2s1_2ch_sdo: i2s1-2ch-sdo { 1591 rockchip,pins = 1592 <2 RK_PC4 1 &pcfg_pull_none>; 1593 }; 1594 }; 1595 1596 i2s2 { 1597 i2s2_2ch_mclk: i2s2-2ch-mclk { 1598 rockchip,pins = 1599 <3 RK_PA1 2 &pcfg_pull_none>; 1600 }; 1601 1602 i2s2_2ch_sclk: i2s2-2ch-sclk { 1603 rockchip,pins = 1604 <3 RK_PA2 2 &pcfg_pull_none>; 1605 }; 1606 1607 i2s2_2ch_lrck: i2s2-2ch-lrck { 1608 rockchip,pins = 1609 <3 RK_PA3 2 &pcfg_pull_none>; 1610 }; 1611 1612 i2s2_2ch_sdi: i2s2-2ch-sdi { 1613 rockchip,pins = 1614 <3 RK_PA5 2 &pcfg_pull_none>; 1615 }; 1616 1617 i2s2_2ch_sdo: i2s2-2ch-sdo { 1618 rockchip,pins = 1619 <3 RK_PA7 2 &pcfg_pull_none>; 1620 }; 1621 }; 1622 1623 sdmmc { 1624 sdmmc_clk: sdmmc-clk { 1625 rockchip,pins = 1626 <1 RK_PD6 1 &pcfg_pull_none_8ma>; 1627 }; 1628 1629 sdmmc_cmd: sdmmc-cmd { 1630 rockchip,pins = 1631 <1 RK_PD7 1 &pcfg_pull_up_8ma>; 1632 }; 1633 1634 sdmmc_det: sdmmc-det { 1635 rockchip,pins = 1636 <0 RK_PA3 1 &pcfg_pull_up_8ma>; 1637 }; 1638 1639 sdmmc_bus1: sdmmc-bus1 { 1640 rockchip,pins = 1641 <1 RK_PD2 1 &pcfg_pull_up_8ma>; 1642 }; 1643 1644 sdmmc_bus4: sdmmc-bus4 { 1645 rockchip,pins = 1646 <1 RK_PD2 1 &pcfg_pull_up_8ma>, 1647 <1 RK_PD3 1 &pcfg_pull_up_8ma>, 1648 <1 RK_PD4 1 &pcfg_pull_up_8ma>, 1649 <1 RK_PD5 1 &pcfg_pull_up_8ma>; 1650 }; 1651 }; 1652 1653 sdio { 1654 sdio_clk: sdio-clk { 1655 rockchip,pins = 1656 <1 RK_PC5 1 &pcfg_pull_none>; 1657 }; 1658 1659 sdio_cmd: sdio-cmd { 1660 rockchip,pins = 1661 <1 RK_PC4 1 &pcfg_pull_up>; 1662 }; 1663 1664 sdio_bus4: sdio-bus4 { 1665 rockchip,pins = 1666 <1 RK_PC6 1 &pcfg_pull_up>, 1667 <1 RK_PC7 1 &pcfg_pull_up>, 1668 <1 RK_PD0 1 &pcfg_pull_up>, 1669 <1 RK_PD1 1 &pcfg_pull_up>; 1670 }; 1671 }; 1672 1673 emmc { 1674 emmc_clk: emmc-clk { 1675 rockchip,pins = 1676 <1 RK_PB1 2 &pcfg_pull_none_8ma>; 1677 }; 1678 1679 emmc_cmd: emmc-cmd { 1680 rockchip,pins = 1681 <1 RK_PB2 2 &pcfg_pull_up_8ma>; 1682 }; 1683 1684 emmc_rstnout: emmc-rstnout { 1685 rockchip,pins = 1686 <1 RK_PB3 2 &pcfg_pull_none>; 1687 }; 1688 1689 emmc_bus1: emmc-bus1 { 1690 rockchip,pins = 1691 <1 RK_PA0 2 &pcfg_pull_up_8ma>; 1692 }; 1693 1694 emmc_bus4: emmc-bus4 { 1695 rockchip,pins = 1696 <1 RK_PA0 2 &pcfg_pull_up_8ma>, 1697 <1 RK_PA1 2 &pcfg_pull_up_8ma>, 1698 <1 RK_PA2 2 &pcfg_pull_up_8ma>, 1699 <1 RK_PA3 2 &pcfg_pull_up_8ma>; 1700 }; 1701 1702 emmc_bus8: emmc-bus8 { 1703 rockchip,pins = 1704 <1 RK_PA0 2 &pcfg_pull_up_8ma>, 1705 <1 RK_PA1 2 &pcfg_pull_up_8ma>, 1706 <1 RK_PA2 2 &pcfg_pull_up_8ma>, 1707 <1 RK_PA3 2 &pcfg_pull_up_8ma>, 1708 <1 RK_PA4 2 &pcfg_pull_up_8ma>, 1709 <1 RK_PA5 2 &pcfg_pull_up_8ma>, 1710 <1 RK_PA6 2 &pcfg_pull_up_8ma>, 1711 <1 RK_PA7 2 &pcfg_pull_up_8ma>; 1712 }; 1713 }; 1714 1715 flash { 1716 flash_cs0: flash-cs0 { 1717 rockchip,pins = 1718 <1 RK_PB0 1 &pcfg_pull_none>; 1719 }; 1720 1721 flash_rdy: flash-rdy { 1722 rockchip,pins = 1723 <1 RK_PB1 1 &pcfg_pull_none>; 1724 }; 1725 1726 flash_dqs: flash-dqs { 1727 rockchip,pins = 1728 <1 RK_PB2 1 &pcfg_pull_none>; 1729 }; 1730 1731 flash_ale: flash-ale { 1732 rockchip,pins = 1733 <1 RK_PB3 1 &pcfg_pull_none>; 1734 }; 1735 1736 flash_cle: flash-cle { 1737 rockchip,pins = 1738 <1 RK_PB4 1 &pcfg_pull_none>; 1739 }; 1740 1741 flash_wrn: flash-wrn { 1742 rockchip,pins = 1743 <1 RK_PB5 1 &pcfg_pull_none>; 1744 }; 1745 1746 flash_csl: flash-csl { 1747 rockchip,pins = 1748 <1 RK_PB6 1 &pcfg_pull_none>; 1749 }; 1750 1751 flash_rdn: flash-rdn { 1752 rockchip,pins = 1753 <1 RK_PB7 1 &pcfg_pull_none>; 1754 }; 1755 1756 flash_bus8: flash-bus8 { 1757 rockchip,pins = 1758 <1 RK_PA0 1 &pcfg_pull_up_12ma>, 1759 <1 RK_PA1 1 &pcfg_pull_up_12ma>, 1760 <1 RK_PA2 1 &pcfg_pull_up_12ma>, 1761 <1 RK_PA3 1 &pcfg_pull_up_12ma>, 1762 <1 RK_PA4 1 &pcfg_pull_up_12ma>, 1763 <1 RK_PA5 1 &pcfg_pull_up_12ma>, 1764 <1 RK_PA6 1 &pcfg_pull_up_12ma>, 1765 <1 RK_PA7 1 &pcfg_pull_up_12ma>; 1766 }; 1767 }; 1768 1769 lcdc { 1770 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { 1771 rockchip,pins = 1772 <3 RK_PA0 1 &pcfg_pull_none_12ma>; 1773 }; 1774 1775 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { 1776 rockchip,pins = 1777 <3 RK_PA1 1 &pcfg_pull_none_12ma>; 1778 }; 1779 1780 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { 1781 rockchip,pins = 1782 <3 RK_PA2 1 &pcfg_pull_none_12ma>; 1783 }; 1784 1785 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin { 1786 rockchip,pins = 1787 <3 RK_PA3 1 &pcfg_pull_none_12ma>; 1788 }; 1789 1790 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins { 1791 rockchip,pins = 1792 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 1793 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 1794 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 1795 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 1796 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 1797 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 1798 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 1799 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 1800 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 1801 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 1802 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 1803 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 1804 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 1805 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 1806 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 1807 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 1808 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 1809 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 1810 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 1811 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 1812 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 1813 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 1814 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 1815 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 1816 }; 1817 1818 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins { 1819 rockchip,pins = 1820 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 1821 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 1822 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 1823 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 1824 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 1825 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 1826 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 1827 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 1828 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 1829 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 1830 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 1831 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 1832 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 1833 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 1834 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 1835 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 1836 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 1837 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 1838 }; 1839 1840 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins { 1841 rockchip,pins = 1842 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 1843 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 1844 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 1845 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 1846 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 1847 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 1848 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 1849 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 1850 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 1851 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 1852 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 1853 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 1854 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 1855 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 1856 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 1857 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 1858 }; 1859 1860 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins { 1861 rockchip,pins = 1862 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 1863 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 1864 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 1865 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 1866 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 1867 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 1868 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 1869 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 1870 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 1871 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 1872 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 1873 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 1874 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 1875 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 1876 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 1877 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 1878 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 1879 }; 1880 1881 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins { 1882 rockchip,pins = 1883 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 1884 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 1885 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 1886 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 1887 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 1888 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 1889 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 1890 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 1891 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 1892 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 1893 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 1894 }; 1895 1896 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins { 1897 rockchip,pins = 1898 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 1899 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 1900 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 1901 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 1902 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 1903 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 1904 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 1905 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 1906 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 1907 }; 1908 }; 1909 1910 pwm0 { 1911 pwm0_pin: pwm0-pin { 1912 rockchip,pins = 1913 <0 RK_PB7 1 &pcfg_pull_none>; 1914 }; 1915 }; 1916 1917 pwm1 { 1918 pwm1_pin: pwm1-pin { 1919 rockchip,pins = 1920 <0 RK_PC0 1 &pcfg_pull_none>; 1921 }; 1922 }; 1923 1924 pwm2 { 1925 pwm2_pin: pwm2-pin { 1926 rockchip,pins = 1927 <2 RK_PB5 1 &pcfg_pull_none>; 1928 }; 1929 }; 1930 1931 pwm3 { 1932 pwm3_pin: pwm3-pin { 1933 rockchip,pins = 1934 <0 RK_PC1 1 &pcfg_pull_none>; 1935 }; 1936 }; 1937 1938 pwm4 { 1939 pwm4_pin: pwm4-pin { 1940 rockchip,pins = 1941 <3 RK_PC2 3 &pcfg_pull_none>; 1942 }; 1943 }; 1944 1945 pwm5 { 1946 pwm5_pin: pwm5-pin { 1947 rockchip,pins = 1948 <3 RK_PC3 3 &pcfg_pull_none>; 1949 }; 1950 }; 1951 1952 pwm6 { 1953 pwm6_pin: pwm6-pin { 1954 rockchip,pins = 1955 <3 RK_PC4 3 &pcfg_pull_none>; 1956 }; 1957 }; 1958 1959 pwm7 { 1960 pwm7_pin: pwm7-pin { 1961 rockchip,pins = 1962 <3 RK_PC5 3 &pcfg_pull_none>; 1963 }; 1964 }; 1965 1966 gmac { 1967 rmii_pins: rmii-pins { 1968 rockchip,pins = 1969 <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */ 1970 <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */ 1971 <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */ 1972 <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */ 1973 <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */ 1974 <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */ 1975 <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */ 1976 <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */ 1977 <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */ 1978 }; 1979 1980 mac_refclk_12ma: mac-refclk-12ma { 1981 rockchip,pins = 1982 <2 RK_PB2 2 &pcfg_pull_none_12ma>; 1983 }; 1984 1985 mac_refclk: mac-refclk { 1986 rockchip,pins = 1987 <2 RK_PB2 2 &pcfg_pull_none>; 1988 }; 1989 }; 1990 1991 cif-m0 { 1992 cif_clkout_m0: cif-clkout-m0 { 1993 rockchip,pins = 1994 <2 RK_PB3 1 &pcfg_pull_none>; 1995 }; 1996 1997 dvp_d2d9_m0: dvp-d2d9-m0 { 1998 rockchip,pins = 1999 <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */ 2000 <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */ 2001 <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */ 2002 <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */ 2003 <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */ 2004 <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */ 2005 <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */ 2006 <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */ 2007 <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */ 2008 <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */ 2009 <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */ 2010 <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */ 2011 }; 2012 2013 dvp_d0d1_m0: dvp-d0d1-m0 { 2014 rockchip,pins = 2015 <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */ 2016 <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */ 2017 }; 2018 2019 dvp_d10d11_m0:d10-d11-m0 { 2020 rockchip,pins = 2021 <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */ 2022 <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */ 2023 }; 2024 }; 2025 2026 cif-m1 { 2027 cif_clkout_m1: cif-clkout-m1 { 2028 rockchip,pins = 2029 <3 RK_PD0 3 &pcfg_pull_none>; 2030 }; 2031 2032 dvp_d2d9_m1: dvp-d2d9-m1 { 2033 rockchip,pins = 2034 <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */ 2035 <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */ 2036 <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */ 2037 <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */ 2038 <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */ 2039 <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */ 2040 <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */ 2041 <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */ 2042 <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */ 2043 <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */ 2044 <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */ 2045 <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */ 2046 }; 2047 2048 dvp_d0d1_m1: dvp-d0d1-m1 { 2049 rockchip,pins = 2050 <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */ 2051 <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */ 2052 }; 2053 2054 dvp_d10d11_m1:d10-d11-m1 { 2055 rockchip,pins = 2056 <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */ 2057 <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */ 2058 }; 2059 }; 2060 2061 isp { 2062 isp_prelight: isp-prelight { 2063 rockchip,pins = 2064 <3 RK_PD1 4 &pcfg_pull_none>; 2065 }; 2066 }; 2067 }; 2068}; 2069