1// SPDX-License-Identifier: GPL-2.0+ OR X11 2/* 3 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH 4 */ 5 6/ { 7 config { 8 u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */ 9 u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */ 10 }; 11 12 chosen { 13 stdout-path = "serial0:115200n8"; 14 u-boot,spl-boot-order = &emmc, &sdmmc; 15 }; 16 17}; 18 19&pinctrl { 20 u-boot,dm-pre-reloc; 21}; 22 23&service_msch { 24 u-boot,dm-pre-reloc; 25}; 26 27&dmc { 28 u-boot,dm-pre-reloc; 29 30 /* 31 * Validation of throughput using SPEC2000 shows the following 32 * relative performance for the different memory schedules: 33 * - CBDR: 30.1 34 * - CBRD: 29.8 35 * - CRBD: 29.9 36 * Note that the best performance for any given application workload 37 * may vary from the default configured here (e.g. 164.gzip is fastest 38 * with CBRD, whereas 252.eon and 186.crafty are fastest with CRBD). 39 * 40 * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for 41 * details on the 'rockchip,memory-schedule' property and how it 42 * affects the physical-address to device-address mapping. 43 */ 44 rockchip,memory-schedule = <DMC_MSCH_CBDR>; 45 rockchip,ddr-frequency = <800000000>; 46 rockchip,ddr-speed-bin = <DDR3_1600K>; 47 48 status = "okay"; 49}; 50 51&pmugrf { 52 u-boot,dm-pre-reloc; 53}; 54 55&sgrf { 56 u-boot,dm-pre-reloc; 57}; 58 59&cru { 60 u-boot,dm-pre-reloc; 61}; 62 63&grf { 64 u-boot,dm-pre-reloc; 65}; 66 67&uart0 { 68 u-boot,dm-pre-reloc; 69}; 70 71&emmc { 72 u-boot,dm-spl; 73}; 74 75&sdmmc { 76 u-boot,dm-spl; 77}; 78 79&spi1 { 80 u-boot,dm-spl; 81 82 spiflash: w25q32dw@0 { 83 u-boot,dm-spl; 84 }; 85}; 86 87&timer0 { 88 u-boot,dm-pre-reloc; 89 clock-frequency = <24000000>; 90 status = "okay"; 91}; 92 93 94