1/* 2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org> 3 * Copyright 2017 Icenowy Zheng <icenowy@aosc.io> 4 * 5 * This file is dual-licensed: you can use it either under the terms 6 * of the GPL or the X11 license, at your option. Note that this dual 7 * licensing only applies to this file, and not this project as a 8 * whole. 9 * 10 * a) This file is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of the 13 * License, or (at your option) any later version. 14 * 15 * This file is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * Or, alternatively, 21 * 22 * b) Permission is hereby granted, free of charge, to any person 23 * obtaining a copy of this software and associated documentation 24 * files (the "Software"), to deal in the Software without 25 * restriction, including without limitation the rights to use, 26 * copy, modify, merge, publish, distribute, sublicense, and/or 27 * sell copies of the Software, and to permit persons to whom the 28 * Software is furnished to do so, subject to the following 29 * conditions: 30 * 31 * The above copyright notice and this permission notice shall be 32 * included in all copies or substantial portions of the Software. 33 * 34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 41 * OTHER DEALINGS IN THE SOFTWARE. 42 */ 43 44#include <dt-bindings/interrupt-controller/arm-gic.h> 45#include <dt-bindings/clock/sun8i-de2.h> 46#include <dt-bindings/clock/sun8i-r40-ccu.h> 47#include <dt-bindings/reset/sun8i-r40-ccu.h> 48#include <dt-bindings/reset/sun8i-de2.h> 49 50/ { 51 #address-cells = <1>; 52 #size-cells = <1>; 53 interrupt-parent = <&gic>; 54 55 clocks { 56 #address-cells = <1>; 57 #size-cells = <1>; 58 ranges; 59 60 osc24M: osc24M { 61 #clock-cells = <0>; 62 compatible = "fixed-clock"; 63 clock-frequency = <24000000>; 64 clock-accuracy = <50000>; 65 clock-output-names = "osc24M"; 66 }; 67 68 osc32k: osc32k { 69 #clock-cells = <0>; 70 compatible = "fixed-clock"; 71 clock-frequency = <32768>; 72 clock-accuracy = <20000>; 73 clock-output-names = "ext-osc32k"; 74 }; 75 }; 76 77 cpus { 78 #address-cells = <1>; 79 #size-cells = <0>; 80 81 cpu@0 { 82 compatible = "arm,cortex-a7"; 83 device_type = "cpu"; 84 reg = <0>; 85 }; 86 87 cpu@1 { 88 compatible = "arm,cortex-a7"; 89 device_type = "cpu"; 90 reg = <1>; 91 }; 92 93 cpu@2 { 94 compatible = "arm,cortex-a7"; 95 device_type = "cpu"; 96 reg = <2>; 97 }; 98 99 cpu@3 { 100 compatible = "arm,cortex-a7"; 101 device_type = "cpu"; 102 reg = <3>; 103 }; 104 }; 105 106 de: display-engine { 107 compatible = "allwinner,sun8i-r40-display-engine"; 108 allwinner,pipelines = <&mixer0>, <&mixer1>; 109 status = "disabled"; 110 }; 111 112 soc { 113 compatible = "simple-bus"; 114 #address-cells = <1>; 115 #size-cells = <1>; 116 ranges; 117 118 display_clocks: clock@1000000 { 119 compatible = "allwinner,sun8i-r40-de2-clk", 120 "allwinner,sun8i-h3-de2-clk"; 121 reg = <0x01000000 0x100000>; 122 clocks = <&ccu CLK_DE>, 123 <&ccu CLK_BUS_DE>; 124 clock-names = "mod", 125 "bus"; 126 resets = <&ccu RST_BUS_DE>; 127 #clock-cells = <1>; 128 #reset-cells = <1>; 129 }; 130 131 mixer0: mixer@1100000 { 132 compatible = "allwinner,sun8i-r40-de2-mixer-0"; 133 reg = <0x01100000 0x100000>; 134 clocks = <&display_clocks CLK_BUS_MIXER0>, 135 <&display_clocks CLK_MIXER0>; 136 clock-names = "bus", 137 "mod"; 138 resets = <&display_clocks RST_MIXER0>; 139 140 ports { 141 #address-cells = <1>; 142 #size-cells = <0>; 143 144 mixer0_out: port@1 { 145 reg = <1>; 146 mixer0_out_tcon_top: endpoint { 147 remote-endpoint = <&tcon_top_mixer0_in_mixer0>; 148 }; 149 }; 150 }; 151 }; 152 153 mixer1: mixer@1200000 { 154 compatible = "allwinner,sun8i-r40-de2-mixer-1"; 155 reg = <0x01200000 0x100000>; 156 clocks = <&display_clocks CLK_BUS_MIXER1>, 157 <&display_clocks CLK_MIXER1>; 158 clock-names = "bus", 159 "mod"; 160 resets = <&display_clocks RST_WB>; 161 162 ports { 163 #address-cells = <1>; 164 #size-cells = <0>; 165 166 mixer1_out: port@1 { 167 reg = <1>; 168 mixer1_out_tcon_top: endpoint { 169 remote-endpoint = <&tcon_top_mixer1_in_mixer1>; 170 }; 171 }; 172 }; 173 }; 174 175 nmi_intc: interrupt-controller@1c00030 { 176 compatible = "allwinner,sun7i-a20-sc-nmi"; 177 interrupt-controller; 178 #interrupt-cells = <2>; 179 reg = <0x01c00030 0x0c>; 180 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 181 }; 182 183 mmc0: mmc@1c0f000 { 184 compatible = "allwinner,sun8i-r40-mmc", 185 "allwinner,sun50i-a64-mmc"; 186 reg = <0x01c0f000 0x1000>; 187 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 188 clock-names = "ahb", "mmc"; 189 resets = <&ccu RST_BUS_MMC0>; 190 reset-names = "ahb"; 191 pinctrl-0 = <&mmc0_pins>; 192 pinctrl-names = "default"; 193 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 194 status = "disabled"; 195 #address-cells = <1>; 196 #size-cells = <0>; 197 }; 198 199 mmc1: mmc@1c10000 { 200 compatible = "allwinner,sun8i-r40-mmc", 201 "allwinner,sun50i-a64-mmc"; 202 reg = <0x01c10000 0x1000>; 203 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 204 clock-names = "ahb", "mmc"; 205 resets = <&ccu RST_BUS_MMC1>; 206 reset-names = "ahb"; 207 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 208 status = "disabled"; 209 #address-cells = <1>; 210 #size-cells = <0>; 211 }; 212 213 mmc2: mmc@1c11000 { 214 compatible = "allwinner,sun8i-r40-emmc", 215 "allwinner,sun50i-a64-emmc"; 216 reg = <0x01c11000 0x1000>; 217 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 218 clock-names = "ahb", "mmc"; 219 resets = <&ccu RST_BUS_MMC2>; 220 reset-names = "ahb"; 221 pinctrl-0 = <&mmc2_pins>; 222 pinctrl-names = "default"; 223 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 224 status = "disabled"; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 }; 228 229 mmc3: mmc@1c12000 { 230 compatible = "allwinner,sun8i-r40-mmc", 231 "allwinner,sun50i-a64-mmc"; 232 reg = <0x01c12000 0x1000>; 233 clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>; 234 clock-names = "ahb", "mmc"; 235 resets = <&ccu RST_BUS_MMC3>; 236 reset-names = "ahb"; 237 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 238 status = "disabled"; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 }; 242 243 usbphy: phy@1c13400 { 244 compatible = "allwinner,sun8i-r40-usb-phy"; 245 reg = <0x01c13400 0x14>, 246 <0x01c14800 0x4>, 247 <0x01c19800 0x4>, 248 <0x01c1c800 0x4>; 249 reg-names = "phy_ctrl", 250 "pmu0", 251 "pmu1", 252 "pmu2"; 253 clocks = <&ccu CLK_USB_PHY0>, 254 <&ccu CLK_USB_PHY1>, 255 <&ccu CLK_USB_PHY2>; 256 clock-names = "usb0_phy", 257 "usb1_phy", 258 "usb2_phy"; 259 resets = <&ccu RST_USB_PHY0>, 260 <&ccu RST_USB_PHY1>, 261 <&ccu RST_USB_PHY2>; 262 reset-names = "usb0_reset", 263 "usb1_reset", 264 "usb2_reset"; 265 status = "disabled"; 266 #phy-cells = <1>; 267 }; 268 269 ehci1: usb@1c19000 { 270 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; 271 reg = <0x01c19000 0x100>; 272 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&ccu CLK_BUS_EHCI1>; 274 resets = <&ccu RST_BUS_EHCI1>; 275 phys = <&usbphy 1>; 276 phy-names = "usb"; 277 status = "disabled"; 278 }; 279 280 ohci1: usb@1c19400 { 281 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; 282 reg = <0x01c19400 0x100>; 283 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&ccu CLK_BUS_OHCI1>, 285 <&ccu CLK_USB_OHCI1>; 286 resets = <&ccu RST_BUS_OHCI1>; 287 phys = <&usbphy 1>; 288 phy-names = "usb"; 289 status = "disabled"; 290 }; 291 292 ehci2: usb@1c1c000 { 293 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; 294 reg = <0x01c1c000 0x100>; 295 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&ccu CLK_BUS_EHCI2>; 297 resets = <&ccu RST_BUS_EHCI2>; 298 phys = <&usbphy 2>; 299 phy-names = "usb"; 300 status = "disabled"; 301 }; 302 303 ohci2: usb@1c1c400 { 304 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; 305 reg = <0x01c1c400 0x100>; 306 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&ccu CLK_BUS_OHCI2>, 308 <&ccu CLK_USB_OHCI2>; 309 resets = <&ccu RST_BUS_OHCI2>; 310 phys = <&usbphy 2>; 311 phy-names = "usb"; 312 status = "disabled"; 313 }; 314 315 ccu: clock@1c20000 { 316 compatible = "allwinner,sun8i-r40-ccu"; 317 reg = <0x01c20000 0x400>; 318 clocks = <&osc24M>, <&rtc 0>; 319 clock-names = "hosc", "losc"; 320 #clock-cells = <1>; 321 #reset-cells = <1>; 322 }; 323 324 rtc: rtc@1c20400 { 325 compatible = "allwinner,sun8i-r40-rtc", 326 "allwinner,sun8i-h3-rtc"; 327 reg = <0x01c20400 0x400>; 328 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 329 clock-output-names = "osc32k", "osc32k-out"; 330 clocks = <&osc32k>; 331 #clock-cells = <1>; 332 }; 333 334 pio: pinctrl@1c20800 { 335 compatible = "allwinner,sun8i-r40-pinctrl"; 336 reg = <0x01c20800 0x400>; 337 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; 339 clock-names = "apb", "hosc", "losc"; 340 gpio-controller; 341 interrupt-controller; 342 #interrupt-cells = <3>; 343 #gpio-cells = <3>; 344 345 clk_out_a_pin: clk-out-a-pin { 346 pins = "PI12"; 347 function = "clk_out_a"; 348 }; 349 350 gmac_rgmii_pins: gmac-rgmii-pins { 351 pins = "PA0", "PA1", "PA2", "PA3", 352 "PA4", "PA5", "PA6", "PA7", 353 "PA8", "PA10", "PA11", "PA12", 354 "PA13", "PA15", "PA16"; 355 function = "gmac"; 356 /* 357 * data lines in RGMII mode use DDR mode 358 * and need a higher signal drive strength 359 */ 360 drive-strength = <40>; 361 }; 362 363 i2c0_pins: i2c0-pins { 364 pins = "PB0", "PB1"; 365 function = "i2c0"; 366 }; 367 368 mmc0_pins: mmc0-pins { 369 pins = "PF0", "PF1", "PF2", 370 "PF3", "PF4", "PF5"; 371 function = "mmc0"; 372 drive-strength = <30>; 373 bias-pull-up; 374 }; 375 376 mmc1_pg_pins: mmc1-pg-pins { 377 pins = "PG0", "PG1", "PG2", 378 "PG3", "PG4", "PG5"; 379 function = "mmc1"; 380 drive-strength = <30>; 381 bias-pull-up; 382 }; 383 384 mmc2_pins: mmc2-pins { 385 pins = "PC5", "PC6", "PC7", "PC8", "PC9", 386 "PC10", "PC11", "PC12", "PC13", "PC14", 387 "PC15", "PC24"; 388 function = "mmc2"; 389 drive-strength = <30>; 390 bias-pull-up; 391 }; 392 393 uart0_pb_pins: uart0-pb-pins { 394 pins = "PB22", "PB23"; 395 function = "uart0"; 396 }; 397 398 uart3_pg_pins: uart3-pg-pins { 399 pins = "PG6", "PG7"; 400 function = "uart3"; 401 }; 402 403 uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins { 404 pins = "PG8", "PG9"; 405 function = "uart3"; 406 }; 407 }; 408 409 wdt: watchdog@1c20c90 { 410 compatible = "allwinner,sun4i-a10-wdt"; 411 reg = <0x01c20c90 0x10>; 412 }; 413 414 uart0: serial@1c28000 { 415 compatible = "snps,dw-apb-uart"; 416 reg = <0x01c28000 0x400>; 417 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 418 reg-shift = <2>; 419 reg-io-width = <4>; 420 clocks = <&ccu CLK_BUS_UART0>; 421 resets = <&ccu RST_BUS_UART0>; 422 status = "disabled"; 423 }; 424 425 uart1: serial@1c28400 { 426 compatible = "snps,dw-apb-uart"; 427 reg = <0x01c28400 0x400>; 428 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 429 reg-shift = <2>; 430 reg-io-width = <4>; 431 clocks = <&ccu CLK_BUS_UART1>; 432 resets = <&ccu RST_BUS_UART1>; 433 status = "disabled"; 434 }; 435 436 uart2: serial@1c28800 { 437 compatible = "snps,dw-apb-uart"; 438 reg = <0x01c28800 0x400>; 439 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 440 reg-shift = <2>; 441 reg-io-width = <4>; 442 clocks = <&ccu CLK_BUS_UART2>; 443 resets = <&ccu RST_BUS_UART2>; 444 status = "disabled"; 445 }; 446 447 uart3: serial@1c28c00 { 448 compatible = "snps,dw-apb-uart"; 449 reg = <0x01c28c00 0x400>; 450 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 451 reg-shift = <2>; 452 reg-io-width = <4>; 453 clocks = <&ccu CLK_BUS_UART3>; 454 resets = <&ccu RST_BUS_UART3>; 455 status = "disabled"; 456 }; 457 458 uart4: serial@1c29000 { 459 compatible = "snps,dw-apb-uart"; 460 reg = <0x01c29000 0x400>; 461 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 462 reg-shift = <2>; 463 reg-io-width = <4>; 464 clocks = <&ccu CLK_BUS_UART4>; 465 resets = <&ccu RST_BUS_UART4>; 466 status = "disabled"; 467 }; 468 469 uart5: serial@1c29400 { 470 compatible = "snps,dw-apb-uart"; 471 reg = <0x01c29400 0x400>; 472 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 473 reg-shift = <2>; 474 reg-io-width = <4>; 475 clocks = <&ccu CLK_BUS_UART5>; 476 resets = <&ccu RST_BUS_UART5>; 477 status = "disabled"; 478 }; 479 480 uart6: serial@1c29800 { 481 compatible = "snps,dw-apb-uart"; 482 reg = <0x01c29800 0x400>; 483 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 484 reg-shift = <2>; 485 reg-io-width = <4>; 486 clocks = <&ccu CLK_BUS_UART6>; 487 resets = <&ccu RST_BUS_UART6>; 488 status = "disabled"; 489 }; 490 491 uart7: serial@1c29c00 { 492 compatible = "snps,dw-apb-uart"; 493 reg = <0x01c29c00 0x400>; 494 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 495 reg-shift = <2>; 496 reg-io-width = <4>; 497 clocks = <&ccu CLK_BUS_UART7>; 498 resets = <&ccu RST_BUS_UART7>; 499 status = "disabled"; 500 }; 501 502 i2c0: i2c@1c2ac00 { 503 compatible = "allwinner,sun6i-a31-i2c"; 504 reg = <0x01c2ac00 0x400>; 505 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&ccu CLK_BUS_I2C0>; 507 resets = <&ccu RST_BUS_I2C0>; 508 pinctrl-0 = <&i2c0_pins>; 509 pinctrl-names = "default"; 510 status = "disabled"; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 }; 514 515 i2c1: i2c@1c2b000 { 516 compatible = "allwinner,sun6i-a31-i2c"; 517 reg = <0x01c2b000 0x400>; 518 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&ccu CLK_BUS_I2C1>; 520 resets = <&ccu RST_BUS_I2C1>; 521 status = "disabled"; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 }; 525 526 i2c2: i2c@1c2b400 { 527 compatible = "allwinner,sun6i-a31-i2c"; 528 reg = <0x01c2b400 0x400>; 529 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&ccu CLK_BUS_I2C2>; 531 resets = <&ccu RST_BUS_I2C2>; 532 status = "disabled"; 533 #address-cells = <1>; 534 #size-cells = <0>; 535 }; 536 537 i2c3: i2c@1c2b800 { 538 compatible = "allwinner,sun6i-a31-i2c"; 539 reg = <0x01c2b800 0x400>; 540 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&ccu CLK_BUS_I2C3>; 542 resets = <&ccu RST_BUS_I2C3>; 543 status = "disabled"; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 }; 547 548 i2c4: i2c@1c2c000 { 549 compatible = "allwinner,sun6i-a31-i2c"; 550 reg = <0x01c2c000 0x400>; 551 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&ccu CLK_BUS_I2C4>; 553 resets = <&ccu RST_BUS_I2C4>; 554 status = "disabled"; 555 #address-cells = <1>; 556 #size-cells = <0>; 557 }; 558 559 ahci: sata@1c18000 { 560 compatible = "allwinner,sun8i-r40-ahci"; 561 reg = <0x01c18000 0x1000>; 562 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 563 clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>; 564 resets = <&ccu RST_BUS_SATA>; 565 resets-name = "ahci"; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 status = "disabled"; 569 570 }; 571 572 gmac: ethernet@1c50000 { 573 compatible = "allwinner,sun8i-r40-gmac"; 574 syscon = <&ccu>; 575 reg = <0x01c50000 0x10000>; 576 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 577 interrupt-names = "macirq"; 578 resets = <&ccu RST_BUS_GMAC>; 579 reset-names = "stmmaceth"; 580 clocks = <&ccu CLK_BUS_GMAC>; 581 clock-names = "stmmaceth"; 582 status = "disabled"; 583 584 gmac_mdio: mdio { 585 compatible = "snps,dwmac-mdio"; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 }; 589 }; 590 591 tcon_top: tcon-top@1c70000 { 592 compatible = "allwinner,sun8i-r40-tcon-top"; 593 reg = <0x01c70000 0x1000>; 594 clocks = <&ccu CLK_BUS_TCON_TOP>, 595 <&ccu CLK_TCON_TV0>, 596 <&ccu CLK_TVE0>, 597 <&ccu CLK_TCON_TV1>, 598 <&ccu CLK_TVE1>, 599 <&ccu CLK_DSI_DPHY>; 600 clock-names = "bus", 601 "tcon-tv0", 602 "tve0", 603 "tcon-tv1", 604 "tve1", 605 "dsi"; 606 clock-output-names = "tcon-top-tv0", 607 "tcon-top-tv1", 608 "tcon-top-dsi"; 609 resets = <&ccu RST_BUS_TCON_TOP>; 610 #clock-cells = <1>; 611 612 ports { 613 #address-cells = <1>; 614 #size-cells = <0>; 615 616 tcon_top_mixer0_in: port@0 { 617 #address-cells = <1>; 618 #size-cells = <0>; 619 reg = <0>; 620 621 tcon_top_mixer0_in_mixer0: endpoint@0 { 622 reg = <0>; 623 remote-endpoint = <&mixer0_out_tcon_top>; 624 }; 625 }; 626 627 tcon_top_mixer0_out: port@1 { 628 #address-cells = <1>; 629 #size-cells = <0>; 630 reg = <1>; 631 632 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { 633 reg = <0>; 634 }; 635 636 tcon_top_mixer0_out_tcon_lcd1: endpoint@1 { 637 reg = <1>; 638 }; 639 640 tcon_top_mixer0_out_tcon_tv0: endpoint@2 { 641 reg = <2>; 642 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; 643 }; 644 645 tcon_top_mixer0_out_tcon_tv1: endpoint@3 { 646 reg = <3>; 647 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>; 648 }; 649 }; 650 651 tcon_top_mixer1_in: port@2 { 652 #address-cells = <1>; 653 #size-cells = <0>; 654 reg = <2>; 655 656 tcon_top_mixer1_in_mixer1: endpoint@1 { 657 reg = <1>; 658 remote-endpoint = <&mixer1_out_tcon_top>; 659 }; 660 }; 661 662 tcon_top_mixer1_out: port@3 { 663 #address-cells = <1>; 664 #size-cells = <0>; 665 reg = <3>; 666 667 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { 668 reg = <0>; 669 }; 670 671 tcon_top_mixer1_out_tcon_lcd1: endpoint@1 { 672 reg = <1>; 673 }; 674 675 tcon_top_mixer1_out_tcon_tv0: endpoint@2 { 676 reg = <2>; 677 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; 678 }; 679 680 tcon_top_mixer1_out_tcon_tv1: endpoint@3 { 681 reg = <3>; 682 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>; 683 }; 684 }; 685 686 tcon_top_hdmi_in: port@4 { 687 #address-cells = <1>; 688 #size-cells = <0>; 689 reg = <4>; 690 691 tcon_top_hdmi_in_tcon_tv0: endpoint@0 { 692 reg = <0>; 693 remote-endpoint = <&tcon_tv0_out_tcon_top>; 694 }; 695 696 tcon_top_hdmi_in_tcon_tv1: endpoint@1 { 697 reg = <1>; 698 remote-endpoint = <&tcon_tv1_out_tcon_top>; 699 }; 700 }; 701 702 tcon_top_hdmi_out: port@5 { 703 reg = <5>; 704 705 tcon_top_hdmi_out_hdmi: endpoint { 706 remote-endpoint = <&hdmi_in_tcon_top>; 707 }; 708 }; 709 }; 710 }; 711 712 tcon_tv0: lcd-controller@1c73000 { 713 compatible = "allwinner,sun8i-r40-tcon-tv"; 714 reg = <0x01c73000 0x1000>; 715 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 716 clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>; 717 clock-names = "ahb", "tcon-ch1"; 718 resets = <&ccu RST_BUS_TCON_TV0>; 719 reset-names = "lcd"; 720 status = "disabled"; 721 722 ports { 723 #address-cells = <1>; 724 #size-cells = <0>; 725 726 tcon_tv0_in: port@0 { 727 #address-cells = <1>; 728 #size-cells = <0>; 729 reg = <0>; 730 731 tcon_tv0_in_tcon_top_mixer0: endpoint@0 { 732 reg = <0>; 733 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; 734 }; 735 736 tcon_tv0_in_tcon_top_mixer1: endpoint@1 { 737 reg = <1>; 738 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; 739 }; 740 }; 741 742 tcon_tv0_out: port@1 { 743 #address-cells = <1>; 744 #size-cells = <0>; 745 reg = <1>; 746 747 tcon_tv0_out_tcon_top: endpoint@1 { 748 reg = <1>; 749 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; 750 }; 751 }; 752 }; 753 }; 754 755 tcon_tv1: lcd-controller@1c74000 { 756 compatible = "allwinner,sun8i-r40-tcon-tv"; 757 reg = <0x01c74000 0x1000>; 758 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 759 clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top 1>; 760 clock-names = "ahb", "tcon-ch1"; 761 resets = <&ccu RST_BUS_TCON_TV1>; 762 reset-names = "lcd"; 763 status = "disabled"; 764 765 ports { 766 #address-cells = <1>; 767 #size-cells = <0>; 768 769 tcon_tv1_in: port@0 { 770 #address-cells = <1>; 771 #size-cells = <0>; 772 reg = <0>; 773 774 tcon_tv1_in_tcon_top_mixer0: endpoint@0 { 775 reg = <0>; 776 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>; 777 }; 778 779 tcon_tv1_in_tcon_top_mixer1: endpoint@1 { 780 reg = <1>; 781 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>; 782 }; 783 }; 784 785 tcon_tv1_out: port@1 { 786 #address-cells = <1>; 787 #size-cells = <0>; 788 reg = <1>; 789 790 tcon_tv1_out_tcon_top: endpoint@1 { 791 reg = <1>; 792 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>; 793 }; 794 }; 795 }; 796 }; 797 798 gic: interrupt-controller@1c81000 { 799 compatible = "arm,gic-400"; 800 reg = <0x01c81000 0x1000>, 801 <0x01c82000 0x1000>, 802 <0x01c84000 0x2000>, 803 <0x01c86000 0x2000>; 804 interrupt-controller; 805 #interrupt-cells = <3>; 806 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 807 }; 808 809 hdmi: hdmi@1ee0000 { 810 compatible = "allwinner,sun8i-r40-dw-hdmi", 811 "allwinner,sun8i-a83t-dw-hdmi"; 812 reg = <0x01ee0000 0x10000>; 813 reg-io-width = <1>; 814 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 815 clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>, 816 <&ccu CLK_HDMI>; 817 clock-names = "iahb", "isfr", "tmds"; 818 resets = <&ccu RST_BUS_HDMI1>; 819 reset-names = "ctrl"; 820 phys = <&hdmi_phy>; 821 phy-names = "hdmi-phy"; 822 status = "disabled"; 823 824 ports { 825 #address-cells = <1>; 826 #size-cells = <0>; 827 828 hdmi_in: port@0 { 829 reg = <0>; 830 831 hdmi_in_tcon_top: endpoint { 832 remote-endpoint = <&tcon_top_hdmi_out_hdmi>; 833 }; 834 }; 835 836 hdmi_out: port@1 { 837 reg = <1>; 838 }; 839 }; 840 }; 841 842 hdmi_phy: hdmi-phy@1ef0000 { 843 compatible = "allwinner,sun8i-r40-hdmi-phy"; 844 reg = <0x01ef0000 0x10000>; 845 clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>, 846 <&ccu 7>, <&ccu 16>; 847 clock-names = "bus", "mod", "pll-0", "pll-1"; 848 resets = <&ccu RST_BUS_HDMI0>; 849 reset-names = "phy"; 850 #phy-cells = <0>; 851 }; 852 }; 853 854 timer { 855 compatible = "arm,armv7-timer"; 856 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 857 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 858 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 859 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 860 }; 861}; 862