1 /* 2 * platform.h 3 * 4 * Register and variable declaration of the chip. 5 * 6 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 * 21 */ 22 23 #ifndef __HI_CHIP_REGS_H__ 24 #define __HI_CHIP_REGS_H__ 25 26 #define _HI3516D_V300 0x003516d300LL 27 #define _HI3516DV300_MASK 0xFFFFFFFFFFLL 28 29 /* -------------------------------------------------------------------- */ 30 #define RAM_START_ADRS 0x04010500 31 #define STACK_TRAINING 0x0401a000 32 33 /* -------------------------------------------------------------------- */ 34 #define FMC_REG_BASE 0x10000000 35 36 /* -------------------------------------------------------------------- */ 37 #define REG_BASE_SF 0x10010000 38 39 /* -------------------------------------------------------------------- */ 40 #define EMMC_REG_BASE 0x10100000 41 #define SDIO0_REG_BASE 0x100F0000 42 43 /* -------------------------------------------------------------------- */ 44 #define USB3_CTRL_REG_BASE 0x100E0000 45 46 /* -------------------------------------------------------------------- */ 47 #define DDRC0_REG_BASE 0x11250000 48 49 /* -------------------------------------------------------------------- */ 50 #define TIMER0_REG_BASE 0x12000000 51 #define TIMER1_REG_BASE 0x12000020 52 #define TIMER2_REG_BASE 0x12001000 53 #define TIMER3_REG_BASE 0x12001020 54 #define TIMER4_REG_BASE 0x12002000 55 #define TIMER5_REG_BASE 0x12002020 56 #define TIMER6_REG_BASE 0x12003000 57 #define TIMER7_REG_BASE 0x12003020 58 59 #define REG_TIMER_RELOAD 0x0 60 #define REG_TIMER_VALUE 0x4 61 #define REG_TIMER_CONTROL 0x8 62 63 #define CFG_TIMER_CLK 3000000 64 #define CFG_TIMERBASE TIMER0_REG_BASE 65 66 /* enable timer.32bit, periodic,mask irq, 1 divider. */ 67 #define CFG_TIMER_CTRL 0xC2 68 69 /* -------------------------------------------------------------------- */ 70 /* Clock and Reset Generator REG */ 71 /* -------------------------------------------------------------------- */ 72 #define CRG_REG_BASE 0x12010000 73 74 #define REG_CRG80 0x0140 75 #define REG_CRG81 0x0144 76 #define REG_CRG91 0x016c 77 #define REG_CRG110 0x01b8 78 79 /* USB 2.0 CRG Control register offset */ 80 #define REG_USB2_CTRL REG_CRG80 81 82 /* FMC CRG register offset */ 83 #define REG_FMC_CRG REG_CRG81 84 #define FMC_SRST (0x1 << 0) 85 #define FMC_CLK_ENABLE (0x1 << 1) 86 #define FMC_CLK_SEL_MASK (0x7 << 2) 87 #define FMC_CLK_SEL_SHIFT 0x2 88 /* SDR/DDR clock */ 89 #define FMC_CLK_24M 0x0 90 #define FMC_CLK_100M 0x1 91 #define FMC_CLK_150M 0x2 92 #define FMC_CLK_163M 0x3 93 #define FMC_CLK_200M 0x4 94 #define FMC_CLK_257M 0x5 95 /* Only DDR clock */ 96 #define FMC_CLK_300M 0x6 97 #define FMC_CLK_396M 0x7 98 99 #define fmc_clk_sel(_clk) \ 100 (((_clk) << FMC_CLK_SEL_SHIFT) & FMC_CLK_SEL_MASK) 101 #define get_fmc_clk_type(_reg) \ 102 (((_reg) & FMC_CLK_SEL_MASK) >> FMC_CLK_SEL_SHIFT) 103 104 /* Ethernet CRG register offset */ 105 #define REG_ETH_CRG REG_CRG91 106 #define REG_ETH_MAC_IF 0x8c 107 108 /* Uart CRG register offset */ 109 #define REG_UART_CRG REG_CRG110 110 #define uart_clk_sel(_clk) (((_clk) & 0x3) << 18) 111 #define UART_CLK_SEL_MASK (0x3 << 18) 112 #define UART_CLK_APB 0 113 #define UART_CLK_24M 1 114 #define UART_CLK_2M 2 115 116 /* -------------------------------------------------------------------- */ 117 /* System Control REG */ 118 /* -------------------------------------------------------------------- */ 119 #define SYS_CTRL_REG_BASE 0x12020000 120 #define REG_BASE_SCTL SYS_CTRL_REG_BASE 121 122 /* System Control register offset */ 123 #define REG_SC_CTRL 0x0000 124 #define sc_ctrl_timer0_clk_sel(_clk) (((_clk) & 0x1) << 16) 125 #define TIMER0_CLK_SEL_MASK (0x1 << 16) 126 #define TIMER_CLK_3M 0 127 #define TIMER_CLK_BUS 1 128 #define SC_CTRL_REMAP_CLEAR (0x1 << 8) 129 130 /* System soft reset register offset */ 131 #define REG_SC_SYSRES 0x0004 132 133 #define REG_PERISTAT 0x0030 134 #define mmc_boot_clk_sel(val) (((val) >> 8) & 0x3) 135 #define MMC_BOOT_CLK_50M 0x2 136 137 /* System Status register offset */ 138 #define REG_SYSSTAT 0x008c 139 /* bit[7]=0: 3-Byte address mode; bit[7]=1: 4-Byte address mode */ 140 #define get_spi_nor_addr_mode(_reg) (((_reg) >> 7) & 0x1) 141 /* bit[6]=0; SPI nor flash; bit[6]=1: SPI nand flash */ 142 #define get_spi_device_type(_reg) (((_reg) >> 6) & 0x1) 143 /* bit[4]=0 SPI; bit[4]=1: EMMC */ 144 #define get_sys_boot_mode(_reg) (((_reg) >> 4) & 0x1) 145 #define BOOT_FROM_SPI 0 146 #define BOOT_FROM_NAND 2 /* NOT SUPPORT */ 147 #define BOOT_FROM_EMMC 1 148 #define NF_BOOTBW_MASK 0 149 150 #define REG_SC_GEN0 0x0138 151 #define REG_SC_GEN1 0x013c 152 #define REG_SC_GEN2 0x0140 153 #define REG_SC_GEN3 0x0144 154 #define REG_SC_GEN4 0x0148 155 #define REG_SC_GEN9 0x0154 156 157 /********** Communication Register and flag used by bootrom *************/ 158 #define REG_START_FLAG (SYS_CTRL_REG_BASE + REG_SC_GEN1) 159 #define START_MAGIC 0x444f574e 160 #define SELF_BOOT_TYPE_USBDEV 0x2 /* debug */ 161 /* -------------------------------------------------------------------- */ 162 /* Peripheral Control REG */ 163 /* -------------------------------------------------------------------- */ 164 #define MISC_REG_BASE 0x12030000 165 166 #define MISC_CTRL8 0x0020 167 #define MISC_CTRL9 0x0024 168 169 /* USB 2.0 MISC Control register offset */ 170 #define REG_USB2_CTRL0 MISC_CTRL8 171 #define REG_USB2_CTRL1 MISC_CTRL9 172 173 /* -------------------------------------------------------------------- */ 174 #define IO_CONFIG_REG_BASE 0x12040000 175 176 /* -------------------------------------------------------------------- */ 177 #define UART0_REG_BASE 0x120A0000 178 #define UART1_REG_BASE 0x120A1000 179 #define UART2_REG_BASE 0x120A2000 180 #define UART3_REG_BASE 0x120A3000 181 182 /* -------------------------------------------------------------------- */ 183 #define GPIO0_REG_BASE 0x120D0000 184 #define GPIO1_REG_BASE 0x120D1000 185 #define GPIO2_REG_BASE 0x120D2000 186 #define GPIO3_REG_BASE 0x120D3000 187 #define GPIO4_REG_BASE 0x120D4000 188 #define GPIO5_REG_BASE 0x120D5000 189 #define GPIO6_REG_BASE 0x120D6000 190 #define GPIO7_REG_BASE 0x120D7000 191 #define GPIO8_REG_BASE 0x120D8000 192 #define GPIO9_REG_BASE 0x120D9000 193 #define GPIO10_REG_BASE 0x120DA000 194 195 #define FMC_MEM_BASE 0x14000000 196 #define FMC_TEXT_ADRS FMC_MEM_BASE 197 #define DDR_MEM_BASE 0x80000000 198 199 #define HW_DEC_INTR 86 200 201 /*--------------------------------------------------------- 202 * Syscounter registers 203 *---------------------------------------------------------*/ 204 #define SYSCNT_REG_BASE 0x12040000 205 #define SYSCNT_ENABLE_REG 0x0 206 #define SYSCNT_FREQ_REG 0x20 207 #define SYSCNT_FREQ 50000000 208 209 #define REG_BASE_SYSCNT 0x12040000 210 #define CNTCR 0x0 211 #define CNTFID0 0x20 212 213 /* --------------------------------------------------------- */ 214 #define NUM_0 0 215 #define NUM_1 1 216 #define NUM_2 2 217 #define NUM_3 3 218 #define NUM_4 4 219 #define NUM_5 5 220 #define NUM_6 6 221 #define NUM_7 7 222 #define NUM_8 8 223 #define NUM_9 9 224 225 #endif /* End of __HI_CHIP_REGS_H__ */ 226 227