1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2015 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <cpu_func.h>
8 #include <asm/armv7.h>
9 #include <asm/pl310.h>
10 #include <asm/io.h>
11 #include <asm/mach-imx/sys_proto.h>
12
enable_ca7_smp(void)13 static void enable_ca7_smp(void)
14 {
15 u32 val;
16
17 /* Read MIDR */
18 asm volatile ("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(val));
19 val = (val >> 4);
20 val &= 0xf;
21
22 /* Only set the SMP for Cortex A7 */
23 if (val == 0x7) {
24 /* Read auxiliary control register */
25 asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(val));
26
27 if (val & (1 << 6))
28 return;
29
30 /* Enable SMP */
31 val |= (1 << 6);
32
33 /* Write auxiliary control register */
34 asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(val));
35
36 DSB;
37 ISB;
38 }
39 }
40
41 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
enable_caches(void)42 void enable_caches(void)
43 {
44 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
45 enum dcache_option option = DCACHE_WRITETHROUGH;
46 #else
47 enum dcache_option option = DCACHE_WRITEBACK;
48 #endif
49 /* Avoid random hang when download by usb */
50 invalidate_dcache_all();
51
52 /* Set ACTLR.SMP bit for Cortex-A7 */
53 enable_ca7_smp();
54
55 /* Enable D-cache. I-cache is already enabled in start.S */
56 dcache_enable();
57
58 /* Enable caching on OCRAM and ROM */
59 mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
60 ROMCP_ARB_END_ADDR,
61 option);
62 mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
63 IRAM_SIZE,
64 option);
65 }
66 #else
enable_caches(void)67 void enable_caches(void)
68 {
69 /*
70 * Set ACTLR.SMP bit for Cortex-A7, even if the caches are
71 * disabled by u-boot
72 */
73 enable_ca7_smp();
74
75 puts("WARNING: Caches not enabled\n");
76 }
77 #endif
78
79 #ifndef CONFIG_SYS_L2CACHE_OFF
80 #ifdef CONFIG_SYS_L2_PL310
81 #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
v7_outer_cache_enable(void)82 void v7_outer_cache_enable(void)
83 {
84 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
85 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
86 unsigned int val, cache_id;
87
88
89 /*
90 * Must disable the L2 before changing the latency parameters
91 * and auxiliary control register.
92 */
93 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
94
95 /*
96 * Set bit 22 in the auxiliary control register. If this bit
97 * is cleared, PL310 treats Normal Shared Non-cacheable
98 * accesses as Cacheable no-allocate.
99 */
100 setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
101
102 if (is_mx6sl() || is_mx6sll()) {
103 val = readl(&iomux->gpr[11]);
104 if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
105 /* L2 cache configured as OCRAM, reset it */
106 val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
107 writel(val, &iomux->gpr[11]);
108 }
109 }
110
111 writel(0x132, &pl310->pl310_tag_latency_ctrl);
112 writel(0x132, &pl310->pl310_data_latency_ctrl);
113
114 val = readl(&pl310->pl310_prefetch_ctrl);
115
116 /* Turn on the L2 I/D prefetch, double linefill */
117 /* Set prefetch offset with any value except 23 as per errata 765569 */
118 val |= 0x7000000f;
119
120 /*
121 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
122 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL/SX/DQP
123 * is r3p2.
124 * But according to ARM PL310 errata: 752271
125 * ID: 752271: Double linefill feature can cause data corruption
126 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
127 * Workaround: The only workaround to this erratum is to disable the
128 * double linefill feature. This is the default behavior.
129 */
130 cache_id = readl(&pl310->pl310_cache_id);
131 if (((cache_id & L2X0_CACHE_ID_PART_MASK) == L2X0_CACHE_ID_PART_L310)
132 && ((cache_id & L2X0_CACHE_ID_RTL_MASK) < L2X0_CACHE_ID_RTL_R3P2))
133 val &= ~(1 << 30);
134 writel(val, &pl310->pl310_prefetch_ctrl);
135
136 val = readl(&pl310->pl310_power_ctrl);
137 val |= L2X0_DYNAMIC_CLK_GATING_EN;
138 val |= L2X0_STNDBY_MODE_EN;
139 writel(val, &pl310->pl310_power_ctrl);
140
141 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
142 }
143
v7_outer_cache_disable(void)144 void v7_outer_cache_disable(void)
145 {
146 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
147
148 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
149 }
150 #endif /* !CONFIG_SYS_L2_PL310 */
151 #endif /* !CONFIG_SYS_L2CACHE_OFF */
152