1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2018-2019 NXP
4 *
5 * Peng Fan <peng.fan@nxp.com>
6 */
7
8 #include <common.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/io.h>
13 #include <clk.h>
14 #include <clk-uclass.h>
15 #include <dt-bindings/clock/imx8mm-clock.h>
16 #include <div64.h>
17 #include <errno.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
21 static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
22
enable_ocotp_clk(unsigned char enable)23 void enable_ocotp_clk(unsigned char enable)
24 {
25 struct clk *clkp;
26 int ret;
27
28 ret = clk_get_by_id(IMX8MM_CLK_OCOTP_ROOT, &clkp);
29 if (ret) {
30 printf("%s: err: %d\n", __func__, ret);
31 return;
32 }
33
34 enable ? clk_enable(clkp) : clk_disable(clkp);
35 }
36
enable_i2c_clk(unsigned char enable,unsigned i2c_num)37 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
38 {
39 struct clk *clkp;
40 int ret;
41
42 ret = clk_get_by_id(IMX8MM_CLK_I2C1_ROOT + i2c_num, &clkp);
43 if (ret) {
44 printf("%s: err: %d\n", __func__, ret);
45 return ret;
46 }
47
48 return enable ? clk_enable(clkp) : clk_disable(clkp);
49 }
50
51 #ifdef CONFIG_SPL_BUILD
52 static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
53 PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
54 PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
55 PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
56 PLL_1443X_RATE(600000000U, 300, 3, 2, 0),
57 PLL_1443X_RATE(594000000U, 99, 1, 2, 0),
58 PLL_1443X_RATE(400000000U, 300, 9, 1, 0),
59 PLL_1443X_RATE(266666667U, 400, 9, 2, 0),
60 PLL_1443X_RATE(167000000U, 334, 3, 4, 0),
61 PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
62 };
63
fracpll_configure(enum pll_clocks pll,u32 freq)64 int fracpll_configure(enum pll_clocks pll, u32 freq)
65 {
66 int i;
67 u32 tmp, div_val;
68 void *pll_base;
69 struct imx_int_pll_rate_table *rate;
70
71 for (i = 0; i < ARRAY_SIZE(imx8mm_fracpll_tbl); i++) {
72 if (freq == imx8mm_fracpll_tbl[i].rate)
73 break;
74 }
75
76 if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) {
77 printf("No matched freq table %u\n", freq);
78 return -EINVAL;
79 }
80
81 rate = &imx8mm_fracpll_tbl[i];
82
83 switch (pll) {
84 case ANATOP_DRAM_PLL:
85 setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7);
86 setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5);
87 writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004);
88
89 pll_base = &ana_pll->dram_pll_gnrl_ctl;
90 break;
91 case ANATOP_VIDEO_PLL:
92 pll_base = &ana_pll->video_pll1_gnrl_ctl;
93 break;
94 default:
95 return 0;
96 }
97 /* Bypass clock and set lock to pll output lock */
98 tmp = readl(pll_base);
99 tmp |= BYPASS_MASK;
100 writel(tmp, pll_base);
101
102 /* Enable RST */
103 tmp &= ~RST_MASK;
104 writel(tmp, pll_base);
105
106 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
107 (rate->sdiv << SDIV_SHIFT);
108 writel(div_val, pll_base + 4);
109 writel(rate->kdiv << KDIV_SHIFT, pll_base + 8);
110
111 __udelay(100);
112
113 /* Disable RST */
114 tmp |= RST_MASK;
115 writel(tmp, pll_base);
116
117 /* Wait Lock*/
118 while (!(readl(pll_base) & LOCK_STATUS))
119 ;
120
121 /* Bypass */
122 tmp &= ~BYPASS_MASK;
123 writel(tmp, pll_base);
124
125 return 0;
126 }
127
dram_pll_init(ulong pll_val)128 void dram_pll_init(ulong pll_val)
129 {
130 fracpll_configure(ANATOP_DRAM_PLL, pll_val);
131 }
132
133 static struct dram_bypass_clk_setting imx8mm_dram_bypass_tbl[] = {
134 DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
135 CLK_ROOT_PRE_DIV2),
136 DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
137 CLK_ROOT_PRE_DIV2),
138 DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
139 CLK_ROOT_PRE_DIV2),
140 };
141
dram_enable_bypass(ulong clk_val)142 void dram_enable_bypass(ulong clk_val)
143 {
144 int i;
145 struct dram_bypass_clk_setting *config;
146
147 for (i = 0; i < ARRAY_SIZE(imx8mm_dram_bypass_tbl); i++) {
148 if (clk_val == imx8mm_dram_bypass_tbl[i].clk)
149 break;
150 }
151
152 if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) {
153 printf("No matched freq table %lu\n", clk_val);
154 return;
155 }
156
157 config = &imx8mm_dram_bypass_tbl[i];
158
159 clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
160 CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
161 CLK_ROOT_PRE_DIV(config->alt_pre_div));
162 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
163 CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
164 CLK_ROOT_PRE_DIV(config->apb_pre_div));
165 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
166 CLK_ROOT_SOURCE_SEL(1));
167 }
168
dram_disable_bypass(void)169 void dram_disable_bypass(void)
170 {
171 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
172 CLK_ROOT_SOURCE_SEL(0));
173 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
174 CLK_ROOT_SOURCE_SEL(4) |
175 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
176 }
177 #endif
178
init_uart_clk(u32 index)179 void init_uart_clk(u32 index)
180 {
181 /*
182 * set uart clock root
183 * 24M OSC
184 */
185 switch (index) {
186 case 0:
187 clock_enable(CCGR_UART1, 0);
188 clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
189 CLK_ROOT_SOURCE_SEL(0));
190 clock_enable(CCGR_UART1, 1);
191 return;
192 case 1:
193 clock_enable(CCGR_UART2, 0);
194 clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
195 CLK_ROOT_SOURCE_SEL(0));
196 clock_enable(CCGR_UART2, 1);
197 return;
198 case 2:
199 clock_enable(CCGR_UART3, 0);
200 clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
201 CLK_ROOT_SOURCE_SEL(0));
202 clock_enable(CCGR_UART3, 1);
203 return;
204 case 3:
205 clock_enable(CCGR_UART4, 0);
206 clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
207 CLK_ROOT_SOURCE_SEL(0));
208 clock_enable(CCGR_UART4, 1);
209 return;
210 default:
211 printf("Invalid uart index\n");
212 return;
213 }
214 }
215
init_wdog_clk(void)216 void init_wdog_clk(void)
217 {
218 clock_enable(CCGR_WDOG1, 0);
219 clock_enable(CCGR_WDOG2, 0);
220 clock_enable(CCGR_WDOG3, 0);
221 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
222 CLK_ROOT_SOURCE_SEL(0));
223 clock_enable(CCGR_WDOG1, 1);
224 clock_enable(CCGR_WDOG2, 1);
225 clock_enable(CCGR_WDOG3, 1);
226 }
227
clock_init(void)228 int clock_init(void)
229 {
230 u32 val_cfg0;
231
232 /*
233 * The gate is not exported to clk tree, so configure them here.
234 * According to ANAMIX SPEC
235 * sys pll1 fixed at 800MHz
236 * sys pll2 fixed at 1GHz
237 * Here we only enable the outputs.
238 */
239 val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl);
240 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
241 INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
242 INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
243 INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
244 INTPLL_DIV20_CLKE_MASK;
245 writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl);
246
247 val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl);
248 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
249 INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
250 INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
251 INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
252 INTPLL_DIV20_CLKE_MASK;
253 writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl);
254
255 /* config GIC to sys_pll2_100m */
256 clock_enable(CCGR_GIC, 0);
257 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON |
258 CLK_ROOT_SOURCE_SEL(3));
259 clock_enable(CCGR_GIC, 1);
260
261 clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
262 CLK_ROOT_SOURCE_SEL(1));
263
264 clock_enable(CCGR_DDR1, 0);
265 clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
266 CLK_ROOT_SOURCE_SEL(1));
267 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
268 CLK_ROOT_SOURCE_SEL(1));
269 clock_enable(CCGR_DDR1, 1);
270
271 init_wdog_clk();
272
273 clock_enable(CCGR_TEMP_SENSOR, 1);
274
275 clock_enable(CCGR_SEC_DEBUG, 1);
276
277 return 0;
278 };
279
imx_get_uartclk(void)280 u32 imx_get_uartclk(void)
281 {
282 return 24000000U;
283 }
284
mxc_get_clock(enum mxc_clock clk)285 u32 mxc_get_clock(enum mxc_clock clk)
286 {
287 struct clk *clkp;
288 int ret;
289
290 switch (clk) {
291 case MXC_IPG_CLK:
292 ret = clk_get_by_id(IMX8MM_CLK_IPG_ROOT, &clkp);
293 if (ret)
294 return 0;
295 return clk_get_rate(clkp);
296 case MXC_ARM_CLK:
297 ret = clk_get_by_id(IMX8MM_CLK_A53_DIV, &clkp);
298 if (ret)
299 return 0;
300 return clk_get_rate(clkp);
301 default:
302 printf("%s: %d not supported\n", __func__, clk);
303 }
304
305 return 0;
306 }
307