1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007
4 * Sascha Hauer, Pengutronix
5 *
6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 */
8
9 #include <common.h>
10 #include <init.h>
11 #include <linux/errno.h>
12 #include <asm/io.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/bootm.h>
17 #include <asm/mach-imx/boot_mode.h>
18 #include <asm/mach-imx/dma.h>
19 #include <asm/mach-imx/hab.h>
20 #include <stdbool.h>
21 #include <asm/arch/mxc_hdmi.h>
22 #include <asm/arch/crm_regs.h>
23 #include <dm.h>
24 #include <imx_thermal.h>
25 #include <mmc.h>
26
27 struct scu_regs {
28 u32 ctrl;
29 u32 config;
30 u32 status;
31 u32 invalidate;
32 u32 fpga_rev;
33 };
34
35 #if defined(CONFIG_IMX_THERMAL)
36 static const struct imx_thermal_plat imx6_thermal_plat = {
37 .regs = (void *)ANATOP_BASE_ADDR,
38 .fuse_bank = 1,
39 .fuse_word = 6,
40 };
41
42 U_BOOT_DEVICE(imx6_thermal) = {
43 .name = "imx_thermal",
44 .platdata = &imx6_thermal_plat,
45 };
46 #endif
47
48 #if defined(CONFIG_IMX_HAB)
49 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
50 .bank = 0,
51 .word = 6,
52 };
53 #endif
54
get_nr_cpus(void)55 u32 get_nr_cpus(void)
56 {
57 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
58 return readl(&scu->config) & 3;
59 }
60
get_cpu_rev(void)61 u32 get_cpu_rev(void)
62 {
63 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
64 u32 reg = readl(&anatop->digprog_sololite);
65 u32 type = ((reg >> 16) & 0xff);
66 u32 major, cfg = 0;
67
68 if (type != MXC_CPU_MX6SL) {
69 reg = readl(&anatop->digprog);
70 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
71 cfg = readl(&scu->config) & 3;
72 type = ((reg >> 16) & 0xff);
73 if (type == MXC_CPU_MX6DL) {
74 if (!cfg)
75 type = MXC_CPU_MX6SOLO;
76 }
77
78 if (type == MXC_CPU_MX6Q) {
79 if (cfg == 1)
80 type = MXC_CPU_MX6D;
81 }
82
83 if (type == MXC_CPU_MX6ULL) {
84 if (readl(SRC_BASE_ADDR + 0x1c) & (1 << 6))
85 type = MXC_CPU_MX6ULZ;
86 }
87 }
88 major = ((reg >> 8) & 0xff);
89 if ((major >= 1) &&
90 ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
91 major--;
92 type = MXC_CPU_MX6QP;
93 if (cfg == 1)
94 type = MXC_CPU_MX6DP;
95 }
96 reg &= 0xff; /* mx6 silicon revision */
97
98 /* For 6DQ, the value 0x00630005 is Silicon revision 1.3*/
99 if (((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D)) && (reg == 0x5))
100 reg = 0x3;
101
102 return (type << 12) | (reg + (0x10 * (major + 1)));
103 }
104
105 /*
106 * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
107 * defines a 2-bit SPEED_GRADING
108 */
109 #define OCOTP_CFG3_SPEED_SHIFT 16
110 #define OCOTP_CFG3_SPEED_800MHZ 0
111 #define OCOTP_CFG3_SPEED_850MHZ 1
112 #define OCOTP_CFG3_SPEED_1GHZ 2
113 #define OCOTP_CFG3_SPEED_1P2GHZ 3
114
115 /*
116 * For i.MX6UL
117 */
118 #define OCOTP_CFG3_SPEED_528MHZ 1
119 #define OCOTP_CFG3_SPEED_696MHZ 2
120
121 /*
122 * For i.MX6ULL
123 */
124 #define OCOTP_CFG3_SPEED_792MHZ 2
125 #define OCOTP_CFG3_SPEED_900MHZ 3
126
get_cpu_speed_grade_hz(void)127 u32 get_cpu_speed_grade_hz(void)
128 {
129 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
130 struct fuse_bank *bank = &ocotp->bank[0];
131 struct fuse_bank0_regs *fuse =
132 (struct fuse_bank0_regs *)bank->fuse_regs;
133 uint32_t val;
134
135 val = readl(&fuse->cfg3);
136 val >>= OCOTP_CFG3_SPEED_SHIFT;
137 val &= 0x3;
138
139 if (is_mx6ul()) {
140 if (val == OCOTP_CFG3_SPEED_528MHZ)
141 return 528000000;
142 else if (val == OCOTP_CFG3_SPEED_696MHZ)
143 return 696000000;
144 else
145 return 0;
146 }
147
148 if (is_mx6ull()) {
149 if (val == OCOTP_CFG3_SPEED_528MHZ)
150 return 528000000;
151 else if (val == OCOTP_CFG3_SPEED_792MHZ)
152 return 792000000;
153 else if (val == OCOTP_CFG3_SPEED_900MHZ)
154 return 900000000;
155 else
156 return 0;
157 }
158
159 switch (val) {
160 /* Valid for IMX6DQ */
161 case OCOTP_CFG3_SPEED_1P2GHZ:
162 if (is_mx6dq() || is_mx6dqp())
163 return 1200000000;
164 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
165 case OCOTP_CFG3_SPEED_1GHZ:
166 return 996000000;
167 /* Valid for IMX6DQ */
168 case OCOTP_CFG3_SPEED_850MHZ:
169 if (is_mx6dq() || is_mx6dqp())
170 return 852000000;
171 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
172 case OCOTP_CFG3_SPEED_800MHZ:
173 return 792000000;
174 }
175 return 0;
176 }
177
178 /*
179 * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
180 * defines a 2-bit Temperature Grade
181 *
182 * return temperature grade and min/max temperature in Celsius
183 */
184 #define OCOTP_MEM0_TEMP_SHIFT 6
185
get_cpu_temp_grade(int * minc,int * maxc)186 u32 get_cpu_temp_grade(int *minc, int *maxc)
187 {
188 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
189 struct fuse_bank *bank = &ocotp->bank[1];
190 struct fuse_bank1_regs *fuse =
191 (struct fuse_bank1_regs *)bank->fuse_regs;
192 uint32_t val;
193
194 val = readl(&fuse->mem0);
195 val >>= OCOTP_MEM0_TEMP_SHIFT;
196 val &= 0x3;
197
198 if (minc && maxc) {
199 if (val == TEMP_AUTOMOTIVE) {
200 *minc = -40;
201 *maxc = 125;
202 } else if (val == TEMP_INDUSTRIAL) {
203 *minc = -40;
204 *maxc = 105;
205 } else if (val == TEMP_EXTCOMMERCIAL) {
206 *minc = -20;
207 *maxc = 105;
208 } else {
209 *minc = 0;
210 *maxc = 95;
211 }
212 }
213 return val;
214 }
215
216 #ifdef CONFIG_REVISION_TAG
get_board_rev(void)217 u32 __weak get_board_rev(void)
218 {
219 u32 cpurev = get_cpu_rev();
220 u32 type = ((cpurev >> 12) & 0xff);
221 if (type == MXC_CPU_MX6SOLO)
222 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
223
224 if (type == MXC_CPU_MX6D)
225 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
226
227 return cpurev;
228 }
229 #endif
230
clear_ldo_ramp(void)231 static void clear_ldo_ramp(void)
232 {
233 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
234 int reg;
235
236 /* ROM may modify LDO ramp up time according to fuse setting, so in
237 * order to be in the safe side we neeed to reset these settings to
238 * match the reset value: 0'b00
239 */
240 reg = readl(&anatop->ana_misc2);
241 reg &= ~(0x3f << 24);
242 writel(reg, &anatop->ana_misc2);
243 }
244
245 /*
246 * Set the PMU_REG_CORE register
247 *
248 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
249 * Possible values are from 0.725V to 1.450V in steps of
250 * 0.025V (25mV).
251 */
set_ldo_voltage(enum ldo_reg ldo,u32 mv)252 int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
253 {
254 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
255 u32 val, step, old, reg = readl(&anatop->reg_core);
256 u8 shift;
257
258 /* No LDO_SOC/PU/ARM */
259 if (is_mx6sll())
260 return 0;
261
262 if (mv < 725)
263 val = 0x00; /* Power gated off */
264 else if (mv > 1450)
265 val = 0x1F; /* Power FET switched full on. No regulation */
266 else
267 val = (mv - 700) / 25;
268
269 clear_ldo_ramp();
270
271 switch (ldo) {
272 case LDO_SOC:
273 shift = 18;
274 break;
275 case LDO_PU:
276 shift = 9;
277 break;
278 case LDO_ARM:
279 shift = 0;
280 break;
281 default:
282 return -EINVAL;
283 }
284
285 old = (reg & (0x1F << shift)) >> shift;
286 step = abs(val - old);
287 if (step == 0)
288 return 0;
289
290 reg = (reg & ~(0x1F << shift)) | (val << shift);
291 writel(reg, &anatop->reg_core);
292
293 /*
294 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
295 * step
296 */
297 udelay(3 * step);
298
299 return 0;
300 }
301
set_ahb_rate(u32 val)302 static void set_ahb_rate(u32 val)
303 {
304 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
305 u32 reg, div;
306
307 div = get_periph_clk() / val - 1;
308 reg = readl(&mxc_ccm->cbcdr);
309
310 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
311 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
312 }
313
clear_mmdc_ch_mask(void)314 static void clear_mmdc_ch_mask(void)
315 {
316 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
317 u32 reg;
318 reg = readl(&mxc_ccm->ccdr);
319
320 /* Clear MMDC channel mask */
321 if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() || is_mx6sll())
322 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
323 else
324 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
325 writel(reg, &mxc_ccm->ccdr);
326 }
327
328 #define OCOTP_MEM0_REFTOP_TRIM_SHIFT 8
329
init_bandgap(void)330 static void init_bandgap(void)
331 {
332 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
333 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
334 struct fuse_bank *bank = &ocotp->bank[1];
335 struct fuse_bank1_regs *fuse =
336 (struct fuse_bank1_regs *)bank->fuse_regs;
337 uint32_t val;
338
339 /*
340 * Ensure the bandgap has stabilized.
341 */
342 while (!(readl(&anatop->ana_misc0) & 0x80))
343 ;
344 /*
345 * For best noise performance of the analog blocks using the
346 * outputs of the bandgap, the reftop_selfbiasoff bit should
347 * be set.
348 */
349 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
350 /*
351 * On i.MX6ULL,we need to set VBGADJ bits according to the
352 * REFTOP_TRIM[3:0] in fuse table
353 * 000 - set REFTOP_VBGADJ[2:0] to 3b'110,
354 * 110 - set REFTOP_VBGADJ[2:0] to 3b'000,
355 * 001 - set REFTOP_VBGADJ[2:0] to 3b'001,
356 * 010 - set REFTOP_VBGADJ[2:0] to 3b'010,
357 * 011 - set REFTOP_VBGADJ[2:0] to 3b'011,
358 * 100 - set REFTOP_VBGADJ[2:0] to 3b'100,
359 * 101 - set REFTOP_VBGADJ[2:0] to 3b'101,
360 * 111 - set REFTOP_VBGADJ[2:0] to 3b'111,
361 */
362 if (is_mx6ull()) {
363 val = readl(&fuse->mem0);
364 val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT;
365 val &= 0x7;
366
367 writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
368 &anatop->ana_misc0_set);
369 }
370 }
371
372 #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL)
noc_setup(void)373 static void noc_setup(void)
374 {
375 enable_ipu_clock();
376
377 writel(0x80000201, 0xbb0608);
378 /* Bypass IPU1 QoS generator */
379 writel(0x00000002, 0x00bb048c);
380 /* Bypass IPU2 QoS generator */
381 writel(0x00000002, 0x00bb050c);
382 /* Bandwidth THR for of PRE0 */
383 writel(0x00000200, 0x00bb0690);
384 /* Bandwidth THR for of PRE1 */
385 writel(0x00000200, 0x00bb0710);
386 /* Bandwidth THR for of PRE2 */
387 writel(0x00000200, 0x00bb0790);
388 /* Bandwidth THR for of PRE3 */
389 writel(0x00000200, 0x00bb0810);
390 /* Saturation THR for of PRE0 */
391 writel(0x00000010, 0x00bb0694);
392 /* Saturation THR for of PRE1 */
393 writel(0x00000010, 0x00bb0714);
394 /* Saturation THR for of PRE2 */
395 writel(0x00000010, 0x00bb0794);
396 /* Saturation THR for of PRE */
397 writel(0x00000010, 0x00bb0814);
398
399 disable_ipu_clock();
400 }
401 #endif
402
arch_cpu_init(void)403 int arch_cpu_init(void)
404 {
405 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
406
407 init_aips();
408
409 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
410 clear_mmdc_ch_mask();
411
412 /*
413 * Disable self-bias circuit in the analog bandap.
414 * The self-bias circuit is used by the bandgap during startup.
415 * This bit should be set after the bandgap has initialized.
416 */
417 init_bandgap();
418
419 if (!is_mx6ul() && !is_mx6ull()) {
420 /*
421 * When low freq boot is enabled, ROM will not set AHB
422 * freq, so we need to ensure AHB freq is 132MHz in such
423 * scenario.
424 *
425 * To i.MX6UL, when power up, default ARM core and
426 * AHB rate is 396M and 132M.
427 */
428 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
429 set_ahb_rate(132000000);
430 }
431
432 if (is_mx6ul()) {
433 if (is_soc_rev(CHIP_REV_1_0) == 0) {
434 /*
435 * According to the design team's requirement on
436 * i.MX6UL,the PMIC_STBY_REQ PAD should be configured
437 * as open drain 100K (0x0000b8a0).
438 * Only exists on TO1.0
439 */
440 writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
441 } else {
442 /*
443 * From TO1.1, SNVS adds internal pull up control
444 * for POR_B, the register filed is GPBIT[1:0],
445 * after system boot up, it can be set to 2b'01
446 * to disable internal pull up.It can save about
447 * 30uA power in SNVS mode.
448 */
449 writel((readl(MX6UL_SNVS_LP_BASE_ADDR + 0x10) &
450 (~0x1400)) | 0x400,
451 MX6UL_SNVS_LP_BASE_ADDR + 0x10);
452 }
453 }
454
455 if (is_mx6ull()) {
456 /*
457 * GPBIT[1:0] is suggested to set to 2'b11:
458 * 2'b00 : always PUP100K
459 * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL
460 * 2'b10 : always disable PUP100K
461 * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL
462 * register offset is different from i.MX6UL, since
463 * i.MX6UL is fixed by ECO.
464 */
465 writel(readl(MX6UL_SNVS_LP_BASE_ADDR) |
466 0x3, MX6UL_SNVS_LP_BASE_ADDR);
467 }
468
469 /* Set perclk to source from OSC 24MHz */
470 if (is_mx6sl())
471 setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK);
472
473 imx_wdog_disable_powerdown(); /* Disable PDE bit of WMCR register */
474
475 if (is_mx6sx())
476 setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL);
477
478 init_src();
479
480 #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL)
481 if (is_mx6dqp())
482 noc_setup();
483 #endif
484 return 0;
485 }
486
487 #ifdef CONFIG_ENV_IS_IN_MMC
board_mmc_get_env_dev(int devno)488 __weak int board_mmc_get_env_dev(int devno)
489 {
490 return CONFIG_SYS_MMC_ENV_DEV;
491 }
492
mmc_get_boot_dev(void)493 static int mmc_get_boot_dev(void)
494 {
495 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
496 u32 soc_sbmr = readl(&src_regs->sbmr1);
497 u32 bootsel;
498 int devno;
499
500 /*
501 * Refer to
502 * "i.MX 6Dual/6Quad Applications Processor Reference Manual"
503 * Chapter "8.5.3.1 Expansion Device eFUSE Configuration"
504 * i.MX6SL/SX/UL has same layout.
505 */
506 bootsel = (soc_sbmr & 0x000000FF) >> 6;
507
508 /* No boot from sd/mmc */
509 if (bootsel != 1)
510 return -1;
511
512 /* BOOT_CFG2[3] and BOOT_CFG2[4] */
513 devno = (soc_sbmr & 0x00001800) >> 11;
514
515 return devno;
516 }
517
mmc_get_env_dev(void)518 int mmc_get_env_dev(void)
519 {
520 int devno = mmc_get_boot_dev();
521
522 /* If not boot from sd/mmc, use default value */
523 if (devno < 0)
524 return CONFIG_SYS_MMC_ENV_DEV;
525
526 return board_mmc_get_env_dev(devno);
527 }
528
529 #ifdef CONFIG_SYS_MMC_ENV_PART
board_mmc_get_env_part(int devno)530 __weak int board_mmc_get_env_part(int devno)
531 {
532 return CONFIG_SYS_MMC_ENV_PART;
533 }
534
mmc_get_env_part(struct mmc * mmc)535 uint mmc_get_env_part(struct mmc *mmc)
536 {
537 int devno = mmc_get_boot_dev();
538
539 /* If not boot from sd/mmc, use default value */
540 if (devno < 0)
541 return CONFIG_SYS_MMC_ENV_PART;
542
543 return board_mmc_get_env_part(devno);
544 }
545 #endif
546 #endif
547
board_postclk_init(void)548 int board_postclk_init(void)
549 {
550 /* NO LDO SOC on i.MX6SLL */
551 if (is_mx6sll())
552 return 0;
553
554 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
555
556 return 0;
557 }
558
559 #ifndef CONFIG_SPL_BUILD
560 /*
561 * cfg_val will be used for
562 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
563 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
564 * instead of SBMR1 to determine the boot device.
565 */
566 const struct boot_mode soc_boot_modes[] = {
567 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
568 /* reserved value should start rom usb */
569 #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
570 {"usb", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
571 #else
572 {"usb", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
573 #endif
574 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
575 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
576 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
577 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
578 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
579 /* 4 bit bus width */
580 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
581 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
582 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
583 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
584 {NULL, 0},
585 };
586 #endif
587
reset_misc(void)588 void reset_misc(void)
589 {
590 #ifndef CONFIG_SPL_BUILD
591 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
592 lcdif_power_down();
593 #endif
594 #endif
595 }
596
s_init(void)597 void s_init(void)
598 {
599 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
600 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
601 u32 mask480;
602 u32 mask528;
603 u32 reg, periph1, periph2;
604
605 if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sll())
606 return;
607
608 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
609 * to make sure PFD is working right, otherwise, PFDs may
610 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
611 * workaround in ROM code, as bus clock need it
612 */
613
614 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
615 ANATOP_PFD_CLKGATE_MASK(1) |
616 ANATOP_PFD_CLKGATE_MASK(2) |
617 ANATOP_PFD_CLKGATE_MASK(3);
618 mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
619 ANATOP_PFD_CLKGATE_MASK(3);
620
621 reg = readl(&ccm->cbcmr);
622 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
623 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
624 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
625 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
626
627 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
628 if ((periph2 != 0x2) && (periph1 != 0x2))
629 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
630
631 if ((periph2 != 0x1) && (periph1 != 0x1) &&
632 (periph2 != 0x3) && (periph1 != 0x3))
633 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
634
635 writel(mask480, &anatop->pfd_480_set);
636 writel(mask528, &anatop->pfd_528_set);
637 writel(mask480, &anatop->pfd_480_clr);
638 writel(mask528, &anatop->pfd_528_clr);
639 }
640
641 #ifdef CONFIG_IMX_HDMI
imx_enable_hdmi_phy(void)642 void imx_enable_hdmi_phy(void)
643 {
644 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
645 u8 reg;
646 reg = readb(&hdmi->phy_conf0);
647 reg |= HDMI_PHY_CONF0_PDZ_MASK;
648 writeb(reg, &hdmi->phy_conf0);
649 udelay(3000);
650 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
651 writeb(reg, &hdmi->phy_conf0);
652 udelay(3000);
653 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
654 writeb(reg, &hdmi->phy_conf0);
655 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
656 }
657
imx_setup_hdmi(void)658 void imx_setup_hdmi(void)
659 {
660 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
661 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
662 int reg, count;
663 u8 val;
664
665 /* Turn on HDMI PHY clock */
666 reg = readl(&mxc_ccm->CCGR2);
667 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
668 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
669 writel(reg, &mxc_ccm->CCGR2);
670 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
671 reg = readl(&mxc_ccm->chsccdr);
672 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
673 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
674 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
675 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
676 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
677 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
678 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
679 writel(reg, &mxc_ccm->chsccdr);
680
681 /* Clear the overflow condition */
682 if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
683 /* TMDS software reset */
684 writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz);
685 val = readb(&hdmi->fc_invidconf);
686 /* Need minimum 3 times to write to clear the register */
687 for (count = 0 ; count < 5 ; count++)
688 writeb(val, &hdmi->fc_invidconf);
689 }
690 }
691 #endif
692
693
694 /*
695 * gpr_init() function is common for boards using MX6S, MX6DL, MX6D,
696 * MX6Q and MX6QP processors
697 */
gpr_init(void)698 void gpr_init(void)
699 {
700 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
701
702 /*
703 * If this function is used in a common MX6 spl implementation
704 * we have to ensure that it is only called for suitable cpu types,
705 * otherwise it breaks hardware parts like enet1, can1, can2, etc.
706 */
707 if (!is_mx6dqp() && !is_mx6dq() && !is_mx6sdl())
708 return;
709
710 /* enable AXI cache for VDOA/VPU/IPU */
711 writel(0xF00000CF, &iomux->gpr[4]);
712 if (is_mx6dqp()) {
713 /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
714 writel(0x77177717, &iomux->gpr[6]);
715 writel(0x77177717, &iomux->gpr[7]);
716 } else {
717 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
718 writel(0x007F007F, &iomux->gpr[6]);
719 writel(0x007F007F, &iomux->gpr[7]);
720 }
721 }
722