1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2016 Stefan Roese <sr@denx.de> 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <fdtdec.h> 9 #include <init.h> 10 #include <linux/libfdt.h> 11 #include <linux/sizes.h> 12 #include <pci.h> 13 #include <asm/io.h> 14 #include <asm/system.h> 15 #include <asm/arch/cpu.h> 16 #include <asm/arch/soc.h> 17 #include <asm/armv8/mmu.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 /* 22 * Not all memory is mapped in the MMU. So we need to restrict the 23 * memory size so that U-Boot does not try to access it. Also, the 24 * internal registers are located at 0xf000.0000 - 0xffff.ffff. 25 * Currently only 2GiB are mapped for system memory. This is what 26 * we pass to the U-Boot subsystem here. 27 */ 28 #define USABLE_RAM_SIZE 0x80000000 29 board_get_usable_ram_top(ulong total_size)30ulong board_get_usable_ram_top(ulong total_size) 31 { 32 if (gd->ram_size > USABLE_RAM_SIZE) 33 return USABLE_RAM_SIZE; 34 35 return gd->ram_size; 36 } 37 38 /* 39 * On ARMv8, MBus is not configured in U-Boot. To enable compilation 40 * of the already implemented drivers, lets add a dummy version of 41 * this function so that linking does not fail. 42 */ mvebu_mbus_dram_info(void)43const struct mbus_dram_target_info *mvebu_mbus_dram_info(void) 44 { 45 return NULL; 46 } 47 48 /* DRAM init code ... */ 49 50 #define MV_SIP_DRAM_SIZE 0x82000010 51 a8k_dram_scan_ap_sz(void)52static u64 a8k_dram_scan_ap_sz(void) 53 { 54 struct pt_regs pregs; 55 56 pregs.regs[0] = MV_SIP_DRAM_SIZE; 57 pregs.regs[1] = SOC_REGS_PHY_BASE; 58 smc_call(&pregs); 59 60 return pregs.regs[0]; 61 } 62 a8k_dram_init_banksize(void)63static void a8k_dram_init_banksize(void) 64 { 65 /* 66 * The firmware (ATF) leaves a 1G whole above the 3G mark for IO 67 * devices. Higher RAM is mapped at 4G. 68 * 69 * Config 2 DRAM banks: 70 * Bank 0 - max size 4G - 1G 71 * Bank 1 - ram size - 4G + 1G 72 */ 73 phys_size_t max_bank0_size = SZ_4G - SZ_1G; 74 75 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 76 if (gd->ram_size <= max_bank0_size) { 77 gd->bd->bi_dram[0].size = gd->ram_size; 78 return; 79 } 80 81 gd->bd->bi_dram[0].size = max_bank0_size; 82 if (CONFIG_NR_DRAM_BANKS > 1) { 83 gd->bd->bi_dram[1].start = SZ_4G; 84 gd->bd->bi_dram[1].size = gd->ram_size - max_bank0_size; 85 } 86 } 87 dram_init_banksize(void)88__weak int dram_init_banksize(void) 89 { 90 if (CONFIG_IS_ENABLED(ARMADA_8K)) 91 a8k_dram_init_banksize(); 92 else 93 fdtdec_setup_memory_banksize(); 94 95 return 0; 96 } 97 dram_init(void)98__weak int dram_init(void) 99 { 100 if (CONFIG_IS_ENABLED(ARMADA_8K)) { 101 gd->ram_size = a8k_dram_scan_ap_sz(); 102 if (gd->ram_size != 0) 103 return 0; 104 } 105 106 if (fdtdec_setup_mem_size_base() != 0) 107 return -EINVAL; 108 109 return 0; 110 } 111 arch_cpu_init(void)112int arch_cpu_init(void) 113 { 114 /* Nothing to do (yet) */ 115 return 0; 116 } 117 arch_early_init_r(void)118int arch_early_init_r(void) 119 { 120 struct udevice *dev; 121 int ret; 122 int i; 123 124 /* 125 * Loop over all MISC uclass drivers to call the comphy code 126 * and init all CP110 devices enabled in the DT 127 */ 128 i = 0; 129 while (1) { 130 /* Call the comphy code via the MISC uclass driver */ 131 ret = uclass_get_device(UCLASS_MISC, i++, &dev); 132 133 /* We're done, once no further CP110 device is found */ 134 if (ret) 135 break; 136 } 137 138 /* Cause the SATA device to do its early init */ 139 uclass_first_device(UCLASS_AHCI, &dev); 140 141 #ifdef CONFIG_DM_PCI 142 /* Trigger PCIe devices detection */ 143 pci_init(); 144 #endif 145 146 return 0; 147 } 148