1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2016 Rockchip Electronics Co., Ltd
4 */
5
6 #include <common.h>
7 #include <asm/arch-rockchip/bootrom.h>
8 #include <asm/arch-rockchip/hardware.h>
9 #include <asm/arch-rockchip/grf_rk3328.h>
10 #include <asm/arch-rockchip/uart.h>
11 #include <asm/armv8/mmu.h>
12 #include <asm/io.h>
13
14 DECLARE_GLOBAL_DATA_PTR;
15
16 #define CRU_BASE 0xFF440000
17 #define GRF_BASE 0xFF100000
18 #define UART2_BASE 0xFF130000
19 #define FW_DDR_CON_REG 0xFF7C0040
20
21 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
22 [BROM_BOOTSOURCE_EMMC] = "/rksdmmc@ff520000",
23 [BROM_BOOTSOURCE_SD] = "/rksdmmc@ff500000",
24 };
25
26 static struct mm_region rk3328_mem_map[] = {
27 {
28 .virt = 0x0UL,
29 .phys = 0x0UL,
30 .size = 0xff000000UL,
31 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
32 PTE_BLOCK_INNER_SHARE
33 }, {
34 .virt = 0xff000000UL,
35 .phys = 0xff000000UL,
36 .size = 0x1000000UL,
37 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
38 PTE_BLOCK_NON_SHARE |
39 PTE_BLOCK_PXN | PTE_BLOCK_UXN
40 }, {
41 /* List terminator */
42 0,
43 }
44 };
45
46 struct mm_region *mem_map = rk3328_mem_map;
47
arch_cpu_init(void)48 int arch_cpu_init(void)
49 {
50 #ifdef CONFIG_SPL_BUILD
51 /* We do some SoC one time setting here. */
52
53 /* Disable the ddr secure region setting to make it non-secure */
54 rk_setreg(FW_DDR_CON_REG, 0x200);
55 #endif
56 return 0;
57 }
58
board_debug_uart_init(void)59 void board_debug_uart_init(void)
60 {
61 struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
62 struct rk_uart * const uart = (void *)UART2_BASE;
63 enum{
64 GPIO2A0_SEL_SHIFT = 0,
65 GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT,
66 GPIO2A0_UART2_TX_M1 = 1,
67
68 GPIO2A1_SEL_SHIFT = 2,
69 GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT,
70 GPIO2A1_UART2_RX_M1 = 1,
71 };
72 enum {
73 IOMUX_SEL_UART2_SHIFT = 0,
74 IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT,
75 IOMUX_SEL_UART2_M0 = 0,
76 IOMUX_SEL_UART2_M1,
77 };
78
79 /* uart_sel_clk default select 24MHz */
80 writel((3 << (8 + 16)) | (2 << 8), CRU_BASE + 0x148);
81
82 /* init uart baud rate 1500000 */
83 writel(0x83, &uart->lcr);
84 writel(0x1, &uart->rbr);
85 writel(0x3, &uart->lcr);
86
87 /* Enable early UART2 */
88 rk_clrsetreg(&grf->com_iomux,
89 IOMUX_SEL_UART2_MASK,
90 IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT);
91 rk_clrsetreg(&grf->gpio2a_iomux,
92 GPIO2A0_SEL_MASK,
93 GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT);
94 rk_clrsetreg(&grf->gpio2a_iomux,
95 GPIO2A1_SEL_MASK,
96 GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT);
97
98 /* enable FIFO */
99 writel(0x1, &uart->sfe);
100 }
101