1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2010,2011
4 * NVIDIA Corporation <www.nvidia.com>
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <env.h>
10 #include <errno.h>
11 #include <init.h>
12 #include <ns16550.h>
13 #include <usb.h>
14 #include <asm/io.h>
15 #include <asm/arch-tegra/ap.h>
16 #include <asm/arch-tegra/board.h>
17 #include <asm/arch-tegra/cboot.h>
18 #include <asm/arch-tegra/clk_rst.h>
19 #include <asm/arch-tegra/pmc.h>
20 #include <asm/arch-tegra/pmu.h>
21 #include <asm/arch-tegra/sys_proto.h>
22 #include <asm/arch-tegra/uart.h>
23 #include <asm/arch-tegra/warmboot.h>
24 #include <asm/arch-tegra/gpu.h>
25 #include <asm/arch-tegra/usb.h>
26 #include <asm/arch-tegra/xusb-padctl.h>
27 #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
28 #include <asm/arch/clock.h>
29 #endif
30 #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
31 #include <asm/arch/funcmux.h>
32 #include <asm/arch/pinmux.h>
33 #endif
34 #include <asm/arch/tegra.h>
35 #ifdef CONFIG_TEGRA_CLOCK_SCALING
36 #include <asm/arch/emc.h>
37 #endif
38 #include "emc.h"
39
40 DECLARE_GLOBAL_DATA_PTR;
41
42 #ifdef CONFIG_SPL_BUILD
43 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
44 U_BOOT_DEVICE(tegra_gpios) = {
45 "gpio_tegra"
46 };
47 #endif
48
pinmux_init(void)49 __weak void pinmux_init(void) {}
pin_mux_usb(void)50 __weak void pin_mux_usb(void) {}
pin_mux_spi(void)51 __weak void pin_mux_spi(void) {}
pin_mux_mmc(void)52 __weak void pin_mux_mmc(void) {}
gpio_early_init_uart(void)53 __weak void gpio_early_init_uart(void) {}
pin_mux_display(void)54 __weak void pin_mux_display(void) {}
start_cpu_fan(void)55 __weak void start_cpu_fan(void) {}
cboot_late_init(void)56 __weak void cboot_late_init(void) {}
57
58 #if defined(CONFIG_TEGRA_NAND)
pin_mux_nand(void)59 __weak void pin_mux_nand(void)
60 {
61 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
62 }
63 #endif
64
65 /*
66 * Routine: power_det_init
67 * Description: turn off power detects
68 */
power_det_init(void)69 static void power_det_init(void)
70 {
71 #if defined(CONFIG_TEGRA20)
72 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
73
74 /* turn off power detects */
75 writel(0, &pmc->pmc_pwr_det_latch);
76 writel(0, &pmc->pmc_pwr_det);
77 #endif
78 }
79
tegra_board_id(void)80 __weak int tegra_board_id(void)
81 {
82 return -1;
83 }
84
85 #ifdef CONFIG_DISPLAY_BOARDINFO
checkboard(void)86 int checkboard(void)
87 {
88 int board_id = tegra_board_id();
89
90 printf("Board: %s", CONFIG_TEGRA_BOARD_STRING);
91 if (board_id != -1)
92 printf(", ID: %d\n", board_id);
93 printf("\n");
94
95 return 0;
96 }
97 #endif /* CONFIG_DISPLAY_BOARDINFO */
98
tegra_lcd_pmic_init(int board_it)99 __weak int tegra_lcd_pmic_init(int board_it)
100 {
101 return 0;
102 }
103
nvidia_board_init(void)104 __weak int nvidia_board_init(void)
105 {
106 return 0;
107 }
108
109 /*
110 * Routine: board_init
111 * Description: Early hardware init.
112 */
board_init(void)113 int board_init(void)
114 {
115 __maybe_unused int err;
116 __maybe_unused int board_id;
117
118 /* Do clocks and UART first so that printf() works */
119 #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
120 clock_init();
121 clock_verify();
122 #endif
123
124 tegra_gpu_config();
125
126 #ifdef CONFIG_TEGRA_SPI
127 pin_mux_spi();
128 #endif
129
130 #ifdef CONFIG_MMC_SDHCI_TEGRA
131 pin_mux_mmc();
132 #endif
133
134 /* Init is handled automatically in the driver-model case */
135 #if defined(CONFIG_DM_VIDEO)
136 pin_mux_display();
137 #endif
138 /* boot param addr */
139 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
140
141 power_det_init();
142
143 #ifdef CONFIG_SYS_I2C_TEGRA
144 # ifdef CONFIG_TEGRA_PMU
145 if (pmu_set_nominal())
146 debug("Failed to select nominal voltages\n");
147 # ifdef CONFIG_TEGRA_CLOCK_SCALING
148 err = board_emc_init();
149 if (err)
150 debug("Memory controller init failed: %d\n", err);
151 # endif
152 # endif /* CONFIG_TEGRA_PMU */
153 #endif /* CONFIG_SYS_I2C_TEGRA */
154
155 #ifdef CONFIG_USB_EHCI_TEGRA
156 pin_mux_usb();
157 #endif
158
159 #if defined(CONFIG_DM_VIDEO)
160 board_id = tegra_board_id();
161 err = tegra_lcd_pmic_init(board_id);
162 if (err) {
163 debug("Failed to set up LCD PMIC\n");
164 return err;
165 }
166 #endif
167
168 #ifdef CONFIG_TEGRA_NAND
169 pin_mux_nand();
170 #endif
171
172 tegra_xusb_padctl_init();
173
174 #ifdef CONFIG_TEGRA_LP0
175 /* save Sdram params to PMC 2, 4, and 24 for WB0 */
176 warmboot_save_sdram_params();
177
178 /* prepare the WB code to LP0 location */
179 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
180 #endif
181 return nvidia_board_init();
182 }
183
184 #ifdef CONFIG_BOARD_EARLY_INIT_F
__gpio_early_init(void)185 static void __gpio_early_init(void)
186 {
187 }
188
189 void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
190
board_early_init_f(void)191 int board_early_init_f(void)
192 {
193 #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
194 if (!clock_early_init_done())
195 clock_early_init();
196 #endif
197
198 #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT)
199 #define USBCMD_FS2 (1 << 15)
200 {
201 struct usb_ctlr *usbctlr = (struct usb_ctlr *)0x7d000000;
202 writel(USBCMD_FS2, &usbctlr->usb_cmd);
203 }
204 #endif
205
206 /* Do any special system timer/TSC setup */
207 #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
208 # if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
209 if (!tegra_cpu_is_non_secure())
210 # endif
211 arch_timer_init();
212 #endif
213
214 pinmux_init();
215 board_init_uart_f();
216
217 /* Initialize periph GPIOs */
218 gpio_early_init();
219 gpio_early_init_uart();
220
221 return 0;
222 }
223 #endif /* EARLY_INIT */
224
board_late_init(void)225 int board_late_init(void)
226 {
227 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
228 if (tegra_cpu_is_non_secure()) {
229 printf("CPU is in NS mode\n");
230 env_set("cpu_ns_mode", "1");
231 } else {
232 env_set("cpu_ns_mode", "");
233 }
234 #endif
235 start_cpu_fan();
236 cboot_late_init();
237
238 return 0;
239 }
240
241 /*
242 * In some SW environments, a memory carve-out exists to house a secure
243 * monitor, a trusted OS, and/or various statically allocated media buffers.
244 *
245 * This carveout exists at the highest possible address that is within a
246 * 32-bit physical address space.
247 *
248 * This function returns the total size of this carve-out. At present, the
249 * returned value is hard-coded for simplicity. In the future, it may be
250 * possible to determine the carve-out size:
251 * - By querying some run-time information source, such as:
252 * - A structure passed to U-Boot by earlier boot software.
253 * - SoC registers.
254 * - A call into the secure monitor.
255 * - In the per-board U-Boot configuration header, based on knowledge of the
256 * SW environment that U-Boot is being built for.
257 *
258 * For now, we support two configurations in U-Boot:
259 * - 32-bit ports without any form of carve-out.
260 * - 64 bit ports which are assumed to use a carve-out of a conservatively
261 * hard-coded size.
262 */
carveout_size(void)263 static ulong carveout_size(void)
264 {
265 #ifdef CONFIG_ARM64
266 return SZ_512M;
267 #elif defined(CONFIG_ARMV7_SECURE_RESERVE_SIZE)
268 // BASE+SIZE might not == 4GB. If so, we want the carveout to cover
269 // from BASE to 4GB, not BASE to BASE+SIZE.
270 return (0 - CONFIG_ARMV7_SECURE_BASE) & ~(SZ_2M - 1);
271 #else
272 return 0;
273 #endif
274 }
275
276 /*
277 * Determine the amount of usable RAM below 4GiB, taking into account any
278 * carve-out that may be assigned.
279 */
usable_ram_size_below_4g(void)280 static ulong usable_ram_size_below_4g(void)
281 {
282 ulong total_size_below_4g;
283 ulong usable_size_below_4g;
284
285 /*
286 * The total size of RAM below 4GiB is the lesser address of:
287 * (a) 2GiB itself (RAM starts at 2GiB, and 4GiB - 2GiB == 2GiB).
288 * (b) The size RAM physically present in the system.
289 */
290 if (gd->ram_size < SZ_2G)
291 total_size_below_4g = gd->ram_size;
292 else
293 total_size_below_4g = SZ_2G;
294
295 /* Calculate usable RAM by subtracting out any carve-out size */
296 usable_size_below_4g = total_size_below_4g - carveout_size();
297
298 return usable_size_below_4g;
299 }
300
301 /*
302 * Represent all available RAM in either one or two banks.
303 *
304 * The first bank describes any usable RAM below 4GiB.
305 * The second bank describes any RAM above 4GiB.
306 *
307 * This split is driven by the following requirements:
308 * - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg
309 * property for memory below and above the 4GiB boundary. The layout of that
310 * DT property is directly driven by the entries in the U-Boot bank array.
311 * - The potential existence of a carve-out at the end of RAM below 4GiB can
312 * only be represented using multiple banks.
313 *
314 * Explicitly removing the carve-out RAM from the bank entries makes the RAM
315 * layout a bit more obvious, e.g. when running "bdinfo" at the U-Boot
316 * command-line.
317 *
318 * This does mean that the DT U-Boot passes to the Linux kernel will not
319 * include this RAM in /memory/reg at all. An alternative would be to include
320 * all RAM in the U-Boot banks (and hence DT), and add a /memreserve/ node
321 * into DT to stop the kernel from using the RAM. IIUC, I don't /think/ the
322 * Linux kernel will ever need to access any RAM in* the carve-out via a CPU
323 * mapping, so either way is acceptable.
324 *
325 * On 32-bit systems, we never define a bank for RAM above 4GiB, since the
326 * start address of that bank cannot be represented in the 32-bit .size
327 * field.
328 */
dram_init_banksize(void)329 int dram_init_banksize(void)
330 {
331 int err;
332
333 /* try to compute DRAM bank size based on cboot DTB first */
334 err = cboot_dram_init_banksize();
335 if (err == 0)
336 return err;
337
338 /* fall back to default DRAM bank size computation */
339
340 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
341 gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
342
343 #ifdef CONFIG_PCI
344 gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
345 #endif
346
347 #ifdef CONFIG_PHYS_64BIT
348 if (gd->ram_size > SZ_2G) {
349 gd->bd->bi_dram[1].start = 0x100000000;
350 gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
351 } else
352 #endif
353 {
354 gd->bd->bi_dram[1].start = 0;
355 gd->bd->bi_dram[1].size = 0;
356 }
357
358 return 0;
359 }
360
361 /*
362 * Most hardware on 64-bit Tegra is still restricted to DMA to the lower
363 * 32-bits of the physical address space. Cap the maximum usable RAM area
364 * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit
365 * boundary that most devices can address. Also, don't let U-Boot use any
366 * carve-out, as mentioned above.
367 *
368 * This function is called before dram_init_banksize(), so we can't simply
369 * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size.
370 */
board_get_usable_ram_top(ulong total_size)371 ulong board_get_usable_ram_top(ulong total_size)
372 {
373 ulong ram_top;
374
375 /* try to get top of usable RAM based on cboot DTB first */
376 ram_top = cboot_get_usable_ram_top(total_size);
377 if (ram_top > 0)
378 return ram_top;
379
380 /* fall back to default usable RAM computation */
381
382 return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
383 }
384