1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
4 */
5
6 #include <common.h>
7 #include <debug_uart.h>
8 #include <linux/io.h>
9 #include <linux/serial_reg.h>
10
11 #include "../sg-regs.h"
12 #include "../soc-info.h"
13 #include "debug-uart.h"
14
15 #define UNIPHIER_UART_TX 0x00
16 #define UNIPHIER_UART_LCR_MCR 0x10
17 #define UNIPHIER_UART_LSR 0x14
18 #define UNIPHIER_UART_LDR 0x24
19
_debug_uart_putc(int c)20 static void _debug_uart_putc(int c)
21 {
22 void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
23
24 while (!(readl(base + UNIPHIER_UART_LSR) & UART_LSR_THRE))
25 ;
26
27 writel(c, base + UNIPHIER_UART_TX);
28 }
29
30 #ifdef CONFIG_SPL_BUILD
sg_set_pinsel(unsigned int pin,unsigned int muxval,unsigned int mux_bits,unsigned int reg_stride)31 void sg_set_pinsel(unsigned int pin, unsigned int muxval,
32 unsigned int mux_bits, unsigned int reg_stride)
33 {
34 unsigned int shift = pin * mux_bits % 32;
35 void __iomem *reg = sg_base + SG_PINCTRL_BASE +
36 pin * mux_bits / 32 * reg_stride;
37 u32 mask = (1U << mux_bits) - 1;
38 u32 tmp;
39
40 tmp = readl(reg);
41 tmp &= ~(mask << shift);
42 tmp |= (mask & muxval) << shift;
43 writel(tmp, reg);
44 }
45
sg_set_iectrl(unsigned int pin)46 void sg_set_iectrl(unsigned int pin)
47 {
48 unsigned int bit = pin % 32;
49 void __iomem *reg = sg_base + SG_IECTRL + pin / 32 * 4;
50 u32 tmp;
51
52 tmp = readl(reg);
53 tmp |= 1 << bit;
54 writel(tmp, reg);
55 }
56 #endif
57
_debug_uart_init(void)58 void _debug_uart_init(void)
59 {
60 #ifdef CONFIG_SPL_BUILD
61 void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
62 unsigned int divisor;
63
64 switch (uniphier_get_soc_id()) {
65 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
66 case UNIPHIER_LD4_ID:
67 divisor = uniphier_ld4_debug_uart_init();
68 break;
69 #endif
70 #if defined(CONFIG_ARCH_UNIPHIER_PRO4)
71 case UNIPHIER_PRO4_ID:
72 divisor = uniphier_pro4_debug_uart_init();
73 break;
74 #endif
75 #if defined(CONFIG_ARCH_UNIPHIER_SLD8)
76 case UNIPHIER_SLD8_ID:
77 divisor = uniphier_sld8_debug_uart_init();
78 break;
79 #endif
80 #if defined(CONFIG_ARCH_UNIPHIER_PRO5)
81 case UNIPHIER_PRO5_ID:
82 divisor = uniphier_pro5_debug_uart_init();
83 break;
84 #endif
85 #if defined(CONFIG_ARCH_UNIPHIER_PXS2)
86 case UNIPHIER_PXS2_ID:
87 divisor = uniphier_pxs2_debug_uart_init();
88 break;
89 #endif
90 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
91 case UNIPHIER_LD6B_ID:
92 divisor = uniphier_ld6b_debug_uart_init();
93 break;
94 #endif
95 default:
96 return;
97 }
98
99 writel(UART_LCR_WLEN8 << 8, base + UNIPHIER_UART_LCR_MCR);
100
101 writel(divisor, base + UNIPHIER_UART_LDR);
102 #endif
103 }
104 DEBUG_UART_FUNCS
105