1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2012 Xilinx, Inc. All rights reserved.
5 */
6 #include <common.h>
7 #include <cpu_func.h>
8 #include <zynqpl.h>
9 #include <asm/io.h>
10 #include <asm/arch/clk.h>
11 #include <asm/arch/hardware.h>
12 #include <asm/arch/ps7_init_gpl.h>
13 #include <asm/arch/sys_proto.h>
14
15 #define ZYNQ_SILICON_VER_MASK 0xF0000000
16 #define ZYNQ_SILICON_VER_SHIFT 28
17
18 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
19 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
20 xilinx_desc fpga = {
21 .family = xilinx_zynq,
22 .iface = devcfg,
23 .operations = &zynq_op,
24 };
25 #endif
26
27 static const struct {
28 u8 idcode;
29 #if defined(CONFIG_FPGA)
30 u32 fpga_size;
31 #endif
32 char *devicename;
33 } zynq_fpga_descs[] = {
34 ZYNQ_DESC(7Z007S),
35 ZYNQ_DESC(7Z010),
36 ZYNQ_DESC(7Z012S),
37 ZYNQ_DESC(7Z014S),
38 ZYNQ_DESC(7Z015),
39 ZYNQ_DESC(7Z020),
40 ZYNQ_DESC(7Z030),
41 ZYNQ_DESC(7Z035),
42 ZYNQ_DESC(7Z045),
43 ZYNQ_DESC(7Z100),
44 { /* Sentinel */ },
45 };
46
arch_cpu_init(void)47 int arch_cpu_init(void)
48 {
49 zynq_slcr_unlock();
50 #ifndef CONFIG_SPL_BUILD
51 /* Device config APB, unlock the PCAP */
52 writel(0x757BDF0D, &devcfg_base->unlock);
53 writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
54
55 #if (CONFIG_SYS_SDRAM_BASE == 0)
56 /* remap DDR to zero, FILTERSTART */
57 writel(0, &scu_base->filter_start);
58
59 /* OCM_CFG, Mask out the ROM, map ram into upper addresses */
60 writel(0x1F, &slcr_base->ocm_cfg);
61 /* FPGA_RST_CTRL, clear resets on AXI fabric ports */
62 writel(0x0, &slcr_base->fpga_rst_ctrl);
63 /* Set urgent bits with register */
64 writel(0x0, &slcr_base->ddr_urgent_sel);
65 /* Urgent write, ports S2/S3 */
66 writel(0xC, &slcr_base->ddr_urgent);
67 #endif
68 #endif
69 zynq_slcr_lock();
70
71 return 0;
72 }
73
zynq_get_silicon_version(void)74 unsigned int zynq_get_silicon_version(void)
75 {
76 return (readl(&devcfg_base->mctrl) & ZYNQ_SILICON_VER_MASK)
77 >> ZYNQ_SILICON_VER_SHIFT;
78 }
79
reset_cpu(ulong addr)80 void reset_cpu(ulong addr)
81 {
82 zynq_slcr_cpu_reset();
83 while (1)
84 ;
85 }
86
87 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
enable_caches(void)88 void enable_caches(void)
89 {
90 /* Enable D-cache. I-cache is already enabled in start.S */
91 dcache_enable();
92 }
93 #endif
94
cpu_desc_id(void)95 static int __maybe_unused cpu_desc_id(void)
96 {
97 u32 idcode;
98 u8 i;
99
100 idcode = zynq_slcr_get_idcode();
101 for (i = 0; zynq_fpga_descs[i].idcode; i++) {
102 if (zynq_fpga_descs[i].idcode == idcode)
103 return i;
104 }
105
106 return -ENODEV;
107 }
108
109 #if defined(CONFIG_ARCH_EARLY_INIT_R)
arch_early_init_r(void)110 int arch_early_init_r(void)
111 {
112 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
113 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
114 int cpu_id = cpu_desc_id();
115
116 if (cpu_id < 0)
117 return 0;
118
119 fpga.size = zynq_fpga_descs[cpu_id].fpga_size;
120 fpga.name = zynq_fpga_descs[cpu_id].devicename;
121 fpga_init();
122 fpga_add(fpga_xilinx, &fpga);
123 #endif
124 return 0;
125 }
126 #endif
127
128 #ifdef CONFIG_DISPLAY_CPUINFO
print_cpuinfo(void)129 int print_cpuinfo(void)
130 {
131 u32 version;
132 int cpu_id = cpu_desc_id();
133
134 if (cpu_id < 0)
135 return 0;
136
137 version = zynq_get_silicon_version() << 1;
138 if (version > (PCW_SILICON_VERSION_3 << 1))
139 version += 1;
140
141 printf("CPU: Zynq %s\n", zynq_fpga_descs[cpu_id].devicename);
142 printf("Silicon: v%d.%d\n", version >> 1, version & 1);
143 return 0;
144 }
145 #endif
146