1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 *
4 * (C) Copyright 2000-2003
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
8 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
9 */
10
11 #include <common.h>
12 #include <cpu_func.h>
13 #include <watchdog.h>
14
15 #include <asm/immap.h>
16 #include <asm/io.h>
17 #include <asm/rtc.h>
18 #include <linux/compiler.h>
19
cfspi_port_conf(void)20 void cfspi_port_conf(void)
21 {
22 gpio_t *gpio = (gpio_t *)MMAP_GPIO;
23
24 out_8(&gpio->par_dspi,
25 GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
26 GPIO_PAR_DSPI_SCK_SCK);
27 }
28
29 /*
30 * Breath some life into the CPU...
31 *
32 * Set up the memory map,
33 * initialize a bunch of registers,
34 * initialize the UPM's
35 */
cpu_init_f(void)36 void cpu_init_f(void)
37 {
38 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
39 fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
40
41 #if !defined(CONFIG_CF_SBF)
42 scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
43 pll_t *pll = (pll_t *)MMAP_PLL;
44
45 /* Workaround, must place before fbcs */
46 out_be32(&pll->psr, 0x12);
47
48 out_be32(&scm1->mpr, 0x77777777);
49 out_be32(&scm1->pacra, 0);
50 out_be32(&scm1->pacrb, 0);
51 out_be32(&scm1->pacrc, 0);
52 out_be32(&scm1->pacrd, 0);
53 out_be32(&scm1->pacre, 0);
54 out_be32(&scm1->pacrf, 0);
55 out_be32(&scm1->pacrg, 0);
56 out_be32(&scm1->pacri, 0);
57
58 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
59 && defined(CONFIG_SYS_CS0_CTRL))
60 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
61 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
62 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
63 #endif
64 #endif /* CONFIG_CF_SBF */
65
66 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
67 && defined(CONFIG_SYS_CS1_CTRL))
68 out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
69 out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
70 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
71 #endif
72
73 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
74 && defined(CONFIG_SYS_CS2_CTRL))
75 out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
76 out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
77 out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
78 #endif
79
80 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
81 && defined(CONFIG_SYS_CS3_CTRL))
82 out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
83 out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
84 out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
85 #endif
86
87 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
88 && defined(CONFIG_SYS_CS4_CTRL))
89 out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
90 out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
91 out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
92 #endif
93
94 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
95 && defined(CONFIG_SYS_CS5_CTRL))
96 out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
97 out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
98 out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
99 #endif
100
101 #ifdef CONFIG_SYS_I2C_FSL
102 out_8(&gpio->par_i2c, GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA);
103 #endif
104
105 icache_enable();
106
107 cfspi_port_conf();
108 }
109
110 /*
111 * initialize higher level parts of CPU like timers
112 */
cpu_init_r(void)113 int cpu_init_r(void)
114 {
115 #ifdef CONFIG_MCFRTC
116 rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
117 rtcex_t *rtcex = (rtcex_t *)&rtc->extended;
118
119 out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
120 out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
121 #endif
122
123 return (0);
124 }
125
uart_port_conf(int port)126 void uart_port_conf(int port)
127 {
128 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
129
130 /* Setup Ports: */
131 switch (port) {
132 case 0:
133 clrbits_be16(&gpio->par_uart,
134 ~(GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK));
135 setbits_be16(&gpio->par_uart,
136 GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
137 break;
138 case 1:
139 clrbits_be16(&gpio->par_uart,
140 ~(GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK));
141 setbits_be16(&gpio->par_uart,
142 GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
143 break;
144 case 2:
145 clrbits_8(&gpio->par_dspi,
146 ~(GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK));
147 out_8(&gpio->par_dspi,
148 GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
149 break;
150 }
151 }
152