1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2006,2009-2010 Freescale Semiconductor, Inc.
4 * Jeff Brown
5 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 */
7
8 #include <common.h>
9 #include <cpu_func.h>
10 #include <vsprintf.h>
11 #include <watchdog.h>
12 #include <command.h>
13 #include <asm/cache.h>
14 #include <asm/mmu.h>
15 #include <mpc86xx.h>
16 #include <asm/fsl_law.h>
17 #include <asm/ppc.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
21 /*
22 * Default board reset function
23 */
24 static void
__board_reset(void)25 __board_reset(void)
26 {
27 /* Do nothing */
28 }
29 void board_reset(void) __attribute__((weak, alias("__board_reset")));
30
31
32 int
checkcpu(void)33 checkcpu(void)
34 {
35 sys_info_t sysinfo;
36 uint pvr, svr;
37 uint major, minor;
38 char buf1[32], buf2[32];
39 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
40 volatile ccsr_gur_t *gur = &immap->im_gur;
41 struct cpu_type *cpu;
42 uint msscr0 = mfspr(MSSCR0);
43
44 svr = get_svr();
45 major = SVR_MAJ(svr);
46 minor = SVR_MIN(svr);
47
48 if (cpu_numcores() > 1) {
49 #ifndef CONFIG_MP
50 puts("Unicore software on multiprocessor system!!\n"
51 "To enable mutlticore build define CONFIG_MP\n");
52 #endif
53 }
54 puts("CPU: ");
55
56 cpu = gd->arch.cpu;
57
58 puts(cpu->name);
59
60 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
61 puts("Core: ");
62
63 pvr = get_pvr();
64 major = PVR_E600_MAJ(pvr);
65 minor = PVR_E600_MIN(pvr);
66
67 printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0);
68 if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
69 puts("\n Core1Translation Enabled");
70 debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
71
72 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
73
74 get_sys_info(&sysinfo);
75
76 puts("Clock Configuration:\n");
77 printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freq_processor));
78 printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
79 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
80 strmhz(buf1, sysinfo.freq_systembus / 2),
81 strmhz(buf2, sysinfo.freq_systembus));
82
83 if (sysinfo.freq_localbus > LCRR_CLKDIV) {
84 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
85 } else {
86 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
87 sysinfo.freq_localbus);
88 }
89
90 puts("L1: D-cache 32 KiB enabled\n");
91 puts(" I-cache 32 KiB enabled\n");
92
93 puts("L2: ");
94 if (get_l2cr() & 0x80000000) {
95 #if defined(CONFIG_ARCH_MPC8610)
96 puts("256");
97 #elif defined(CONFIG_ARCH_MPC8641)
98 puts("512");
99 #endif
100 puts(" KiB enabled\n");
101 } else {
102 puts("Disabled\n");
103 }
104
105 return 0;
106 }
107
108
do_reset(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])109 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
110 {
111 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
112 volatile ccsr_gur_t *gur = &immap->im_gur;
113
114 /* Attempt board-specific reset */
115 board_reset();
116
117 /* Next try asserting HRESET_REQ */
118 out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ);
119
120 while (1)
121 ;
122
123 return 1;
124 }
125
126
127 /*
128 * Get timebase clock frequency
129 */
130 unsigned long
get_tbclk(void)131 get_tbclk(void)
132 {
133 sys_info_t sys_info;
134
135 get_sys_info(&sys_info);
136 return (sys_info.freq_systembus + 3L) / 4L;
137 }
138
139
140 #if defined(CONFIG_WATCHDOG)
141 void
watchdog_reset(void)142 watchdog_reset(void)
143 {
144 #if defined(CONFIG_ARCH_MPC8610)
145 /*
146 * This actually feed the hard enabled watchdog.
147 */
148 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
149 volatile ccsr_wdt_t *wdt = &immap->im_wdt;
150 volatile ccsr_gur_t *gur = &immap->im_gur;
151 u32 tmp = gur->pordevsr;
152
153 if (tmp & 0x4000) {
154 wdt->swsrr = 0x556c;
155 wdt->swsrr = 0xaa39;
156 }
157 #endif
158 }
159 #endif /* CONFIG_WATCHDOG */
160
161 /*
162 * Print out the state of various machine registers.
163 * Currently prints out LAWs, BR0/OR0, and BATs
164 */
print_reginfo(void)165 void print_reginfo(void)
166 {
167 print_bats();
168 print_laws();
169 print_lbc_regs();
170 }
171
172 /*
173 * Set the DDR BATs to reflect the actual size of DDR.
174 *
175 * dram_size is the actual size of DDR, in bytes
176 *
177 * Note: we assume that CONFIG_MAX_MEM_MAPPED is 2G or smaller as we only
178 * are using a single BAT to cover DDR.
179 *
180 * If this is not true, (e.g. CONFIG_MAX_MEM_MAPPED is 2GB but HID0_XBSEN
181 * is not defined) then we might have a situation where U-Boot will attempt
182 * to relocated itself outside of the region mapped by DBAT0.
183 * This will cause a machine check.
184 *
185 * Currently we are limited to power of two sized DDR since we only use a
186 * single bat. If a non-power of two size is used that is less than
187 * CONFIG_MAX_MEM_MAPPED u-boot will crash.
188 *
189 */
setup_ddr_bat(phys_addr_t dram_size)190 void setup_ddr_bat(phys_addr_t dram_size)
191 {
192 unsigned long batu, bl;
193
194 bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED));
195
196 if (BATU_SIZE(bl) != dram_size) {
197 u64 sz = (u64)dram_size - BATU_SIZE(bl);
198 print_size(sz, " left unmapped\n");
199 }
200
201 batu = bl | BATU_VS | BATU_VP;
202 write_bat(DBAT0, batu, CONFIG_SYS_DBAT0L);
203 write_bat(IBAT0, batu, CONFIG_SYS_IBAT0L);
204 }
205