1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2000-2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 */
6
7 /*
8 * m8xx.c
9 *
10 * CPU specific code
11 *
12 * written or collected and sometimes rewritten by
13 * Magnus Damm <damm@bitsmart.com>
14 *
15 * minor modifications by
16 * Wolfgang Denk <wd@denx.de>
17 */
18
19 #include <common.h>
20 #include <cpu_func.h>
21 #include <vsprintf.h>
22 #include <watchdog.h>
23 #include <command.h>
24 #include <mpc8xx.h>
25 #include <netdev.h>
26 #include <asm/cache.h>
27 #include <asm/cpm_8xx.h>
28 #include <linux/compiler.h>
29 #include <asm/io.h>
30
31 #if defined(CONFIG_OF_LIBFDT)
32 #include <linux/libfdt.h>
33 #include <fdt_support.h>
34 #endif
35
36 DECLARE_GLOBAL_DATA_PTR;
37
38 /* ------------------------------------------------------------------------- */
39 /* L1 i-cache */
40
checkicache(void)41 int checkicache(void)
42 {
43 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
44 memctl8xx_t __iomem *memctl = &immap->im_memctl;
45 u32 cacheon = rd_ic_cst() & IDC_ENABLED;
46 /* probe in flash memoryarea */
47 u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
48 u32 m;
49 u32 lines = -1;
50
51 wr_ic_cst(IDC_UNALL);
52 wr_ic_cst(IDC_INVALL);
53 wr_ic_cst(IDC_DISABLE);
54 __asm__ volatile ("isync");
55
56 while (!((m = rd_ic_cst()) & IDC_CERR2)) {
57 wr_ic_adr(k);
58 wr_ic_cst(IDC_LDLCK);
59 __asm__ volatile ("isync");
60
61 lines++;
62 k += 0x10; /* the number of bytes in a cacheline */
63 }
64
65 wr_ic_cst(IDC_UNALL);
66 wr_ic_cst(IDC_INVALL);
67
68 if (cacheon)
69 wr_ic_cst(IDC_ENABLE);
70 else
71 wr_ic_cst(IDC_DISABLE);
72
73 __asm__ volatile ("isync");
74
75 return lines << 4;
76 };
77
78 /* ------------------------------------------------------------------------- */
79 /* L1 d-cache */
80 /* call with cache disabled */
81
checkdcache(void)82 static int checkdcache(void)
83 {
84 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
85 memctl8xx_t __iomem *memctl = &immap->im_memctl;
86 u32 cacheon = rd_dc_cst() & IDC_ENABLED;
87 /* probe in flash memoryarea */
88 u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
89 u32 m;
90 u32 lines = -1;
91
92 wr_dc_cst(IDC_UNALL);
93 wr_dc_cst(IDC_INVALL);
94 wr_dc_cst(IDC_DISABLE);
95
96 while (!((m = rd_dc_cst()) & IDC_CERR2)) {
97 wr_dc_adr(k);
98 wr_dc_cst(IDC_LDLCK);
99 lines++;
100 k += 0x10; /* the number of bytes in a cacheline */
101 }
102
103 wr_dc_cst(IDC_UNALL);
104 wr_dc_cst(IDC_INVALL);
105
106 if (cacheon)
107 wr_dc_cst(IDC_ENABLE);
108 else
109 wr_dc_cst(IDC_DISABLE);
110
111 return lines << 4;
112 };
113
check_CPU(long clock,uint pvr,uint immr)114 static int check_CPU(long clock, uint pvr, uint immr)
115 {
116 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
117 uint k;
118 char buf[32];
119
120 /* the highest 16 bits should be 0x0050 for a 860 */
121
122 if (PVR_VER(pvr) != PVR_VER(PVR_8xx))
123 return -1;
124
125 k = (immr << 16) |
126 in_be16(&immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]);
127
128 /*
129 * Some boards use sockets so different CPUs can be used.
130 * We have to check chip version in run time.
131 */
132 switch (k) {
133 /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
134 case 0x08010004: /* Rev. A.0 */
135 printf("MPC866xxxZPnnA");
136 break;
137 case 0x08000003: /* Rev. 0.3 */
138 printf("MPC866xxxZPnn");
139 break;
140 case 0x09000000: /* 870/875/880/885 */
141 puts("MPC885ZPnn");
142 break;
143
144 default:
145 printf("unknown MPC86x (0x%08x)", k);
146 break;
147 }
148
149 printf(" at %s MHz: ", strmhz(buf, clock));
150
151 print_size(checkicache(), " I-Cache ");
152 print_size(checkdcache(), " D-Cache");
153
154 /* do we have a FEC (860T/P or 852/859/866/885)? */
155
156 out_be32(&immap->im_cpm.cp_fec.fec_addr_low, 0x12345678);
157 if (in_be32(&immap->im_cpm.cp_fec.fec_addr_low) == 0x12345678)
158 printf(" FEC present");
159
160 putc('\n');
161
162 return 0;
163 }
164
165 /* ------------------------------------------------------------------------- */
166
checkcpu(void)167 int checkcpu(void)
168 {
169 ulong clock = gd->cpu_clk;
170 uint immr = get_immr(); /* Return full IMMR contents */
171 uint pvr = get_pvr();
172
173 puts("CPU: ");
174
175 return check_CPU(clock, pvr, immr);
176 }
177
178 /* ------------------------------------------------------------------------- */
179
upmconfig(uint upm,uint * table,uint size)180 void upmconfig(uint upm, uint *table, uint size)
181 {
182 uint i;
183 uint addr = 0;
184 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
185 memctl8xx_t __iomem *memctl = &immap->im_memctl;
186
187 for (i = 0; i < size; i++) {
188 out_be32(&memctl->memc_mdr, table[i]); /* (16-15) */
189 out_be32(&memctl->memc_mcr, addr | upm); /* (16-16) */
190 addr++;
191 }
192 }
193
194 /* ------------------------------------------------------------------------- */
195
do_reset(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])196 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
197 {
198 ulong msr, addr;
199
200 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
201
202 /* Checkstop Reset enable */
203 setbits_be32(&immap->im_clkrst.car_plprcr, PLPRCR_CSR);
204
205 /* Interrupts and MMU off */
206 __asm__ volatile ("mtspr 81, 0");
207 __asm__ volatile ("mfmsr %0" : "=r" (msr));
208
209 msr &= ~0x1030;
210 __asm__ volatile ("mtmsr %0" : : "r" (msr));
211
212 /*
213 * Trying to execute the next instruction at a non-existing address
214 * should cause a machine check, resulting in reset
215 */
216 #ifdef CONFIG_SYS_RESET_ADDRESS
217 addr = CONFIG_SYS_RESET_ADDRESS;
218 #else
219 /*
220 * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
221 * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid address.
222 * Better pick an address known to be invalid on your system and assign
223 * it to CONFIG_SYS_RESET_ADDRESS.
224 * "(ulong)-1" used to be a good choice for many systems...
225 */
226 addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong);
227 #endif
228 ((void (*)(void)) addr)();
229 return 1;
230 }
231
232 /* ------------------------------------------------------------------------- */
233
234 /*
235 * Get timebase clock frequency (like cpu_clk in Hz)
236 *
237 * See sections 14.2 and 14.6 of the User's Manual
238 */
get_tbclk(void)239 unsigned long get_tbclk(void)
240 {
241 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
242 ulong oscclk, factor, pll;
243
244 if (in_be32(&immap->im_clkrst.car_sccr) & SCCR_TBS)
245 return gd->cpu_clk / 16;
246
247 pll = in_be32(&immap->im_clkrst.car_plprcr);
248
249 #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
250
251 /*
252 * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication
253 * factor is calculated as follows:
254 *
255 * MFN
256 * MFI + -------
257 * MFD + 1
258 * factor = -----------------
259 * (PDF + 1) * 2^S
260 *
261 */
262 factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD) + 1)) /
263 (PLPRCR_val(PDF) + 1) / (1 << PLPRCR_val(S));
264
265 oscclk = gd->cpu_clk / factor;
266
267 if ((in_be32(&immap->im_clkrst.car_sccr) & SCCR_RTSEL) == 0 ||
268 factor > 2)
269 return oscclk / 4;
270
271 return oscclk / 16;
272 }
273
274 /*
275 * Initializes on-chip ethernet controllers.
276 * to override, implement board_eth_init()
277 */
cpu_eth_init(bd_t * bis)278 int cpu_eth_init(bd_t *bis)
279 {
280 #if defined(CONFIG_MPC8XX_FEC)
281 fec_initialize(bis);
282 #endif
283 return 0;
284 }
285