1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2019, Rick Chen <rick@andestech.com>
4 *
5 * U-Boot syscon driver for Andes's Platform Level Interrupt Controller (PLIC).
6 * The PLIC block holds memory-mapped claim and pending registers
7 * associated with software interrupt.
8 */
9
10 #include <common.h>
11 #include <dm.h>
12 #include <dm/device-internal.h>
13 #include <dm/lists.h>
14 #include <dm/uclass-internal.h>
15 #include <regmap.h>
16 #include <syscon.h>
17 #include <asm/io.h>
18 #include <asm/syscon.h>
19 #include <cpu.h>
20
21 /* pending register */
22 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4)
23 /* enable register */
24 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
25 /* claim register */
26 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000)
27
28 #define ENABLE_HART_IPI (0x80808080)
29 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart))
30
31 DECLARE_GLOBAL_DATA_PTR;
32 static int init_plic(void);
33
34 #define PLIC_BASE_GET(void) \
35 do { \
36 long *ret; \
37 \
38 if (!gd->arch.plic) { \
39 ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
40 if (IS_ERR(ret)) \
41 return PTR_ERR(ret); \
42 gd->arch.plic = ret; \
43 init_plic(); \
44 } \
45 } while (0)
46
enable_ipi(int hart)47 static int enable_ipi(int hart)
48 {
49 unsigned int en;
50
51 en = ENABLE_HART_IPI >> hart;
52 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart));
53
54 return 0;
55 }
56
init_plic(void)57 static int init_plic(void)
58 {
59 struct udevice *dev;
60 ofnode node;
61 int ret;
62 u32 reg;
63
64 ret = uclass_find_first_device(UCLASS_CPU, &dev);
65 if (ret)
66 return ret;
67
68 if (ret == 0 && dev) {
69 ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
70 const char *device_type;
71
72 device_type = ofnode_read_string(node, "device_type");
73 if (!device_type)
74 continue;
75
76 if (strcmp(device_type, "cpu"))
77 continue;
78
79 /* skip if hart is marked as not available */
80 if (!ofnode_is_available(node))
81 continue;
82
83 /* read hart ID of CPU */
84 ret = ofnode_read_u32(node, "reg", ®);
85 if (ret == 0)
86 enable_ipi(reg);
87 }
88
89 return 0;
90 }
91
92 return -ENODEV;
93 }
94
riscv_send_ipi(int hart)95 int riscv_send_ipi(int hart)
96 {
97 unsigned int ipi;
98
99 PLIC_BASE_GET();
100
101 ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
102 writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic,
103 gd->arch.boot_hart));
104
105 return 0;
106 }
107
riscv_clear_ipi(int hart)108 int riscv_clear_ipi(int hart)
109 {
110 u32 source_id;
111
112 PLIC_BASE_GET();
113
114 source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
115 writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart));
116
117 return 0;
118 }
119
riscv_get_ipi(int hart,int * pending)120 int riscv_get_ipi(int hart, int *pending)
121 {
122 PLIC_BASE_GET();
123
124 *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
125 gd->arch.boot_hart));
126 *pending = !!(*pending & SEND_IPI_TO_HART(hart));
127
128 return 0;
129 }
130
131 static const struct udevice_id andes_plic_ids[] = {
132 { .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
133 { }
134 };
135
136 U_BOOT_DRIVER(andes_plic) = {
137 .name = "andes_plic",
138 .id = UCLASS_SYSCON,
139 .of_match = andes_plic_ids,
140 .flags = DM_FLAG_PRE_RELOC,
141 };
142