1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2008-2011
4 * Graeme Russ, <graeme.russ@gmail.com>
5 *
6 * (C) Copyright 2002
7 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
8 *
9 * (C) Copyright 2002
10 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
11 * Marius Groeger <mgroeger@sysgo.de>
12 *
13 * (C) Copyright 2002
14 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
15 * Alex Zuepke <azu@sysgo.de>
16 *
17 * Part of this file is adapted from coreboot
18 * src/arch/x86/lib/cpu.c
19 */
20
21 #include <common.h>
22 #include <acpi_s3.h>
23 #include <command.h>
24 #include <cpu_func.h>
25 #include <dm.h>
26 #include <errno.h>
27 #include <malloc.h>
28 #include <syscon.h>
29 #include <asm/acpi.h>
30 #include <asm/acpi_table.h>
31 #include <asm/control_regs.h>
32 #include <asm/coreboot_tables.h>
33 #include <asm/cpu.h>
34 #include <asm/lapic.h>
35 #include <asm/microcode.h>
36 #include <asm/mp.h>
37 #include <asm/mrccache.h>
38 #include <asm/msr.h>
39 #include <asm/mtrr.h>
40 #include <asm/post.h>
41 #include <asm/processor.h>
42 #include <asm/processor-flags.h>
43 #include <asm/interrupt.h>
44 #include <asm/tables.h>
45 #include <linux/compiler.h>
46
47 DECLARE_GLOBAL_DATA_PTR;
48
49 static const char *const x86_vendor_name[] = {
50 [X86_VENDOR_INTEL] = "Intel",
51 [X86_VENDOR_CYRIX] = "Cyrix",
52 [X86_VENDOR_AMD] = "AMD",
53 [X86_VENDOR_UMC] = "UMC",
54 [X86_VENDOR_NEXGEN] = "NexGen",
55 [X86_VENDOR_CENTAUR] = "Centaur",
56 [X86_VENDOR_RISE] = "Rise",
57 [X86_VENDOR_TRANSMETA] = "Transmeta",
58 [X86_VENDOR_NSC] = "NSC",
59 [X86_VENDOR_SIS] = "SiS",
60 };
61
x86_cleanup_before_linux(void)62 int __weak x86_cleanup_before_linux(void)
63 {
64 #ifdef CONFIG_BOOTSTAGE_STASH
65 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
66 CONFIG_BOOTSTAGE_STASH_SIZE);
67 #endif
68
69 return 0;
70 }
71
x86_init_cache(void)72 int x86_init_cache(void)
73 {
74 enable_caches();
75
76 return 0;
77 }
78 int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
79
flush_cache(unsigned long dummy1,unsigned long dummy2)80 void flush_cache(unsigned long dummy1, unsigned long dummy2)
81 {
82 asm("wbinvd\n");
83 }
84
85 /* Define these functions to allow ehch-hcd to function */
flush_dcache_range(unsigned long start,unsigned long stop)86 void flush_dcache_range(unsigned long start, unsigned long stop)
87 {
88 }
89
invalidate_dcache_range(unsigned long start,unsigned long stop)90 void invalidate_dcache_range(unsigned long start, unsigned long stop)
91 {
92 }
93
dcache_enable(void)94 void dcache_enable(void)
95 {
96 enable_caches();
97 }
98
dcache_disable(void)99 void dcache_disable(void)
100 {
101 disable_caches();
102 }
103
icache_enable(void)104 void icache_enable(void)
105 {
106 }
107
icache_disable(void)108 void icache_disable(void)
109 {
110 }
111
icache_status(void)112 int icache_status(void)
113 {
114 return 1;
115 }
116
cpu_vendor_name(int vendor)117 const char *cpu_vendor_name(int vendor)
118 {
119 const char *name;
120 name = "<invalid cpu vendor>";
121 if (vendor < ARRAY_SIZE(x86_vendor_name) &&
122 x86_vendor_name[vendor])
123 name = x86_vendor_name[vendor];
124
125 return name;
126 }
127
cpu_get_name(char * name)128 char *cpu_get_name(char *name)
129 {
130 unsigned int *name_as_ints = (unsigned int *)name;
131 struct cpuid_result regs;
132 char *ptr;
133 int i;
134
135 /* This bit adds up to 48 bytes */
136 for (i = 0; i < 3; i++) {
137 regs = cpuid(0x80000002 + i);
138 name_as_ints[i * 4 + 0] = regs.eax;
139 name_as_ints[i * 4 + 1] = regs.ebx;
140 name_as_ints[i * 4 + 2] = regs.ecx;
141 name_as_ints[i * 4 + 3] = regs.edx;
142 }
143 name[CPU_MAX_NAME_LEN - 1] = '\0';
144
145 /* Skip leading spaces. */
146 ptr = name;
147 while (*ptr == ' ')
148 ptr++;
149
150 return ptr;
151 }
152
default_print_cpuinfo(void)153 int default_print_cpuinfo(void)
154 {
155 printf("CPU: %s, vendor %s, device %xh\n",
156 cpu_has_64bit() ? "x86_64" : "x86",
157 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
158
159 #ifdef CONFIG_HAVE_ACPI_RESUME
160 debug("ACPI previous sleep state: %s\n",
161 acpi_ss_string(gd->arch.prev_sleep_state));
162 #endif
163
164 return 0;
165 }
166
show_boot_progress(int val)167 void show_boot_progress(int val)
168 {
169 outb(val, POST_PORT);
170 }
171
172 #if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB)
173 /*
174 * Implement a weak default function for boards that optionally
175 * need to clean up the system before jumping to the kernel.
176 */
board_final_cleanup(void)177 __weak void board_final_cleanup(void)
178 {
179 }
180
last_stage_init(void)181 int last_stage_init(void)
182 {
183 struct acpi_fadt __maybe_unused *fadt;
184
185 board_final_cleanup();
186
187 #ifdef CONFIG_HAVE_ACPI_RESUME
188 fadt = acpi_find_fadt();
189
190 if (fadt && gd->arch.prev_sleep_state == ACPI_S3)
191 acpi_resume(fadt);
192 #endif
193
194 write_tables();
195
196 #ifdef CONFIG_GENERATE_ACPI_TABLE
197 fadt = acpi_find_fadt();
198
199 /* Don't touch ACPI hardware on HW reduced platforms */
200 if (fadt && !(fadt->flags & ACPI_FADT_HW_REDUCED_ACPI)) {
201 /*
202 * Other than waiting for OSPM to request us to switch to ACPI
203 * mode, do it by ourselves, since SMI will not be triggered.
204 */
205 enter_acpi_mode(fadt->pm1a_cnt_blk);
206 }
207 #endif
208
209 return 0;
210 }
211 #endif
212
x86_init_cpus(void)213 static int x86_init_cpus(void)
214 {
215 #ifdef CONFIG_SMP
216 debug("Init additional CPUs\n");
217 x86_mp_init();
218 #else
219 struct udevice *dev;
220
221 /*
222 * This causes the cpu-x86 driver to be probed.
223 * We don't check return value here as we want to allow boards
224 * which have not been converted to use cpu uclass driver to boot.
225 */
226 uclass_first_device(UCLASS_CPU, &dev);
227 #endif
228
229 return 0;
230 }
231
cpu_init_r(void)232 int cpu_init_r(void)
233 {
234 struct udevice *dev;
235 int ret;
236
237 if (!ll_boot_init())
238 return 0;
239
240 ret = x86_init_cpus();
241 if (ret)
242 return ret;
243
244 /*
245 * Set up the northbridge, PCH and LPC if available. Note that these
246 * may have had some limited pre-relocation init if they were probed
247 * before relocation, but this is post relocation.
248 */
249 uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
250 uclass_first_device(UCLASS_PCH, &dev);
251 uclass_first_device(UCLASS_LPC, &dev);
252
253 /* Set up pin control if available */
254 ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
255 debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret);
256
257 return 0;
258 }
259
260 #ifndef CONFIG_EFI_STUB
reserve_arch(void)261 int reserve_arch(void)
262 {
263 #ifdef CONFIG_ENABLE_MRC_CACHE
264 mrccache_reserve();
265 #endif
266
267 #ifdef CONFIG_SEABIOS
268 high_table_reserve();
269 #endif
270
271 #ifdef CONFIG_HAVE_ACPI_RESUME
272 acpi_s3_reserve();
273
274 #ifdef CONFIG_HAVE_FSP
275 /*
276 * Save stack address to CMOS so that at next S3 boot,
277 * we can use it as the stack address for fsp_contiue()
278 */
279 fsp_save_s3_stack();
280 #endif /* CONFIG_HAVE_FSP */
281 #endif /* CONFIG_HAVE_ACPI_RESUME */
282
283 return 0;
284 }
285 #endif
286