1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
4 * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz>
5 *
6 * Derived from the code for
7 * Marvell/db-88f6820-gp by Stefan Roese <sr@denx.de>
8 */
9
10 #include <common.h>
11 #include <env.h>
12 #include <i2c.h>
13 #include <init.h>
14 #include <miiphy.h>
15 #include <netdev.h>
16 #include <asm/io.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/soc.h>
19 #include <dm/uclass.h>
20 #include <fdt_support.h>
21 #include <time.h>
22 #include <u-boot/crc.h>
23 # include <atsha204a-i2c.h>
24
25 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
26 #include <../serdes/a38x/high_speed_env_spec.h>
27
28 DECLARE_GLOBAL_DATA_PTR;
29
30 #define OMNIA_I2C_BUS_NAME "i2c@11000->i2cmux@70->i2c@0"
31
32 #define OMNIA_I2C_MCU_CHIP_ADDR 0x2a
33 #define OMNIA_I2C_MCU_CHIP_LEN 1
34
35 #define OMNIA_I2C_EEPROM_CHIP_ADDR 0x54
36 #define OMNIA_I2C_EEPROM_CHIP_LEN 2
37 #define OMNIA_I2C_EEPROM_MAGIC 0x0341a034
38
39 enum mcu_commands {
40 CMD_GET_STATUS_WORD = 0x01,
41 CMD_GET_RESET = 0x09,
42 CMD_WATCHDOG_STATE = 0x0b,
43 };
44
45 enum status_word_bits {
46 CARD_DET_STSBIT = 0x0010,
47 MSATA_IND_STSBIT = 0x0020,
48 };
49
50 #define OMNIA_ATSHA204_OTP_VERSION 0
51 #define OMNIA_ATSHA204_OTP_SERIAL 1
52 #define OMNIA_ATSHA204_OTP_MAC0 3
53 #define OMNIA_ATSHA204_OTP_MAC1 4
54
55 /*
56 * Those values and defines are taken from the Marvell U-Boot version
57 * "u-boot-2013.01-2014_T3.0"
58 */
59 #define OMNIA_GPP_OUT_ENA_LOW \
60 (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
61 BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
62 BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
63 #define OMNIA_GPP_OUT_ENA_MID \
64 (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
65 BIT(16) | BIT(17) | BIT(18)))
66
67 #define OMNIA_GPP_OUT_VAL_LOW 0x0
68 #define OMNIA_GPP_OUT_VAL_MID 0x0
69 #define OMNIA_GPP_POL_LOW 0x0
70 #define OMNIA_GPP_POL_MID 0x0
71
72 static struct serdes_map board_serdes_map_pex[] = {
73 {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
74 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
75 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
76 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
77 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
78 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
79 };
80
81 static struct serdes_map board_serdes_map_sata[] = {
82 {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
83 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
84 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
85 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
86 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
87 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
88 };
89
omnia_get_i2c_chip(const char * name,uint addr,uint offset_len)90 static struct udevice *omnia_get_i2c_chip(const char *name, uint addr,
91 uint offset_len)
92 {
93 struct udevice *bus, *dev;
94 int ret;
95
96 ret = uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_BUS_NAME, &bus);
97 if (ret) {
98 printf("Cannot get I2C bus %s: uclass_get_device_by_name failed: %i\n",
99 OMNIA_I2C_BUS_NAME, ret);
100 return NULL;
101 }
102
103 ret = i2c_get_chip(bus, addr, offset_len, &dev);
104 if (ret) {
105 printf("Cannot get %s I2C chip: i2c_get_chip failed: %i\n",
106 name, ret);
107 return NULL;
108 }
109
110 return dev;
111 }
112
omnia_mcu_read(u8 cmd,void * buf,int len)113 static int omnia_mcu_read(u8 cmd, void *buf, int len)
114 {
115 struct udevice *chip;
116
117 chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
118 OMNIA_I2C_MCU_CHIP_LEN);
119 if (!chip)
120 return -ENODEV;
121
122 return dm_i2c_read(chip, cmd, buf, len);
123 }
124
125 #ifndef CONFIG_SPL_BUILD
omnia_mcu_write(u8 cmd,const void * buf,int len)126 static int omnia_mcu_write(u8 cmd, const void *buf, int len)
127 {
128 struct udevice *chip;
129
130 chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
131 OMNIA_I2C_MCU_CHIP_LEN);
132 if (!chip)
133 return -ENODEV;
134
135 return dm_i2c_write(chip, cmd, buf, len);
136 }
137
disable_mcu_watchdog(void)138 static bool disable_mcu_watchdog(void)
139 {
140 int ret;
141
142 puts("Disabling MCU watchdog... ");
143
144 ret = omnia_mcu_write(CMD_WATCHDOG_STATE, "\x00", 1);
145 if (ret) {
146 printf("omnia_mcu_write failed: %i\n", ret);
147 return false;
148 }
149
150 puts("disabled\n");
151
152 return true;
153 }
154 #endif
155
omnia_detect_sata(void)156 static bool omnia_detect_sata(void)
157 {
158 int ret;
159 u16 stsword;
160
161 puts("MiniPCIe/mSATA card detection... ");
162
163 ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword));
164 if (ret) {
165 printf("omnia_mcu_read failed: %i, defaulting to MiniPCIe card\n",
166 ret);
167 return false;
168 }
169
170 if (!(stsword & CARD_DET_STSBIT)) {
171 puts("none\n");
172 return false;
173 }
174
175 if (stsword & MSATA_IND_STSBIT)
176 puts("mSATA\n");
177 else
178 puts("MiniPCIe\n");
179
180 return stsword & MSATA_IND_STSBIT ? true : false;
181 }
182
hws_board_topology_load(struct serdes_map ** serdes_map_array,u8 * count)183 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
184 {
185 if (omnia_detect_sata()) {
186 *serdes_map_array = board_serdes_map_sata;
187 *count = ARRAY_SIZE(board_serdes_map_sata);
188 } else {
189 *serdes_map_array = board_serdes_map_pex;
190 *count = ARRAY_SIZE(board_serdes_map_pex);
191 }
192
193 return 0;
194 }
195
196 struct omnia_eeprom {
197 u32 magic;
198 u32 ramsize;
199 char region[4];
200 u32 crc;
201 };
202
omnia_read_eeprom(struct omnia_eeprom * oep)203 static bool omnia_read_eeprom(struct omnia_eeprom *oep)
204 {
205 struct udevice *chip;
206 u32 crc;
207 int ret;
208
209 chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR,
210 OMNIA_I2C_EEPROM_CHIP_LEN);
211
212 if (!chip)
213 return false;
214
215 ret = dm_i2c_read(chip, 0, (void *)oep, sizeof(*oep));
216 if (ret) {
217 printf("dm_i2c_read failed: %i, cannot read EEPROM\n", ret);
218 return false;
219 }
220
221 if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) {
222 printf("bad EEPROM magic number (%08x, should be %08x)\n",
223 oep->magic, OMNIA_I2C_EEPROM_MAGIC);
224 return false;
225 }
226
227 crc = crc32(0, (void *)oep, sizeof(*oep) - 4);
228 if (crc != oep->crc) {
229 printf("bad EEPROM CRC (stored %08x, computed %08x)\n",
230 oep->crc, crc);
231 return false;
232 }
233
234 return true;
235 }
236
omnia_get_ram_size_gb(void)237 static int omnia_get_ram_size_gb(void)
238 {
239 static int ram_size;
240 struct omnia_eeprom oep;
241
242 if (!ram_size) {
243 /* Get the board config from EEPROM */
244 if (omnia_read_eeprom(&oep)) {
245 debug("Memory config in EEPROM: 0x%02x\n", oep.ramsize);
246
247 if (oep.ramsize == 0x2)
248 ram_size = 2;
249 else
250 ram_size = 1;
251 } else {
252 /* Hardcoded fallback */
253 puts("Memory config from EEPROM read failed!\n");
254 puts("Falling back to default 1 GiB!\n");
255 ram_size = 1;
256 }
257 }
258
259 return ram_size;
260 }
261
262 /*
263 * Define the DDR layout / topology here in the board file. This will
264 * be used by the DDR3 init code in the SPL U-Boot version to configure
265 * the DDR3 controller.
266 */
267 static struct mv_ddr_topology_map board_topology_map_1g = {
268 DEBUG_LEVEL_ERROR,
269 0x1, /* active interfaces */
270 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
271 { { { {0x1, 0, 0, 0},
272 {0x1, 0, 0, 0},
273 {0x1, 0, 0, 0},
274 {0x1, 0, 0, 0},
275 {0x1, 0, 0, 0} },
276 SPEED_BIN_DDR_1600K, /* speed_bin */
277 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
278 MV_DDR_DIE_CAP_4GBIT, /* mem_size */
279 MV_DDR_FREQ_800, /* frequency */
280 0, 0, /* cas_wl cas_l */
281 MV_DDR_TEMP_NORMAL, /* temperature */
282 MV_DDR_TIM_2T} }, /* timing */
283 BUS_MASK_32BIT, /* Busses mask */
284 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
285 { {0} }, /* raw spd data */
286 {0} /* timing parameters */
287 };
288
289 static struct mv_ddr_topology_map board_topology_map_2g = {
290 DEBUG_LEVEL_ERROR,
291 0x1, /* active interfaces */
292 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
293 { { { {0x1, 0, 0, 0},
294 {0x1, 0, 0, 0},
295 {0x1, 0, 0, 0},
296 {0x1, 0, 0, 0},
297 {0x1, 0, 0, 0} },
298 SPEED_BIN_DDR_1600K, /* speed_bin */
299 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
300 MV_DDR_DIE_CAP_8GBIT, /* mem_size */
301 MV_DDR_FREQ_800, /* frequency */
302 0, 0, /* cas_wl cas_l */
303 MV_DDR_TEMP_NORMAL, /* temperature */
304 MV_DDR_TIM_2T} }, /* timing */
305 BUS_MASK_32BIT, /* Busses mask */
306 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
307 { {0} }, /* raw spd data */
308 {0} /* timing parameters */
309 };
310
mv_ddr_topology_map_get(void)311 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
312 {
313 if (omnia_get_ram_size_gb() == 2)
314 return &board_topology_map_2g;
315 else
316 return &board_topology_map_1g;
317 }
318
319 #ifndef CONFIG_SPL_BUILD
set_regdomain(void)320 static int set_regdomain(void)
321 {
322 struct omnia_eeprom oep;
323 char rd[3] = {' ', ' ', 0};
324
325 if (omnia_read_eeprom(&oep))
326 memcpy(rd, &oep.region, 2);
327 else
328 puts("EEPROM regdomain read failed.\n");
329
330 printf("Regdomain set to %s\n", rd);
331 return env_set("regdomain", rd);
332 }
333
334 /*
335 * default factory reset bootcommand on Omnia first sets all the front LEDs
336 * to green and then tries to load the rescue image from SPI flash memory and
337 * boot it
338 */
339 #define OMNIA_FACTORY_RESET_BOOTCMD \
340 "i2c dev 2; " \
341 "i2c mw 0x2a.1 0x3 0x1c 1; " \
342 "i2c mw 0x2a.1 0x4 0x1c 1; " \
343 "mw.l 0x01000000 0x00ff000c; " \
344 "i2c write 0x01000000 0x2a.1 0x5 4 -s; " \
345 "setenv bootargs \"earlyprintk console=ttyS0,115200" \
346 " omniarescue=$omnia_reset\"; " \
347 "sf probe; " \
348 "sf read 0x1000000 0x100000 0x700000; " \
349 "bootm 0x1000000; " \
350 "bootz 0x1000000"
351
handle_reset_button(void)352 static void handle_reset_button(void)
353 {
354 int ret;
355 u8 reset_status;
356
357 ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1);
358 if (ret) {
359 printf("omnia_mcu_read failed: %i, reset status unknown!\n",
360 ret);
361 return;
362 }
363
364 env_set_ulong("omnia_reset", reset_status);
365
366 if (reset_status) {
367 printf("RESET button was pressed, overwriting bootcmd!\n");
368 env_set("bootcmd", OMNIA_FACTORY_RESET_BOOTCMD);
369 }
370 }
371 #endif
372
board_early_init_f(void)373 int board_early_init_f(void)
374 {
375 /* Configure MPP */
376 writel(0x11111111, MVEBU_MPP_BASE + 0x00);
377 writel(0x11111111, MVEBU_MPP_BASE + 0x04);
378 writel(0x11244011, MVEBU_MPP_BASE + 0x08);
379 writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
380 writel(0x22200002, MVEBU_MPP_BASE + 0x10);
381 writel(0x30042022, MVEBU_MPP_BASE + 0x14);
382 writel(0x55550555, MVEBU_MPP_BASE + 0x18);
383 writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
384
385 /* Set GPP Out value */
386 writel(OMNIA_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
387 writel(OMNIA_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
388
389 /* Set GPP Polarity */
390 writel(OMNIA_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
391 writel(OMNIA_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
392
393 /* Set GPP Out Enable */
394 writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
395 writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
396
397 return 0;
398 }
399
board_init(void)400 int board_init(void)
401 {
402 /* address of boot parameters */
403 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
404
405 #ifndef CONFIG_SPL_BUILD
406 disable_mcu_watchdog();
407 #endif
408
409 return 0;
410 }
411
board_late_init(void)412 int board_late_init(void)
413 {
414 #ifndef CONFIG_SPL_BUILD
415 set_regdomain();
416 handle_reset_button();
417 #endif
418 pci_init();
419
420 return 0;
421 }
422
get_atsha204a_dev(void)423 static struct udevice *get_atsha204a_dev(void)
424 {
425 static struct udevice *dev;
426
427 if (dev)
428 return dev;
429
430 if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) {
431 puts("Cannot find ATSHA204A on I2C bus!\n");
432 dev = NULL;
433 }
434
435 return dev;
436 }
437
checkboard(void)438 int checkboard(void)
439 {
440 u32 version_num, serial_num;
441 int err = 1;
442
443 struct udevice *dev = get_atsha204a_dev();
444
445 if (dev) {
446 err = atsha204a_wakeup(dev);
447 if (err)
448 goto out;
449
450 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
451 OMNIA_ATSHA204_OTP_VERSION,
452 (u8 *)&version_num);
453 if (err)
454 goto out;
455
456 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
457 OMNIA_ATSHA204_OTP_SERIAL,
458 (u8 *)&serial_num);
459 if (err)
460 goto out;
461
462 atsha204a_sleep(dev);
463 }
464
465 out:
466 printf("Turris Omnia:\n");
467 printf(" RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024);
468 if (err)
469 printf(" Serial Number: unknown\n");
470 else
471 printf(" Serial Number: %08X%08X\n", be32_to_cpu(version_num),
472 be32_to_cpu(serial_num));
473
474 return 0;
475 }
476
increment_mac(u8 * mac)477 static void increment_mac(u8 *mac)
478 {
479 int i;
480
481 for (i = 5; i >= 3; i--) {
482 mac[i] += 1;
483 if (mac[i])
484 break;
485 }
486 }
487
misc_init_r(void)488 int misc_init_r(void)
489 {
490 int err;
491 struct udevice *dev = get_atsha204a_dev();
492 u8 mac0[4], mac1[4], mac[6];
493
494 if (!dev)
495 goto out;
496
497 err = atsha204a_wakeup(dev);
498 if (err)
499 goto out;
500
501 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
502 OMNIA_ATSHA204_OTP_MAC0, mac0);
503 if (err)
504 goto out;
505
506 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
507 OMNIA_ATSHA204_OTP_MAC1, mac1);
508 if (err)
509 goto out;
510
511 atsha204a_sleep(dev);
512
513 mac[0] = mac0[1];
514 mac[1] = mac0[2];
515 mac[2] = mac0[3];
516 mac[3] = mac1[1];
517 mac[4] = mac1[2];
518 mac[5] = mac1[3];
519
520 if (is_valid_ethaddr(mac))
521 eth_env_set_enetaddr("eth1addr", mac);
522
523 increment_mac(mac);
524
525 if (is_valid_ethaddr(mac))
526 eth_env_set_enetaddr("eth2addr", mac);
527
528 increment_mac(mac);
529
530 if (is_valid_ethaddr(mac))
531 eth_env_set_enetaddr("ethaddr", mac);
532
533 out:
534 return 0;
535 }
536
537