1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012 Atmel Corporation
4 */
5
6 #include <common.h>
7 #include <init.h>
8 #include <asm/io.h>
9 #include <asm/arch/at91sam9x5_matrix.h>
10 #include <asm/arch/at91sam9_smc.h>
11 #include <asm/arch/at91_common.h>
12 #include <asm/arch/at91_rstc.h>
13 #include <asm/arch/clk.h>
14 #include <asm/arch/gpio.h>
15 #include <debug_uart.h>
16 #include <asm/mach-types.h>
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20 /* ------------------------------------------------------------------------- */
21 /*
22 * Miscelaneous platform dependent initialisations
23 */
24
25 void at91_prepare_cpu_var(void);
26
27 #ifdef CONFIG_CMD_NAND
at91sam9x5ek_nand_hw_init(void)28 static void at91sam9x5ek_nand_hw_init(void)
29 {
30 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
31 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
32 unsigned long csa;
33
34 /* Enable CS3 */
35 csa = readl(&matrix->ebicsa);
36 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
37 /* NAND flash on D16 */
38 csa |= AT91_MATRIX_NFD0_ON_D16;
39
40 /* Configure IO drive */
41 csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
42
43 writel(csa, &matrix->ebicsa);
44
45 /* Configure SMC CS3 for NAND/SmartMedia */
46 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
47 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
48 &smc->cs[3].setup);
49 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
50 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
51 &smc->cs[3].pulse);
52 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
53 &smc->cs[3].cycle);
54 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
55 AT91_SMC_MODE_EXNW_DISABLE |
56 #ifdef CONFIG_SYS_NAND_DBW_16
57 AT91_SMC_MODE_DBW_16 |
58 #else /* CONFIG_SYS_NAND_DBW_8 */
59 AT91_SMC_MODE_DBW_8 |
60 #endif
61 AT91_SMC_MODE_TDF_CYCLE(1),
62 &smc->cs[3].mode);
63
64 at91_periph_clk_enable(ATMEL_ID_PIOCD);
65
66 /* Configure RDY/BSY */
67 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
68 /* Enable NandFlash */
69 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
70
71 at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
72 at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
73 at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
74 at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */
75 at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
76 at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
77 at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
78 at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
79 at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
80 at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
81 at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
82 at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
83 }
84 #endif
85
86 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)87 int board_late_init(void)
88 {
89 #ifdef CONFIG_DM_VIDEO
90 at91_video_show_board_info();
91 #endif
92 at91_prepare_cpu_var();
93 return 0;
94 }
95 #endif
96
97 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
board_debug_uart_init(void)98 void board_debug_uart_init(void)
99 {
100 at91_seriald_hw_init();
101 }
102 #endif
103
104 #ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f(void)105 int board_early_init_f(void)
106 {
107 #ifdef CONFIG_DEBUG_UART
108 debug_uart_init();
109 #endif
110 return 0;
111 }
112 #endif
113
board_init(void)114 int board_init(void)
115 {
116 /* arch number of AT91SAM9X5EK-Board */
117 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK;
118
119 /* adress of boot parameters */
120 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
121
122 #ifdef CONFIG_CMD_NAND
123 at91sam9x5ek_nand_hw_init();
124 #endif
125
126 #if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI_HCD)
127 at91_uhp_hw_init();
128 #endif
129 return 0;
130 }
131
dram_init(void)132 int dram_init(void)
133 {
134 gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
135 CONFIG_SYS_SDRAM_SIZE);
136 return 0;
137 }
138
139 #if defined(CONFIG_SPL_BUILD)
140 #include <spl.h>
141 #include <nand.h>
142
at91_spl_board_init(void)143 void at91_spl_board_init(void)
144 {
145 #ifdef CONFIG_SD_BOOT
146 at91_mci_hw_init();
147 #elif CONFIG_NAND_BOOT
148 at91sam9x5ek_nand_hw_init();
149 #endif
150 }
151
152 #include <asm/arch/atmel_mpddrc.h>
ddr2_conf(struct atmel_mpddrc_config * ddr2)153 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
154 {
155 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
156
157 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
158 ATMEL_MPDDRC_CR_NR_ROW_13 |
159 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
160 ATMEL_MPDDRC_CR_NB_8BANKS |
161 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
162
163 ddr2->rtr = 0x411;
164
165 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
166 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
167 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
168 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
169 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
170 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
171 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
172 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
173
174 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
175 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
176 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
177 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
178
179 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
180 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
181 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
182 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
183 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
184 }
185
mem_init(void)186 void mem_init(void)
187 {
188 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
189 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
190 struct atmel_mpddrc_config ddr2;
191 unsigned long csa;
192
193 ddr2_conf(&ddr2);
194
195 /* enable DDR2 clock */
196 writel(AT91_PMC_DDR, &pmc->scer);
197
198 /* Chip select 1 is for DDR2/SDRAM */
199 csa = readl(&matrix->ebicsa);
200 csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
201 csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
202 csa |= AT91_MATRIX_EBI_DBPD_OFF;
203 csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
204 writel(csa, &matrix->ebicsa);
205
206 /* DDRAM2 Controller initialize */
207 ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
208 }
209 #endif
210