1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2019 NXP
4 */
5
6 #include <common.h>
7 #include <i2c.h>
8 #include <fdt_support.h>
9 #include <asm/io.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/fsl_serdes.h>
12 #include <asm/arch/soc.h>
13 #include <asm/arch-fsl-layerscape/fsl_icid.h>
14 #include <hwconfig.h>
15 #include <ahci.h>
16 #include <mmc.h>
17 #include <scsi.h>
18 #include <fm_eth.h>
19 #include <fsl_csu.h>
20 #include <fsl_esdhc.h>
21 #include <fsl_sec.h>
22 #include <fsl_dspi.h>
23
24 #define LS1046A_PORSR1_REG 0x1EE0000
25 #define BOOT_SRC_SD 0x20000000
26 #define BOOT_SRC_MASK 0xFF800000
27 #define BOARD_REV_GPIO 13
28 #define USB2_SEL_MASK 0x00000100
29
30 #define BYTE_SWAP_32(word) ((((word) & 0xff000000) >> 24) | \
31 (((word) & 0x00ff0000) >> 8) | \
32 (((word) & 0x0000ff00) << 8) | \
33 (((word) & 0x000000ff) << 24))
34 #define SPI_MCR_REG 0x2100000
35
36 DECLARE_GLOBAL_DATA_PTR;
37
select_i2c_ch_pca9547(u8 ch)38 int select_i2c_ch_pca9547(u8 ch)
39 {
40 int ret;
41
42 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
43 if (ret) {
44 puts("PCA: failed to select proper channel\n");
45 return ret;
46 }
47
48 return 0;
49 }
50
demux_select_usb2(void)51 static inline void demux_select_usb2(void)
52 {
53 u32 val;
54 struct ccsr_gpio *pgpio = (void *)(GPIO3_BASE_ADDR);
55
56 val = in_be32(&pgpio->gpdir);
57 val |= USB2_SEL_MASK;
58 out_be32(&pgpio->gpdir, val);
59
60 val = in_be32(&pgpio->gpdat);
61 val |= USB2_SEL_MASK;
62 out_be32(&pgpio->gpdat, val);
63 }
64
set_spi_cs_signal_inactive(void)65 static inline void set_spi_cs_signal_inactive(void)
66 {
67 /* default: all CS signals inactive state is high */
68 uint mcr_val;
69 uint mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
70 DSPI_MCR_CRXF | DSPI_MCR_CTXF;
71
72 mcr_val = in_be32(SPI_MCR_REG);
73 mcr_val |= DSPI_MCR_HALT;
74 out_be32(SPI_MCR_REG, mcr_val);
75 out_be32(SPI_MCR_REG, mcr_cfg_val);
76 mcr_val = in_be32(SPI_MCR_REG);
77 mcr_val &= ~DSPI_MCR_HALT;
78 out_be32(SPI_MCR_REG, mcr_val);
79 }
80
board_early_init_f(void)81 int board_early_init_f(void)
82 {
83 fsl_lsch2_early_init_f();
84
85 return 0;
86 }
87
get_board_version(void)88 static inline uint8_t get_board_version(void)
89 {
90 u8 val;
91 struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
92
93 val = (in_le32(&pgpio->gpdat) >> BOARD_REV_GPIO) & 0x03;
94
95 return val;
96 }
97
checkboard(void)98 int checkboard(void)
99 {
100 static const char *freq[2] = {"100.00MHZ", "100.00MHZ"};
101 u32 boot_src;
102 u8 rev;
103
104 rev = get_board_version();
105 switch (rev) {
106 case 0x00:
107 puts("Board: LS1046AFRWY, Rev: A, boot from ");
108 break;
109 case 0x01:
110 puts("Board: LS1046AFRWY, Rev: B, boot from ");
111 break;
112 default:
113 puts("Board: LS1046AFRWY, Rev: Unknown, boot from ");
114 break;
115 }
116 boot_src = BYTE_SWAP_32(readl(LS1046A_PORSR1_REG));
117
118 if ((boot_src & BOOT_SRC_MASK) == BOOT_SRC_SD)
119 puts("SD\n");
120 else
121 puts("QSPI\n");
122 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[0], freq[1]);
123
124 return 0;
125 }
126
board_init(void)127 int board_init(void)
128 {
129 #ifdef CONFIG_NXP_ESBC
130 /*
131 * In case of Secure Boot, the IBR configures the SMMU
132 * to allow only Secure transactions.
133 * SMMU must be reset in bypass mode.
134 * Set the ClientPD bit and Clear the USFCFG Bit
135 */
136 u32 val;
137 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
138 out_le32(SMMU_SCR0, val);
139 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
140 out_le32(SMMU_NSCR0, val);
141 #endif
142
143 #ifdef CONFIG_FSL_CAAM
144 sec_init();
145 #endif
146
147 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
148 return 0;
149 }
150
board_setup_core_volt(u32 vdd)151 int board_setup_core_volt(u32 vdd)
152 {
153 return 0;
154 }
155
config_board_mux(void)156 void config_board_mux(void)
157 {
158 #ifdef CONFIG_HAS_FSL_XHCI_USB
159 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
160 u32 usb_pwrfault;
161 /*
162 * USB2 is used, configure mux to USB2_DRVVBUS/USB2_PWRFAULT
163 * USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
164 */
165 out_be32(&scfg->rcwpmuxcr0, 0x3300);
166 #ifdef CONFIG_HAS_FSL_IIC3
167 /* IIC3 is used, configure mux to use IIC3_SCL/IIC3/SDA */
168 out_be32(&scfg->rcwpmuxcr0, 0x0000);
169 #endif
170 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
171 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
172 SCFG_USBPWRFAULT_USB3_SHIFT) |
173 (SCFG_USBPWRFAULT_DEDICATED <<
174 SCFG_USBPWRFAULT_USB2_SHIFT) |
175 (SCFG_USBPWRFAULT_SHARED <<
176 SCFG_USBPWRFAULT_USB1_SHIFT);
177 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
178 #ifndef CONFIG_HAS_FSL_IIC3
179 /*
180 * LS1046A FRWY board has demultiplexer NX3DV42GU with GPIO3_23 as input
181 * to select I2C3_USB2_SEL_IO
182 * I2C3_USB2_SEL = 0: I2C3_SCL/SDA signals are routed to
183 * I2C3 header (default)
184 * I2C3_USB2_SEL = 1: USB2_DRVVBUS/PWRFAULT signals are routed to
185 * USB2 port
186 * programmed to select USB2 by setting GPIO3_23 output to one
187 */
188 demux_select_usb2();
189 #endif
190 #endif
191 set_spi_cs_signal_inactive();
192 }
193
194 #ifdef CONFIG_MISC_INIT_R
misc_init_r(void)195 int misc_init_r(void)
196 {
197 config_board_mux();
198 return 0;
199 }
200 #endif
201
ft_board_setup(void * blob,bd_t * bd)202 int ft_board_setup(void *blob, bd_t *bd)
203 {
204 u64 base[CONFIG_NR_DRAM_BANKS];
205 u64 size[CONFIG_NR_DRAM_BANKS];
206
207 /* fixup DT for the two DDR banks */
208 base[0] = gd->bd->bi_dram[0].start;
209 size[0] = gd->bd->bi_dram[0].size;
210 base[1] = gd->bd->bi_dram[1].start;
211 size[1] = gd->bd->bi_dram[1].size;
212
213 fdt_fixup_memory_banks(blob, base, size, 2);
214 ft_cpu_setup(blob, bd);
215
216 #ifdef CONFIG_SYS_DPAA_FMAN
217 fdt_fixup_fman_ethernet(blob);
218 #endif
219
220 fdt_fixup_icid(blob);
221
222 return 0;
223 }
224