1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2015 Freescale Semiconductor
4 * Copyright 2017 NXP
5 */
6 #include <common.h>
7 #include <env.h>
8 #include <malloc.h>
9 #include <errno.h>
10 #include <netdev.h>
11 #include <fsl_ifc.h>
12 #include <fsl_ddr.h>
13 #include <asm/io.h>
14 #include <hwconfig.h>
15 #include <fdt_support.h>
16 #include <linux/libfdt.h>
17 #include <fsl-mc/fsl_mc.h>
18 #include <env_internal.h>
19 #include <efi_loader.h>
20 #include <i2c.h>
21 #include <asm/arch/mmu.h>
22 #include <asm/arch/soc.h>
23 #include <asm/arch/ppa.h>
24 #include <fsl_sec.h>
25 #include <asm/arch-fsl-layerscape/fsl_icid.h>
26
27 #ifdef CONFIG_FSL_QIXIS
28 #include "../common/qixis.h"
29 #include "ls2080ardb_qixis.h"
30 #endif
31 #include "../common/vid.h"
32
33 #define PIN_MUX_SEL_SDHC 0x00
34 #define PIN_MUX_SEL_DSPI 0x0a
35
36 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
37 DECLARE_GLOBAL_DATA_PTR;
38
39 enum {
40 MUX_TYPE_SDHC,
41 MUX_TYPE_DSPI,
42 };
43
get_qixis_addr(void)44 unsigned long long get_qixis_addr(void)
45 {
46 unsigned long long addr;
47
48 if (gd->flags & GD_FLG_RELOC)
49 addr = QIXIS_BASE_PHYS;
50 else
51 addr = QIXIS_BASE_PHYS_EARLY;
52
53 /*
54 * IFC address under 256MB is mapped to 0x30000000, any address above
55 * is mapped to 0x5_10000000 up to 4GB.
56 */
57 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
58
59 return addr;
60 }
61
checkboard(void)62 int checkboard(void)
63 {
64 #ifdef CONFIG_FSL_QIXIS
65 u8 sw;
66 #endif
67 char buf[15];
68
69 cpu_name(buf);
70 printf("Board: %s-RDB, ", buf);
71
72 #ifdef CONFIG_TARGET_LS2081ARDB
73 #ifdef CONFIG_FSL_QIXIS
74 sw = QIXIS_READ(arch);
75 printf("Board version: %c, ", (sw & 0xf) + 'A');
76
77 sw = QIXIS_READ(brdcfg[0]);
78 sw = (sw >> QIXIS_QMAP_SHIFT) & QIXIS_QMAP_MASK;
79 switch (sw) {
80 case 0:
81 puts("boot from QSPI DEV#0\n");
82 puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
83 break;
84 case 1:
85 puts("boot from QSPI DEV#1\n");
86 puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
87 break;
88 case 2:
89 puts("boot from QSPI EMU\n");
90 puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
91 break;
92 case 3:
93 puts("boot from QSPI EMU\n");
94 puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
95 break;
96 case 4:
97 puts("boot from QSPI DEV#0\n");
98 puts("QSPI_CSA_1 mapped to QSPI EMU\n");
99 break;
100 default:
101 printf("invalid setting of SW%u\n", sw);
102 break;
103 }
104 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
105 #endif
106 puts("SERDES1 Reference : ");
107 printf("Clock1 = 100MHz ");
108 printf("Clock2 = 161.13MHz");
109 #else
110 #ifdef CONFIG_FSL_QIXIS
111 sw = QIXIS_READ(arch);
112 printf("Board Arch: V%d, ", sw >> 4);
113 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
114
115 sw = QIXIS_READ(brdcfg[0]);
116 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
117
118 if (sw < 0x8)
119 printf("vBank: %d\n", sw);
120 else if (sw == 0x9)
121 puts("NAND\n");
122 else
123 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
124
125 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
126 #endif
127 puts("SERDES1 Reference : ");
128 printf("Clock1 = 156.25MHz ");
129 printf("Clock2 = 156.25MHz");
130 #endif
131
132 puts("\nSERDES2 Reference : ");
133 printf("Clock1 = 100MHz ");
134 printf("Clock2 = 100MHz\n");
135
136 return 0;
137 }
138
get_board_sys_clk(void)139 unsigned long get_board_sys_clk(void)
140 {
141 #ifdef CONFIG_FSL_QIXIS
142 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
143
144 switch (sysclk_conf & 0x0F) {
145 case QIXIS_SYSCLK_83:
146 return 83333333;
147 case QIXIS_SYSCLK_100:
148 return 100000000;
149 case QIXIS_SYSCLK_125:
150 return 125000000;
151 case QIXIS_SYSCLK_133:
152 return 133333333;
153 case QIXIS_SYSCLK_150:
154 return 150000000;
155 case QIXIS_SYSCLK_160:
156 return 160000000;
157 case QIXIS_SYSCLK_166:
158 return 166666666;
159 }
160 #endif
161 return 100000000;
162 }
163
select_i2c_ch_pca9547(u8 ch)164 int select_i2c_ch_pca9547(u8 ch)
165 {
166 int ret;
167
168 #ifndef CONFIG_DM_I2C
169 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
170 #else
171 struct udevice *dev;
172
173 ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
174 if (!ret)
175 ret = dm_i2c_write(dev, 0, &ch, 1);
176 #endif
177
178 if (ret) {
179 puts("PCA: failed to select proper channel\n");
180 return ret;
181 }
182
183 return 0;
184 }
185
i2c_multiplexer_select_vid_channel(u8 channel)186 int i2c_multiplexer_select_vid_channel(u8 channel)
187 {
188 return select_i2c_ch_pca9547(channel);
189 }
190
config_board_mux(int ctrl_type)191 int config_board_mux(int ctrl_type)
192 {
193 #ifdef CONFIG_FSL_QIXIS
194 u8 reg5;
195
196 reg5 = QIXIS_READ(brdcfg[5]);
197
198 switch (ctrl_type) {
199 case MUX_TYPE_SDHC:
200 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
201 break;
202 case MUX_TYPE_DSPI:
203 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
204 break;
205 default:
206 printf("Wrong mux interface type\n");
207 return -1;
208 }
209
210 QIXIS_WRITE(brdcfg[5], reg5);
211 #endif
212 return 0;
213 }
214
board_init(void)215 int board_init(void)
216 {
217 #ifdef CONFIG_FSL_MC_ENET
218 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
219 #endif
220
221 init_final_memctl_regs();
222
223 #ifdef CONFIG_ENV_IS_NOWHERE
224 gd->env_addr = (ulong)&default_environment[0];
225 #endif
226 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
227
228 #ifdef CONFIG_FSL_QIXIS
229 QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
230 #endif
231
232 #ifdef CONFIG_FSL_CAAM
233 sec_init();
234 #endif
235 #ifdef CONFIG_FSL_LS_PPA
236 ppa_init();
237 #endif
238
239 #ifdef CONFIG_FSL_MC_ENET
240 /* invert AQR405 IRQ pins polarity */
241 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
242 #endif
243 #ifdef CONFIG_FSL_CAAM
244 sec_init();
245 #endif
246
247 return 0;
248 }
249
board_early_init_f(void)250 int board_early_init_f(void)
251 {
252 #ifdef CONFIG_SYS_I2C_EARLY_INIT
253 i2c_early_init_f();
254 #endif
255 fsl_lsch3_early_init_f();
256 return 0;
257 }
258
misc_init_r(void)259 int misc_init_r(void)
260 {
261 char *env_hwconfig;
262 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
263 u32 val;
264 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
265 u32 svr = gur_in32(&gur->svr);
266
267 val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
268
269 env_hwconfig = env_get("hwconfig");
270
271 if (hwconfig_f("dspi", env_hwconfig) &&
272 DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
273 config_board_mux(MUX_TYPE_DSPI);
274 else
275 config_board_mux(MUX_TYPE_SDHC);
276
277 /*
278 * LS2081ARDB RevF board has smart voltage translator
279 * which needs to be programmed to enable high speed SD interface
280 * by setting GPIO4_10 output to zero
281 */
282 #ifdef CONFIG_TARGET_LS2081ARDB
283 out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
284 in_le32(GPIO4_GPDIR_ADDR)));
285 out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
286 in_le32(GPIO4_GPDAT_ADDR)));
287 #endif
288 if (hwconfig("sdhc"))
289 config_board_mux(MUX_TYPE_SDHC);
290
291 if (adjust_vdd(0))
292 printf("Warning: Adjusting core voltage failed.\n");
293 /*
294 * Default value of board env is based on filename which is
295 * ls2080ardb. Modify board env for other supported SoCs
296 */
297 if ((SVR_SOC_VER(svr) == SVR_LS2088A) ||
298 (SVR_SOC_VER(svr) == SVR_LS2048A))
299 env_set("board", "ls2088ardb");
300 else if ((SVR_SOC_VER(svr) == SVR_LS2081A) ||
301 (SVR_SOC_VER(svr) == SVR_LS2041A))
302 env_set("board", "ls2081ardb");
303
304 return 0;
305 }
306
detail_board_ddr_info(void)307 void detail_board_ddr_info(void)
308 {
309 puts("\nDDR ");
310 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
311 print_ddr_info(0);
312 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
313 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
314 puts("\nDP-DDR ");
315 print_size(gd->bd->bi_dram[2].size, "");
316 print_ddr_info(CONFIG_DP_DDR_CTRL);
317 }
318 #endif
319 }
320
321 #if defined(CONFIG_ARCH_MISC_INIT)
arch_misc_init(void)322 int arch_misc_init(void)
323 {
324 return 0;
325 }
326 #endif
327
328 #ifdef CONFIG_FSL_MC_ENET
fdt_fixup_board_enet(void * fdt)329 void fdt_fixup_board_enet(void *fdt)
330 {
331 int offset;
332
333 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
334
335 if (offset < 0)
336 offset = fdt_path_offset(fdt, "/fsl-mc");
337
338 if (offset < 0) {
339 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
340 __func__, offset);
341 return;
342 }
343
344 if (get_mc_boot_status() == 0 &&
345 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
346 fdt_status_okay(fdt, offset);
347 else
348 fdt_status_fail(fdt, offset);
349 }
350
board_quiesce_devices(void)351 void board_quiesce_devices(void)
352 {
353 fsl_mc_ldpaa_exit(gd->bd);
354 }
355 #endif
356
357 #ifdef CONFIG_OF_BOARD_SETUP
fsl_fdt_fixup_flash(void * fdt)358 void fsl_fdt_fixup_flash(void *fdt)
359 {
360 int offset;
361 #ifdef CONFIG_TFABOOT
362 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
363 u32 val;
364 #endif
365
366 /*
367 * IFC and QSPI are muxed on board.
368 * So disable IFC node in dts if QSPI is enabled or
369 * disable QSPI node in dts in case QSPI is not enabled.
370 */
371 #ifdef CONFIG_TFABOOT
372 enum boot_src src = get_boot_src();
373 bool disable_ifc = false;
374
375 switch (src) {
376 case BOOT_SOURCE_IFC_NOR:
377 disable_ifc = false;
378 break;
379 case BOOT_SOURCE_QSPI_NOR:
380 disable_ifc = true;
381 break;
382 default:
383 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
384 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
385 disable_ifc = true;
386 break;
387 }
388
389 if (disable_ifc) {
390 offset = fdt_path_offset(fdt, "/soc/ifc");
391
392 if (offset < 0)
393 offset = fdt_path_offset(fdt, "/ifc");
394 } else {
395 offset = fdt_path_offset(fdt, "/soc/quadspi");
396
397 if (offset < 0)
398 offset = fdt_path_offset(fdt, "/quadspi");
399 }
400
401 #else
402 #ifdef CONFIG_FSL_QSPI
403 offset = fdt_path_offset(fdt, "/soc/ifc");
404
405 if (offset < 0)
406 offset = fdt_path_offset(fdt, "/ifc");
407 #else
408 offset = fdt_path_offset(fdt, "/soc/quadspi");
409
410 if (offset < 0)
411 offset = fdt_path_offset(fdt, "/quadspi");
412 #endif
413 #endif
414
415 if (offset < 0)
416 return;
417
418 fdt_status_disabled(fdt, offset);
419 }
420
ft_board_setup(void * blob,bd_t * bd)421 int ft_board_setup(void *blob, bd_t *bd)
422 {
423 int i;
424 u16 mc_memory_bank = 0;
425
426 u64 *base;
427 u64 *size;
428 u64 mc_memory_base = 0;
429 u64 mc_memory_size = 0;
430 u16 total_memory_banks;
431
432 ft_cpu_setup(blob, bd);
433
434 fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
435
436 if (mc_memory_base != 0)
437 mc_memory_bank++;
438
439 total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
440
441 base = calloc(total_memory_banks, sizeof(u64));
442 size = calloc(total_memory_banks, sizeof(u64));
443
444 /* fixup DT for the two GPP DDR banks */
445 base[0] = gd->bd->bi_dram[0].start;
446 size[0] = gd->bd->bi_dram[0].size;
447 base[1] = gd->bd->bi_dram[1].start;
448 size[1] = gd->bd->bi_dram[1].size;
449
450 #ifdef CONFIG_RESV_RAM
451 /* reduce size if reserved memory is within this bank */
452 if (gd->arch.resv_ram >= base[0] &&
453 gd->arch.resv_ram < base[0] + size[0])
454 size[0] = gd->arch.resv_ram - base[0];
455 else if (gd->arch.resv_ram >= base[1] &&
456 gd->arch.resv_ram < base[1] + size[1])
457 size[1] = gd->arch.resv_ram - base[1];
458 #endif
459
460 if (mc_memory_base != 0) {
461 for (i = 0; i <= total_memory_banks; i++) {
462 if (base[i] == 0 && size[i] == 0) {
463 base[i] = mc_memory_base;
464 size[i] = mc_memory_size;
465 break;
466 }
467 }
468 }
469
470 fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
471
472 fdt_fsl_mc_fixup_iommu_map_entry(blob);
473
474 fsl_fdt_fixup_dr_usb(blob, bd);
475
476 fsl_fdt_fixup_flash(blob);
477
478 #ifdef CONFIG_FSL_MC_ENET
479 fdt_fixup_board_enet(blob);
480 #endif
481
482 fdt_fixup_icid(blob);
483
484 return 0;
485 }
486 #endif
487
qixis_dump_switch(void)488 void qixis_dump_switch(void)
489 {
490 #ifdef CONFIG_FSL_QIXIS
491 int i, nr_of_cfgsw;
492
493 QIXIS_WRITE(cms[0], 0x00);
494 nr_of_cfgsw = QIXIS_READ(cms[1]);
495
496 puts("DIP switch settings dump:\n");
497 for (i = 1; i <= nr_of_cfgsw; i++) {
498 QIXIS_WRITE(cms[0], i);
499 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
500 }
501 #endif
502 }
503
504 /*
505 * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
506 * Both slots has 0x54, resulting 2nd slot unusable.
507 */
update_spd_address(unsigned int ctrl_num,unsigned int slot,unsigned int * addr)508 void update_spd_address(unsigned int ctrl_num,
509 unsigned int slot,
510 unsigned int *addr)
511 {
512 #ifndef CONFIG_TARGET_LS2081ARDB
513 #ifdef CONFIG_FSL_QIXIS
514 u8 sw;
515
516 sw = QIXIS_READ(arch);
517 if ((sw & 0xf) < 0x3) {
518 if (ctrl_num == 1 && slot == 0)
519 *addr = SPD_EEPROM_ADDRESS4;
520 else if (ctrl_num == 1 && slot == 1)
521 *addr = SPD_EEPROM_ADDRESS3;
522 }
523 #endif
524 #endif
525 }
526