1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2018-2019 NXP
4 *
5 */
6
7 #include <common.h>
8 #include <env.h>
9 #include <hwconfig.h>
10 #include <command.h>
11 #include <netdev.h>
12 #include <malloc.h>
13 #include <fsl_mdio.h>
14 #include <miiphy.h>
15 #include <phy.h>
16 #include <fm_eth.h>
17 #include <asm/io.h>
18 #include <exports.h>
19 #include <asm/arch/fsl_serdes.h>
20 #include <fsl-mc/fsl_mc.h>
21 #include <fsl-mc/ldpaa_wriop.h>
22
23 #include "../common/qixis.h"
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 #define EMI_NONE 0
28 #define EMI1 1 /* Mdio Bus 1 */
29 #define EMI2 2 /* Mdio Bus 2 */
30
31 #if defined(CONFIG_FSL_MC_ENET)
32 enum io_slot {
33 IO_SLOT_NONE = 0,
34 IO_SLOT_1,
35 IO_SLOT_2,
36 IO_SLOT_3,
37 IO_SLOT_4,
38 IO_SLOT_5,
39 IO_SLOT_6,
40 IO_SLOT_7,
41 IO_SLOT_8,
42 EMI1_RGMII1,
43 EMI1_RGMII2,
44 IO_SLOT_MAX
45 };
46
47 struct lx2160a_qds_mdio {
48 enum io_slot ioslot : 4;
49 u8 realbusnum : 4;
50 struct mii_dev *realbus;
51 };
52
53 /* structure explaining the phy configuration on 8 lanes of a serdes*/
54 struct serdes_phy_config {
55 u8 serdes; /* serdes protocol */
56 struct phy_config {
57 u8 dpmacid;
58 /* -1 terminated array */
59 int phy_address[WRIOP_MAX_PHY_NUM + 1];
60 u8 mdio_bus;
61 enum io_slot ioslot;
62 } phy_config[SRDS_MAX_LANES];
63 };
64
65 /* Table defining the phy configuration on 8 lanes of a serdes.
66 * Various assumptions have been made while defining this table.
67 * e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII
68 * card is being used for dpmac 3-4. (X-M12-XFI could also have been used)
69 * And also that this card is connected to IO Slot 1 (could have been connected
70 * to any of the 8 IO slots (IO slot 1 - IO slot 8)).
71 * similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G card
72 * used in serdes1 protocol 19 (could have selected MDIO 2)
73 * To override these settings "dpmac" environment variable can be used after
74 * defining "dpmac_override" in hwconfig environment variable.
75 * This table has limited serdes protocol entries. It can be expanded as per
76 * requirement.
77 */
78 static const struct serdes_phy_config serdes1_phy_config[] = {
79 {3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
80 EMI1, IO_SLOT_1},
81 {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
82 EMI1, IO_SLOT_1},
83 {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
84 EMI1, IO_SLOT_1},
85 {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
86 EMI1, IO_SLOT_1} } },
87 {7, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
88 EMI1, IO_SLOT_1},
89 {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
90 EMI1, IO_SLOT_1},
91 {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
92 EMI1, IO_SLOT_1},
93 {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
94 EMI1, IO_SLOT_1},
95 {WRIOP1_DPMAC7, {SGMII_CARD_PORT1_PHY_ADDR, -1},
96 EMI1, IO_SLOT_2},
97 {WRIOP1_DPMAC8, {SGMII_CARD_PORT2_PHY_ADDR, -1},
98 EMI1, IO_SLOT_2},
99 {WRIOP1_DPMAC9, {SGMII_CARD_PORT3_PHY_ADDR, -1},
100 EMI1, IO_SLOT_2},
101 {WRIOP1_DPMAC10, {SGMII_CARD_PORT4_PHY_ADDR, -1},
102 EMI1, IO_SLOT_2} } },
103 {8, {} },
104 {13, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
105 EMI1, IO_SLOT_1},
106 {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
107 EMI1, IO_SLOT_2} } },
108 {14, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
109 EMI1, IO_SLOT_1} } },
110 {15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
111 EMI1, IO_SLOT_1},
112 {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
113 EMI1, IO_SLOT_1} } },
114 {17, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
115 EMI1, IO_SLOT_1},
116 {WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
117 EMI1, IO_SLOT_1},
118 {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
119 EMI1, IO_SLOT_1},
120 {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
121 EMI1, IO_SLOT_1} } },
122 {19, {{WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
123 EMI1, IO_SLOT_2},
124 {WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
125 EMI1, IO_SLOT_1},
126 {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
127 EMI1, IO_SLOT_1},
128 {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
129 EMI1, IO_SLOT_6},
130 {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
131 EMI1, IO_SLOT_6} } },
132 {20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1},
133 EMI1, IO_SLOT_1},
134 {WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
135 EMI1, IO_SLOT_2} } }
136 };
137
138 static const struct serdes_phy_config serdes2_phy_config[] = {
139 {2, {} },
140 {3, {} },
141 {5, {} },
142 {11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
143 EMI1, IO_SLOT_7},
144 {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
145 EMI1, IO_SLOT_7},
146 {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
147 EMI1, IO_SLOT_7},
148 {WRIOP1_DPMAC16, {SGMII_CARD_PORT2_PHY_ADDR, -1},
149 EMI1, IO_SLOT_8},
150 {WRIOP1_DPMAC13, {SGMII_CARD_PORT3_PHY_ADDR, -1},
151 EMI1, IO_SLOT_8},
152 {WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1},
153 EMI1, IO_SLOT_8} } },
154 };
155
156 static const struct serdes_phy_config serdes3_phy_config[] = {
157 {2, {} },
158 {3, {} }
159 };
160
161 static inline
get_phy_config(u8 serdes,const struct serdes_phy_config * table,u8 table_size)162 const struct phy_config *get_phy_config(u8 serdes,
163 const struct serdes_phy_config *table,
164 u8 table_size)
165 {
166 int i;
167
168 for (i = 0; i < table_size; i++) {
169 if (table[i].serdes == serdes)
170 return table[i].phy_config;
171 }
172
173 return NULL;
174 }
175
176 /* BRDCFG4 controls EMI routing for the board.
177 * Bits Function
178 * 7-6 EMI Interface #1 Primary Routing (CFG_MUX1_EMI1) (1.8V):
179 * EMI1 00= On-board PHY #1
180 * 01= On-board PHY #2
181 * 10= (reserved)
182 * 11= Slots 1..8 multiplexer and translator.
183 * 5-3 EMI Interface #1 Secondary Routing (CFG_MUX2_EMI1) (2.5V):
184 * EMI1X 000= Slot #1
185 * 001= Slot #2
186 * 010= Slot #3
187 * 011= Slot #4
188 * 100= Slot #5
189 * 101= Slot #6
190 * 110= Slot #7
191 * 111= Slot #8
192 * 2-0 EMI Interface #2 Routing (CFG_MUX_EMI2):
193 * EMI2 000= Slot #1 (secondary EMI)
194 * 001= Slot #2 (secondary EMI)
195 * 010= Slot #3 (secondary EMI)
196 * 011= Slot #4 (secondary EMI)
197 * 100= Slot #5 (secondary EMI)
198 * 101= Slot #6 (secondary EMI)
199 * 110= Slot #7 (secondary EMI)
200 * 111= Slot #8 (secondary EMI)
201 */
lx2160a_qds_get_mdio_mux_val(u8 realbusnum,enum io_slot ioslot)202 static int lx2160a_qds_get_mdio_mux_val(u8 realbusnum, enum io_slot ioslot)
203 {
204 switch (realbusnum) {
205 case EMI1:
206 switch (ioslot) {
207 case EMI1_RGMII1:
208 return 0;
209 case EMI1_RGMII2:
210 return 0x40;
211 default:
212 return (((ioslot - 1) << BRDCFG4_EMI1SEL_SHIFT) | 0xC0);
213 }
214 break;
215 case EMI2:
216 return ((ioslot - 1) << BRDCFG4_EMI2SEL_SHIFT);
217 default:
218 return -1;
219 }
220 }
221
lx2160a_qds_mux_mdio(struct lx2160a_qds_mdio * priv)222 static void lx2160a_qds_mux_mdio(struct lx2160a_qds_mdio *priv)
223 {
224 u8 brdcfg4, mux_val, reg;
225
226 brdcfg4 = QIXIS_READ(brdcfg[4]);
227 reg = brdcfg4;
228 mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
229
230 switch (priv->realbusnum) {
231 case EMI1:
232 brdcfg4 &= ~BRDCFG4_EMI1SEL_MASK;
233 brdcfg4 |= mux_val;
234 break;
235 case EMI2:
236 brdcfg4 &= ~BRDCFG4_EMI2SEL_MASK;
237 brdcfg4 |= mux_val;
238 break;
239 }
240
241 if (brdcfg4 ^ reg)
242 QIXIS_WRITE(brdcfg[4], brdcfg4);
243 }
244
lx2160a_qds_mdio_read(struct mii_dev * bus,int addr,int devad,int regnum)245 static int lx2160a_qds_mdio_read(struct mii_dev *bus, int addr,
246 int devad, int regnum)
247 {
248 struct lx2160a_qds_mdio *priv = bus->priv;
249
250 lx2160a_qds_mux_mdio(priv);
251
252 return priv->realbus->read(priv->realbus, addr, devad, regnum);
253 }
254
lx2160a_qds_mdio_write(struct mii_dev * bus,int addr,int devad,int regnum,u16 value)255 static int lx2160a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
256 int regnum, u16 value)
257 {
258 struct lx2160a_qds_mdio *priv = bus->priv;
259
260 lx2160a_qds_mux_mdio(priv);
261
262 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
263 }
264
lx2160a_qds_mdio_reset(struct mii_dev * bus)265 static int lx2160a_qds_mdio_reset(struct mii_dev *bus)
266 {
267 struct lx2160a_qds_mdio *priv = bus->priv;
268
269 return priv->realbus->reset(priv->realbus);
270 }
271
lx2160a_qds_mdio_init(u8 realbusnum,enum io_slot ioslot)272 static struct mii_dev *lx2160a_qds_mdio_init(u8 realbusnum, enum io_slot ioslot)
273 {
274 struct lx2160a_qds_mdio *pmdio;
275 struct mii_dev *bus;
276 /*should be within MDIO_NAME_LEN*/
277 char dummy_mdio_name[] = "LX2160A_QDS_MDIO1_IOSLOT1";
278
279 if (realbusnum == EMI2) {
280 if (ioslot < IO_SLOT_1 || ioslot > IO_SLOT_8) {
281 printf("invalid ioslot %d\n", ioslot);
282 return NULL;
283 }
284 } else if (realbusnum == EMI1) {
285 if (ioslot < IO_SLOT_1 || ioslot > EMI1_RGMII2) {
286 printf("invalid ioslot %d\n", ioslot);
287 return NULL;
288 }
289 } else {
290 printf("not supported real mdio bus %d\n", realbusnum);
291 return NULL;
292 }
293
294 if (ioslot == EMI1_RGMII1)
295 strcpy(dummy_mdio_name, "LX2160A_QDS_MDIO1_RGMII1");
296 else if (ioslot == EMI1_RGMII2)
297 strcpy(dummy_mdio_name, "LX2160A_QDS_MDIO1_RGMII2");
298 else
299 sprintf(dummy_mdio_name, "LX2160A_QDS_MDIO%d_IOSLOT%d",
300 realbusnum, ioslot);
301 bus = miiphy_get_dev_by_name(dummy_mdio_name);
302
303 if (bus)
304 return bus;
305
306 bus = mdio_alloc();
307 if (!bus) {
308 printf("Failed to allocate %s bus\n", dummy_mdio_name);
309 return NULL;
310 }
311
312 pmdio = malloc(sizeof(*pmdio));
313 if (!pmdio) {
314 printf("Failed to allocate %s private data\n", dummy_mdio_name);
315 free(bus);
316 return NULL;
317 }
318
319 switch (realbusnum) {
320 case EMI1:
321 pmdio->realbus =
322 miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
323 break;
324 case EMI2:
325 pmdio->realbus =
326 miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
327 break;
328 }
329
330 if (!pmdio->realbus) {
331 printf("No real mdio bus num %d found\n", realbusnum);
332 free(bus);
333 free(pmdio);
334 return NULL;
335 }
336
337 pmdio->realbusnum = realbusnum;
338 pmdio->ioslot = ioslot;
339 bus->read = lx2160a_qds_mdio_read;
340 bus->write = lx2160a_qds_mdio_write;
341 bus->reset = lx2160a_qds_mdio_reset;
342 strcpy(bus->name, dummy_mdio_name);
343 bus->priv = pmdio;
344
345 if (!mdio_register(bus))
346 return bus;
347
348 printf("No bus with name %s\n", dummy_mdio_name);
349 free(bus);
350 free(pmdio);
351 return NULL;
352 }
353
do_phy_config(const struct phy_config * phy_config)354 static inline void do_phy_config(const struct phy_config *phy_config)
355 {
356 struct mii_dev *bus;
357 int i, phy_num, phy_address;
358
359 for (i = 0; i < SRDS_MAX_LANES; i++) {
360 if (!phy_config[i].dpmacid)
361 continue;
362
363 for (phy_num = 0;
364 phy_num < ARRAY_SIZE(phy_config[i].phy_address);
365 phy_num++) {
366 phy_address = phy_config[i].phy_address[phy_num];
367 if (phy_address == -1)
368 break;
369 wriop_set_phy_address(phy_config[i].dpmacid,
370 phy_num, phy_address);
371 }
372 /*Register the muxing front-ends to the MDIO buses*/
373 bus = lx2160a_qds_mdio_init(phy_config[i].mdio_bus,
374 phy_config[i].ioslot);
375 if (!bus)
376 printf("could not get bus for mdio %d ioslot %d\n",
377 phy_config[i].mdio_bus,
378 phy_config[i].ioslot);
379 else
380 wriop_set_mdio(phy_config[i].dpmacid, bus);
381 }
382 }
383
do_dpmac_config(int dpmac,const char * arg_dpmacid,char * env_dpmac)384 static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid,
385 char *env_dpmac)
386 {
387 const char *ret;
388 size_t len;
389 u8 realbusnum, ioslot;
390 struct mii_dev *bus;
391 int phy_num;
392 char *phystr = "phy00";
393
394 /*search phy in dpmac arg*/
395 for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
396 sprintf(phystr, "phy%d", phy_num + 1);
397 ret = hwconfig_subarg_f(arg_dpmacid, phystr, &len, env_dpmac);
398 if (!ret) {
399 /*look for phy instead of phy1*/
400 if (!phy_num)
401 ret = hwconfig_subarg_f(arg_dpmacid, "phy",
402 &len, env_dpmac);
403 if (!ret)
404 continue;
405 }
406
407 if (len != 4 || strncmp(ret, "0x", 2))
408 printf("invalid phy format in %s variable.\n"
409 "specify phy%d for %s in hex format e.g. 0x12\n",
410 env_dpmac, phy_num + 1, arg_dpmacid);
411 else
412 wriop_set_phy_address(dpmac, phy_num,
413 simple_strtoul(ret, NULL, 16));
414 }
415
416 /*search mdio in dpmac arg*/
417 ret = hwconfig_subarg_f(arg_dpmacid, "mdio", &len, env_dpmac);
418 if (ret)
419 realbusnum = *ret - '0';
420 else
421 realbusnum = EMI_NONE;
422
423 if (realbusnum) {
424 /*search io in dpmac arg*/
425 ret = hwconfig_subarg_f(arg_dpmacid, "io", &len, env_dpmac);
426 if (ret)
427 ioslot = *ret - '0';
428 else
429 ioslot = IO_SLOT_NONE;
430 /*Register the muxing front-ends to the MDIO buses*/
431 bus = lx2160a_qds_mdio_init(realbusnum, ioslot);
432 if (!bus)
433 printf("could not get bus for mdio %d ioslot %d\n",
434 realbusnum, ioslot);
435 else
436 wriop_set_mdio(dpmac, bus);
437 }
438 }
439
440 #endif
441
board_eth_init(bd_t * bis)442 int board_eth_init(bd_t *bis)
443 {
444 #if defined(CONFIG_FSL_MC_ENET)
445 struct memac_mdio_info mdio_info;
446 struct memac_mdio_controller *regs;
447 int i;
448 const char *ret;
449 char *env_dpmac;
450 char dpmacid[] = "dpmac00", srds[] = "00_00_00";
451 size_t len;
452 struct mii_dev *bus;
453 const struct phy_config *phy_config;
454 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
455 u32 srds_s1, srds_s2, srds_s3;
456
457 srds_s1 = in_le32(&gur->rcwsr[28]) &
458 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
459 srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
460
461 srds_s2 = in_le32(&gur->rcwsr[28]) &
462 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
463 srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
464
465 srds_s3 = in_le32(&gur->rcwsr[28]) &
466 FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK;
467 srds_s3 >>= FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT;
468
469 sprintf(srds, "%d_%d_%d", srds_s1, srds_s2, srds_s3);
470
471 regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
472 mdio_info.regs = regs;
473 mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
474
475 /*Register the EMI 1*/
476 fm_memac_mdio_init(bis, &mdio_info);
477
478 regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
479 mdio_info.regs = regs;
480 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
481
482 /*Register the EMI 2*/
483 fm_memac_mdio_init(bis, &mdio_info);
484
485 /* "dpmac" environment variable can be used after
486 * defining "dpmac_override" in hwconfig environment variable.
487 */
488 if (hwconfig("dpmac_override")) {
489 env_dpmac = env_get("dpmac");
490 if (env_dpmac) {
491 ret = hwconfig_arg_f("srds", &len, env_dpmac);
492 if (ret) {
493 if (strncmp(ret, srds, strlen(srds))) {
494 printf("SERDES configuration changed.\n"
495 "previous: %.*s, current: %s.\n"
496 "update dpmac variable.\n",
497 (int)len, ret, srds);
498 }
499 } else {
500 printf("SERDES configuration not found.\n"
501 "Please add srds:%s in dpmac variable\n",
502 srds);
503 }
504
505 for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
506 /* Look for dpmac1 to dpmac24(current max) arg
507 * in dpmac environment variable
508 */
509 sprintf(dpmacid, "dpmac%d", i);
510 ret = hwconfig_arg_f(dpmacid, &len, env_dpmac);
511 if (ret)
512 do_dpmac_config(i, dpmacid, env_dpmac);
513 }
514 } else {
515 printf("Warning: environment dpmac not found.\n"
516 "DPAA network interfaces may not work\n");
517 }
518 } else {
519 /*Look for phy config for serdes1 in phy config table*/
520 phy_config = get_phy_config(srds_s1, serdes1_phy_config,
521 ARRAY_SIZE(serdes1_phy_config));
522 if (!phy_config) {
523 printf("%s WRIOP: Unsupported SerDes1 Protocol %d\n",
524 __func__, srds_s1);
525 } else {
526 do_phy_config(phy_config);
527 }
528 phy_config = get_phy_config(srds_s2, serdes2_phy_config,
529 ARRAY_SIZE(serdes2_phy_config));
530 if (!phy_config) {
531 printf("%s WRIOP: Unsupported SerDes2 Protocol %d\n",
532 __func__, srds_s2);
533 } else {
534 do_phy_config(phy_config);
535 }
536 phy_config = get_phy_config(srds_s3, serdes3_phy_config,
537 ARRAY_SIZE(serdes3_phy_config));
538 if (!phy_config) {
539 printf("%s WRIOP: Unsupported SerDes3 Protocol %d\n",
540 __func__, srds_s3);
541 } else {
542 do_phy_config(phy_config);
543 }
544 }
545
546 if (wriop_get_enet_if(WRIOP1_DPMAC17) == PHY_INTERFACE_MODE_RGMII_ID) {
547 wriop_set_phy_address(WRIOP1_DPMAC17, 0, RGMII_PHY_ADDR1);
548 bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII1);
549 if (!bus)
550 printf("could not get bus for RGMII1\n");
551 else
552 wriop_set_mdio(WRIOP1_DPMAC17, bus);
553 }
554
555 if (wriop_get_enet_if(WRIOP1_DPMAC18) == PHY_INTERFACE_MODE_RGMII_ID) {
556 wriop_set_phy_address(WRIOP1_DPMAC18, 0, RGMII_PHY_ADDR2);
557 bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII2);
558 if (!bus)
559 printf("could not get bus for RGMII2\n");
560 else
561 wriop_set_mdio(WRIOP1_DPMAC18, bus);
562 }
563
564 cpu_eth_init(bis);
565 #endif /* CONFIG_FMAN_ENET */
566
567 #ifdef CONFIG_PHY_AQUANTIA
568 /*
569 * Export functions to be used by AQ firmware
570 * upload application
571 */
572 gd->jt->strcpy = strcpy;
573 gd->jt->mdelay = mdelay;
574 gd->jt->mdio_get_current_dev = mdio_get_current_dev;
575 gd->jt->phy_find_by_mask = phy_find_by_mask;
576 gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
577 gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
578 #endif
579 return pci_eth_init(bis);
580 }
581
582 #if defined(CONFIG_RESET_PHY_R)
reset_phy(void)583 void reset_phy(void)
584 {
585 #if defined(CONFIG_FSL_MC_ENET)
586 mc_env_boot();
587 #endif
588 }
589 #endif /* CONFIG_RESET_PHY_R */
590
591 #if defined(CONFIG_FSL_MC_ENET)
fdt_fixup_dpmac_phy_handle(void * fdt,int dpmac_id,int node_phandle)592 int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
593 {
594 int offset;
595 int ret;
596 char dpmac_str[] = "dpmacs@00";
597 const char *phy_string;
598
599 offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs");
600
601 if (offset < 0)
602 offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs");
603
604 if (offset < 0) {
605 printf("dpmacs node not found in device tree\n");
606 return offset;
607 }
608
609 sprintf(dpmac_str, "dpmac@%x", dpmac_id);
610 debug("dpmac_str = %s\n", dpmac_str);
611
612 offset = fdt_subnode_offset(fdt, offset, dpmac_str);
613 if (offset < 0) {
614 printf("%s node not found in device tree\n", dpmac_str);
615 return offset;
616 }
617
618 ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle);
619 if (ret)
620 printf("%d@%s %d\n", __LINE__, __func__, ret);
621
622 phy_string = phy_string_for_interface(wriop_get_enet_if(dpmac_id));
623 ret = fdt_setprop_string(fdt, offset, "phy-connection-type",
624 phy_string);
625 if (ret)
626 printf("%d@%s %d\n", __LINE__, __func__, ret);
627
628 return ret;
629 }
630
fdt_get_ioslot_offset(void * fdt,struct mii_dev * mii_dev,int fpga_offset)631 int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
632 {
633 char mdio_ioslot_str[] = "mdio@00";
634 struct lx2160a_qds_mdio *priv;
635 u64 reg;
636 u32 phandle;
637 int offset, mux_val;
638
639 /*Test if the MDIO bus is real mdio bus or muxing front end ?*/
640 if (strncmp(mii_dev->name, "LX2160A_QDS_MDIO",
641 strlen("LX2160A_QDS_MDIO")))
642 return -1;
643
644 /*Get the real MDIO bus num and ioslot info from bus's priv data*/
645 priv = mii_dev->priv;
646
647 debug("real_bus_num = %d, ioslot = %d\n",
648 priv->realbusnum, priv->ioslot);
649
650 if (priv->realbusnum == EMI1)
651 reg = CONFIG_SYS_FSL_WRIOP1_MDIO1;
652 else
653 reg = CONFIG_SYS_FSL_WRIOP1_MDIO2;
654
655 offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg);
656 if (offset < 0) {
657 printf("mdio@%llx node not found in device tree\n", reg);
658 return offset;
659 }
660
661 phandle = fdt_get_phandle(fdt, offset);
662 phandle = cpu_to_fdt32(phandle);
663 offset = fdt_node_offset_by_prop_value(fdt, -1, "mdio-parent-bus",
664 &phandle, 4);
665 if (offset < 0) {
666 printf("mdio-mux-%d node not found in device tree\n",
667 priv->realbusnum == EMI1 ? 1 : 2);
668 return offset;
669 }
670
671 mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
672 if (priv->realbusnum == EMI1)
673 mux_val >>= BRDCFG4_EMI1SEL_SHIFT;
674 else
675 mux_val >>= BRDCFG4_EMI2SEL_SHIFT;
676 sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val);
677
678 offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);
679 if (offset < 0) {
680 printf("%s node not found in device tree\n", mdio_ioslot_str);
681 return offset;
682 }
683
684 return offset;
685 }
686
fdt_create_phy_node(void * fdt,int offset,u8 phyaddr,int * subnodeoffset,struct phy_device * phy_dev,int phandle)687 int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset,
688 struct phy_device *phy_dev, int phandle)
689 {
690 char phy_node_name[] = "ethernet-phy@00";
691 char phy_id_compatible_str[] = "ethernet-phy-id0000.0000,";
692 int ret;
693
694 sprintf(phy_node_name, "ethernet-phy@%x", phyaddr);
695 debug("phy_node_name = %s\n", phy_node_name);
696
697 *subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);
698 if (*subnodeoffset <= 0) {
699 printf("Could not add subnode %s inside node %s err = %s\n",
700 phy_node_name, fdt_get_name(fdt, offset, NULL),
701 fdt_strerror(*subnodeoffset));
702 return *subnodeoffset;
703 }
704
705 sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x,",
706 phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF);
707 debug("phy_id_compatible_str %s\n", phy_id_compatible_str);
708
709 ret = fdt_setprop_string(fdt, *subnodeoffset, "compatible",
710 phy_id_compatible_str);
711 if (ret) {
712 printf("%d@%s %d\n", __LINE__, __func__, ret);
713 goto out;
714 }
715
716 if (phy_dev->is_c45) {
717 ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
718 "ethernet-phy-ieee802.3-c45");
719 if (ret) {
720 printf("%d@%s %d\n", __LINE__, __func__, ret);
721 goto out;
722 }
723 } else {
724 ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
725 "ethernet-phy-ieee802.3-c22");
726 if (ret) {
727 printf("%d@%s %d\n", __LINE__, __func__, ret);
728 goto out;
729 }
730 }
731
732 ret = fdt_setprop_cell(fdt, *subnodeoffset, "reg", phyaddr);
733 if (ret) {
734 printf("%d@%s %d\n", __LINE__, __func__, ret);
735 goto out;
736 }
737
738 ret = fdt_set_phandle(fdt, *subnodeoffset, phandle);
739 if (ret) {
740 printf("%d@%s %d\n", __LINE__, __func__, ret);
741 goto out;
742 }
743
744 out:
745 if (ret)
746 fdt_del_node(fdt, *subnodeoffset);
747
748 return ret;
749 }
750
fdt_fixup_board_phy(void * fdt)751 int fdt_fixup_board_phy(void *fdt)
752 {
753 int fpga_offset, offset, subnodeoffset;
754 struct mii_dev *mii_dev;
755 struct list_head *mii_devs, *entry;
756 int ret, dpmac_id, phandle, i;
757 struct phy_device *phy_dev;
758 char ethname[ETH_NAME_LEN];
759 phy_interface_t phy_iface;
760
761 ret = 0;
762 /* we know FPGA is connected to i2c0, therefore search path directly,
763 * instead of compatible property, as it saves time
764 */
765 fpga_offset = fdt_path_offset(fdt, "/soc/i2c@2000000/fpga");
766
767 if (fpga_offset < 0)
768 fpga_offset = fdt_path_offset(fdt, "/i2c@2000000/fpga");
769
770 if (fpga_offset < 0) {
771 printf("i2c@2000000/fpga node not found in device tree\n");
772 return fpga_offset;
773 }
774
775 phandle = fdt_alloc_phandle(fdt);
776 mii_devs = mdio_get_list_head();
777
778 list_for_each(entry, mii_devs) {
779 mii_dev = list_entry(entry, struct mii_dev, link);
780 debug("mii_dev name : %s\n", mii_dev->name);
781 offset = fdt_get_ioslot_offset(fdt, mii_dev, fpga_offset);
782 if (offset < 0)
783 continue;
784
785 // Look for phy devices attached to MDIO bus muxing front end
786 // and create their entries with compatible being the device id
787 for (i = 0; i < PHY_MAX_ADDR; i++) {
788 phy_dev = mii_dev->phymap[i];
789 if (!phy_dev)
790 continue;
791
792 // TODO: use sscanf instead of loop
793 dpmac_id = WRIOP1_DPMAC1;
794 while (dpmac_id < NUM_WRIOP_PORTS) {
795 phy_iface = wriop_get_enet_if(dpmac_id);
796 snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s",
797 dpmac_id,
798 phy_string_for_interface(phy_iface));
799 if (strcmp(ethname, phy_dev->dev->name) == 0)
800 break;
801 dpmac_id++;
802 }
803 if (dpmac_id == NUM_WRIOP_PORTS)
804 continue;
805 ret = fdt_create_phy_node(fdt, offset, i,
806 &subnodeoffset,
807 phy_dev, phandle);
808 if (ret)
809 break;
810
811 ret = fdt_fixup_dpmac_phy_handle(fdt,
812 dpmac_id, phandle);
813 if (ret) {
814 fdt_del_node(fdt, subnodeoffset);
815 break;
816 }
817 /* calculate offset again as new node addition may have
818 * changed offset;
819 */
820 offset = fdt_get_ioslot_offset(fdt, mii_dev,
821 fpga_offset);
822 phandle++;
823 }
824
825 if (ret)
826 break;
827 }
828
829 return ret;
830 }
831 #endif // CONFIG_FSL_MC_ENET
832
833