1 /*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 *
4 * Michael Barkowski <michael.barkowski@freescale.com>
5 * Based on mpc832xmds file by Dave Liu <daveliu@freescale.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <common.h>
13 #include <eeprom.h>
14 #include <env.h>
15 #include <init.h>
16 #include <ioports.h>
17 #include <mpc83xx.h>
18 #include <i2c.h>
19 #include <miiphy.h>
20 #include <command.h>
21 #include <linux/libfdt.h>
22 #include <u-boot/crc.h>
23 #if defined(CONFIG_PCI)
24 #include <pci.h>
25 #endif
26 #include <asm/mmu.h>
27
28 DECLARE_GLOBAL_DATA_PTR;
29
30 const qe_iop_conf_t qe_iop_conf_tab[] = {
31 /* UCC3 */
32 {1, 0, 1, 0, 1}, /* TxD0 */
33 {1, 1, 1, 0, 1}, /* TxD1 */
34 {1, 2, 1, 0, 1}, /* TxD2 */
35 {1, 3, 1, 0, 1}, /* TxD3 */
36 {1, 9, 1, 0, 1}, /* TxER */
37 {1, 12, 1, 0, 1}, /* TxEN */
38 {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
39
40 {1, 4, 2, 0, 1}, /* RxD0 */
41 {1, 5, 2, 0, 1}, /* RxD1 */
42 {1, 6, 2, 0, 1}, /* RxD2 */
43 {1, 7, 2, 0, 1}, /* RxD3 */
44 {1, 8, 2, 0, 1}, /* RxER */
45 {1, 10, 2, 0, 1}, /* RxDV */
46 {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
47 {1, 11, 2, 0, 1}, /* COL */
48 {1, 13, 2, 0, 1}, /* CRS */
49
50 /* UCC2 */
51 {0, 18, 1, 0, 1}, /* TxD0 */
52 {0, 19, 1, 0, 1}, /* TxD1 */
53 {0, 20, 1, 0, 1}, /* TxD2 */
54 {0, 21, 1, 0, 1}, /* TxD3 */
55 {0, 27, 1, 0, 1}, /* TxER */
56 {0, 30, 1, 0, 1}, /* TxEN */
57 {3, 23, 2, 0, 1}, /* TxCLK->CLK3 */
58
59 {0, 22, 2, 0, 1}, /* RxD0 */
60 {0, 23, 2, 0, 1}, /* RxD1 */
61 {0, 24, 2, 0, 1}, /* RxD2 */
62 {0, 25, 2, 0, 1}, /* RxD3 */
63 {0, 26, 1, 0, 1}, /* RxER */
64 {0, 28, 2, 0, 1}, /* Rx_DV */
65 {3, 21, 2, 0, 1}, /* RxCLK->CLK16 */
66 {0, 29, 2, 0, 1}, /* COL */
67 {0, 31, 2, 0, 1}, /* CRS */
68
69 {3, 4, 3, 0, 2}, /* MDIO */
70 {3, 5, 1, 0, 2}, /* MDC */
71
72 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
73 };
74
75 int fixed_sdram(void);
76
dram_init(void)77 int dram_init(void)
78 {
79 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
80 u32 msize = 0;
81
82 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
83 return -ENXIO;
84
85 /* DDR SDRAM - Main SODIMM */
86 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
87
88 msize = fixed_sdram();
89
90 /* set total bus SDRAM size(bytes) -- DDR */
91 gd->ram_size = msize * 1024 * 1024;
92
93 return 0;
94 }
95
96 /*************************************************************************
97 * fixed sdram init -- doesn't use serial presence detect.
98 ************************************************************************/
fixed_sdram(void)99 int fixed_sdram(void)
100 {
101 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
102 u32 msize = 0;
103 u32 ddr_size;
104 u32 ddr_size_log2;
105
106 msize = CONFIG_SYS_DDR_SIZE;
107 for (ddr_size = msize << 20, ddr_size_log2 = 0;
108 (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
109 if (ddr_size & 1) {
110 return -1;
111 }
112 }
113 im->sysconf.ddrlaw[0].ar =
114 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
115 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
116 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
117 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
118 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
119 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
120 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
121 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
122 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
123 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
124 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
125 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
126 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
127 __asm__ __volatile__ ("sync");
128 udelay(200);
129
130 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
131 __asm__ __volatile__ ("sync");
132 return msize;
133 }
134
checkboard(void)135 int checkboard(void)
136 {
137 puts("Board: Freescale MPC8323ERDB\n");
138 return 0;
139 }
140
141 static struct pci_region pci_regions[] = {
142 {
143 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
144 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
145 size: CONFIG_SYS_PCI1_MEM_SIZE,
146 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
147 },
148 {
149 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
150 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
151 size: CONFIG_SYS_PCI1_MMIO_SIZE,
152 flags: PCI_REGION_MEM
153 },
154 {
155 bus_start: CONFIG_SYS_PCI1_IO_BASE,
156 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
157 size: CONFIG_SYS_PCI1_IO_SIZE,
158 flags: PCI_REGION_IO
159 }
160 };
161
pci_init_board(void)162 void pci_init_board(void)
163 {
164 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
165 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
166 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
167 struct pci_region *reg[] = { pci_regions };
168
169 /* Enable all 3 PCI_CLK_OUTPUTs. */
170 clk->occr |= 0xe0000000;
171
172 /* Configure PCI Local Access Windows */
173 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
174 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
175
176 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
177 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
178
179 mpc83xx_pci_init(1, reg);
180 }
181
182 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,bd_t * bd)183 int ft_board_setup(void *blob, bd_t *bd)
184 {
185 ft_cpu_setup(blob, bd);
186 #ifdef CONFIG_PCI
187 ft_pci_setup(blob, bd);
188 #endif
189
190 return 0;
191 }
192 #endif
193
194 #if defined(CONFIG_SYS_I2C_MAC_OFFSET)
mac_read_from_eeprom(void)195 int mac_read_from_eeprom(void)
196 {
197 uchar buf[28];
198 char str[18];
199 int i = 0;
200 unsigned int crc = 0;
201 unsigned char enetvar[32];
202
203 /* Read MAC addresses from EEPROM */
204 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_MAC_OFFSET, buf, 28)) {
205 printf("\nEEPROM @ 0x%02x read FAILED!!!\n",
206 CONFIG_SYS_I2C_EEPROM_ADDR);
207 } else {
208 uint32_t crc_buf;
209
210 memcpy(&crc_buf, &buf[24], sizeof(uint32_t));
211
212 if (crc32(crc, buf, 24) == crc_buf) {
213 printf("Reading MAC from EEPROM\n");
214 for (i = 0; i < 4; i++) {
215 if (memcmp(&buf[i * 6], "\0\0\0\0\0\0", 6)) {
216 sprintf(str,
217 "%02X:%02X:%02X:%02X:%02X:%02X",
218 buf[i * 6], buf[i * 6 + 1],
219 buf[i * 6 + 2], buf[i * 6 + 3],
220 buf[i * 6 + 4], buf[i * 6 + 5]);
221 sprintf((char *)enetvar,
222 i ? "eth%daddr" : "ethaddr", i);
223 env_set((char *)enetvar, str);
224 }
225 }
226 }
227 }
228 return 0;
229 }
230 #endif /* CONFIG_I2C_MAC_OFFSET */
231