1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
4 */
5
6 #include <init.h>
7 #include <asm/mmu.h>
8 #include <asm/io.h>
9 #include <common.h>
10 #include <env.h>
11 #include <mpc83xx.h>
12 #include <pci.h>
13 #include <i2c.h>
14 #include <fdt_support.h>
15 #include <asm/fsl_i2c.h>
16 #include <asm/fsl_mpc83xx_serdes.h>
17
18 static struct pci_region pci_regions[] = {
19 {
20 bus_start: CONFIG_SYS_PCI_MEM_BASE,
21 phys_start: CONFIG_SYS_PCI_MEM_PHYS,
22 size: CONFIG_SYS_PCI_MEM_SIZE,
23 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
24 },
25 {
26 bus_start: CONFIG_SYS_PCI_MMIO_BASE,
27 phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
28 size: CONFIG_SYS_PCI_MMIO_SIZE,
29 flags: PCI_REGION_MEM
30 },
31 {
32 bus_start: CONFIG_SYS_PCI_IO_BASE,
33 phys_start: CONFIG_SYS_PCI_IO_PHYS,
34 size: CONFIG_SYS_PCI_IO_SIZE,
35 flags: PCI_REGION_IO
36 }
37 };
38
39 static struct pci_region pcie_regions_0[] = {
40 {
41 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
42 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
43 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
44 .flags = PCI_REGION_MEM,
45 },
46 {
47 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
48 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
49 .size = CONFIG_SYS_PCIE1_IO_SIZE,
50 .flags = PCI_REGION_IO,
51 },
52 };
53
54 static struct pci_region pcie_regions_1[] = {
55 {
56 .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
57 .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
58 .size = CONFIG_SYS_PCIE2_MEM_SIZE,
59 .flags = PCI_REGION_MEM,
60 },
61 {
62 .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
63 .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
64 .size = CONFIG_SYS_PCIE2_IO_SIZE,
65 .flags = PCI_REGION_IO,
66 },
67 };
68
is_pex_x2(void)69 static int is_pex_x2(void)
70 {
71 const char *pex_x2 = env_get("pex_x2");
72
73 if (pex_x2 && !strcmp(pex_x2, "yes"))
74 return 1;
75 return 0;
76 }
77
pci_init_board(void)78 void pci_init_board(void)
79 {
80 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
81 volatile sysconf83xx_t *sysconf = &immr->sysconf;
82 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
83 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
84 volatile law83xx_t *pcie_law = sysconf->pcielaw;
85 struct pci_region *reg[] = { pci_regions };
86 struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
87 u32 spridr = in_be32(&immr->sysconf.spridr);
88 int pex2 = is_pex_x2();
89
90 if (board_pci_host_broken())
91 goto skip_pci;
92
93 /* Enable all 5 PCI_CLK_OUTPUTS */
94 clk->occr |= 0xf8000000;
95 udelay(2000);
96
97 /* Configure PCI Local Access Windows */
98 pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
99 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
100
101 pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
102 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
103
104 udelay(2000);
105
106 mpc83xx_pci_init(1, reg);
107 skip_pci:
108 /* There is no PEX in MPC8379 parts. */
109 if (PARTID_NO_E(spridr) == SPR_8379)
110 return;
111
112 if (pex2)
113 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
114 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
115 else
116 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
117 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
118
119 /* Configure the clock for PCIE controller */
120 clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
121 SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
122
123 /* Deassert the resets in the control register */
124 out_be32(&sysconf->pecr1, 0xE0008000);
125 if (!pex2)
126 out_be32(&sysconf->pecr2, 0xE0008000);
127 udelay(2000);
128
129 /* Configure PCI Express Local Access Windows */
130 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
131 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
132
133 out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
134 out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
135
136 mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg);
137 }
138
ft_pcie_fixup(void * blob,bd_t * bd)139 void ft_pcie_fixup(void *blob, bd_t *bd)
140 {
141 const char *status = "disabled (PCIE1 is x2)";
142
143 if (!is_pex_x2())
144 return;
145
146 do_fixup_by_path(blob, "pci2", "status", status,
147 strlen(status) + 1, 1);
148 }
149