1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012 Freescale Semiconductor, Inc.
4 *
5 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 */
7
8 #include <common.h>
9 #include <init.h>
10 #include <asm/io.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/iomux.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <env.h>
16 #include <linux/errno.h>
17 #include <asm/gpio.h>
18 #include <asm/mach-imx/iomux-v3.h>
19 #include <asm/mach-imx/mxc_i2c.h>
20 #include <asm/mach-imx/boot_mode.h>
21 #include <asm/mach-imx/spi.h>
22 #include <mmc.h>
23 #include <fsl_esdhc_imx.h>
24 #include <miiphy.h>
25 #include <netdev.h>
26 #include <asm/arch/sys_proto.h>
27 #include <i2c.h>
28 #include <input.h>
29 #include <asm/arch/mxc_hdmi.h>
30 #include <asm/mach-imx/video.h>
31 #include <asm/arch/crm_regs.h>
32 #include <pca953x.h>
33 #include <power/pmic.h>
34 #include <power/pfuze100_pmic.h>
35 #include "../common/pfuze.h"
36
37 DECLARE_GLOBAL_DATA_PTR;
38
39 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
40 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
41 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
42
43 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
44 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
45 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
46
47 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
48 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
49
50 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
51 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
52 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
53
54 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
55 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
56 PAD_CTL_SRE_FAST)
57 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
58
59 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
60
61 #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
62 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
63 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
64
65 #define I2C_PMIC 1
66
dram_init(void)67 int dram_init(void)
68 {
69 gd->ram_size = imx_ddr_size();
70
71 return 0;
72 }
73
74 static iomux_v3_cfg_t const uart4_pads[] = {
75 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
76 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
77 };
78
79 static iomux_v3_cfg_t const enet_pads[] = {
80 IOMUX_PADS(PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
81 IOMUX_PADS(PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
82 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
83 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
84 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
85 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
86 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
87 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
88 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
89 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
90 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
91 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
92 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
93 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
94 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
95 };
96
97 /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
98 static struct i2c_pads_info mx6q_i2c_pad_info1 = {
99 .scl = {
100 .i2c_mode = MX6Q_PAD_EIM_EB2__I2C2_SCL | PC,
101 .gpio_mode = MX6Q_PAD_EIM_EB2__GPIO2_IO30 | PC,
102 .gp = IMX_GPIO_NR(2, 30)
103 },
104 .sda = {
105 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
106 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
107 .gp = IMX_GPIO_NR(4, 13)
108 }
109 };
110
111 static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
112 .scl = {
113 .i2c_mode = MX6DL_PAD_EIM_EB2__I2C2_SCL | PC,
114 .gpio_mode = MX6DL_PAD_EIM_EB2__GPIO2_IO30 | PC,
115 .gp = IMX_GPIO_NR(2, 30)
116 },
117 .sda = {
118 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
119 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
120 .gp = IMX_GPIO_NR(4, 13)
121 }
122 };
123
124 #ifndef CONFIG_SYS_FLASH_CFI
125 /*
126 * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
127 * Compass Sensor, Accelerometer, Res Touch
128 */
129 static struct i2c_pads_info mx6q_i2c_pad_info2 = {
130 .scl = {
131 .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
132 .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
133 .gp = IMX_GPIO_NR(1, 3)
134 },
135 .sda = {
136 .i2c_mode = MX6Q_PAD_EIM_D18__I2C3_SDA | PC,
137 .gpio_mode = MX6Q_PAD_EIM_D18__GPIO3_IO18 | PC,
138 .gp = IMX_GPIO_NR(3, 18)
139 }
140 };
141
142 static struct i2c_pads_info mx6dl_i2c_pad_info2 = {
143 .scl = {
144 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
145 .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
146 .gp = IMX_GPIO_NR(1, 3)
147 },
148 .sda = {
149 .i2c_mode = MX6DL_PAD_EIM_D18__I2C3_SDA | PC,
150 .gpio_mode = MX6DL_PAD_EIM_D18__GPIO3_IO18 | PC,
151 .gp = IMX_GPIO_NR(3, 18)
152 }
153 };
154 #endif
155
156 static iomux_v3_cfg_t const i2c3_pads[] = {
157 IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
158 };
159
160 static iomux_v3_cfg_t const port_exp[] = {
161 IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
162 };
163
164 #ifdef CONFIG_MTD_NOR_FLASH
165 static iomux_v3_cfg_t const eimnor_pads[] = {
166 IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
167 IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
168 IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
169 IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
170 IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
171 IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
172 IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
173 IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
174 IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
175 IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
176 IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
177 IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
178 IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
179 IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
180 IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
181 IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
182 IOMUX_PADS(PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
183 IOMUX_PADS(PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
184 IOMUX_PADS(PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
185 IOMUX_PADS(PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
186 IOMUX_PADS(PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
187 IOMUX_PADS(PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
188 IOMUX_PADS(PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
189 IOMUX_PADS(PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
190 IOMUX_PADS(PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
191 IOMUX_PADS(PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
192 IOMUX_PADS(PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
193 IOMUX_PADS(PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
194 IOMUX_PADS(PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
195 IOMUX_PADS(PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
196 IOMUX_PADS(PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
197 IOMUX_PADS(PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
198 IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
199 IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
200 IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
201 IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
202 IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
203 IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
204 IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
205 IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
206 IOMUX_PADS(PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
207 IOMUX_PADS(PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)),
208 IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
209 };
210
eimnor_cs_setup(void)211 static void eimnor_cs_setup(void)
212 {
213 struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
214
215 writel(0x00020181, &weim_regs->cs0gcr1);
216 writel(0x00000001, &weim_regs->cs0gcr2);
217 writel(0x0a020000, &weim_regs->cs0rcr1);
218 writel(0x0000c000, &weim_regs->cs0rcr2);
219 writel(0x0804a240, &weim_regs->cs0wcr1);
220 writel(0x00000120, &weim_regs->wcr);
221
222 set_chipselect_size(CS0_128);
223 }
224
eim_clk_setup(void)225 static void eim_clk_setup(void)
226 {
227 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
228 int cscmr1, ccgr6;
229
230
231 /* Turn off EIM clock */
232 ccgr6 = readl(&imx_ccm->CCGR6);
233 ccgr6 &= ~(0x3 << 10);
234 writel(ccgr6, &imx_ccm->CCGR6);
235
236 /*
237 * Configure clk_eim_slow_sel = 00 --> derive clock from AXI clk root
238 * and aclk_eim_slow_podf = 01 --> divide by 2
239 * so that we can have EIM at the maximum clock of 132MHz
240 */
241 cscmr1 = readl(&imx_ccm->cscmr1);
242 cscmr1 &= ~(MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK |
243 MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK);
244 cscmr1 |= (1 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET);
245 writel(cscmr1, &imx_ccm->cscmr1);
246
247 /* Turn on EIM clock */
248 ccgr6 |= (0x3 << 10);
249 writel(ccgr6, &imx_ccm->CCGR6);
250 }
251
setup_iomux_eimnor(void)252 static void setup_iomux_eimnor(void)
253 {
254 SETUP_IOMUX_PADS(eimnor_pads);
255
256 gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
257
258 eimnor_cs_setup();
259 }
260 #endif
261
setup_iomux_enet(void)262 static void setup_iomux_enet(void)
263 {
264 SETUP_IOMUX_PADS(enet_pads);
265 }
266
267 static iomux_v3_cfg_t const usdhc3_pads[] = {
268 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
269 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
270 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
271 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
272 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
273 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
274 IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
275 IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
276 IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
277 IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
278 IOMUX_PADS(PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
279 IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
280 };
281
setup_iomux_uart(void)282 static void setup_iomux_uart(void)
283 {
284 SETUP_IOMUX_PADS(uart4_pads);
285 }
286
287 #ifdef CONFIG_FSL_ESDHC_IMX
288 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
289 {USDHC3_BASE_ADDR},
290 };
291
board_mmc_getcd(struct mmc * mmc)292 int board_mmc_getcd(struct mmc *mmc)
293 {
294 gpio_direction_input(IMX_GPIO_NR(6, 15));
295 return !gpio_get_value(IMX_GPIO_NR(6, 15));
296 }
297
board_mmc_init(bd_t * bis)298 int board_mmc_init(bd_t *bis)
299 {
300 SETUP_IOMUX_PADS(usdhc3_pads);
301
302 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
303 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
304 }
305 #endif
306
307 #ifdef CONFIG_NAND_MXS
308 static iomux_v3_cfg_t gpmi_pads[] = {
309 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
310 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
311 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
312 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
313 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
314 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
315 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
316 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
317 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
318 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
319 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
320 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
321 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
322 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
323 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
324 IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1)),
325 };
326
setup_gpmi_nand(void)327 static void setup_gpmi_nand(void)
328 {
329 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
330
331 /* config gpmi nand iomux */
332 SETUP_IOMUX_PADS(gpmi_pads);
333
334 setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
335 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
336 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
337
338 /* enable apbh clock gating */
339 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
340 }
341 #endif
342
setup_fec(void)343 static void setup_fec(void)
344 {
345 if (is_mx6dqp()) {
346 /*
347 * select ENET MAC0 TX clock from PLL
348 */
349 imx_iomux_set_gpr_register(5, 9, 1, 1);
350 enable_fec_anatop_clock(0, ENET_125MHZ);
351 }
352
353 setup_iomux_enet();
354 }
355
board_eth_init(bd_t * bis)356 int board_eth_init(bd_t *bis)
357 {
358 setup_fec();
359
360 return cpu_eth_init(bis);
361 }
362
get_board_rev(void)363 u32 get_board_rev(void)
364 {
365 int rev = nxp_board_rev();
366
367 return (get_cpu_rev() & ~(0xF << 8)) | rev;
368 }
369
ar8031_phy_fixup(struct phy_device * phydev)370 static int ar8031_phy_fixup(struct phy_device *phydev)
371 {
372 unsigned short val;
373
374 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
375 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
376 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
377 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
378
379 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
380 val &= 0xffe3;
381 val |= 0x18;
382 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
383
384 /* introduce tx clock delay */
385 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
386 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
387 val |= 0x0100;
388 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
389
390 return 0;
391 }
392
board_phy_config(struct phy_device * phydev)393 int board_phy_config(struct phy_device *phydev)
394 {
395 ar8031_phy_fixup(phydev);
396
397 if (phydev->drv->config)
398 phydev->drv->config(phydev);
399
400 return 0;
401 }
402
403 #if defined(CONFIG_VIDEO_IPUV3)
disable_lvds(struct display_info_t const * dev)404 static void disable_lvds(struct display_info_t const *dev)
405 {
406 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
407
408 clrbits_le32(&iomux->gpr[2],
409 IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
410 IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
411 }
412
do_enable_hdmi(struct display_info_t const * dev)413 static void do_enable_hdmi(struct display_info_t const *dev)
414 {
415 disable_lvds(dev);
416 imx_enable_hdmi_phy();
417 }
418
419 struct display_info_t const displays[] = {{
420 .bus = -1,
421 .addr = 0,
422 .pixfmt = IPU_PIX_FMT_RGB666,
423 .detect = NULL,
424 .enable = NULL,
425 .mode = {
426 .name = "Hannstar-XGA",
427 .refresh = 60,
428 .xres = 1024,
429 .yres = 768,
430 .pixclock = 15385,
431 .left_margin = 220,
432 .right_margin = 40,
433 .upper_margin = 21,
434 .lower_margin = 7,
435 .hsync_len = 60,
436 .vsync_len = 10,
437 .sync = FB_SYNC_EXT,
438 .vmode = FB_VMODE_NONINTERLACED
439 } }, {
440 .bus = -1,
441 .addr = 0,
442 .pixfmt = IPU_PIX_FMT_RGB24,
443 .detect = detect_hdmi,
444 .enable = do_enable_hdmi,
445 .mode = {
446 .name = "HDMI",
447 .refresh = 60,
448 .xres = 1024,
449 .yres = 768,
450 .pixclock = 15385,
451 .left_margin = 220,
452 .right_margin = 40,
453 .upper_margin = 21,
454 .lower_margin = 7,
455 .hsync_len = 60,
456 .vsync_len = 10,
457 .sync = FB_SYNC_EXT,
458 .vmode = FB_VMODE_NONINTERLACED,
459 } } };
460 size_t display_count = ARRAY_SIZE(displays);
461
462 iomux_v3_cfg_t const backlight_pads[] = {
463 IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
464 };
465
setup_iomux_backlight(void)466 static void setup_iomux_backlight(void)
467 {
468 gpio_request(IMX_GPIO_NR(2, 9), "backlight");
469 gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
470 SETUP_IOMUX_PADS(backlight_pads);
471 }
472
setup_display(void)473 static void setup_display(void)
474 {
475 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
476 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
477 int reg;
478
479 setup_iomux_backlight();
480 enable_ipu_clock();
481 imx_setup_hdmi();
482
483 /* Turn on LDB_DI0 and LDB_DI1 clocks */
484 reg = readl(&mxc_ccm->CCGR3);
485 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
486 writel(reg, &mxc_ccm->CCGR3);
487
488 /* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */
489 reg = readl(&mxc_ccm->cs2cdr);
490 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
491 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
492 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
493 (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
494 writel(reg, &mxc_ccm->cs2cdr);
495
496 reg = readl(&mxc_ccm->cscmr2);
497 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
498 writel(reg, &mxc_ccm->cscmr2);
499
500 reg = readl(&mxc_ccm->chsccdr);
501 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
502 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
503 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
504 MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
505 writel(reg, &mxc_ccm->chsccdr);
506
507 reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
508 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
509 IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
510 IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
511 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
512 IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
513 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
514 IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED;
515 writel(reg, &iomux->gpr[2]);
516
517 reg = readl(&iomux->gpr[3]);
518 reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
519 IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
520 reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
521 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
522 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
523 IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET);
524 writel(reg, &iomux->gpr[3]);
525 }
526 #endif /* CONFIG_VIDEO_IPUV3 */
527
528 /*
529 * Do not overwrite the console
530 * Use always serial for U-Boot console
531 */
overwrite_console(void)532 int overwrite_console(void)
533 {
534 return 1;
535 }
536
board_early_init_f(void)537 int board_early_init_f(void)
538 {
539 setup_iomux_uart();
540
541 #ifdef CONFIG_NAND_MXS
542 setup_gpmi_nand();
543 #endif
544
545 #ifdef CONFIG_MTD_NOR_FLASH
546 eim_clk_setup();
547 #endif
548 return 0;
549 }
550
board_init(void)551 int board_init(void)
552 {
553 /* address of boot parameters */
554 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
555
556 /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
557 if (is_mx6dq() || is_mx6dqp())
558 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
559 else
560 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
561 /* I2C 3 Steer */
562 gpio_request(IMX_GPIO_NR(5, 4), "steer logic");
563 gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
564 SETUP_IOMUX_PADS(i2c3_pads);
565 #ifndef CONFIG_SYS_FLASH_CFI
566 if (is_mx6dq() || is_mx6dqp())
567 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
568 else
569 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
570 #endif
571 gpio_request(IMX_GPIO_NR(1, 15), "expander en");
572 gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
573 SETUP_IOMUX_PADS(port_exp);
574
575 #ifdef CONFIG_VIDEO_IPUV3
576 setup_display();
577 #endif
578
579 #ifdef CONFIG_MTD_NOR_FLASH
580 setup_iomux_eimnor();
581 #endif
582 return 0;
583 }
584
585 #ifdef CONFIG_MXC_SPI
board_spi_cs_gpio(unsigned bus,unsigned cs)586 int board_spi_cs_gpio(unsigned bus, unsigned cs)
587 {
588 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
589 }
590 #endif
591
power_init_board(void)592 int power_init_board(void)
593 {
594 struct pmic *p;
595 unsigned int value;
596
597 p = pfuze_common_init(I2C_PMIC);
598 if (!p)
599 return -ENODEV;
600
601 if (is_mx6dqp()) {
602 /* set SW2 staby volatage 0.975V*/
603 pmic_reg_read(p, PFUZE100_SW2STBY, &value);
604 value &= ~0x3f;
605 value |= 0x17;
606 pmic_reg_write(p, PFUZE100_SW2STBY, value);
607 }
608
609 return pfuze_mode_init(p, APS_PFM);
610 }
611
612 #ifdef CONFIG_CMD_BMODE
613 static const struct boot_mode board_boot_modes[] = {
614 /* 4 bit bus width */
615 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
616 {NULL, 0},
617 };
618 #endif
619
board_late_init(void)620 int board_late_init(void)
621 {
622 #ifdef CONFIG_CMD_BMODE
623 add_board_boot_modes(board_boot_modes);
624 #endif
625
626 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
627 env_set("board_name", "SABREAUTO");
628
629 if (is_mx6dqp())
630 env_set("board_rev", "MX6QP");
631 else if (is_mx6dq())
632 env_set("board_rev", "MX6Q");
633 else if (is_mx6sdl())
634 env_set("board_rev", "MX6DL");
635 #endif
636
637 return 0;
638 }
639
checkboard(void)640 int checkboard(void)
641 {
642 printf("Board: MX6Q-Sabreauto rev%c\n", nxp_board_rev_string());
643
644 return 0;
645 }
646
647 #ifdef CONFIG_USB_EHCI_MX6
board_ehci_hcd_init(int port)648 int board_ehci_hcd_init(int port)
649 {
650 switch (port) {
651 case 0:
652 /*
653 * Set daisy chain for otg_pin_id on 6q.
654 * For 6dl, this bit is reserved.
655 */
656 imx_iomux_set_gpr_register(1, 13, 1, 0);
657 break;
658 case 1:
659 break;
660 default:
661 printf("MXC USB port %d not yet supported\n", port);
662 return -EINVAL;
663 }
664 return 0;
665 }
666 #endif
667
668 #ifdef CONFIG_SPL_BUILD
669 #include <asm/arch/mx6-ddr.h>
670 #include <spl.h>
671 #include <linux/libfdt.h>
672
673 #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)674 int spl_start_uboot(void)
675 {
676 return 0;
677 }
678 #endif
679
ccgr_init(void)680 static void ccgr_init(void)
681 {
682 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
683
684 writel(0x00C03F3F, &ccm->CCGR0);
685 writel(0x0030FC03, &ccm->CCGR1);
686 writel(0x0FFFC000, &ccm->CCGR2);
687 writel(0x3FF00000, &ccm->CCGR3);
688 writel(0x00FFF300, &ccm->CCGR4);
689 writel(0x0F0000C3, &ccm->CCGR5);
690 writel(0x000003FF, &ccm->CCGR6);
691 }
692
693 static int mx6q_dcd_table[] = {
694 0x020e0798, 0x000C0000,
695 0x020e0758, 0x00000000,
696 0x020e0588, 0x00000030,
697 0x020e0594, 0x00000030,
698 0x020e056c, 0x00000030,
699 0x020e0578, 0x00000030,
700 0x020e074c, 0x00000030,
701 0x020e057c, 0x00000030,
702 0x020e058c, 0x00000000,
703 0x020e059c, 0x00000030,
704 0x020e05a0, 0x00000030,
705 0x020e078c, 0x00000030,
706 0x020e0750, 0x00020000,
707 0x020e05a8, 0x00000028,
708 0x020e05b0, 0x00000028,
709 0x020e0524, 0x00000028,
710 0x020e051c, 0x00000028,
711 0x020e0518, 0x00000028,
712 0x020e050c, 0x00000028,
713 0x020e05b8, 0x00000028,
714 0x020e05c0, 0x00000028,
715 0x020e0774, 0x00020000,
716 0x020e0784, 0x00000028,
717 0x020e0788, 0x00000028,
718 0x020e0794, 0x00000028,
719 0x020e079c, 0x00000028,
720 0x020e07a0, 0x00000028,
721 0x020e07a4, 0x00000028,
722 0x020e07a8, 0x00000028,
723 0x020e0748, 0x00000028,
724 0x020e05ac, 0x00000028,
725 0x020e05b4, 0x00000028,
726 0x020e0528, 0x00000028,
727 0x020e0520, 0x00000028,
728 0x020e0514, 0x00000028,
729 0x020e0510, 0x00000028,
730 0x020e05bc, 0x00000028,
731 0x020e05c4, 0x00000028,
732 0x021b0800, 0xa1390003,
733 0x021b080c, 0x001F001F,
734 0x021b0810, 0x001F001F,
735 0x021b480c, 0x001F001F,
736 0x021b4810, 0x001F001F,
737 0x021b083c, 0x43260335,
738 0x021b0840, 0x031A030B,
739 0x021b483c, 0x4323033B,
740 0x021b4840, 0x0323026F,
741 0x021b0848, 0x483D4545,
742 0x021b4848, 0x44433E48,
743 0x021b0850, 0x41444840,
744 0x021b4850, 0x4835483E,
745 0x021b081c, 0x33333333,
746 0x021b0820, 0x33333333,
747 0x021b0824, 0x33333333,
748 0x021b0828, 0x33333333,
749 0x021b481c, 0x33333333,
750 0x021b4820, 0x33333333,
751 0x021b4824, 0x33333333,
752 0x021b4828, 0x33333333,
753 0x021b08b8, 0x00000800,
754 0x021b48b8, 0x00000800,
755 0x021b0004, 0x00020036,
756 0x021b0008, 0x09444040,
757 0x021b000c, 0x8A8F7955,
758 0x021b0010, 0xFF328F64,
759 0x021b0014, 0x01FF00DB,
760 0x021b0018, 0x00001740,
761 0x021b001c, 0x00008000,
762 0x021b002c, 0x000026d2,
763 0x021b0030, 0x008F1023,
764 0x021b0040, 0x00000047,
765 0x021b0000, 0x841A0000,
766 0x021b001c, 0x04088032,
767 0x021b001c, 0x00008033,
768 0x021b001c, 0x00048031,
769 0x021b001c, 0x09408030,
770 0x021b001c, 0x04008040,
771 0x021b0020, 0x00005800,
772 0x021b0818, 0x00011117,
773 0x021b4818, 0x00011117,
774 0x021b0004, 0x00025576,
775 0x021b0404, 0x00011006,
776 0x021b001c, 0x00000000,
777 0x020c4068, 0x00C03F3F,
778 0x020c406c, 0x0030FC03,
779 0x020c4070, 0x0FFFC000,
780 0x020c4074, 0x3FF00000,
781 0x020c4078, 0xFFFFF300,
782 0x020c407c, 0x0F0000F3,
783 0x020c4080, 0x00000FFF,
784 0x020e0010, 0xF00000CF,
785 0x020e0018, 0x007F007F,
786 0x020e001c, 0x007F007F,
787 };
788
789 static int mx6qp_dcd_table[] = {
790 0x020e0798, 0x000C0000,
791 0x020e0758, 0x00000000,
792 0x020e0588, 0x00000030,
793 0x020e0594, 0x00000030,
794 0x020e056c, 0x00000030,
795 0x020e0578, 0x00000030,
796 0x020e074c, 0x00000030,
797 0x020e057c, 0x00000030,
798 0x020e058c, 0x00000000,
799 0x020e059c, 0x00000030,
800 0x020e05a0, 0x00000030,
801 0x020e078c, 0x00000030,
802 0x020e0750, 0x00020000,
803 0x020e05a8, 0x00000030,
804 0x020e05b0, 0x00000030,
805 0x020e0524, 0x00000030,
806 0x020e051c, 0x00000030,
807 0x020e0518, 0x00000030,
808 0x020e050c, 0x00000030,
809 0x020e05b8, 0x00000030,
810 0x020e05c0, 0x00000030,
811 0x020e0774, 0x00020000,
812 0x020e0784, 0x00000030,
813 0x020e0788, 0x00000030,
814 0x020e0794, 0x00000030,
815 0x020e079c, 0x00000030,
816 0x020e07a0, 0x00000030,
817 0x020e07a4, 0x00000030,
818 0x020e07a8, 0x00000030,
819 0x020e0748, 0x00000030,
820 0x020e05ac, 0x00000030,
821 0x020e05b4, 0x00000030,
822 0x020e0528, 0x00000030,
823 0x020e0520, 0x00000030,
824 0x020e0514, 0x00000030,
825 0x020e0510, 0x00000030,
826 0x020e05bc, 0x00000030,
827 0x020e05c4, 0x00000030,
828 0x021b0800, 0xa1390003,
829 0x021b080c, 0x001b001e,
830 0x021b0810, 0x002e0029,
831 0x021b480c, 0x001b002a,
832 0x021b4810, 0x0019002c,
833 0x021b083c, 0x43240334,
834 0x021b0840, 0x0324031a,
835 0x021b483c, 0x43340344,
836 0x021b4840, 0x03280276,
837 0x021b0848, 0x44383A3E,
838 0x021b4848, 0x3C3C3846,
839 0x021b0850, 0x2e303230,
840 0x021b4850, 0x38283E34,
841 0x021b081c, 0x33333333,
842 0x021b0820, 0x33333333,
843 0x021b0824, 0x33333333,
844 0x021b0828, 0x33333333,
845 0x021b481c, 0x33333333,
846 0x021b4820, 0x33333333,
847 0x021b4824, 0x33333333,
848 0x021b4828, 0x33333333,
849 0x021b08c0, 0x24912492,
850 0x021b48c0, 0x24912492,
851 0x021b08b8, 0x00000800,
852 0x021b48b8, 0x00000800,
853 0x021b0004, 0x00020036,
854 0x021b0008, 0x09444040,
855 0x021b000c, 0x898E7955,
856 0x021b0010, 0xFF328F64,
857 0x021b0014, 0x01FF00DB,
858 0x021b0018, 0x00001740,
859 0x021b001c, 0x00008000,
860 0x021b002c, 0x000026d2,
861 0x021b0030, 0x008E1023,
862 0x021b0040, 0x00000047,
863 0x021b0400, 0x14420000,
864 0x021b0000, 0x841A0000,
865 0x00bb0008, 0x00000004,
866 0x00bb000c, 0x2891E41A,
867 0x00bb0038, 0x00000564,
868 0x00bb0014, 0x00000040,
869 0x00bb0028, 0x00000020,
870 0x00bb002c, 0x00000020,
871 0x021b001c, 0x04088032,
872 0x021b001c, 0x00008033,
873 0x021b001c, 0x00048031,
874 0x021b001c, 0x09408030,
875 0x021b001c, 0x04008040,
876 0x021b0020, 0x00005800,
877 0x021b0818, 0x00011117,
878 0x021b4818, 0x00011117,
879 0x021b0004, 0x00025576,
880 0x021b0404, 0x00011006,
881 0x021b001c, 0x00000000,
882 0x020c4068, 0x00C03F3F,
883 0x020c406c, 0x0030FC03,
884 0x020c4070, 0x0FFFC000,
885 0x020c4074, 0x3FF00000,
886 0x020c4078, 0xFFFFF300,
887 0x020c407c, 0x0F0000F3,
888 0x020c4080, 0x00000FFF,
889 0x020e0010, 0xF00000CF,
890 0x020e0018, 0x77177717,
891 0x020e001c, 0x77177717,
892 };
893
894 static int mx6dl_dcd_table[] = {
895 0x020e0774, 0x000C0000,
896 0x020e0754, 0x00000000,
897 0x020e04ac, 0x00000030,
898 0x020e04b0, 0x00000030,
899 0x020e0464, 0x00000030,
900 0x020e0490, 0x00000030,
901 0x020e074c, 0x00000030,
902 0x020e0494, 0x00000030,
903 0x020e04a0, 0x00000000,
904 0x020e04b4, 0x00000030,
905 0x020e04b8, 0x00000030,
906 0x020e076c, 0x00000030,
907 0x020e0750, 0x00020000,
908 0x020e04bc, 0x00000028,
909 0x020e04c0, 0x00000028,
910 0x020e04c4, 0x00000028,
911 0x020e04c8, 0x00000028,
912 0x020e04cc, 0x00000028,
913 0x020e04d0, 0x00000028,
914 0x020e04d4, 0x00000028,
915 0x020e04d8, 0x00000028,
916 0x020e0760, 0x00020000,
917 0x020e0764, 0x00000028,
918 0x020e0770, 0x00000028,
919 0x020e0778, 0x00000028,
920 0x020e077c, 0x00000028,
921 0x020e0780, 0x00000028,
922 0x020e0784, 0x00000028,
923 0x020e078c, 0x00000028,
924 0x020e0748, 0x00000028,
925 0x020e0470, 0x00000028,
926 0x020e0474, 0x00000028,
927 0x020e0478, 0x00000028,
928 0x020e047c, 0x00000028,
929 0x020e0480, 0x00000028,
930 0x020e0484, 0x00000028,
931 0x020e0488, 0x00000028,
932 0x020e048c, 0x00000028,
933 0x021b0800, 0xa1390003,
934 0x021b080c, 0x001F001F,
935 0x021b0810, 0x001F001F,
936 0x021b480c, 0x001F001F,
937 0x021b4810, 0x001F001F,
938 0x021b083c, 0x42190217,
939 0x021b0840, 0x017B017B,
940 0x021b483c, 0x4176017B,
941 0x021b4840, 0x015F016C,
942 0x021b0848, 0x4C4C4D4C,
943 0x021b4848, 0x4A4D4C48,
944 0x021b0850, 0x3F3F3F40,
945 0x021b4850, 0x3538382E,
946 0x021b081c, 0x33333333,
947 0x021b0820, 0x33333333,
948 0x021b0824, 0x33333333,
949 0x021b0828, 0x33333333,
950 0x021b481c, 0x33333333,
951 0x021b4820, 0x33333333,
952 0x021b4824, 0x33333333,
953 0x021b4828, 0x33333333,
954 0x021b08b8, 0x00000800,
955 0x021b48b8, 0x00000800,
956 0x021b0004, 0x00020025,
957 0x021b0008, 0x00333030,
958 0x021b000c, 0x676B5313,
959 0x021b0010, 0xB66E8B63,
960 0x021b0014, 0x01FF00DB,
961 0x021b0018, 0x00001740,
962 0x021b001c, 0x00008000,
963 0x021b002c, 0x000026d2,
964 0x021b0030, 0x006B1023,
965 0x021b0040, 0x00000047,
966 0x021b0000, 0x841A0000,
967 0x021b001c, 0x04008032,
968 0x021b001c, 0x00008033,
969 0x021b001c, 0x00048031,
970 0x021b001c, 0x05208030,
971 0x021b001c, 0x04008040,
972 0x021b0020, 0x00005800,
973 0x021b0818, 0x00011117,
974 0x021b4818, 0x00011117,
975 0x021b0004, 0x00025565,
976 0x021b0404, 0x00011006,
977 0x021b001c, 0x00000000,
978 0x020c4068, 0x00C03F3F,
979 0x020c406c, 0x0030FC03,
980 0x020c4070, 0x0FFFC000,
981 0x020c4074, 0x3FF00000,
982 0x020c4078, 0xFFFFF300,
983 0x020c407c, 0x0F0000C3,
984 0x020c4080, 0x00000FFF,
985 0x020e0010, 0xF00000CF,
986 0x020e0018, 0x007F007F,
987 0x020e001c, 0x007F007F,
988 };
989
ddr_init(int * table,int size)990 static void ddr_init(int *table, int size)
991 {
992 int i;
993
994 for (i = 0; i < size / 2 ; i++)
995 writel(table[2 * i + 1], table[2 * i]);
996 }
997
spl_dram_init(void)998 static void spl_dram_init(void)
999 {
1000 if (is_mx6dq())
1001 ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
1002 else if (is_mx6dqp())
1003 ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
1004 else if (is_mx6sdl())
1005 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1006 }
1007
board_init_f(ulong dummy)1008 void board_init_f(ulong dummy)
1009 {
1010 /* DDR initialization */
1011 spl_dram_init();
1012
1013 /* setup AIPS and disable watchdog */
1014 arch_cpu_init();
1015
1016 ccgr_init();
1017 gpr_init();
1018
1019 /* iomux and setup of i2c */
1020 board_early_init_f();
1021
1022 /* setup GP timer */
1023 timer_init();
1024
1025 /* UART clocks enabled and gd valid - init serial console */
1026 preloader_console_init();
1027
1028 /* Clear the BSS. */
1029 memset(__bss_start, 0, __bss_end - __bss_start);
1030
1031 /* load/boot image from boot device */
1032 board_init_r(NULL, 0);
1033 }
1034 #endif
1035
1036 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)1037 int board_fit_config_name_match(const char *name)
1038 {
1039 if (is_mx6dq()) {
1040 if (!strcmp(name, "imx6q-sabreauto"))
1041 return 0;
1042 } else if (is_mx6dqp()) {
1043 if (!strcmp(name, "imx6qp-sabreauto"))
1044 return 0;
1045 } else if (is_mx6dl()) {
1046 if (!strcmp(name, "imx6dl-sabreauto"))
1047 return 0;
1048 }
1049
1050 return -1;
1051 }
1052 #endif
1053