1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 *
5 * Author: Ye Li <ye.li@nxp.com>
6 */
7
8 #include <init.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/gpio.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/mach-imx/boot_mode.h>
18 #include <asm/io.h>
19 #include <linux/sizes.h>
20 #include <common.h>
21 #include <fsl_esdhc_imx.h>
22 #include <miiphy.h>
23 #include <netdev.h>
24 #include <power/pmic.h>
25 #include <power/pfuze100_pmic.h>
26 #include "../common/pfuze.h"
27 #include <usb.h>
28 #include <usb/ehci-ci.h>
29 #include <pca953x.h>
30
31 DECLARE_GLOBAL_DATA_PTR;
32
33 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
34 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
35 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
36
37 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
38 PAD_CTL_SPEED_HIGH | \
39 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
40
41 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
42 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
43
44 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
45 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
46
47 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
48 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
49 PAD_CTL_SRE_FAST)
50 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
51
dram_init(void)52 int dram_init(void)
53 {
54 gd->ram_size = imx_ddr_size();
55
56 return 0;
57 }
58
59 static iomux_v3_cfg_t const uart1_pads[] = {
60 MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
61 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
62 };
63
64 static iomux_v3_cfg_t const fec2_pads[] = {
65 MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
66 MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
67 MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
68 MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
69 MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
70 MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
71 MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
72 MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
73 MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
74 MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
75 MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
76 MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
77 MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
78 MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
79 };
80
setup_iomux_uart(void)81 static void setup_iomux_uart(void)
82 {
83 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
84 }
85
setup_fec(void)86 static int setup_fec(void)
87 {
88 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
89
90 /* Use 125MHz anatop loopback REF_CLK1 for ENET2 */
91 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0);
92
93 return enable_fec_anatop_clock(1, ENET_125MHZ);
94 }
95
board_eth_init(bd_t * bis)96 int board_eth_init(bd_t *bis)
97 {
98 int ret;
99
100 imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
101 setup_fec();
102
103 ret = fecmxc_initialize_multi(bis, 1,
104 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
105 if (ret)
106 printf("FEC%d MXC: %s:failed\n", 1, __func__);
107
108 return ret;
109 }
110
board_phy_config(struct phy_device * phydev)111 int board_phy_config(struct phy_device *phydev)
112 {
113 /*
114 * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
115 * Phy control debug reg 0
116 */
117 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
118 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
119
120 /* rgmii tx clock delay enable */
121 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
122 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
123
124 if (phydev->drv->config)
125 phydev->drv->config(phydev);
126
127 return 0;
128 }
129
power_init_board(void)130 int power_init_board(void)
131 {
132 struct udevice *dev;
133 int ret;
134 u32 dev_id, rev_id, i;
135 u32 switch_num = 6;
136 u32 offset = PFUZE100_SW1CMODE;
137
138 ret = pmic_get("pfuze100", &dev);
139 if (ret == -ENODEV)
140 return 0;
141
142 if (ret != 0)
143 return ret;
144
145 dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
146 rev_id = pmic_reg_read(dev, PFUZE100_REVID);
147 printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
148
149
150 /* Init mode to APS_PFM */
151 pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
152
153 for (i = 0; i < switch_num - 1; i++)
154 pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
155
156 /* set SW1AB staby volatage 0.975V */
157 pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
158
159 /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
160 pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
161
162 /* set SW1C staby volatage 1.10V */
163 pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x20);
164
165 /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
166 pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
167
168 return 0;
169 }
170
171 #ifdef CONFIG_USB_EHCI_MX6
172 #define USB_OTHERREGS_OFFSET 0x800
173 #define UCTRL_PWR_POL (1 << 9)
174
175 static iomux_v3_cfg_t const usb_otg_pads[] = {
176 /* OGT1 */
177 MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
178 MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
179 /* OTG2 */
180 MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
181 };
182
setup_usb(void)183 static void setup_usb(void)
184 {
185 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
186 ARRAY_SIZE(usb_otg_pads));
187 }
188
board_usb_phy_mode(int port)189 int board_usb_phy_mode(int port)
190 {
191 if (port == 1)
192 return USB_INIT_HOST;
193 else
194 return usb_phy_mode(port);
195 }
196
board_ehci_hcd_init(int port)197 int board_ehci_hcd_init(int port)
198 {
199 u32 *usbnc_usb_ctrl;
200
201 if (port > 1)
202 return -EINVAL;
203
204 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
205 port * 4);
206
207 /* Set Power polarity */
208 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
209
210 return 0;
211 }
212 #endif
213
board_early_init_f(void)214 int board_early_init_f(void)
215 {
216 setup_iomux_uart();
217
218 return 0;
219 }
220
221 #ifdef CONFIG_FSL_QSPI
board_qspi_init(void)222 int board_qspi_init(void)
223 {
224 /* Set the clock */
225 enable_qspi_clk(0);
226
227 return 0;
228 }
229 #endif
230
231 #ifdef CONFIG_NAND_MXS
232 iomux_v3_cfg_t gpmi_pads[] = {
233 MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
234 MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
235 MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
236 MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
237 MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
238 MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
239 MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
240 MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
241 MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
242 MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
243 MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
244 MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
245 MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
246 MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
247 MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
248 };
249
setup_gpmi_nand(void)250 static void setup_gpmi_nand(void)
251 {
252 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
253
254 /* config gpmi nand iomux */
255 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
256
257 setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) |
258 MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) |
259 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3)));
260
261 /* enable apbh clock gating */
262 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
263 }
264 #endif
265
board_init(void)266 int board_init(void)
267 {
268 struct gpio_desc desc;
269 int ret;
270
271 /* Address of boot parameters */
272 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
273
274 ret = dm_gpio_lookup_name("gpio@30_4", &desc);
275 if (ret)
276 return ret;
277
278 ret = dm_gpio_request(&desc, "cpu_per_rst_b");
279 if (ret)
280 return ret;
281 /* Reset CPU_PER_RST_B signal for enet phy and PCIE */
282 dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
283 udelay(500);
284 dm_gpio_set_value(&desc, 1);
285
286 ret = dm_gpio_lookup_name("gpio@32_2", &desc);
287 if (ret)
288 return ret;
289
290 ret = dm_gpio_request(&desc, "steer_enet");
291 if (ret)
292 return ret;
293
294 dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
295 udelay(500);
296 /* Set steering signal to L for selecting B0 */
297 dm_gpio_set_value(&desc, 0);
298
299 #ifdef CONFIG_USB_EHCI_MX6
300 setup_usb();
301 #endif
302
303 #ifdef CONFIG_FSL_QSPI
304 board_qspi_init();
305 #endif
306
307 #ifdef CONFIG_NAND_MXS
308 setup_gpmi_nand();
309 #endif
310
311 return 0;
312 }
313
314 #ifdef CONFIG_CMD_BMODE
315 static const struct boot_mode board_boot_modes[] = {
316 {"sda", MAKE_CFGVAL(0x42, 0x30, 0x00, 0x00)},
317 {"sdb", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
318 {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
319 {"nand", MAKE_CFGVAL(0x82, 0x00, 0x00, 0x00)},
320 {NULL, 0},
321 };
322 #endif
323
board_late_init(void)324 int board_late_init(void)
325 {
326 #ifdef CONFIG_CMD_BMODE
327 add_board_boot_modes(board_boot_modes);
328 #endif
329
330 return 0;
331 }
332
checkboard(void)333 int checkboard(void)
334 {
335 puts("Board: MX6SX SABRE AUTO\n");
336
337 return 0;
338 }
339