1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 *
5 * Authors: Roy Zang <tie-fei.zang@freescale.com>
6 * Chunhe Lan <Chunhe.Lan@freescale.com>
7 */
8
9 #include <common.h>
10 #include <command.h>
11 #include <env.h>
12 #include <init.h>
13 #include <pci.h>
14 #include <asm/io.h>
15 #include <asm/cache.h>
16 #include <asm/processor.h>
17 #include <asm/mmu.h>
18 #include <asm/immap_85xx.h>
19 #include <asm/fsl_pci.h>
20 #include <fsl_ddr_sdram.h>
21 #include <asm/fsl_portals.h>
22 #include <fsl_qbman.h>
23 #include <linux/libfdt.h>
24 #include <fdt_support.h>
25 #include <netdev.h>
26 #include <malloc.h>
27 #include <fm_eth.h>
28 #include <fsl_mdio.h>
29 #include <miiphy.h>
30 #include <phy.h>
31 #include <fsl_dtsec.h>
32
33 DECLARE_GLOBAL_DATA_PTR;
34
board_early_init_f(void)35 int board_early_init_f(void)
36 {
37 fsl_lbc_t *lbc = LBC_BASE_ADDR;
38
39 /* Set ABSWP to implement conversion of addresses in the LBC */
40 setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
41
42 return 0;
43 }
44
checkboard(void)45 int checkboard(void)
46 {
47 printf("Board: P1023 RDB\n");
48
49 return 0;
50 }
51
52 #ifdef CONFIG_PCI
pci_init_board(void)53 void pci_init_board(void)
54 {
55 fsl_pcie_init_board(0);
56 }
57 #endif
58
board_early_init_r(void)59 int board_early_init_r(void)
60 {
61 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
62 int flash_esel = find_tlb_idx((void *)flashbase, 1);
63
64 /*
65 * Remap Boot flash + PROMJET region to caching-inhibited
66 * so that flash can be erased properly.
67 */
68
69 /* Flush d-cache and invalidate i-cache of any FLASH data */
70 flush_dcache();
71 invalidate_icache();
72
73 if (flash_esel == -1) {
74 /* very unlikely unless something is messed up */
75 puts("Error: Could not find TLB for FLASH BASE\n");
76 flash_esel = 2; /* give our best effort to continue */
77 } else {
78 /* invalidate existing TLB entry for flash + promjet */
79 disable_tlb(flash_esel);
80 }
81
82 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
83 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
84 0, flash_esel, BOOKE_PAGESZ_256M, 1);
85
86 setup_qbman_portals();
87
88 return 0;
89 }
90
get_board_sys_clk(ulong dummy)91 unsigned long get_board_sys_clk(ulong dummy)
92 {
93 return gd->bus_clk;
94 }
95
get_board_ddr_clk(ulong dummy)96 unsigned long get_board_ddr_clk(ulong dummy)
97 {
98 return gd->mem_clk;
99 }
100
board_eth_init(bd_t * bis)101 int board_eth_init(bd_t *bis)
102 {
103 ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
104 struct fsl_pq_mdio_info dtsec_mdio_info;
105
106 /*
107 * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting
108 * is not correct.
109 */
110 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1);
111
112 dtsec_mdio_info.regs =
113 (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
114 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
115
116 /* Register the 1G MDIO bus */
117 fsl_pq_mdio_init(bis, &dtsec_mdio_info);
118
119 fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
120 fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
121
122 fm_info_set_mdio(FM1_DTSEC1,
123 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
124 fm_info_set_mdio(FM1_DTSEC2,
125 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
126
127 #ifdef CONFIG_FMAN_ENET
128 cpu_eth_init(bis);
129 #endif
130
131 return pci_eth_init(bis);
132 }
133
134 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,bd_t * bd)135 int ft_board_setup(void *blob, bd_t *bd)
136 {
137 phys_addr_t base;
138 phys_size_t size;
139
140 ft_cpu_setup(blob, bd);
141
142 base = env_get_bootm_low();
143 size = env_get_bootm_size();
144
145 fdt_fixup_memory(blob, (u64)base, (u64)size);
146
147 #ifdef CONFIG_HAS_FSL_DR_USB
148 fsl_fdt_fixup_dr_usb(blob, bd);
149 #endif
150
151 fdt_fixup_fman_ethernet(blob);
152
153 return 0;
154 }
155 #endif
156