1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2011,2012 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <command.h>
8 #include <env.h>
9 #include <init.h>
10 #include <netdev.h>
11 #include <linux/compiler.h>
12 #include <asm/mmu.h>
13 #include <asm/processor.h>
14 #include <asm/cache.h>
15 #include <asm/immap_85xx.h>
16 #include <asm/fsl_law.h>
17 #include <asm/fsl_serdes.h>
18 #include <asm/fsl_liodn.h>
19 #include <fm_eth.h>
20
21 extern void pci_of_setup(void *blob, bd_t *bd);
22
23 #include "cpld.h"
24
25 DECLARE_GLOBAL_DATA_PTR;
26
checkboard(void)27 int checkboard(void)
28 {
29 u8 sw;
30 struct cpu_type *cpu = gd->arch.cpu;
31 unsigned int i;
32
33 printf("Board: %sRDB, ", cpu->name);
34 printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver),
35 CPLD_READ(cpld_ver_sub));
36
37 sw = CPLD_READ(fbank_sel);
38 printf("vBank: %d\n", sw & 0x1);
39
40 /*
41 * Display the actual SERDES reference clocks as configured by the
42 * dip switches on the board. Note that the SWx registers could
43 * technically be set to force the reference clocks to match the
44 * values that the SERDES expects (or vice versa). For now, however,
45 * we just display both values and hope the user notices when they
46 * don't match.
47 */
48 puts("SERDES Reference Clocks: ");
49 sw = in_8(&CPLD_SW(2)) >> 2;
50 for (i = 0; i < 2; i++) {
51 static const char * const freq[][3] = {{"0", "100", "125"},
52 {"100", "156.25", "125"}
53 };
54 unsigned int clock = (sw >> (2 * i)) & 3;
55
56 printf("Bank%u=%sMhz ", i+1, freq[i][clock]);
57 }
58 puts("\n");
59
60 return 0;
61 }
62
board_early_init_f(void)63 int board_early_init_f(void)
64 {
65 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
66
67 /* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */
68 setbits_be32(&gur->ddrclkdr, 0x000f000f);
69
70 return 0;
71 }
72
73 #define CPLD_LANE_A_SEL 0x1
74 #define CPLD_LANE_G_SEL 0x2
75 #define CPLD_LANE_C_SEL 0x4
76 #define CPLD_LANE_D_SEL 0x8
77
board_config_lanes_mux(void)78 void board_config_lanes_mux(void)
79 {
80 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
81 int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
82 FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
83
84 u8 mux = 0;
85 switch (srds_prtcl) {
86 case 0x2:
87 case 0x5:
88 case 0x9:
89 case 0xa:
90 case 0xf:
91 break;
92 case 0x8:
93 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
94 break;
95 case 0x14:
96 mux |= CPLD_LANE_A_SEL;
97 break;
98 case 0x17:
99 mux |= CPLD_LANE_G_SEL;
100 break;
101 case 0x16:
102 case 0x19:
103 case 0x1a:
104 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
105 break;
106 case 0x1c:
107 mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
108 break;
109 default:
110 printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl);
111 break;
112 }
113 CPLD_WRITE(serdes_mux, mux);
114 }
115
board_early_init_r(void)116 int board_early_init_r(void)
117 {
118 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
119 int flash_esel = find_tlb_idx((void *)flashbase, 1);
120
121 /*
122 * Remap Boot flash + PROMJET region to caching-inhibited
123 * so that flash can be erased properly.
124 */
125
126 /* Flush d-cache and invalidate i-cache of any FLASH data */
127 flush_dcache();
128 invalidate_icache();
129
130 if (flash_esel == -1) {
131 /* very unlikely unless something is messed up */
132 puts("Error: Could not find TLB for FLASH BASE\n");
133 flash_esel = 2; /* give our best effort to continue */
134 } else {
135 /* invalidate existing TLB entry for flash + promjet */
136 disable_tlb(flash_esel);
137 }
138
139 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
140 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
141 0, flash_esel, BOOKE_PAGESZ_256M, 1);
142
143 board_config_lanes_mux();
144
145 return 0;
146 }
147
get_board_sys_clk(unsigned long dummy)148 unsigned long get_board_sys_clk(unsigned long dummy)
149 {
150 u8 sysclk_conf = CPLD_READ(sysclk_sw1);
151
152 switch (sysclk_conf & 0x7) {
153 case CPLD_SYSCLK_83:
154 return 83333333;
155 case CPLD_SYSCLK_100:
156 return 100000000;
157 default:
158 return 66666666;
159 }
160 }
161
162 #define NUM_SRDS_BANKS 2
163
misc_init_r(void)164 int misc_init_r(void)
165 {
166 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
167 u32 actual[NUM_SRDS_BANKS];
168 unsigned int i;
169 u8 sw;
170 static const int freq[][3] = {
171 {0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125},
172 {SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25,
173 SRDS_PLLCR0_RFCK_SEL_125}
174 };
175
176 sw = in_8(&CPLD_SW(2)) >> 2;
177 for (i = 0; i < NUM_SRDS_BANKS; i++) {
178 unsigned int clock = (sw >> (2 * i)) & 3;
179 if (clock == 0x3) {
180 printf("Warning: SDREFCLK%u switch setting of '11' is "
181 "unsupported\n", i + 1);
182 break;
183 }
184 if (i == 0 && clock == 0)
185 puts("Warning: SDREFCLK1 switch setting of"
186 "'00' is unsupported\n");
187 else
188 actual[i] = freq[i][clock];
189
190 /*
191 * PC board uses a different CPLD with PB board, this CPLD
192 * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB
193 * board has cpld_ver_sub = 0, and pcba_ver = 4.
194 */
195 if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) &&
196 (CPLD_READ(pcba_ver) == 5)) {
197 /* PC board bank2 frequency */
198 actual[i] = freq[i-1][clock];
199 }
200 }
201
202 for (i = 0; i < NUM_SRDS_BANKS; i++) {
203 u32 expected = in_be32(®s->bank[i].pllcr0);
204 expected &= SRDS_PLLCR0_RFCK_SEL_MASK;
205 if (expected != actual[i]) {
206 printf("Warning: SERDES bank %u expects reference clock"
207 " %sMHz, but actual is %sMHz\n", i + 1,
208 serdes_clock_to_string(expected),
209 serdes_clock_to_string(actual[i]));
210 }
211 }
212
213 return 0;
214 }
215
ft_board_setup(void * blob,bd_t * bd)216 int ft_board_setup(void *blob, bd_t *bd)
217 {
218 phys_addr_t base;
219 phys_size_t size;
220
221 ft_cpu_setup(blob, bd);
222
223 base = env_get_bootm_low();
224 size = env_get_bootm_size();
225
226 fdt_fixup_memory(blob, (u64)base, (u64)size);
227
228 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
229 fsl_fdt_fixup_dr_usb(blob, bd);
230 #endif
231
232 #ifdef CONFIG_PCI
233 pci_of_setup(blob, bd);
234 #endif
235
236 fdt_fixup_liodn(blob);
237 #ifdef CONFIG_SYS_DPAA_FMAN
238 fdt_fixup_fman_ethernet(blob);
239 #endif
240
241 return 0;
242 }
243